Packaging structure and forming method thereof

Abstract

Some embodiments of this disclosure provide a packaging structure and a method for forming the same. The packaging structure includes a packaging substrate, a semiconductor chip on top of the packaging substrate, and at least one integrated device integrated with the semiconductor chip. The integrated device is integrated directly below the semiconductor chip to facilitate signal transmission. Therefore, signal integration and power integration of the packaging structure are improved. Furthermore, the integrated device does not need to occupy mounting space above the packaging substrate, thus reducing the size of the packaging substrate and the overall size of the packaging structure.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to semiconductor packages. Background Art

[0002] Integrated circuits (ICs) have been made practical through technological advances in the manufacture of semiconductor devices. Driven by technological advances that fit more and more components on the same size chip, the size, speed, and capacity of chips have increased dramatically. Continued advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and / or higher levels of integration. Functional density (i.e., the number of interconnect devices per unit chip area) generally increases, while feature size (i.e., the smallest component that can be produced using a manufacturing process) decreases. Such scaling-down processes generally provide benefits by increasing manufacturing efficiency and reducing associated costs.

[0003] The chip package not only provides protection for the semiconductor device to prevent the semiconductor device from being polluted by the environment, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures that utilize less area or lower height have been developed to package semiconductor devices.

[0004] Although existing packaging techniques have been generally adequate for their intended purposes, existing packaging techniques are not entirely satisfactory in all respects. Summary of the invention

[0005] According to some embodiments, a packaging structure is provided. The packaging structure includes a packaging substrate, a semiconductor chip, and an integrated device. The semiconductor chip is disposed above the packaging substrate and has a lower surface facing the packaging substrate. The integrated device is disposed between the packaging substrate and the semiconductor chip and bonded to the lower surface of the semiconductor chip.

[0006] According to some embodiments, a method for forming a package structure is provided. The method includes bonding an integrated device to a semiconductor chip. The method also includes arranging the semiconductor chip having the integrated device above a package substrate, such that the integrated device is between a lower surface of the semiconductor chip and an upper surface of the package substrate.

[0007] According to some embodiments, a packaging structure is provided. The packaging structure includes a packaging substrate, a semiconductor chip, and an integrated device. The semiconductor chip is bonded to the upper surface of the packaging substrate via a plurality of first conductive structures between an upper surface of the packaging substrate and a lower surface of the semiconductor chip. The integrated device is bonded to the lower surface of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When reading the accompanying drawings of the specification, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that the various features are not necessarily drawn to scale. In fact, the size of the various features may be arbitrarily enlarged or reduced to make a clear description.

[0009] Figures 1A to 1E are cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0010] Figure 2 is a schematic top view of a package structure according to some embodiments.

[0011] Figure 3 is a cross-sectional view of a package structure according to some embodiments.

[0012] Figure 4 is a cross-sectional view of a package structure according to some embodiments.

[0013] Figure 5A is a cross-sectional view of a package structure according to some embodiments.

[0014] Figure 5B is a cross-sectional view of a package structure according to some embodiments.

[0015] Figure 6 is a cross-sectional view of a package structure according to some embodiments.

[0016] Figure 7 According to some embodiments Figure 1B Schematic cross-sectional view of the integrated device in.

[0017] Description of reference numerals:

[0018] 100: Carrier substrate

[0019] 102: Package substrate

[0020] 102A: Upper surface of package substrate

[0021] 104: Insulation layer

[0022] 106: Conductive characteristics

[0023] 108: Conductive element

[0024] 110: Semiconductor chips

[0025] 110A: Lower surface of semiconductor chip

[0026] 110B: Upper surface of semiconductor chip

[0027] 112: Conductive pad

[0028] 112A, 112B: Contact pad

[0029] 114: Integrated device

[0030] 114A: Contact pads or electrodes of integrated devices

[0031] 116,120: Conductive structure

[0032] 116A: Conductive connector

[0033] 116B,120B: Solder balls

[0034] 118: Bottom filling components

[0035] 120A: metal pillar

[0036] 122: Protective layer

[0037] 122A: Top surface of protective layer

[0038] 124: Conductive bump

[0039] 130: Groove

[0040] 130A: Bottom of the groove

[0041] 1140: Deep Trench Capacitors

[0042] 1141,1142: Electrode

[0043] 1140A: Substrate for deep trench capacitors

[0044] 1140B: Deep Groove

[0045] 1140C: Doped layer

[0046] 1140D: Dielectric layer

[0047] 1140E: Conductive layer

[0048] 1140F: First conductive contact

[0049] 1140G: Second conductive contact

[0050] D1: Direction

[0051] H,H1,H2: Height

[0052] W1, W2: Size DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments or examples to implement the different features of the present disclosure. The following describes embodiments of specific components and their arrangements to illustrate the present disclosure. Of course, these embodiments are only examples and should not be used to limit the scope of the present disclosure. For example, the specification describes a first feature formed on or above a second feature, which may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, repeated reference symbols and / or marks may be used in various examples of the present disclosure. This repetition is for the purpose of simplicity and clarity, and is not used to limit the specific relationship between the various embodiments and / or configurations discussed.

[0054] In addition, spatially relative terms such as "below," "beneath," "below," "above," "upper," and similar terms are used to facilitate describing the relationship between one element or feature and another element or feature in the figure. In addition to the orientation shown in the drawings, these spatially relative terms are intended to include different orientations of the device in use or operation. The device / apparatus may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0055] The term "substantially" in the specification, such as "substantially flat" or "substantially coplanar", etc., can be understood by those skilled in the art. In some embodiments, the adjective can be substantially removed. Where applicable, the term "substantially" may also include embodiments of "entirely", "completely", "all", etc. Where applicable, the term "substantially" may also relate to 90% or higher, such as 95% or higher, in particular 99% or higher, including 100%. In addition, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding minor deviations from a specific arrangement, and may, for example, include deviations of up to 10°. The term "substantially" does not exclude "completely", for example, a composition that is "substantially free" of Y may be completely free of Y.

[0056] Terms such as "about" used in conjunction with a specific distance or size should be interpreted as not excluding minor deviations from the specific distance or size and may include deviations of up to 10%, for example. The term "about" relative to a numerical value X may mean X ± 5 or 10%.

[0057] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during, and / or after the stages described in these embodiments. In different embodiments, some of the stages described may be replaced or eliminated. Additional features may be added to the semiconductor device structure. In different embodiments, some of the features described may be replaced or eliminated. Although some embodiments are discussed below with operations performed in a particular order, these operations may also be performed in other logical orders.

[0058] Some embodiments of the present disclosure may relate to 3D packages or 3D-IC devices. Other features and processes may also be included. For example, a test structure may be included to help perform verification testing on the 3D package or 3D-IC device. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3D-IC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with test methods for intermediate verification of known good dies to increase yield and reduce costs.

[0059] Figures 1A to 1E is a cross-sectional view of various stages of a process for forming a package structure according to some embodiments. Figure 1A As shown, according to some embodiments, a packaging substrate 102 is formed on a carrier substrate 100. The carrier substrate 100 may be a glass substrate, a semiconductor substrate or other suitable substrate. Figure 1E After the carrier substrate 100 is removed (as shown), the packaging substrate 102 may be used to provide electrical connections between a semiconductor device (to be described below) packaged in the packaging structure and an external electronic device.

[0060] The packaging substrate 102 may be used for routing. In some embodiments, the packaging substrate 102 is a redistribution substrate. In some alternative embodiments, the packaging substrate 102 is a build-up substrate including a core and build-up layers on both sides of the core. In the subsequent discussion of the embodiments of the present disclosure, a redistribution substrate is shown as an example of the packaging substrate 102, however, the teachings shown according to some example embodiments are easily applicable to the build-up substrate. Figure 1AAs shown, the package substrate 102 includes a plurality of laminated insulating layers 104 and a plurality of conductive features 106 surrounded by the insulating layers 104. The conductive features 106 may include conductive lines, conductive vias and / or conductive pads. In some embodiments, some conductive vias are stacked on each other. The upper conductive vias are substantially aligned with the lower conductive vias to have a shorter routing length. However, in some examples, some vias are staggered vias, which have a limited routing method. The upper conductive vias are not aligned with the lower conductive vias.

[0061] The insulating layer 104 may include or be made of one or more polymer materials. The polymer material may include polybenzoxazole (PBO), polyimide (PI), epoxy resin, one or more other suitable polymer materials, or a combination of the foregoing materials. In some embodiments, the polymer material is photosensitive. Therefore, a photolithography process may be used to form an opening having a desired pattern in the insulating layer 104.

[0062] In some other embodiments, part or all of the insulating layer 104 includes or is made of a dielectric material other than a polymer material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination of the foregoing materials.

[0063] Conductive features 106 may include conductive wires that provide electrical connections in the horizontal direction and conductive vias that provide electrical connections in the vertical direction. Conductive features 106 may include or be made of copper, aluminum, gold, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, or a combination of the foregoing materials. In some embodiments, conductive features 106 include multiple sublayers. For example, each conductive feature 106 includes multiple sublayers, including titanium / copper, titanium / nickel / copper, titanium / copper / titanium, aluminum / titanium / nickel / silver, other suitable multiple sublayers, or a combination of the foregoing sublayers.

[0064] The formation of the package substrate 102 may involve multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes.

[0065] Deposition or coating processes may be used to form the insulating layer and / or the conductive layer. The deposition or coating process may include a spin coating process, an electroplating process, an electroless process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, one or more other suitable processes, or a combination of the foregoing processes.

[0066] The patterning process may be used to pattern the formed insulating layer and / or the formed conductive layer. The patterning process may include a photolithography process, an energy beam drilling process (e.g., a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), an etching process, a mechanical drilling process, one or more other suitable processes, or a combination of the foregoing processes.

[0067] The planarization process may be used to provide a flat top surface for the formed insulating layer and / or the formed conductive layer to facilitate subsequent processes. The planarization process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process, one or more other suitable processes, or a combination of the foregoing processes.

[0068] like Figure 1A As shown, according to some embodiments, the package substrate 102 also includes a plurality of conductive elements 108 formed thereon. Each conductive element 108 may be exposed or protruded from the topmost surface of the insulating layer 104 and may be electrically connected to one of the conductive features 106. The conductive elements 108 may be used to electrically conduct, hold or receive a semiconductor chip, as will be described below.

[0069] The conductive element 108 may include or be made of copper, aluminum, gold, cobalt, titanium, tin, one or more other suitable materials, or a combination of the foregoing materials. The conductive element 108 may be formed using an electroplating process, an electroless plating process, a placement process, a printing process, a physical vapor deposition process, a chemical vapor deposition process, one or more other suitable processes, or a combination of the foregoing processes.

[0070] like Figure 1B As shown, according to some embodiments, one or more semiconductor chips 110 are provided above the package substrate 102 (in FIG. 1 ) (for simplicity, only one semiconductor chip 110 is shown). Figure 1BAs shown, each semiconductor chip 110 is a surface-mount device (SMD) and has a plurality of conductive pads 112 exposed on its surface. In some embodiments, the semiconductor chip 110 further has a passivation layer (not shown) covering the conductive pads 112, and a portion of each conductive pad 112 is exposed through a corresponding opening for electrical connection formed in the passivation layer. The conductive pad 112 may include or be made of copper, aluminum, gold, cobalt, titanium, tin, one or more other suitable conductive materials, or a combination of the foregoing materials. The semiconductor chip 110 may be mounted on or bonded to the package substrate 102 using a flip-chip bonding method, which will be described below.

[0071] Each semiconductor chip 110 is a functional integrated circuit chip. Depending on actual needs, the semiconductor chip 110 may include one or more application processors, logic circuits, memory devices, power management integrated circuits, analog circuits, digital circuits, mixed signal circuits, one or more other suitable functional integrated circuits, or a combination of the foregoing integrated circuits.

[0072] In some embodiments, one or more integrated devices 114 are integrated with each semiconductor chip 110. Figure 1B Only one integrated device 114 is described below as being integrated with one semiconductor chip 110. However, the teachings shown according to some exemplary embodiments are also applicable to an example in which multiple integrated devices 114 are integrated with each semiconductor chip 110. In some embodiments, the integrated device 114 and the corresponding semiconductor chip 110 are different types of semiconductor devices. For example, the integrated device 114 may be a passive device including one or more passive elements, and the passive elements may be, for example, resistors, capacitors, inductors, etc., or a combination of the aforementioned passive elements. In some embodiments, the integrated device 114 includes at least one deep trench capacitor 1140, whose structure is Figure 7. The deep trench capacitor 1140 may include a substrate 1140A and a plurality of deep trenches 1140B extending from the top surface of the substrate 1140A to the interior of the substrate 1140A. The deep trench capacitor 1140 also includes a doped layer 1140C formed in the substrate 1140A and surrounding the deep trenches 1140B. A dielectric layer 1140D conformably covers the sidewalls and bottom wall of each deep trench 1140B, and a portion of the dielectric layer 1140D extends to the top surface of the deep trench capacitor 1140. A conductive layer 1140E is disposed above the dielectric layer 1140D, and a portion of the conductive layer 1140E extends to the deep trench 1140B covered by the dielectric layer 1140D. A first conductive contact 1140F is disposed above the conductive layer 1140E and electrically connected to the conductive layer 1140E, and a second conductive contact 1140G is disposed on the top surface of the deep trench capacitor 1140 and electrically connected to the doped layer 1140C. However, the embodiments of the present disclosure are not limited to the aforementioned structure, and integrated devices 114 of other structures may also be applicable.

[0073] In some embodiments, the integrated device 114 may be an active device including one or more active elements, and the active element may be, for example, a diode, a transistor, etc., or a combination of the foregoing active elements. In some embodiments, the integrated device 114 may include a semiconductor die having only metal wiring (i.e., without a functional semiconductor chip, active or passive device, or module).

[0074] As other embodiments, the integrated device 114 and the corresponding semiconductor chip 110 may be functional chips of different types. For example, in some examples, the semiconductor chip 110 is an application processor, and the integrated device 114 is a memory device. In some embodiments, when viewed from above, the size (i.e., area) of the integrated device 114 is smaller than the size (i.e., area) of the corresponding semiconductor chip 110, which will be described below.

[0075] In some embodiments, Figure 1B As shown, the integrated device 114 is bonded to the conductive pad 112 of the semiconductor chip 110 via the conductive structure 116. The conductive structure 116 may be formed on one surface of the integrated device 114 and electrically connected to an exposed pad region or electrode (e.g., such as Figure 5A , Figure 5B , Figure 6). Conductive structures 116 may be used to electrically connect the integrated device 114 to the semiconductor chip 110. The conductive structures 116 may include conductive pillars, solder balls, controlled collapse chip connection (C4) bumps, micro bumps, one or more other suitable bonding structures, or a combination of the foregoing bonding structures.

[0076] The conductive structure 116 may include or be made of a metal material, such as copper, aluminum, gold, nickel, silver, palladium, etc., or a combination of the foregoing metal materials. The conductive structure 116 may be formed using an electroplating process, a chemical plating process, a placement process, a printing process, a physical vapor deposition process, a chemical vapor deposition process, a photolithography process, one or more other suitable processes, or a combination of the foregoing processes.

[0077] In some other embodiments, the conductive structure 116 may be made of a tin-containing material. The tin-containing material may further include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination of the foregoing materials. In some other embodiments, the conductive structure 116 is lead-free. In addition, in order to shape the tin-containing material into a desired bump or spherical shape, a reflow process may be performed.

[0078] In some embodiments, Figure 1B As shown, a bottom filling (underfill) element 118 is further formed to surround and protect the conductive structure 116 and enhance the connection between the integrated device 114 and the semiconductor chip 110. The bottom filling element 118 may include or be made of an insulating material, such as a bottom filling material. The bottom filling material may include epoxy resin, resin, filler material, stress release agent (SRA), adhesion promoter, other suitable materials or a combination of the foregoing materials. In some embodiments, a liquid bottom filling material is dispersed in the gap between the integrated device 114 and the semiconductor chip 110 to strengthen the conductive structure 116 and the overall strength of the package structure. After the aforementioned dispersion operation, the bottom filling material is cured to form the bottom filling element 118. The bottom filling element 118 can also provide a heat conduction path for the package structure. In this embodiment, the bottom filling element 118 fills the entire gap between the integrated device 114 and the semiconductor chip 110 and covers the entire lower surface of the integrated device 114. In some other embodiments, the underfill element 118 is not formed, or the underfill element 118 only covers a portion of the lower surface of the integrated device 114 .

[0079] like Figure 1C As shown, according to some embodiments, Figure 1B1 is inverted and disposed above the packaging substrate 102. In some embodiments, after the semiconductor chip 110 is internally connected to the integrated device 114, the semiconductor chip 110 is placed on the packaging substrate 102 so that the lower surface 110A of the semiconductor chip 110 (with the integrated device 114 mounted thereon) faces and is substantially parallel to the upper surface 102A of the packaging substrate 102. Thereafter, the semiconductor chip 110 is bonded to the conductive element 108 above the packaging substrate 102 via the conductive structure 120 between the conductive element 108 and some contact pads 112 of the semiconductor chip 110 that are not yet coupled to the integrated device 114. In some other embodiments, the conductive element 108 is not formed, and the semiconductor chip 110 is bonded to the exposed pad area (constituted by some conductive features 106) of the packaging substrate 102 via the conductive structure 120.

[0080] The conductive structure 120 may include a conductive column, a solder ball, a C4 bump, a micro bump, one or more other suitable bonding structures, or a combination of the foregoing bonding structures. In some embodiments, the material and the formation method of the conductive structure 120 may be the same as or similar to Figure 1B In some embodiments, the conductive structure 120 is different from the conductive structure 116 in terms of scheme, size, height, material, or a combination of the foregoing properties. Figure 5A Described in the content.

[0081] In some embodiments, the semiconductor chip 110 and the package substrate 102 are pressed against each other at high temperature. Therefore, the semiconductor chip 110 is bonded to the package substrate 102 via the conductive structure 120. In some embodiments, a thermal compression process is used to achieve the above bonding process.

[0082] like Figure 1C As shown, according to some embodiments, after the semiconductor chip 110 is mounted on the package substrate 102 and connected to the package substrate 102 using the flip chip bonding method described above, the conductive structure 120 is located next to the integrated device 114. In some embodiments, the integrated device 114 is separated from the upper surface 102A of the package substrate 102 by a gap (e.g., see Figure 1C ) separated by . Figure 1C The spacing (eg, height) in direction D1 shown in FIG. 1 may be greater than about 20 micrometers, but the disclosure is not limited thereto. In some embodiments, integrated device 114 may directly contact upper surface 102A. In some embodiments, conductive structure 120 surrounds or encircles integrated device 114.

[0083] In some embodiments, Figure 1C As shown, (also see Figure 2, wherein the integrated devices 114 below the semiconductor chip 110 are shown in dotted lines), each integrated device 114 is located below the corresponding semiconductor chip 110. For example, each integrated device 114 is located below the corresponding semiconductor chip 110, and when viewed from above (for example, when viewed from a direction D1 that is substantially perpendicular to the lower surface 110A of the semiconductor chip 110), each integrated device 114 does not exceed the boundary or projection of the corresponding semiconductor chip 110 (that is, the semiconductor chip 110 extends across the edge of the integrated device 114).

[0084] like Figure 1D As shown, according to some embodiments, a protective layer 122 is formed to surround and protect the semiconductor chip 110. In some embodiments, the protective layer 122 also surrounds and protects the conductive structure 120. Figure 1D As shown, a portion of the protective layer 122 is between the lower surface 110A of the semiconductor chip 110 and the upper surface 102A of the package substrate 120, and another portion of the protective layer 122 is between the integrated device 114 and the upper surface 102A of the package substrate 102 (that is, filling the gap between the integrated device 114 and the package substrate 102). The portion of the protective layer 122 formed between the integrated device 114 and the package substrate 102 helps to provide a thermal path for the integrated device 114 (that is, the heat generated by operating the integrated device 114 can be dissipated through the protective layer 122). In some embodiments, the protective layer 122 is separated from the conductive structure 116 under the corresponding semiconductor chip 110 by the bottom filling element 118. However, the embodiments of the present disclosure are not limited thereto. Many changes and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, the bottom filling element 118 is not formed. In these cases, the protective layer 122 may directly contact the conductive structure 116 under the corresponding semiconductor chip 110.

[0085] In some embodiments, the protective layer 122 includes or is made of an insulating material, such as a molding material. The molding material may include a polymer material, such as an epoxy resin in which a filler is dispersed. In some embodiments, the molding material (e.g., a liquid molding material) is dispensed onto the top surface 102A of the package substrate 102 and / or above the semiconductor chip 110. Thereafter, in some embodiments, a thermal process is used to cure the liquid molding material and convert it into the protective layer 122.

[0086] In some embodiments, a planarization process is performed on the protective layer 122 to partially remove the protective layer 122. Figure 1DAs shown, the upper surface 110B of each semiconductor chip 110 is exposed (that is, the upper surface 110B of each semiconductor chip 110 is substantially flush with the top surface 122A of the protection layer 122). The planarization process may include a grinding process, a chemical mechanical grinding process, an etching process, a dry grinding process, one or more other suitable processes, or a combination of the foregoing processes.

[0087] Afterwards, if Figure 1E As shown, according to some embodiments, the carrier substrate 100 is removed to expose the surface of the package substrate 102. In some embodiments, before forming the package substrate 102, a release film (not shown) is first formed on the carrier substrate 100. The release film is a temporary bonding material that facilitates the separation operation between the carrier substrate 100 and the package substrate 102.

[0088] Then, in some embodiments, as Figure 1E As shown, a plurality of conductive bumps 124 are formed above the surface of the package substrate 102 that was originally covered by the carrier substrate 100. Each conductive bump 124 can be electrically connected to one of the conductive features 106 of the package substrate 102. The conductive bumps 124 enable the package structure to be electrically connected to an external device (not shown). The conductive bumps 124 may include or be solder bumps, for example, tin-containing solder bumps. The tin-containing solder bumps may further include copper, silver, gold, aluminum, lead, one or more other suitable materials, or a combination of the foregoing materials. In some embodiments, the tin-containing solder bumps are lead-free.

[0089] In some embodiments, after removing the carrier substrate 100, a solder ball (or solder element) is disposed on the exposed conductive feature 106. Thereafter, a reflow process is performed to melt the solder ball into a conductive bump 124. In some other embodiments, before disposing the solder ball, an under bump metallization (UBM) element is formed above the exposed conductive feature 106. In some other embodiments, a solder element is electroplated onto the exposed conductive feature 106. Thereafter, a reflow process is used to melt the solder element to form the conductive bump 124.

[0090] Afterwards, in some embodiments, a singulation process is performed. Thus, a plurality of separated package structures are formed. Figure 1E In FIG. 1 , one of the packaging structures is shown. Figure 1EAs shown, the integrated device 114 is integrated with the semiconductor chip 110 and bonded to the semiconductor chip 110. Therefore, the semiconductor chip 110 and the integrated device 114 can communicate with each other directly without other components (e.g., the package substrate 102). Therefore, since the wiring length is reduced, the signal integration and power integration of the package structure are improved.

[0091] In addition, Figure 2 As shown, since the smaller integrated device 114 can be integrated under the corresponding semiconductor chip 110 without occupying the installation space above the package substrate 102, the size of the package substrate 102 and the overall size of the package structure can be further reduced.

[0092] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 3 is a cross-sectional view of a packaging structure according to some embodiments. It should be understood that Figure 3 Most of the structures in are equivalent to Figure 2 Most of the structures in , so only the differences are described here. Figure 3 As shown, according to some embodiments, a groove 130 is further formed on the upper surface 102A of the package substrate 102. The groove 130 may have an appropriate depth (for example, about 10 microns to 30 microns in some examples, but the embodiments of the present disclosure are not limited thereto) in a direction D1 substantially perpendicular to the upper surface 102A of the package substrate 102 to accommodate the integrated device 114 integrated under the semiconductor chip 110. Moreover, the groove 130 may have a shape and size (for example, area) corresponding to the received integrated device 114 in a portion perpendicular to the direction D1 to allow the integrated device 114 to enter.

[0093] In some embodiments, Figure 3 As shown, a portion of the integrated device 114 extends into the recess 130, and the bottom of the integrated device 114 is separated from the bottom 130A of the recess 130 by a gap. The gap (e.g., height) in the direction D1 may be greater than about 20 microns, but the present disclosure is not limited thereto. In some embodiments, a portion of the protective layer 122 is between the integrated device 114 and the bottom surface 130A of the recess 130 (i.e., fills the gap between the integrated device 114 and the bottom surface 130A) to provide an additional thermal path for the integrated device 114.

[0094] In some other embodiments, the package substrate 102 may have two or more recesses 130 depending on the number of integrated devices 114. For example, one recess 130 may receive one integrated device 114. However, in some examples, more than one integrated device 114 may be received in one recess 130.

[0095] In some embodiments, the groove 130 is formed before the semiconductor chip 110 and the integrated device 114 are placed on the package substrate 102. A wet etching process, a dry etching process, an energy beam drilling process (e.g., a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), a mechanical drilling process, one or more other applicable processes, or a combination of the foregoing processes may be used to form the groove 130. The sidewall of the formed groove 130 may be perpendicular to the upper surface 102A of the package substrate 102 or inclined relative to the upper surface 102A of the package substrate 102.

[0096] exist Figure 3 In the embodiment, the recess 130 is formed on the package substrate 102 to accommodate the integrated device 114, and thus the height H of the conductive structure 120 in the direction D1 is smaller than the height that the conductive structure 120 may have in the direction D1 when the package substrate 102 without the recess is used. This is because the height H of the conductive structure 120 in the direction D1 no longer needs to be greater than the thickness of the integrated device 114 in the direction D1. Therefore, a thinner package structure as a whole can be obtained.

[0097] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 4 is a cross-sectional view of a packaging structure according to some embodiments. It should be understood that Figure 4 Most of the structures in are equivalent to Figure 3 Most of the structures in , so only the differences are described here. Figure 4 As shown, a portion of the integrated device 114 extends into the recess 130 of the package substrate 102, and the integrated device 114 is further electrically connected to the package substrate 102 via a conductive structure 140 between the integrated device 114 and a pad region (composed by some conductive features 106) exposed at the bottom surface 130A of the recess 130. After the integrated semiconductor chip 110 and the integrated device 114 are stacked on the package substrate 102, the conductive structure 140 enables the integrated device 114 and / or the semiconductor chip 110 to be electrically connected to the package substrate 102.

[0098] In some embodiments, before stacking the semiconductor chip 110 on top of the packaging substrate 102, a conductive structure 140 is formed on a surface of the integrated device 114 opposite to the conductive structure 116, and the conductive structure 140 is electrically connected to an exposed pad area or electrode of the integrated device 114. The conductive structure 140 is also electrically connected to an internal circuit of the integrated device 114. For example, a plurality of conductive vias may be formed in the integrated device 114 and pass through the integrated device 114 to connect the conductive structure 116 on the opposite surface of the integrated device 114 with the conductive structure 140. The conductive structure 140 may include a conductive column, a solder ball, a C4 bump, a micro bump, one or more other suitable bonding structures, or a combination of the foregoing bonding structures. In some embodiments, the material and formation method of the conductive structure 140 may be the same as or similar to. Figure 1B 1. In some embodiments, the conductive structure 140 is different from the conductive structure 120 in style, size, height, material, or a combination of the foregoing properties, but is similar to the conductive structure 116, which will be described below.

[0099] In some embodiments, the protective layer 122 is formed to also surround and protect the conductive structure 140 below the integrated device 114. Figure 4 As shown, a portion of the protective layer 122 is between the integrated device 114 and the bottom surface 130A of the cavity 130. The portion of the protective layer 122 between the integrated device 114 and the bottom surface 130A of the cavity 130 may also help provide a thermal path for the integrated device 114.

[0100] exist Figure 4 In the embodiment, the integrated device 114 integrated with the semiconductor chip 110 is also electrically connected to the packaging substrate 102 below, thereby providing additional wiring of the semiconductor chip 110 (in addition to the conductive structure 120) to connect the semiconductor chip 110 to the packaging substrate 102. Therefore, the overall electrical performance of the packaging structure is further improved.

[0101] Figure 5A is a cross-sectional view of a package structure according to some embodiments. In some embodiments, Figure 5A 1 is an enlarged view showing the packaging structure near the integrated device 114. Figure 5AAs shown, in some embodiments, the package structure includes two integrated devices 114 of different thicknesses (in the direction D1) integrated below the semiconductor chip 110 (that is, at the lower surface 110A of the semiconductor chip 110 facing the package substrate 102). One of the integrated devices 114 is separated from the upper surface 102A of the package substrate 102 by a gap (for example, greater than about 20 microns), and the other integrated device 114 extends to the groove 130 of the package substrate 102 and is separated from the bottom surface 130A of the groove 130 by a gap (for example, greater than about 20 microns). However, the embodiments of the present disclosure are not limited thereto, and in some other embodiments, at least one of the integrated devices 114 may directly contact the semiconductor substrate 102.

[0102] like Figure 5A As shown, in some embodiments, the package structure also includes a conductive structure 120 and a conductive structure 116. The conductive structure 120 is used to connect the semiconductor chip 110 to the package substrate 102, and the conductive structure 116 is used to connect the semiconductor chip 110 to the integrated device 114. The material and formation method of the conductive structure 120 can be the same as or similar to Figure 1C The conductive structure 120 shown in FIG. The material and the formation method of the conductive structure 116 may be equal to or similar to Figure 1B The conductive structure 116 is shown in FIG.

[0103] According to some embodiments, the conductive structure 120 and the conductive structure 116 have different styles and / or materials. Figure 5AAs shown, in some embodiments, each conductive structure 120 includes a metal pillar 120A (also called a C4 bump) made of a metal material (e.g., copper, gold, etc., or an alloy of copper and gold) and a solder ball 120B, and each conductive structure 116 includes a conductive connector 116A made of a metal material different from or equal to the metal pillar 120A (e.g., copper, gold, etc., or an alloy of copper and gold) and a solder ball 116B. In some embodiments, the metal pillar 120A is bonded to one of the contact pads 112A of the semiconductor chip 110, and the solder ball 120B is formed between the metal pillar 120A and one of the conductive elements 108 above the package substrate 102. The conductive connector 116A is formed on one of the contact pads 112B of the semiconductor chip 110, and the solder ball 116B is formed between the conductive connector 116A and one of the contact pads or electrodes 114A of the integrated device 114. In some other embodiments, before providing the conductive structure 120, an under bump metallization element is formed over the contact pads 112A of the semiconductor chip 110. In some other embodiments, the conductive connectors 116A are omitted, and solder balls 116B are formed between some of the contact pads 112B of the semiconductor chip 110 and corresponding contact pads or electrodes 114A of the integrated device 114.

[0104] In addition, according to some embodiments, the conductive structure 120 and the conductive structure 116 have different sizes and / or heights. Figure 5A In some embodiments shown, the height H1 of each conductive structure 120 in the direction D1 (e.g., about 70 to 120 microns) is greater than the height H2 of each conductive structure 116 in the direction D1 (e.g., about 10 to 30 microns). Additionally or alternatively, the dimension W1 (e.g., area) of each conductive structure 120 in a portion perpendicular to the direction D1 is greater than the dimension W2 (e.g., area) of each conductive structure 116 in a portion perpendicular to the direction D1. In some embodiments, as Figure 5A As shown, the size of each contact pad 112A of the semiconductor chip 110 for the conductive structure 120 is also larger than that of each contact pad 112B for the conductive structure 116 .

[0105] It should be understood that the materials, structures and geometric properties of the conductive structures 120 and 116 are merely illustrative and are not intended to limit the present disclosure and should not be interpreted as limiting the present disclosure. Many changes and modifications are obvious to those skilled in the art once the present disclosure is understood.

[0106] In some embodiments, Figure 5BAs shown, as described above, protection layer 122 may be formed to surround and protect semiconductor chip 110, and underfill element 118 may be optionally formed to surround and protect conductive structure 116. A portion of protection layer 122 may be formed between integrated device 114 and bottom surface 130A of recess 130.

[0107] Figure 6 is a cross-sectional view of a package structure according to some embodiments. In some embodiments, Figure 6 is an enlarged view showing the packaging structure of the integrated device 114, which can be applied to FIG. 1 to FIG. Figure 4 , Figure 5A , Figure 5B Examples of Figure 6 As shown, in some embodiments, the integrated device 114 includes an electrode 1141 and an electrode 1142. In some embodiments, as Figure 6 As shown, the cross-sectional view of the electrode 1141 and the electrode 1142 has a C-shaped profile. The electrode 1141 and the electrode 1142 can be bonded to (e.g., soldered or directly contacted) the contact pad 112 of the semiconductor chip 110. In some embodiments, an underfill element 118 is formed to surround and protect the connection between the electrode 1141 and the electrode 1142 and the contact pad 112. In some embodiments, the electrode 1141 and the electrode 1142 can have other profiles, for example, a rectangular shape.

[0108] The embodiments of the present disclosure form a packaging structure, which includes a packaging substrate, a semiconductor chip above the packaging substrate, and at least one integrated device integrated with the semiconductor chip. The integrated device is integrated directly below the semiconductor chip to facilitate signal transmission. Therefore, the signal integration and power integration of the packaging structure are improved. In addition, the integrated device does not need to occupy the installation space above the packaging substrate, which means that the size of the packaging substrate and the overall size of the packaging structure can be reduced.

[0109] According to some embodiments, a packaging structure is provided. The packaging structure includes a packaging substrate, a semiconductor chip, and an integrated device. The semiconductor chip is disposed above the packaging substrate and has a lower surface facing the packaging substrate. The integrated device is disposed between the packaging substrate and the semiconductor chip and bonded to the lower surface of the semiconductor chip.

[0110] In some embodiments, the integrated device is located below the semiconductor chip, and when viewed from a direction perpendicular to the lower surface of the semiconductor chip, the integrated device is located within the boundary of the semiconductor chip. In some embodiments, the integrated device is electrically connected to the semiconductor chip via a plurality of conductive structures between the lower surface of the semiconductor chip and the integrated device. In some embodiments, the package structure further comprises a bottom filling element, the bottom filling element being configured to surround the conductive structure, wherein a portion of the bottom filling element is between the lower surface of the semiconductor chip and the integrated device. In some embodiments, the semiconductor chip is electrically connected to the package substrate via a plurality of conductive structures between the lower surface of the semiconductor chip and the package substrate, wherein the conductive structure surrounds the integrated device. In some embodiments, the integrated device is separated from an upper surface of the package substrate by a spacing. In some embodiments, the package substrate has an upper surface facing the lower surface of the semiconductor chip and a groove formed on the upper surface, wherein the groove is configured to accommodate the integrated device. In some embodiments, the integrated device is an integrated passive device. In some embodiments, the integrated device extends into the groove, and the integrated device is electrically connected to the package substrate at a bottom surface of the groove. In some embodiments, the integrated device and the semiconductor chip are different types of semiconductor devices.

[0111] According to some embodiments, a method for forming a package structure is provided. The method includes bonding an integrated device to a semiconductor chip. The method also includes arranging the semiconductor chip having the integrated device above a package substrate, such that the integrated device is between a lower surface of the semiconductor chip and an upper surface of the package substrate.

[0112] In some embodiments, the integrated device is bonded to the lower surface of the semiconductor chip via a plurality of conductive structures, wherein before the semiconductor chip with the integrated device is disposed above the packaging substrate, the method for forming the packaging structure further comprises forming a bottom filling element to surround the conductive structure. In some embodiments, after the semiconductor chip with the integrated device is disposed above the packaging substrate, the integrated device is separated from the upper surface of the packaging substrate by a spacing. In some embodiments, before the semiconductor chip with the integrated device is disposed above the packaging substrate, the method for forming the packaging structure further comprises forming a groove on the upper surface of the packaging substrate to accommodate the integrated device. In some embodiments, after the semiconductor chip with the integrated device is disposed above the packaging substrate, the method for forming the packaging structure further comprises electrically connecting the integrated device to the packaging substrate at a bottom surface of the groove via a plurality of conductive structures between the integrated device and the bottom surface of the groove.

[0113] According to some embodiments, a packaging structure is provided. The packaging structure includes a packaging substrate, a semiconductor chip, and an integrated device. The semiconductor chip is bonded to the upper surface of the packaging substrate via a plurality of first conductive structures between an upper surface of the packaging substrate and a lower surface of the semiconductor chip. The integrated device is bonded to the lower surface of the semiconductor chip.

[0114] In some embodiments, the integrated device is bonded to the lower surface of the semiconductor chip via a plurality of second conductive structures between the lower surface of the semiconductor chip and the integrated device. In some embodiments, the style, size, height, material, or a combination of the foregoing properties of the second conductive structure is different from the style, size, height, material, or a combination of the foregoing properties of the first conductive structure. In some embodiments, the package structure further comprises a protective layer, the protective layer being configured to surround the first conductive structure and the integrated device, wherein a portion of the protective layer is between the lower surface of the semiconductor chip and the upper surface of the package substrate, and another portion of the protective layer is between the integrated device and the upper surface of the package substrate. In some embodiments, the integrated device is located directly below the semiconductor chip, and when viewed from a direction perpendicular to the lower surface of the semiconductor chip, the integrated device is located within the boundary of the semiconductor chip.

[0115] The features of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present disclosure. It should be understood by those skilled in the art that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent configurations do not depart from the concept and scope of the present disclosure, and that various changes, substitutions and modifications may be made to the present disclosure without departing from the concept and scope of the present disclosure.

Claims

1. A packaging structure, comprising: a packaging substrate; A semiconductor chip is disposed above the packaging substrate, wherein the semiconductor chip has a lower surface facing the packaging substrate; as well as an integrated device disposed between the package substrate and the semiconductor chip and bonded to the lower surface of the semiconductor chip; wherein the package substrate has an upper surface facing the lower surface of the semiconductor chip and a groove formed on the upper surface of the package substrate, the groove being configured to accommodate the integrated device; The groove has a bottom surface, the integrated device extends into the groove, and the bottom of the integrated device and the bottom surface of the groove are separated by a distance. 2 . The package structure of claim 1 , wherein the integrated device is located below the semiconductor chip, and when viewed from a direction perpendicular to the lower surface of the semiconductor chip, the integrated device is located within a boundary of the semiconductor chip. 3 . The package structure of claim 1 , wherein the integrated device is electrically connected to the semiconductor chip via a plurality of conductive structures between the lower surface of the semiconductor chip and the integrated device. 4 . The package structure of claim 3 , further comprising an underfill element configured to surround the plurality of conductive structures, wherein a portion of the underfill element is between the lower surface of the semiconductor chip and the integrated device. 5 . The package structure of claim 1 , wherein the semiconductor chip is electrically connected to the package substrate via a plurality of conductive structures between the lower surface of the semiconductor chip and the package substrate, wherein the plurality of conductive structures surround the integrated device. 6 . The package structure of claim 1 , wherein the integrated device and the upper surface of the package substrate are separated by a gap. The package structure of claim 1 , wherein the integrated device is an integrated passive device. 8 . The package structure of claim 1 , wherein the integrated device is electrically connected to the package substrate at the bottom surface of the recess.

9. The package structure of claim 1, wherein the integrated device and the semiconductor chip are different types of semiconductor devices.

10. A method for forming a packaging structure, comprising: bonding an integrated device to a semiconductor chip; Disposing the semiconductor chip having the integrated device above a packaging substrate so that the integrated device is between a lower surface of the semiconductor chip and an upper surface of the packaging substrate; as well as Before placing the semiconductor chip with the integrated device on the packaging substrate, forming a groove on the upper surface of the packaging substrate to accommodate the integrated device; The groove has a bottom surface, the integrated device extends into the groove, and the bottom of the integrated device and the bottom surface of the groove are separated by a distance.

11. A method for forming a packaging structure as claimed in claim 10, wherein the integrated device is bonded to the lower surface of the semiconductor chip via a plurality of conductive structures, and wherein before the semiconductor chip having the integrated device is disposed above the packaging substrate, the method for forming a packaging structure further comprises forming a bottom filling element to surround the plurality of conductive structures. 12 . The method for forming a package structure according to claim 10 , wherein after the semiconductor chip having the integrated device is disposed above the package substrate, the integrated device is separated from the upper surface of the package substrate by a gap.

13. A method for forming a packaging structure as claimed in claim 10, wherein after the semiconductor chip having the integrated device is disposed above the packaging substrate, the method for forming the packaging structure further comprises electrically connecting the integrated device to the packaging substrate at the bottom surface of the groove via a plurality of conductive structures between the integrated device and the bottom surface of the groove.

14. A packaging structure, comprising: a packaging substrate; a semiconductor chip bonded to an upper surface of the packaging substrate via a plurality of first conductive structures between an upper surface of the packaging substrate and a lower surface of the semiconductor chip; and an integrated device bonded to the lower surface of the semiconductor chip; wherein the packaging substrate has a groove formed on the upper surface of the packaging substrate, the groove being configured to accommodate the integrated device; The groove has a bottom surface, the integrated device extends into the groove, and the bottom of the integrated device and the bottom surface of the groove are separated by a distance. 15 . The package structure of claim 14 , wherein the integrated device is bonded to the lower surface of the semiconductor chip via a plurality of second conductive structures between the lower surface of the semiconductor chip and the integrated device. 16 . The package structure of claim 15 , wherein the pattern, size, height, material, or a combination of the foregoing properties of the plurality of second conductive structures are different from the pattern, size, height, material, or a combination of the foregoing properties of the plurality of first conductive structures.

17. The packaging structure as claimed in claim 14, further comprising a protective layer configured to surround the multiple first conductive structures and the integrated device, wherein a portion of the protective layer is between the lower surface of the semiconductor chip and the upper surface of the packaging substrate, and another portion of the protective layer is between the integrated device and the upper surface of the packaging substrate. 18 . The package structure of claim 14 , wherein the integrated device is located directly below the semiconductor chip, and when viewed from a direction perpendicular to the lower surface of the semiconductor chip, the integrated device is located within a boundary of the semiconductor chip.

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