Optical semiconductor device and carrier

Abstract

An optical semiconductor device and a carrier are disclosed. The optical semiconductor device includes a semiconductor laser chip, an insulating substrate, a ground pattern, a mounting pattern, a resistor, and an extended ground pattern. The insulating substrate has a surface on which the semiconductor laser chip is mounted. The ground pattern and the mounting pattern are arranged on the surface. The mounting pattern has an opposite side opposite to the ground pattern. The resistor is arranged so that the side edge of the resistor is separated from the extended area of ​​the opposite side. The extended ground pattern is positioned in the extended area of ​​the opposite side and is electrically connected to the ground pattern. A capacitor is arranged on the mounting pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-152028, filed on August 22, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an optical semiconductor device and a carrier. Background Art

[0004] JPH05-251939A discloses a coplanar waveguide in which ground patterns as a structure for transmitting a high-frequency signal are provided on both sides of one signal line. Summary of the invention

[0005] The present disclosure provides an optical semiconductor device. The optical semiconductor device includes a semiconductor laser chip, an insulating substrate, a ground pattern, a mounting pattern, a resistor, an extended ground pattern and a capacitor. The insulating substrate has a surface on which the semiconductor laser chip is mounted. The ground pattern and the mounting pattern are arranged on the surface. The mounting pattern has an opposite side opposite to the ground pattern. The resistor is arranged so that the side edge of the resistor is separated from the extended area of ​​the opposite side. The extended ground pattern is positioned in the extended area of ​​the opposite side and is electrically connected to the ground pattern. The capacitor is arranged on the mounting pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The foregoing and other objects, aspects and advantages will be better understood through the following detailed description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0007] Figure 1 is a plan view showing the configuration of an optical semiconductor device according to an embodiment of the present disclosure;

[0008] Figure 2 It means in Figure 1 A plan view of a configuration in which one bonding wire is omitted in the optical semiconductor device shown;

[0009] Figure 3 Yes means including Figure 1 A plan view of a configuration example of an optical transmitter of an optical semiconductor device shown;

[0010] Figure 4 S of the embodiment and the comparative example are shown. 21 A graph of the simulation results of the characteristics;

[0011] Figure 5A is a diagram showing an equivalent circuit in the vicinity of a capacitor of an optical semiconductor device of a comparative example; and Figure 5Bis a diagram showing an equivalent circuit in the vicinity of a capacitor of an optical semiconductor device of an embodiment;

[0012] Figure 6 is a plan view showing an optical semiconductor device according to a modification;

[0013] Figure 7 is a plan view showing an optical semiconductor device according to a modification;

[0014] Figure 8 is a diagram showing the S of Modification Example 1 21 A graph of the simulation results of the characteristics;

[0015] Fig. 9 is a plan view showing an optical semiconductor device according to Modification 2; and

[0016] Fig.10 is a plan view showing an optical semiconductor device according to a comparative example. DETAILED DESCRIPTION

[0017] [Problems to be Solved by the Present Disclosure]

[0018] A semiconductor laser chip can be mounted on the surface of an insulating substrate in an optical transmitter of an optical communication system. A high-frequency drive signal is provided to the semiconductor laser chip via a transmission line such as a coplanar line arranged on the surface of the insulating substrate. In recent years, as the capacity of the optical communication system increases, the frequency of the drive signal has further increased. Therefore, the optical transmitter is required to have stable characteristics over a wide frequency band, and in particular, the electro-optical conversion characteristics (EO characteristics) are required to have flat characteristics with few discontinuities over a wide frequency band.

[0019] [Effects of the present disclosure]

[0020] According to one aspect of the present disclosure, discontinuities may be reduced so that EO characteristics may be closer to being flatter.

[0021] [Description of Embodiments of the Present Disclosure]

[0022] Embodiments of the present disclosure will be listed and described. An optical semiconductor device according to an embodiment of the present disclosure includes: a semiconductor laser chip, an insulating substrate, a ground pattern, a mounting pattern, a resistor, an extended ground pattern, and a capacitor. The insulating substrate has a surface on which the semiconductor laser chip is mounted. The ground pattern and the mounting pattern are arranged on the surface. The mounting pattern has an opposite side opposite to the ground pattern. The resistor is arranged so that the side edge of the resistor is separated from the extended area of ​​the opposite side. The extended ground pattern is positioned in the extended area of ​​the opposite side and is electrically connected to the ground pattern. The capacitor is arranged on the mounting pattern.

[0023] As an embodiment, the extended ground pattern may be a pair of extended ground patterns, and the pair of extended ground patterns may sandwich the resistor therebetween. The optical semiconductor device may further include bonding wires connecting the pair of extended ground patterns positioned on both sides of the resistor to each other. In the optical semiconductor device, a protrusion having a width narrower than that of the ground pattern may be arranged between the ground pattern and the resistor. In the optical semiconductor device, one end of the resistor may be electrically connected to the mounting pattern, and the other end of the resistor may be electrically connected to the protrusion extending from the ground pattern. The protrusion has a width narrower than that of the mounting pattern.

[0024] An optical semiconductor device according to an embodiment of the present disclosure includes: a semiconductor laser chip, an insulating substrate, a ground pattern, a ground pattern, a resistor, and a capacitor. The insulating substrate has a surface on which the semiconductor laser chip is mounted. The ground pattern and the mounting pattern are arranged on the surface. The mounting pattern includes a main area and a protrusion having a width narrower than the main area. The protrusion has a side edge, and the side edge is on the extension of the opposite side of the main area opposite to the ground pattern. The resistor is arranged on the extension of the protrusion, wherein the side of the resistor is opposite to the ground pattern. The capacitor is arranged on the main area of ​​the mounting pattern.

[0025] As one embodiment, the optical semiconductor device may further include an extended ground pattern arranged to be opposite to the ground pattern so as to sandwich the protrusion and the resistor therebetween. The extended ground pattern may be electrically connected to the ground pattern.

[0026] A carrier according to an embodiment of the present disclosure includes: an insulating substrate having a surface configured to mount a semiconductor laser chip thereon; a ground pattern disposed on the surface; a mounting pattern disposed on the surface, the mounting pattern having an upper surface configured to arrange a capacitor thereon and an opposite side opposite to the ground pattern; an area configured to arrange a resistor connected to the mounting pattern thereon; and an extended ground pattern positioned on an extended area on the opposite side, the extended ground pattern being electrically connected to the ground pattern.

[0027] As an embodiment, the extended ground pattern of the carrier may be a pair of extended ground patterns, and the pair of extended ground patterns may sandwich the region, wherein the resistor is arranged therebetween. In the carrier, an extension portion having a width narrower than that of the mounting pattern may be arranged between the mounting pattern and the region, wherein the resistor is arranged in the region.

[0028] A carrier according to an embodiment of the present disclosure includes: an insulating substrate having a surface configured to mount a semiconductor laser chip thereon; a ground pattern disposed on the surface; a mounting pattern disposed on the surface, the mounting pattern including an upper surface configured to arrange a capacitor thereon, a main region, and a protrusion having a width narrower than the main region, wherein the protrusion has a side edge, the side edge is on an extension of an opposite side of the main region opposite to the ground pattern; and a region configured to arrange a resistor thereon, the region being located on an extension of the protrusion.

[0029] As an embodiment, the carrier may further include an extended ground pattern arranged to be opposite to the ground pattern so as to sandwich a region where the protrusion and the resistor are arranged. The extended ground pattern may be electrically connected to the ground pattern.

[0030] An optical semiconductor device according to an embodiment of the present disclosure includes: a semiconductor laser chip, an insulating substrate, a ground pattern, a transmission line, a mounting pattern, a capacitor, and a resistor. The semiconductor laser chip includes an electrode pad. The insulating substrate has a surface on which the semiconductor laser chip is mounted. The ground pattern is disposed on the surface. The transmission line is disposed on the surface and is connected to the electrode pad of the semiconductor laser chip via a first wire. The mounting pattern is disposed on the surface close to the ground pattern. The capacitor has a first electrode and a second electrode. The first electrode is connected to the electrode pad of the semiconductor laser chip via a second wire, and the second electrode is connected to the mounting pattern. The resistor is disposed on the surface. The resistor has a first end connected to the mounting pattern and a second end connected to the ground pattern. The ground pattern includes at least one extended ground pattern, which is arranged on both sides or one side of the resistor to extend along the resistor. The first width between the mounting pattern and the ground pattern and the second width between the resistor and at least one extended ground pattern are 20 μm or more and 60 μm or less.

[0031] In the optical semiconductor device, a semiconductor laser chip is mounted on the surface of an insulating substrate, and a high-frequency drive signal is provided to the semiconductor laser chip via a transmission line and a wire. In order to terminate the high-frequency signal path, a capacitor and a resistor are arranged on the surface of the insulating substrate. The distal end of the wire extending from the transmission line to the semiconductor laser chip further extends to the capacitor and is connected to one electrode of the capacitor. The other electrode of the capacitor is connected to a ground pattern via a mounting pattern and a resistor.

[0032] In this optical semiconductor device, the inventors have found that the spacing of the gap between the resistor connected to the capacitor and the ground pattern and the mounting pattern greatly affects the EO characteristics. That is, if the gap between the mounting pattern and the ground pattern and the gap between the resistor and the ground pattern are empty in a large part, the EO characteristics partially decrease (become discontinuous) due to the resonance caused by the stray capacitance generated in these parts. Therefore, the flatness of the EO characteristics is impaired. Therefore, in the above-mentioned optical semiconductor device, the width of the gap between the mounting pattern and the ground pattern except for the area where the resistor is provided, and the width of the gap between the resistor and the ground pattern except for the part connected to each other, at any position of the gap, the above two widths are set to 20μm or more and 60μm or less. According to the inventors' knowledge, this reduces the decrease in EO characteristics, and the discontinuity points can be reduced, so that the EO characteristics can be close to being flatter.

[0033] As an embodiment, at least one extended ground pattern may be a pair of extended ground patterns, and the pair of extended ground patterns may sandwich a resistor therebetween. In this embodiment, each second width between the resistor and each of the pair of extended ground patterns may be 20 μm or more and 60 μm or less in any region. The pair of extended ground patterns and the resistor may be composed of coplanar lines (coplanar circuits). In this case, high frequency characteristics may be stabilized and the decline in EO characteristics may be further reduced.

[0034] As an embodiment, the at least one extended ground pattern may be one extended ground pattern, and the one extended ground pattern may be arranged at one side of the resistor.

[0035] As an embodiment, the mounting pattern may include a main area and a protrusion extending from the main area. The protrusion may be connected to the first end of the resistor. In this embodiment, at least one extended ground pattern may be provided on both sides or one side of the protrusion, and the third width between the protrusion and the at least one extended ground pattern may be 20 μm or more and 60 μm or less in any area. In this case, the protrusion is provided from a manufacturing perspective. According to the inventor's knowledge, in the case of providing the protrusion, by configuring the coplanar line (coplanar circuit) using the extended ground pattern located on both sides or one side of the protrusion, the high-frequency signal is transmitted through the coplanar line to reduce the radiation loss, and therefore, the high-frequency characteristics in the protrusion are stabilized, so that the decline in EO characteristics can be further reduced. In this case, at any position, the width of the gap between the protrusion and the extended ground pattern is 20 μm or more and 60 μm or less. The second electrode of the capacitor may be connected to the main area of ​​the mounting pattern.

[0036] As an embodiment, a pair of extended ground patterns as at least one extended ground pattern may be arranged on both sides of the protrusion or the resistor, and the pair of extended ground patterns may be electrically connected to each other via a third wire so that the third wire crosses the protrusion. In this case, the high-frequency characteristics in the protrusion are further stabilized, and therefore, the degradation of the EO characteristics can be more effectively reduced.

[0037] As an embodiment, the mounting pattern may include a main region connected to the second electrode of the capacitor, and the resistor may be directly connected to the main region.

[0038] As an embodiment, the transmission line can be arranged along the semiconductor laser chip and can be composed of coplanar lines passing through the signal line and two parts of the ground pattern arranged on both sides of the signal line. In this case, the high frequency characteristics can be stabilized and the degradation of the EO characteristics can be further reduced.

[0039] As an example, the capacitance of the capacitor may be 90 nF or more and 120 nF or less. In such a capacitor having a larger capacitance, the size of the capacitor also becomes larger, and its mounting pattern also becomes wider. In this case, the effect of the above optical semiconductor device is particularly effective.

[0040] [Detailed description of embodiments of the present disclosure]

[0041] Specific examples of optical semiconductor devices according to embodiments of the present disclosure will be described below with reference to the accompanying drawings. The present invention is not limited to these examples, but the present invention is defined by the scope of the claims and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope. In the following description, the same reference numerals are assigned to the same elements in the description of the drawings, and repeated descriptions will be omitted.

[0042] Figure 1 1 is a plan view showing the configuration of an optical semiconductor device 1A according to an embodiment of the present disclosure. The optical semiconductor device 1A is installed in an optical transmitter of an optical communication system. Figure 1 As shown, the optical semiconductor device 1A includes a carrier (insulating substrate) 10, a coplanar line 11, a ground pattern 13, a bias pattern 14, a mounting pattern 15, capacitors 16 and 19, a thin film resistor (TFR) 17, bonding wires 18a to 18d, and a semiconductor laser chip 20.

[0043] The semiconductor laser chip 20 has a monolithic structure in which a laser diode and an optical modulator are integrated on a common substrate. The semiconductor laser chip 20 has a pad 21 connected to an anode electrode to provide a bias current to the laser diode and a pad 22 connected to an anode electrode to provide a drive current to the optical modulator. These pads 21 and 22 are formed by, for example, Au plating.

[0044] The carrier 10 is a quadrilateral plate-like (substrate-like) member, and has a surface 10a, a pair of side surfaces 10c and 10d facing each other, and a pair of end surfaces 10e and 10f facing each other. A pair of side surfaces 10c and 10d extend in a first direction (hereinafter referred to as a vertical direction) respectively, and are arranged side by side in a second direction (hereinafter referred to as a lateral direction) intersecting the vertical direction. A pair of end surfaces 10e and 10f extend in a lateral direction respectively to connect the side surface 10c and the side surface 10d, and are arranged side by side in a vertical direction. In the carrier 10, a semiconductor laser chip 20 is mounted on the surface 10a at a position close to the end surface 10e. The carrier 10 is made of a dielectric material such as aluminum nitride (AlN). The thickness of the carrier 10 is 0.3mm or more, and in one example, the thickness is 0.45mm. The lateral dimension of the carrier 10 is, for example, 1.0mm, and the longitudinal dimension of the carrier 10 is, for example, 2.0mm.

[0045] The coplanar line 11 is an example of a transmission line. The form of the transmission line in the embodiment is not limited to the coplanar line, and various other line forms can be adopted. The coplanar line 11 is configured to include two parts of a signal line 12 and a ground pattern 13. The signal line 12 is a conductive metal film that extends from a position near the end face 10f to a position near the end face 10e in a vertical direction on the surface 10a. The portion near the end face 10f becomes a pad 12a for wire bonding, and one end of a bonding wire for electrically connecting to a lead terminal of a package (not shown) is bonded to the pad 12a. The portion near the other end face 10e becomes a pad 12b for wire bonding, and the pad 12b and the pad 22 of the semiconductor laser chip 20 are electrically connected via a bonding wire 18a.

[0046] The portion (including the pad 12b) closer to the end face 10e than the center of the signal line 12 in the vertical direction is arranged between the semiconductor laser chip 20 and the side 10c. The portion (including the pad 12a) closer to the end face 10f than the center of the signal line 12 in the vertical direction is slightly separated from the side 10c, but the distance from the side 10c is shorter than the distance from the side 10d. Therefore, as a whole, the signal line 12 is arranged to be biased in a region close to one side 10c.

[0047] The ground pattern 13 is a conductive metal film provided on the surface 10a at uniform intervals with both sides of the signal line 12 in the lateral direction. In the present embodiment, the ground pattern 13 is provided on almost the entire area on the surface 10a except for the formation area of ​​the signal line 12, the bias pattern 14, and the mounting pattern 15. In the ground pattern 13 located on the side 10d side relative to the signal line 12, a first mounting area for the semiconductor laser chip 20 and a second mounting area for the capacitor 19 are defined. On the first mounting area of ​​the ground pattern 13, the semiconductor laser chip 20 is mounted, and the back surface electrode (cathode) of the semiconductor laser chip 20 is conductively connected to the ground pattern 13. The capacitor 19 is mounted on the second mounting area of ​​the ground pattern 13, and the back surface electrode of the capacitor 19 is conductively connected to the ground pattern 13. One end of each bonding wire electrically connected to the ground lead terminal of the package (not shown) is bonded to each portion of the ground pattern 13 located on both sides of the signal line 12.

[0048] The bias pattern 14 is a conductive metal film disposed on the surface 10a at a position close to the side surface 10d and close to the end surface 10f. The bias pattern 14 and the front surface electrode of the capacitor 19 are electrically connected via a bonding wire 18c. The front surface electrode of the capacitor 19 and the pad 21 of the semiconductor laser chip 20 are electrically connected via a bonding wire 18b. In addition, one end of a bonding wire for electrically connecting to a power lead terminal of a package (not shown) is bonded to the bias pattern 14. A bias current is provided to the pad 21 of the semiconductor laser chip 20 via the bias pattern 14 and the bonding wires 18b and 18c. The capacitor 19 is used as a bypass capacitor for reducing the noise of the bias current. The capacitance value of the capacitor 19 is, for example, 2nF (nanofarad).

[0049] The mounting pattern 15, the capacitor 16, and the thin film resistor 17 constitute an impedance matching circuit for terminating the transmission path of the high-frequency signal. The mounting pattern 15 is a conductive metal film provided on the surface 10a at a position close to the end surface 10e and close to the side surface 10d. The mounting pattern 15 is provided side by side with the ground pattern 13 relative to the signal line 12, and the ground pattern 13 is located on the side of the side surface 10d. "Two patterns are provided side by side with each other" means a state in which no other pattern is provided between the patterns, and their edges face each other via a dielectric or air.

[0050] The mounting pattern 15 includes a main region 15a and a protrusion 15b. The main region 15a has a planar shape such as a rectangle or a square, and the capacitor 16 is mounted on the main region 15a. Therefore, the area of ​​the main region 15a is larger than the area of ​​the back side of the capacitor 16. The side 15c of the main region 15a extends along the end surface 10e, and the other side 15d of the main region 15a extends along the side 10d. The side 15e of the main region 15a opposite to the side 15c and the side 15f of the main region 15a opposite to the side 15d face the ground pattern 13 via a gap and extend along the ground pattern 13. The protrusion 15b is a portion electrically connected to the ground pattern 13 via the thin film resistor 17, and is formed by allowing a portion of the mounting pattern 15 to protrude. The protrusion 15b of the embodiment protrudes in the vertical direction from the central portion of the side 15e of the main region 15a toward the thin film resistor 17. A pair of side edges 15g and 15h of the protrusion 15b extend in the vertical direction.

[0051] The thin film resistor 17 is a film resistor formed on the surface 10a. The constituent material of the thin film resistor 17 is, for example, tantalum nitride (TaN). The resistance value of the thin film resistor 17 is, for example, 50Ω. The thin film resistor 17 extends in the vertical direction and is arranged between the protrusion 15b and the ground pattern 13. One end of the thin film resistor 17 is electrically connected to the protrusion 15b by contacting the protrusion 15b. The other end of the thin film resistor 17 is electrically connected to the ground pattern 13 by contacting the ground pattern 13. More specifically, the thin film resistor 17 has a planar shape such as a square or a rectangle. One side of the thin film resistor 17 extends in the lateral direction and contacts the protrusion 15b. The other side facing one side of the thin film resistor 17 extends in the lateral direction and contacts the ground pattern 13. A pair of side edges 17a and 17b of the thin film resistor 17 extending in the vertical direction face the ground pattern 13 via a gap and extend along the ground pattern 13. In one example, as viewed in a plan view, the side edge 17 a and the side edge 15 g are located on a straight line, and the side edge 17 b and the side edge 15 h are located on a straight line.

[0052] The ground pattern 13 includes a pair of extended ground patterns 13a and 13b. The extended ground patterns 13a and 13b are located on both sides of the protrusion 15b and the thin film resistor 17 in the lateral direction. As a result, the protrusion 15b forms a coplanar line with the extended ground patterns 13a and 13b, and the thin film resistor 17 forms a coplanar line with the extended ground patterns 13a and 13b. Specifically, the extended ground pattern 13a has a planar shape such as a square or a rectangle. One side of the extended ground pattern 13a is oriented toward the side edge 15g of the protrusion 15b and the side edge 17a of the thin film resistor 17, and extends along the side edges 15g and 17a. In addition, the other side of the extended ground pattern 13a is oriented toward the side 15e of the main area 15a and extends along the side 15e. One side of the extended ground pattern 13b is oriented toward the side edge 15h of the protrusion 15b and the side edge 17b of the thin film resistor 17, and extends along the side edges 15h and 17b. In addition, the other side of the extended ground pattern 13b is directed toward the side 15e of the main region 15a and extends along the side 15e. The extended ground patterns 13a and 13b sandwich the protrusion 15b and the resistor 17 therebetween.

[0053] The bonding wire 18d extends laterally across the protrusion 15b and electrically connects the pair of extended ground patterns 13a, 13b to each other. Therefore, the potential of the bonding wire 18d is the same as the potential of the ground pattern 13. Figure 2 As shown, the bonding wire 18d may be omitted as appropriate.

[0054] The width Wa of the gap between the mounting pattern 15 and the ground pattern 13 is λ / 4 or less (λ is the wavelength of the resonant frequency), which is the resonant frequency at any position of the gap except for the area where the thin film resistor 17 is provided, and specifically is 20μm or more and 60μm or less. That is, the width of the gap between the side 15f of the main area 15a and the ground pattern 13 and the width of the gap between the side 15e of the main area 15a and the ground pattern 13 are both 20μm or more and 60μm or less. The width of the gap between the side edge 15g of the protrusion 15b and the ground pattern 13 and the width of the gap between the side edge 15h of the protrusion 15b and the ground pattern 13 are also both 20μm or more and 60μm or less. In one example, these widths are all set to a constant size. In one example, the width of the gap is 40μm. In Figure 1 and Figure 2 In the embodiment, as long as the width of the gap between the protrusion 15b and the thin film resistor 17 and the extended ground pattern 13a (13b) is 20μm or more and 60μm or less, the lateral widths (widths in the direction intersecting the side edges) of the protrusion 15b and the thin film resistor 17 may be different from each other. For example, the lateral width of the protrusion 15b may be larger or smaller than the lateral width of the thin film resistor 17. Figure 1 and Figure 2 In the embodiment of FIG. 1 , the extended ground pattern 13 b may be formed and the extended ground pattern 13 a may not be formed.

[0055] The width Wb of the gap between the thin film resistor 17 and the ground pattern 13 is λ / 4 or less at any position except for the portion connected to each other, specifically 20 μm or more and 60 μm or less. That is, the width of the gap between the side edge 17a of the thin film resistor 17 and the ground pattern 13 and the width of the gap between the side edge 17b of the thin film resistor 17 and the ground pattern 13 are both 20 μm or more and 60 μm or less. In one example, these widths are all set to a constant size.

[0056] The signal line 12, ground pattern 13, bias pattern 14 and mounting pattern 15 are formed by electroplating Au and include a Ti film, a Pt film and an Au film from the carrier 10 side. The thickness of the Ti film is, for example, 0.1 μm. The thickness of the Pt film is, for example, 0.2 μm. The thickness of the Au film is, for example, 1 μm.

[0057] The capacitor 16 is mounted on the mounting pattern 15. Specifically, the capacitor 16 has a front surface electrode and a back surface electrode provided on the side opposite to the front surface electrode. The back surface electrode of the capacitor 16 faces the main region 15a of the mounting pattern 15, and is conductively bonded to the main region 15a via a conductive adhesive such as solder. The front surface electrode of the capacitor 16 is electrically connected to the pad 22 of the semiconductor laser chip 20 via a bonding wire 18a. The capacitance value of the capacitor 16 is, for example, 90nF or more and 120nF or less, and in one example, the capacitance value is 100nF. The capacitor 16 blocks the DC component and allows only the high frequency component to pass through the terminal circuit of the high frequency signal.

[0058] Figure 3 1 is a plan view showing a configuration example of an optical transmitter 2 including an optical semiconductor device 1A. In addition to the optical semiconductor device 1A, the optical transmitter 2 includes a package 61, a lens 62, a wiring board 63, and a thermoelectric cooler (TEC) 68. The package 61 is a substantially rectangular parallelepiped box, and houses the optical semiconductor device 1A, the lens 62, and the wiring board 63. At the rear end of the package 61, terminals 67 extending from lead terminals are arranged side by side. A signal line 65 and a ground pattern 66 constituting a coplanar line are provided on a feedthrough 69 located at the rear end of the package 61.

[0059] The TEC 68 is provided on the bottom surface of the package 61. The TEC 68 is a member that controls the temperature of the components provided on the upper surface according to the driving power provided from the outside of the optical transmitter 2. The electrical insulating plate 68a is provided on the upper surface of the TEC 68. A metal pattern corresponding to the size and shape of the back surface of the optical semiconductor device 1A, a metal pattern corresponding to the size and shape of the back surface of the lens 62, and a metal pattern corresponding to the size and shape of the back surface of the wiring board 63 are provided on the plate 68a. The optical semiconductor device 1A is mounted on the plate 68a by bonding the back surface to the metal pattern on the plate 68a via a conductive adhesive. Similarly, the lens 62 and the wiring board 63 are mounted on the plate 68a by bonding the back surface to the respective metal patterns on the plate 68a via a conductive adhesive.

[0060] The lens 62 is optically coupled to the light emitting end face of the semiconductor laser chip 20, and collimates the laser beam P emitted from the semiconductor laser chip 20. The collimated laser beam P is output to the outside of the package 61 through a light output port (not shown).

[0061] The wiring board 63 is arranged between the optical semiconductor device 1A and the feed-through 69. The signal line 63a and the ground pattern 63b constituting the coplanar line are provided on the wiring board 63. The signal line 63a extends in the vertical direction, and one end thereof is electrically connected to the pad 12a of the signal line 12 of the optical semiconductor device 1A via a bonding wire 74. The other end of the signal line 63a is electrically connected to the signal line 65 of the feed-through 69 via a bonding wire 77. A drive signal is provided to the signal line 65 of the feed-through 69 from the outside of the package 61 via a lead pin (not shown).

[0062] The ground pattern 63b is provided at a predetermined interval on both sides of the signal line 63a, and one end thereof is electrically connected to the ground pattern 13 of the optical semiconductor device 1A via a bonding wire 73. The other end of the ground pattern 63b is electrically connected to the ground pattern 66 of the feedthrough 69 via a bonding wire 75. The ground pattern 66 of the feedthrough 69 is electrically connected to the ground line outside the package 61 via a lead pin (not shown).

[0063] The bias pattern 14 is electrically connected to one terminal 67 via a bonding wire 71. A bias voltage is applied to the terminal 67 from the outside of the package 61 via a lead pin (not shown).

[0064] The effects obtained by the optical semiconductor device 1A of the above-described embodiment will be described. In the optical semiconductor device 1A, the semiconductor laser chip 20 is mounted on the surface 10a of the carrier 10, and a high-frequency drive signal is supplied to the semiconductor laser chip 20 via the coplanar wire 11 and the bonding wire 18a. In order to terminate the high-frequency signal path, a capacitor 16 and a thin-film resistor 17 are provided on the surface 10a of the carrier 10. The distal end of the bonding wire 18a extending from the coplanar wire 11 to the semiconductor laser chip 20 further extends onto the capacitor 16 and is connected to one electrode of the capacitor 16. The other electrode of the capacitor 16 is connected to the ground pattern 13 via the mounting pattern 15 and the thin-film resistor 17.

[0065] In the optical semiconductor device 1A, the spacing of the gap between the mounting pattern 15 connected to the capacitor 16 and the ground pattern 13 and the gap between the thin-film resistor 17 connected to the capacitor 16 and the ground pattern 13 greatly affects the EO characteristics. Fig.10 1 is a plan view showing an optical semiconductor device 100 according to a comparative example. The optical semiconductor device 100 is different from the optical semiconductor device 1A of the present embodiment in the shape of the ground pattern. That is, unlike the ground pattern 13 of the optical semiconductor device 1A, the ground pattern 13 of the optical semiconductor device 100 does not include a pair of extended ground patterns 13a and 13b. Therefore, the gap between the protrusion 15b of the mounting pattern 15 of the comparative example and the ground pattern 13 is larger than the gap between the main area 15a of the optical semiconductor device 1A and the ground pattern 13. In the optical semiconductor device 100, the lateral width of the resistor 117 is smaller than the lateral width of the protrusion 15b. Therefore, the gap between the resistor 117 and the ground pattern 13 is larger than the gap between the protrusion 15b and the ground pattern 13.

[0066] Figure 4 S of the examples and comparative examples are shown. 21 The simulation results of the characteristics are shown in the graph. Figure 4 In the figure, the vertical axis represents S 21 The horizontal axis represents the frequency (unit: GHz). Figure 4 The curve G11 in FIG. 1 shows the characteristics of the comparative example (refer to Fig.10 ), curve G12 shows the characteristics of the embodiment (refer to Figure 2 The curve G13 shows the characteristics of the embodiment (refer to Figure 1 Reference Figure 4 It can be understood that in the comparative example (curve G11), S 21 The drop in the characteristics occurs around 30 GHz. On the other hand, in this embodiment (curve G12 in the case where the bonding wire 18d is not provided), the S 21Then, in this embodiment (curve G13 in the case where bonding wire 18d is provided), the S 21 characteristics. Figure 4 The width of the middle gap was set constant at 40 μm, but equivalent simulation results were obtained within the range of 20 μm or more and 60 μm or less.

[0067] Figure 5A and 5B 1 is a diagram showing an equivalent circuit in the vicinity of capacitor 16 to describe the function of the embodiment. Figure 5A and 5B In FIG. 1 , the inductors L1 to L3 simulate the inductance of the mounting pattern 15, and the capacitor C1 is a parasitic capacitance generated by the gap between the main area 15a of the mounting pattern 15 and the ground pattern 13. Figure 5A As shown in FIG. 1 , in the comparative example, since the gap between the mounting pattern 15 and the ground pattern 13 and the gap between the resistor 117 and the ground pattern 13 are largely empty, stray capacitance C2 is generated in this portion. When the high-frequency current F flows, resonance occurs due to the stray capacitance C2. It is considered that high-frequency loss (leakage) is generated due to this resonance, as shown in FIG. Figure 4 As shown by the curve G11 in FIG. 1 , the EO characteristic partially decreases (becomes discontinuous). Therefore, in the comparative example, the flatness of the EO characteristic is impaired.

[0068] On the other hand, in the optical semiconductor device 1A of the present embodiment, for example, by providing a pair of extended ground patterns 13a and 13b to the ground pattern 13, it is possible to allow the gap between the mounting pattern 15 and the ground pattern 13 and the gap between the thin film resistor 17 and the ground pattern 13 to be uniform. Specifically, the width Wa of the gap between the mounting pattern 15 and the ground pattern 13 except for the region where the thin film resistor 17 is provided and the width Wb of the gap between the thin film resistor 17 and the ground pattern 13 except for the portion connected to each other can be set to 20 μm or more and 60 μm or less at any position of the gap. Therefore, as Figure 5B As shown, the stray capacitance C2 becomes a parasitic capacitance C1 having a constant size. Therefore, it is considered that the electric field strength becomes constant over the entire path of the high-frequency current F, and the above-mentioned resonance phenomenon is alleviated, thereby reducing high-frequency loss. In the optical semiconductor device 1A, if the gap between the resistor and the ground pattern 13 is 20 μm or more and 60 μm or less, a resistor such as a chip resistor other than the thin film resistor 17 can be used.

[0069] As described above, according to the optical semiconductor device 1A of the embodiment, the degradation of the EO characteristics can be reduced, and the discontinuous points can be reduced, so that the EO characteristics can be made close to being flatter.

[0070] As in the embodiment, the mounting pattern 15 may include a main area 15a on which the capacitor 16 is mounted and a protrusion 15b protruding from the main area 15a toward the thin film resistor 17, and the ground pattern 13 may include a pair of extended ground patterns 13a and 13b located on both sides of the protrusion 15b. From a manufacturing perspective, the protrusion 15b protrudes toward the thin film resistor 17. The purpose is (1) to provide a manufacturing margin on both sides of the thin film resistor 17, and (2) to add solder flow resistance (TaN) when mounting the capacitor 16. In the case where the protrusion 15b protrudes toward the thin film resistor 17, the ground pattern 13 includes a pair of extended ground patterns 13a and 13b located on both sides of the protrusion 15b to stabilize the high frequency characteristics of the protrusion 15b, so that the degradation of the EO characteristics can be further reduced.

[0071] As in Figure 1 In the example shown, the optical semiconductor device 1A may include a bonding wire 18d that electrically connects the pair of extended ground patterns 13a and 13b to each other across the protrusion 15b. In this case, the high frequency characteristics in the protrusion 15b are further stabilized, and therefore, the degradation of the EO characteristics can be more effectively reduced.

[0072] As in the embodiment, the capacitance of the capacitor 16 may be 90 nF or more and 120 nF or less. In such a capacitor having a relatively large capacitance, the size of the capacitor also becomes larger, and the mounting pattern 15 also becomes wider. In this case, Fig.10 In the comparative example of FIG. 1 , the gap between the mount pattern 15 and the ground pattern 13 further expands locally. In this case, the effect of the optical semiconductor device 1A of the present embodiment is particularly effective.

[0073] (Revision 1)

[0074] Figure 6 and Figure 7 The optical semiconductor devices 1B and 1C are plan views showing modifications of the above-described embodiment, respectively. The optical semiconductor devices 1B and 1C are different from the optical semiconductor device 1A of the above-described embodiment in the planar shape of the mounting pattern and the planar shape of the ground pattern.

[0075] like Figure 6As shown, in the mounting pattern 15A of the optical semiconductor device 1B, the protrusion 15b protrudes not from the central portion of the side 15e in the main region 15a but from the portion near the side 15f (in the illustrated example, the end of the side 15e closer to the side 15f). In this case, the width of the gap between the main region 15a of the mounting pattern 15A and the ground pattern 13 and the width of the gap between the protrusion 15b and the ground pattern 13 are constant. Since the thin film resistor 17 is arranged on the extension of the protrusion 15b, the width of the gap between the thin film resistor 17 and the ground pattern 13 is close to the width of the gap between the main region 15a of the mounting pattern 15A and the ground pattern 13 and the width of the gap between the main region 15b of the mounting pattern 15A and the ground pattern 13. Therefore, the difference between the parasitic capacitances in the above-mentioned gaps becomes smaller. Therefore, the degradation of the EO characteristics can be reduced. The ground pattern 13 includes an extended ground pattern 13a located on one side of the protrusion 15b and one side of the thin film resistor 17 in the lateral direction. The extended ground pattern 13a is provided between the protrusion 15b and the side 10d of the carrier 10 and between the thin film resistor 17 and the side 10d of the carrier 10. Therefore, the EO characteristics can be further improved by providing the ground pattern 13a.

[0076] like Figure 7 As shown, in the mounting pattern 15B of the optical semiconductor device 1C, the protrusion 15b protrudes not from the central portion of the side 15e of the main region 15a but from a portion near the side 15d (in the illustrated example, an end portion of the side 15e closer to the side 15d) and is close to the side 10d. The ground pattern 13 includes an extended ground pattern 13b located on one side of the protrusion 15b and on one side of the thin film resistor 17 in the lateral direction. The extended ground pattern 13b is provided at a position between the protrusion 15b and the thin film resistor 17 between the extended ground pattern 13b and the side 10d of the carrier 10.

[0077] In addition, in the present modification, the width of the gap between the mounting patterns 15A and 15B and the ground pattern 13 is 20 μm or more and 60 μm or less at any position of the gap except for the region where the thin film resistor 17 is provided. In one example, the width is all set to a constant size. The width of the gap between the thin film resistor 17 and the ground pattern 13 is 20 μm or more and 60 μm or less at any position of the gap except for the portions connected to each other. In one example, the width is all set to a constant size. Figure 6 and Figure 7In the embodiment, as long as the width of the gap between the protrusion 15b and each of the thin film resistor 17 and the extended ground pattern 13a (13b) is 20 μm or more and 60 μm or less, the lateral widths (widths in the direction intersecting the side edges) of the protrusion 15b and the thin film resistor 17 may be different from each other. For example, the lateral width of the protrusion 15b may be larger or smaller than the lateral width of the thin film resistor 17.

[0078] As in this modification, the protrusion 15b may protrude from any position in the lateral direction of the main region 15a. Even in this case, the same effects as those of the above-described embodiment can be obtained. Figure 8 This is a diagram showing S in this modification. 21 The simulation results of the characteristics are shown in the graph. Figure 8 In the figure, the vertical axis represents S 21 The horizontal axis represents the frequency (unit: GHz). Figure 8 The curve G31 in FIG. 1 shows the characteristics of the optical semiconductor device 1B (refer to FIG. 1B ). Figure 6 ), curve G32 shows the characteristics of the optical semiconductor device 1C (refer to Figure 7 ). refer to Figure 8 In this modification, similarly to the above-described embodiment (curve G12), S 21 The degradation of characteristics is alleviated.

[0079] (Revision 2)

[0080] Fig. 9 1 is a plan view showing an optical semiconductor device 1D of another modified example of the above-described embodiment. The optical semiconductor device 1D is different from the optical semiconductor device 1A of the above-described embodiment in the planar shapes of the mounting pattern and the ground pattern. Fig. 9 As shown, the mounting pattern 15C of the optical semiconductor device 1D includes only the main area 15a and does not include the protrusion 15b. Therefore, the mounting pattern 15C has a planar shape such as a square or a rectangle. The ground pattern 13 of this modification includes a protrusion 13c in addition to a pair of extended ground patterns 13a and 13b. The protrusion 13c protrudes toward the thin film resistor 17 between the pair of extended ground patterns 13a and 13b. The thin film resistor 17 is arranged between the mounting pattern 15C and the protrusion 13c of the ground pattern 13. Specifically, one end of the thin film resistor 17 is connected to the mounting pattern 15C, and the other end of the thin film resistor 17 is connected to the protrusion 13c of the ground pattern 13.

[0081] A pair of extended ground patterns 13a and 13b of the ground pattern 13 are provided on both sides of the thin film resistor 17 and the protrusion 13c in the lateral direction. One side of the extended ground pattern 13a faces the side edge 17a of the thin film resistor 17 and the side edge 13d of the protrusion 13c, and extends along the side edges 17a and 13d. One side of the extended ground pattern 13b faces the side edge 17b of the thin film resistor 17 and the side edge 13e of the protrusion 13c, and extends along the side edges 17b and 13e.

[0082] In addition, in the present modification, the width of the gap between the mounting pattern 15C and the ground pattern 13 is 20 μm or more and 60 μm or less at any position of the gap except the area where the thin film resistor 17 is set. In one example, the width is all set to a constant size. In addition, the width of the gap between the thin film resistor 17 and the ground pattern 13 is 20 μm or more and 60 μm or less at any position of the gap except the parts connected to each other. In one example, the width is all set to a constant size. In addition, as long as the width of the gap between the protrusion 13c and each of the thin film resistor 17 and the extended ground pattern 13a (13b) is 20 μm or more and 60 μm or less, the lateral widths (widths in the direction intersecting the side edges) of the protrusion 13c and the thin film resistor 17 can be different from each other. For example, the lateral width of the protrusion 13c can be greater than or less than the lateral width of the thin film resistor 17.

[0083] As in this modification, the portion protruding toward the thin film resistor 17 may be provided on the ground pattern instead of the mounting pattern. Then, the thin film resistor 17 may be directly connected to the main region 15a of the mounting pattern. Even in this case, the same effect as the above embodiment can be obtained.

[0084] The optical semiconductor device according to the present disclosure is not limited to the above-mentioned embodiments and examples, and various modifications may be made. For example, in the above-mentioned embodiments, an indirect modulation method using a laser diode and an optical modulator is exemplified, but the present disclosure may be applied to a direct modulation method for driving a laser diode. In this case, the signal line of the coplanar line is connected to the electrode of the laser diode.

Claims

1. An optical semiconductor device, comprising: Semiconductor laser chips; an insulating substrate having a surface on which the semiconductor laser chip is mounted; a ground pattern disposed on the surface; a mounting pattern disposed on the surface, the mounting pattern having an opposite side opposite to the ground pattern; a resistor arranged so that a side edge of the resistor is separated from an extension area of ​​the opposite side; an extended ground pattern positioned in the extended region of the opposite side, the extended ground pattern being electrically connected to the ground pattern; a capacitor arranged on the mounting pattern, One end of the resistor is electrically connected to the mounting pattern, and the other end of the resistor is electrically connected to a protrusion extending from the ground pattern, the protrusion having a narrower width than the mounting pattern.

2. The optical semiconductor device according to claim 1, in, The extended ground pattern is a pair of extended ground patterns, and the pair of extended ground patterns sandwich the resistor therebetween.

3. The optical semiconductor device according to claim 2, further comprising: A bonding wire connects the pair of extended ground patterns positioned on both sides of the resistor to each other.

4. An optical semiconductor device, comprising: Semiconductor laser chips; an insulating substrate having a surface on which the semiconductor laser chip is mounted; a ground pattern disposed on the surface; a mounting pattern disposed on the surface, the mounting pattern including a main region and a protrusion having a width narrower than the main region, wherein the protrusion has a side edge extending on an opposite side of the main region from the ground pattern; a resistor arranged on an extension of the protrusion, wherein a side surface of the resistor is opposite to the ground pattern; a capacitor arranged on the main area of ​​the mounting pattern; and An extended ground pattern is arranged to be opposite to the ground pattern so as to sandwich the protrusion and the resistor therebetween, the extended ground pattern being electrically connected to the ground pattern.

5. A carrier comprising: an insulating substrate having a surface configured to mount a semiconductor laser chip thereon; a ground pattern disposed on the surface; a mounting pattern disposed on the surface, the mounting pattern having an upper surface configured to arrange a capacitor thereon and an opposite side opposite to the ground pattern; an area configured to arrange thereon a resistor connected to the mounting pattern; as well as an extended ground pattern positioned on the extended region of the opposite side, the extended ground pattern being electrically connected to the ground pattern, One end of the resistor is electrically connected to the mounting pattern, and the other end of the resistor is electrically connected to a protrusion extending from the ground pattern, the protrusion having a narrower width than the mounting pattern.

6. The vector according to claim 5, in, The extended ground pattern is a pair of extended ground patterns sandwiching the region with the resistor disposed therebetween.

7. A carrier comprising: an insulating substrate having a surface configured to mount a semiconductor laser chip thereon; a ground pattern disposed on the surface; a mounting pattern disposed on the surface, the mounting pattern including an upper surface configured to arrange a capacitor thereon, a main region, and a protrusion having a width narrower than that of the main region, wherein the protrusion has a side edge extending on an opposite side of the main region opposite to the ground pattern; an area configured to arrange a resistor thereon, the area being located on an extension of the protrusion; and An extended ground pattern is arranged to be opposite to the ground pattern so as to sandwich the region, the extended ground pattern being electrically connected to the ground pattern, wherein the protrusion and the resistor are arranged in the region.

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