Voltage Controlled Oscillator Power Supply with Automatic Gain Control

Abstract

The present invention relates to a technique for powering a voltage controlled oscillator (VCO). A peak detector circuit is used to determine the amplitude of the output of the VCO, and the amplitude is compared with a reference value in an automatic gain control loop. The input voltage of the VCO is determined based on the difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.

Description

[0001] Cross-application of related applications

[0002] This application claims priority to U.S. non-provisional patent application serial number 16 / 049,612, filed on July 30, 2018, and entitled “Power Supply For Voltage Controlled Oscillators With Automatic Gain Control,” the entire contents of which are incorporated herein by reference as if reproduced in full. Technical Field

[0003] The present invention generally relates to power supplies for voltage controlled oscillators (VCOs) and methods of using the same. Background Art

[0004] A voltage controlled oscillator (VCO) is a component of a frequency reference circuit in a transmitter and receiver that generates a carrier wave that is modulated by information transmitted in telecommunications equipment. In the prior art, the power supply for a VCO is either a voltage source or a current source. As the tolerances of electronic components in integrated circuit processes increase, the variation in VCO performance also increases, which often results in the VCO failing to meet key performance specifications in mass production. To reduce this variation, the power supply to the VCO is sometimes made programmable so that the power supply to the VCO can be adjusted when the VCO frequency changes or its operating temperature changes. In some prior art, replica circuits of the active components of the VCO are used to try to reflect the behavior of the VCO so that the power supply to the VCO can be adjusted according to the variation of these active devices. The limitation of these methods is that since the VCO is oscillating, they cannot reflect the actual performance of the VCO. The oscillating circuit has characteristics related to the quality factor or Q factor of its resonator, which vary with tolerances and cannot be reflected by simple active devices or programmable power supplies. Creating a replica oscillator circuit to mirror the behavior of a voltage controlled oscillator generates a frequency that interferes with the frequency of the VCO itself, thereby generating spurs. Therefore, these prior art approaches cannot fully compensate for VCO variations due to tolerances. Summary of the invention

[0005] According to one aspect of the present invention, an oscillator system is provided, comprising a voltage controlled oscillator (VCO), a peak detector, a reference generator and a gain control circuit. The VCO is used to generate an oscillator output waveform having a certain amplitude according to an input voltage. The peak detector is used to receive the oscillator output waveform and determine an indication of the amplitude of the oscillator output waveform. The reference generator is used to provide a reference value. The gain control circuit is used to receive the reference value and an indication of the amplitude of the oscillator output waveform, and generate the input voltage according to the difference between the reference value and the indication of the amplitude of the oscillator output waveform.

[0006] Optionally, in any of the above aspects, the oscillator system may further include a source follower circuit and a low-pass filter. The source follower circuit is connected between the gain control circuit and the VCO to provide the input voltage to the VCO. The low-pass filter is connected between the gain control circuit and the source follower circuit, wherein the low-pass filter is used to filter the input voltage received from the gain control circuit and provided to the source follower circuit.

[0007] Optionally, in any of the above aspects, the oscillator system may include a bypass path and one or more control circuits. The bypass path is connected in parallel with the low pass filter between the gain control circuit and the source follower circuit. The one or more control circuits are connected to the bypass path for selectively connecting the bypass path during the startup mode.

[0008] Optionally, in any of the above aspects, the gain control circuit may include: an analog summing circuit for receiving the reference value and an indication of the amplitude of the oscillator output waveform, and determining the difference between the reference value and the indication of the amplitude of the oscillator output waveform; an amplifier for generating the input voltage based on the difference between the reference value and the indication of the amplitude of the oscillator output waveform.

[0009] Optionally, in any of the above aspects, the gain control circuit may include an analog-to-digital converter, a digital controller, and a digital-to-analog converter. The analog-to-digital converter is used to receive an indication of the amplitude of the oscillator output waveform and provide a digital representation of the indication. The digital controller is used to receive the reference value and the digital representation of the indication of the amplitude of the oscillator output waveform, and determine a digital value of the difference. The digital-to-analog converter is used to receive the digital value of the difference and generate the input voltage based on the digital value.

[0010] Optionally, in any of the above aspects, the reference generator includes a voltage divider.

[0011] Optionally, in any of the above aspects, the reference value is programmable, and the oscillator system further comprises: one or more control circuits connected to the reference generator for programming the reference value.

[0012] Optionally, in any of the above aspects, the reference generator is also used to provide a zero reference level, corresponding to an oscillator output waveform having zero amplitude, wherein the peak detector is used to determine an indication of the amplitude of the oscillator output waveform relative to the zero reference level.

[0013] Optionally, in any of the above aspects, the peak detector, the reference generator and the gain control circuit are formed in an integrated circuit using CMOS technology, and the peak detector is implemented as a plurality of parasitic bipolar junction transistors formed in the integrated circuit.

[0014] Optionally, in any of the above aspects, the oscillator output waveform of the VCO is a differential signal.

[0015] According to another aspect of the present invention, a method for controlling the amplitude of an output waveform of a voltage controlled oscillator (VCO) is provided. The method comprises: generating an output waveform by a VCO, the amplitude of the output waveform depending on an input voltage; receiving a reference level; receiving the output waveform of the VCO. The method further comprises: determining an indication of the amplitude of the output waveform; determining a difference between the indication of the amplitude and the reference level; updating the input voltage according to the difference; and providing the updated input voltage to the VCO.

[0016] Optionally, in any of the above aspects, the reference level is an analog voltage level, the indication of the amplitude of the output waveform is an analog voltage level, the difference is determined as an analog voltage level, and updating the input voltage includes: amplifying the analog voltage level of the difference.

[0017] Optionally, in any of the above aspects, the difference is calculated as a digital value, and updating the input voltage includes: generating an analog voltage according to the digital value.

[0018] Optionally, in any of the above aspects, providing the updated input voltage to the VCO includes: filtering the updated input voltage through a low-pass filter; and providing the filtered updated input voltage to the VCO through a source follower circuit.

[0019] Optionally, in any of the above aspects, providing the updated input voltage to the VCO also includes: before providing the filtered updated input voltage to the VCO through the source follower circuit, providing the input voltage to the VCO through the source follower circuit without filtering the updated input voltage through the low-pass filter.

[0020] According to another aspect of the present invention, a power supply for a voltage controlled oscillator (VCO) is provided. The power supply includes: a reference generator for providing a reference value and an automatic gain control loop. The automatic gain control loop may include a peak detector and an automatic gain control circuit. The peak detector is used to receive an oscillator output waveform of the VCO and determine an indication of the amplitude of the oscillator output waveform. The automatic gain control circuit is used to receive the reference value and the indication of the amplitude of the oscillator output waveform, and generate an input voltage of the VCO according to the difference between the reference value and the indication of the amplitude of the oscillator output waveform. The automatic gain control circuit may include: a differential circuit for determining the difference between the reference value and the indication of the amplitude of the oscillator output waveform of the VCO; and an analog voltage generation circuit for generating the input voltage according to the difference.

[0021] Optionally, in any of the above aspects, the differential circuit includes an analog summing circuit, and the analog voltage generating circuit includes an amplifier for generating the input voltage according to the difference value.

[0022] Optionally, in any of the above aspects, the differential circuit includes a digital controller, the analog voltage generating circuit includes a digital-to-analog converter, and the digital-to-analog converter is used to receive a digital value of the difference and generate the input voltage according to the digital value.

[0023] Optionally, in any of the above aspects, the automatic gain control circuit also includes: a source follower circuit, connected between the analog voltage generating circuit and the VCO, providing the input voltage to the VCO; a low-pass filter, connected between the analog voltage generating circuit and the source follower circuit, wherein the low-pass filter is used to filter the input voltage received from the analog voltage generating circuit and provided to the source follower circuit.

[0024] Optionally, in any of the above aspects, the automatic gain control circuit also includes: a bypass path connected in parallel with the low-pass filter between the analog voltage generating circuit and the source follower circuit; and one or more control circuits connected to the bypass path for selectively connecting the bypass path during a startup mode.

[0025] The summary of the invention briefly introduces a series of concepts, which will be further described in the detailed description. The summary of the invention is not intended to provide the key features or basic features of the subject matter claimed in the patent application, nor is it intended to determine the scope of the subject matter claimed in the patent application. The subject matter claimed in the patent application is not limited to the implementation method of solving any or all problems mentioned in the background technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention in its various aspects is illustrated by way of example and not limitation in the accompanying figures, in which like references indicate similar elements.

[0027] Figure 1 An example of a wireless network for communicating data is shown;

[0028] Figure 2 Shown in Figure 1 Exemplary details of a user equipment (UE) instance introduced in;

[0029] Figure 3 Shown in Figure 1 Exemplary details of the base station (BS) instance introduced in

[0030] Figure 4 Shows Figure 2 and Figure 3 Exemplary details of a receiver included in a UE or BS are shown;

[0031] Figure 5 Shows Figure 2 and Figure 3 Exemplary details of a transmitter included in a UE or BS are shown;

[0032] Figure 6 An embodiment of a VCO system including a VCO and a power supply with automatic gain control is shown;

[0033] Figure 7 An embodiment of a peak detection circuit is shown, wherein the peak detection circuit can be implemented as a bipolar device in a CMOS circuit;

[0034] Fig. 8A , Figure 8B and Figure 8C are some embodiments of a reference voltage generator;

[0035] Fig. 9 Another embodiment of a VCO system including a VCO and a power supply with automatic gain control is shown;

[0036] Fig.10is a high-level flow chart summarizing methods of operating a power supply for a VCO according to various embodiments of the present technology. DETAILED DESCRIPTION

[0037] The present invention will now be described with reference to the accompanying drawings, which generally relate to power supply circuits for use with voltage controlled oscillators (VCOs) and methods of using the same. The input voltage to the VCO is generated by a closed loop automatic gain control (AGC) loop that monitors the peak amplitude of the VCO output waveform, compares the peak amplitude to a reference value, and adjusts the input voltage accordingly. The VCO can be used to provide a local oscillator frequency for up-conversion and / or down-conversion in transmitters and receivers that can be used in wireless networks, as described below in conjunction with Figure 1 Examples of the wireless network are described and incorporated into other devices. Although discussed below primarily in the context of providing a local oscillator frequency for a receiver or transmitter, the techniques presented in the following description can also be used in any application that uses a VCO: telecommunications equipment, cable system satellite receivers, any phase locked loop (PLL) based frequency synthesizer, etc.

[0038] As the size of integrated circuits (ICs) decreases, the process tolerances of electronic components used in the circuit design of VCOs increase. When the power supply voltage of the VCO used on these IC devices is a fixed value, the performance characteristics of the VCO vary greatly due to the tolerances between components. The following disclosure proposes a power supply that can adjust the operation of a VCO with a larger tolerance in a way that the VCO meets the specifications. The power supply has low noise and therefore does not affect the noise of the VCO, and can start quickly. The proposed AGC loop is used to achieve these goals using a peak detector structure, but the AGC loop does not have an error integrator. The term "device" used herein may refer to a chip, a subcircuit of a larger circuit included in a chip, a subcircuit of a larger circuit included on a printed circuit board (PCB), or more generally, a circuit.

[0039] It should be understood that the current embodiments of the present invention can be implemented in many different forms, and the scope of the claims should not be interpreted as being limited to the embodiments set forth herein. In fact, these embodiments are provided to make the present invention thorough and complete, and to fully convey the concept of the embodiments of the present invention to those skilled in the art. In fact, the present invention is intended to cover substitutes, modifications and equivalents of these embodiments, which are included in the spirit and scope of the present invention as defined by the appended claims. In addition, in the following detailed description of the current embodiments of the present invention, many specific details are set forth to provide a thorough understanding. However, it should be clear to those of ordinary skill in the art that the current embodiments of the present invention can be practiced without these specific details.

[0040] Before providing additional details of the VCO power supply circuit for embodiments of the present technology, Figure 1 Describes an example of a wireless network for transmitting data; uses Figure 2 Described in Figure 1 Details of the user equipment (UE) example introduced in ; use Figure 3 Described in Figure 1 Details of the base station (BS) example introduced in . In addition, use Figure 4 and Figure 5 Describes details of examples of receivers and transmitters included in a UE or BS. The VCO power supply described herein can be combined with a receiver (such as Figure 4 described receiver) or transmitter (such as a combination of Figure 5 The invention may be used with, but is not limited to, the transmitter described herein.

[0041] Figure 1 An example of a wireless network for transmitting data is shown. For example, the communication system 100 includes user equipment 110A, 110B, and 110C, radio access networks (RAN) 120A and 120B, a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and other networks 160. Other or alternative networks include private and public data packet networks, including corporate intranets. Although a certain number of these components or elements are shown in the figure, any number of these components or elements may be included in the system 100.

[0042] In one embodiment, the wireless network may be a fifth generation (5G) network, comprising at least one 5G base station, wherein the 5G base station uses orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM and a transmission time interval (TTI) shorter than 1 ms (e.g., 100 microseconds or 200 microseconds) to communicate with a communication device. Generally, a base station may also refer to any one of an eNB and a 5G BS (gNB). In addition, the network may further include a network server for processing information received from the communication device via at least one eNB or gNB.

[0043] System 100 enables multiple wireless users to transmit and receive data and other content. System 100 may implement one or more channel access methods such as, but not limited to, code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0044] User equipment (UE) 110A, 110B, and 110C may be individually referred to as UE 110, or collectively referred to as UE 110, and may be used to work and / or communicate in the system 100. For example, UE 110 may be used to send and / or receive wireless signals or wired signals. Each UE 110 represents any suitable end-user device, and may include (or may be referred to as): user equipment, wireless transmission / reception unit (UE), mobile station, fixed or mobile user unit, pager, cellular phone, personal digital assistant (PDA), smart phone, laptop, computer, touch pad, wireless sensor, wearable device, or consumer electronic device.

[0045] In the described embodiment, the RAN 120A and the RAN 120B include one or more base stations (BS) 170A and 170B, respectively. The RAN 120A and the RAN 120B may be individually referred to as the RAN 120, or collectively referred to as the RAN 120. Similarly, the base stations (BS) 170A and 170B may be individually referred to as the base station (BS) 170, or collectively referred to as the base station (BS) 170. Each BS 170 is used to wirelessly connect to one or more UEs 110 to access the core network 130, the PSTN 140, the Internet 150 and / or other networks 160. For example, the base station (BS) 170 may include one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (eNB), a next generation (fifth generation) (5G) NodeB (gNB), a home NodeB, a home eNodeB, a site controller, an access point (AP), or a wireless router, or a server, a router, a switch, or a processing entity having a wired network or a wireless network.

[0046] In one embodiment, BS 170A forms part of RAN 120A, which may include one or more other BS 170, elements and / or devices. Similarly, BS 170B forms part of RAN 120B, which may include one or more other BS 170, elements and / or devices. Each BS 170 operates within a specific geographic area (sometimes referred to as a "cell") to send and / or receive wireless signals. In some embodiments, multiple-input multiple-output (MIMO) technology may be used, with each cell having multiple transceivers.

[0047] BS 170 communicates with one or more UEs 110 using wireless communication links over one or more air interfaces (not shown). The air interfaces may utilize any suitable radio access technology.

[0048] It is contemplated that the system 100 may use multiple channel access functions, such as including BS 170 and UE 110 for implementing the Long Term Evolution (LTE) wireless communication standard, LTE-Advanced (LTE-A) and / or LTE Multimedia Broadcast Multicast Service (MBMS) scheme. In other embodiments, the base station 170 and the user equipment 110A-110C are used to implement UMTS, HSPA or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may also be used.

[0049] The RAN 120 communicates with the core network 130 to provide voice, data, applications, Voice over Internet Protocol (VoIP) or other services to the UE 110. It should be understood that the RAN 120 and / or the core network 130 can communicate directly or indirectly with one or more other RANs (not shown). The core network 130 can also serve as a gateway access to other networks (such as the PSTN 140, the Internet 150, and other networks 160). In addition, some or all of the UEs 110 may include the ability to communicate with different wireless networks through different wireless links using different wireless technologies and / or protocols.

[0050] RAN 120 may also include millimeter wave and / or microwave access points (APs). The AP may be part of BS 170 or located remotely from BS 170. APs may include, but are not limited to, connection points (mmW CPs) or BS 170 capable of mmW communications (e.g., mmW base stations). For example, mmW APs may send and receive signals in the frequency range of 24 GHz to 100 GHz, but are not required to operate throughout the frequency range. As used herein, the term "base station" is used to refer to a base station and / or a wireless access point.

[0051] Although Figure 1 An example of a communication system is shown, but the Figure 1Various changes may be made. For example, the communication system 100 may include any number of user devices, base stations, networks, or other components in any suitable configuration. It should also be understood that the term "user device" may refer to any type of wireless device that communicates with a wireless network node in a cellular or mobile communication system. Non-limiting examples of user devices are target devices, device-to-device (D2D) user devices, machine-type user devices, or user devices capable of machine-to-machine (M2M) communication, laptops, PDAs, iPads, tablet computers, mobile terminals, smart phones, laptop embedded equipment (laptop embedded equipment, LEE), laptop mounted equipment (laptop mounted equipment, LME), and USB dongles.

[0052] Figure 2 1 shows example details of a UE 110 that can implement the methods and teachings provided by the present invention. For example, the UE 110 can be a mobile phone, but in other examples can be other devices, such as a desktop computer, a laptop computer, a tablet computer, a handheld computing device, an automotive computing device, and / or other computing devices. As shown in the figure, the exemplary UE 110 is shown to include at least one transmitter 202, at least one receiver 204, a memory 206, at least one processor 208, and at least one input / output device 212. The processor 208 can implement various processing operations of the UE 110. For example, the processor 208 can perform signal decoding, data processing, power control, input / output processing, or any other operation that enables the UE 110 to operate in the system 100 ( Figure 1 ). The processor 208 may include any suitable processing or computing device for performing one or more operations. For example, the processor 208 may include a microprocessor, a microcontroller, a digital signal processor, a field programmable gate array, or an application-specific integrated circuit.

[0053] The transmitter 202 is used to modulate data or other content for transmission via at least one antenna 210. The transmitter 202 may also be used to amplify, filter, and frequency convert RF signals before providing them to the antenna 210 for transmission. The transmitter 202 may include any suitable structure for generating signals for wireless transmission.

[0054] The receiver 204 may be used to demodulate data or other content received by at least one antenna 210. The receiver 204 may also be used to amplify, filter, and frequency convert RF signals received by the antenna 210. The receiver 204 may include any suitable structure for processing wirelessly received signals. The antenna 210 may include any suitable structure for transmitting and / or receiving wireless signals. The same antenna 210 may be used to transmit and receive RF signals, or different antennas 210 may be used to transmit and receive signals.

[0055] It should be understood that one or more transmitters 202, one or more receivers 204, and one or more antennas 210 may be used in the UE 110. Although shown as separate blocks or components, at least one transmitter 202 and at least one receiver 204 may be combined into a transceiver. Therefore, a single block of a transceiver may be shown instead of showing Figure 2 A separate block for the transmitter 202 and a separate block for the receiver 204 in .

[0056] UE 110 also includes one or more input / output devices 212. Input / output devices 212 facilitate interaction with a user. Each input / output device 212 includes any suitable structure for providing information to a user or receiving information from a user, such as a speaker, microphone, keypad, keyboard, display, or touch screen.

[0057] In addition, the UE 110 includes at least one memory 206. The memory 206 stores instructions and data used, generated, or collected by the UE 110. For example, the memory 206 can store software or firmware instructions executed by one or more processors 208 and data for reducing or eliminating interference in incoming signals. Each memory 206 includes any suitable one or more volatile and / or non-volatile storage and retrieval devices. Any suitable type of memory can be used, such as random access memory (RAM), read only memory (ROM), hard disk, optical disk, subscriber identity module (SIM) card, memory stick, secure digital (SD) memory card, etc.

[0058] Figure 3An exemplary BS 170 that can implement the methods and teachings provided by the present invention is shown. As shown, BS 170 includes at least one processor 308, at least one transmitter 302, at least one receiver 304, one or more antennas 310, and at least one memory 306. Processor 308 implements various processing operations of BS 170, such as signal decoding, data processing, power control, input / output processing, or any other function. Each processor 308 includes any suitable processing or computing device for performing one or more operations. For example, each processor 308 may include a microprocessor, a microcontroller, a digital signal processor, a field programmable gate array, or an application specific integrated circuit.

[0059] Each transmitter 302 includes any suitable structure for generating signals for wireless transmission to one or more UEs 110 or other devices. Each receiver 304 includes any suitable structure for processing signals wirelessly received from one or more UEs 110 or other devices. Although shown as separate blocks or components, at least one transmitter 302 and at least one receiver 304 can be combined into a transceiver. Each antenna 310 includes any suitable structure for transmitting and / or receiving wireless signals. Although the shared antenna 310 is shown here as being coupled to both the transmitter 302 and the receiver 304, one or more antennas 310 can be coupled to one or more transmitters 302, and one or more separate antennas 310 can be coupled to one or more receivers 304. Each memory 306 includes any suitable one or more volatile and / or non-volatile storage and retrieval devices.

[0060] Certain embodiments of the technology of the present invention described herein may be implemented using hardware, software, or a combination of hardware and software. The software used is stored in one or more processor-readable storage devices described above to program one or more processors to perform the functions described herein. Processor-readable storage devices may include computer-readable media, such as volatile and non-volatile media, removable and non-removable media. By way of example and not limitation, computer-readable media may include computer-readable storage media and communication media. Computer-readable storage media may be implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include RAM, ROM, EEPROM, flash memory or other storage technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, cassettes, tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. One or more computer-readable media do not include propagation, modulation, or transient signals.

[0061] Communication media typically embodies computer readable instructions, data structures, program modules or other data in a propagated, modulated or transient data signal (such as a carrier wave or other transmission mechanism), and includes any information delivery medium. The term "modulated data signal" refers to information that sets or changes one or more of its characteristics in a manner that encodes the information in the signal. By way of example and not limitation, communication media include wired media, such as a wired network or a direct wired connection, and wireless media, such as RF and other wireless media. Combinations of the above are also included within the scope of computer readable media.

[0062] In alternative embodiments, some or all of the software may be replaced by dedicated hardware logic components. For example, and not limitation, illustrative types of hardware logic components that may be used include field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip systems (SOCs), complex programmable logic devices (CPLDs), special-purpose computers, and the like. In one embodiment, one or more processors are programmed using software (stored in a storage device) that implements one or more embodiments. One or more processors may communicate with one or more computer-readable media / storage devices, peripherals, and / or communication interfaces.

[0063] Figure 4 4 shows example details of a receiver 404, where the receiver 404 may be a receiver 204 (eg, Figure 2 ) or a receiver 304 included in BS 170 (such as Figure 3 ), but not limited to this. Figure 4, the receiver 404 is shown to include an input terminal 406, at which a radio frequency (RF) signal is received, and therefore, the input terminal 406 may also be referred to as an RF input terminal 406. The RF input terminal 406 may be coupled to an antenna or a coupler, but is not limited thereto. The RF signal received by the RF input terminal 406 is provided to a low noise amplifier (LNA) 408, which may have an adjustable gain. The LNA 408 amplifies the received low-power RF signal without significantly reducing the signal-to-noise ratio (SNR) of the signal. The amplified RF signal output by the LNA 408 is provided to a mixer 410. In addition to receiving the amplifier RF signal from the LNA 408, the mixer 410 also receives an oscillator LO signal from a local oscillator and adjusts the frequency of the amplifier RF signal, for example, from a first frequency to a second frequency lower than the first frequency. More specifically, the mixer 410 may be a down-mixer (DN MIX) that down-converts the amplified RF signal from a relatively high frequency to a baseband frequency, or down-converts the signal to an intermediate frequency (IF) that is offset from the baseband frequency.

[0064] Still reference Figure 4, the down-converted RF signal output from the mixer 410 is shown as being provided to a trans-impedance amplifier (TIA) 412. The TIA 412 acts as a current buffer to isolate a multi-feedback (MFB) filter 414 downstream of the TIA 412 from the mixer 410 upstream of the TIA 412. The MBF filter 414 low-pass filters the down-converted RF signal to filter out irrelevant high-frequency signal components, such as HF noise. The filtered RF signal output from the MBF filter 414 is provided to a variable gain amplifier (VGA), which is used to amplify the RF signal before providing it to an analog-to-digital (A / D) converter 418, which converts the RF signal from an analog signal to a digital signal. The digital signal output from the A / D converter 418 is then provided to a digital filter 420, which performs additional filtering to remove out-of-band signal components and attenuate quantization energy from the A / D 418. The filtered digital signal output from the digital filter 420 is then provided to other digital circuits downstream of the digital filter 420. For example, such other digital circuits may include a digital signal processor (DSP), but are not limited thereto. The digital filter 420 may be implemented using the same DSP or different DSPs.

[0065] Figure 4 The local oscillator (LO) signal in the receiver 404 may be provided by a voltage controlled oscillator (VCO) system 431, which is typically incorporated into a phase locked loop. The LO signal is provided to the mixer 410 for use in the down conversion process. Although the VCO system 431 is shown as being external to the receiver 404, according to an embodiment, the VCO system 431 may be connected to the mixer 410. Figure 4 One or more other components are formed in the same integrated circuit. Figure 6-Figure 10 The VCO and its power supply are further described.

[0066] Figure 5 Detail of an example of a transmitter 502 is shown, where the transmitter 502 may be a transmitter 202 (eg, Figure 2 ) or a transmitter 302 included in BS 170 (such as Figure 3 ), but not limited to this. Figure 5, the transmitter 502 is shown as including an output terminal 518, at which a radio frequency (RF) signal is provided, so the output terminal 518 may also be referred to as an RF output terminal 518. The RF output terminal 518 may be coupled to an antenna or a coupler, but is not limited thereto. The RF signal provided by the RF output terminal 518 is provided from the power amplifier PA 514 through a bandpass filter or a notch filter 516. For example, the filter 516 may be a duplex / SAW filter for removing undesired frequency components above and below the desired RF frequency range from the amplified RF output signal generated by the PA 514. The power amplifier PA 514 receives its input from the power pre-amplifier PPA 512, which first receives the up-converted signal to be transmitted from the mixer 510.

[0067] Still reference Figure 5 , in the digital-to-analog converter 506, from Figure 2 The processor 208 of the UE 110 or Figure 3 The processor 308 of the BS 170 receives a signal to be transmitted, wherein the digitized signal is filtered by a low pass filter 508 to first remove any high frequency noise before being up-converted in a mixer 510. In addition to receiving an analog version of the signal (usually an intermediate frequency (IF) signal) from the low pass filter 508, the mixer 510 also receives an oscillator LO signal from a local oscillator and adjusts the received IF signal, for example, from a first frequency to a second frequency higher than the first frequency. More specifically, the mixer 510 can be an up mixer (UP MIX) that up-converts the IF signal to an RF signal.

[0068] Figure 5 The local oscillator LO signal in the transmitter 502 may be provided by a voltage controlled oscillator VCO system 531, which is typically incorporated into a phase locked loop. The LO signal is provided to the mixer 510 for use in the up-conversion process. Although the VCO system 531 is shown as being external to the transmitter 502, according to an embodiment, the VCO system 531 may be connected to the phase locked loop 510. Figure 5 One or more other components are formed in the same integrated circuit. Figure 6-Figure 10 The VCO and its power supply are further described.

[0069] More specifically, the following disclosure describes power supply structures for use with VCOs, such as those that may be implemented in complementary metal oxide semiconductor (CMOS) ICs in telecommunications equipment. Existing power supplies for VCOs are typically voltage or current sources; however, as the tolerances of electronic components in IC processes increase, the performance variation of the VCOs also increases, often resulting in the VCOs failing to meet key performance specifications in mass production. To reduce this variation, the power supply to the VCO is sometimes made programmable so that the power supply to the VCO can be adjusted as the VCO frequency changes or the operating temperature changes. Another approach is to use replica circuits of the active components of the VCO to attempt to reflect the behavior of the VCO so that the power supply to the VCO can be adjusted based on the variations of these active devices. A limitation of these approaches is that, since the VCO is oscillating, they do not reflect the actual performance of the VCO. The oscillating circuit has characteristics related to the quality factor of its resonator, which vary with tolerances and cannot be reflected by simple active devices or programmable power supplies. Creating a replica oscillator circuit to mirror the behavior of a voltage controlled oscillator generates a frequency that interferes with the frequency of the VCO itself, thereby generating spurs. Therefore, none of these prior art approaches can fully compensate for VCO variations due to tolerances.

[0070] Other approaches include using automatic gain control to improve the startup time of a crystal oscillator, where a crystal is used instead of an inductor and capacitor resonator. This approach uses a traditional automatic gain control (AGC) loop, where an error integrator provides a startup time in the millisecond range, which is too slow for modern transceivers that require startup times an order of magnitude faster or faster. When the startup stabilization time of the VCO is too slow, it causes the frequency of the communication device to slowly drift at the beginning of communication, resulting in information loss or errors.

[0071] As mentioned above, as CMOS dimensions shrink, the tolerance values ​​of components in the IC increase, and these tolerances cause huge variations in the performance of the circuits in the IC. For example, the Q factor, or quality factor, of the capacitors of a VCO can vary by as much as 7 times in some processes. The Q factor of these capacitors affects the amplitude or level of the VCO by changing the impedance that the power supply needs to drive the VCO. If the impedance of the fixed power supply current becomes too low, the VCO may stop working completely. Figure 6-Figure 10The described structure and method can help solve this problem by continuously monitoring the amplitude of the VCO and adjusting its supply voltage to keep the VCO operating within an acceptable range. The power supply achieves this by feeding the VCO amplitude back to the power supply, comparing that VCO amplitude to a desired result, and then modifying the supply voltage until the desired result is achieved. This method improves upon traditional AGC feedback by eliminating the need for an error integrator in the AGC loop, which greatly increases the VCO's startup time.

[0072] Figure 6 The main functional blocks of an embodiment of a VCO system 600 having a VCO 601 and a power supply for the VCO 601 are shown. Considering that the power supply is at a high level, the elements of the power supply include: a reference generator 621, which provides information about the desired amplitude of the VCO signal; a summing (or difference function) circuit 613; an amplifier 615 with gain; a low-pass filter 617; a source follower 619; and a peak detector 611. The output waveform of the VCO 601 is an alternating current (AC) signal, which is passed to the peak detector 611, which converts the AC amplitude to a representative direct current (DC) level. The summing circuit 613 compares the DC level with a reference value DC voltage of the reference generator 621, where the reference value DC voltage represents the desired VCO amplitude as a voltage difference. Figure 6 In the embodiment of FIG. 6 , peak detector 611 is implemented as a negative peak detector, providing a peak detector output that increases as the amplitude of the LO output waveform of VCO 601 decreases. If peak detector 611 were instead implemented as a positive peak detector, the polarity of the summing circuit would be reversed.

[0073] The voltage difference of the summing circuit 613 is multiplied by the gain of the amplifier 615 and passed to the low pass filter 617. The low pass filter 617 reduces the circuit noise in the AGC loop without changing the multiplied voltage difference. The output of the low pass filter 617 is input to the source follower 619, which is used to match the high impedance of the output of the low pass filter 617 to the low impedance of the input voltage as the power supply node of the VCO 601. The VCO amplitude is proportional to the input voltage of the power supply. If the VCO amplitude is lower than the desired level, the voltage difference will be higher, thereby increasing the VCO power supply voltage. If the VCO amplitude is higher than the desired level, the voltage difference will be lower, thereby reducing the VCO power supply voltage. When the voltage controlled oscillator amplitude is at the desired level, the voltage difference will remain constant and the VCO power supply voltage will also remain constant.

[0074] Figure 6The operation of the power supply of the VCO system 600 is independent of process tolerances of the circuit. Thus, since the AGC loop will adjust the VCO input voltage as needed, the amplitude of the VCO system will automatically adjust to the desired level set according to the reference value, regardless of the variations in VCO operation normally seen at a fixed supply voltage. Figure 6 The arrangement uses a simple amplifier 615 instead of an error integrator function. The error integrator function compares the voltage difference to a summing node; however, instead of multiplying the voltage by the gain of amplifier 615, an error integrator function is used to integrate the voltage difference over time.

[0075] Further considerations Figure 6 6, and an embodiment of a VCO system 600 including a VCO 601, a reference generator 621, and elements of an automatic gain control (AGC) loop, the automatic gain control loop including a summing circuit 613, an amplifier 615, a low pass filter 617, and a source follower 619. The VCO 601 generates an LO output waveform whose amplitude depends on an input voltage to the AGC loop, wherein the input voltage is based on the amplitude of the LO output waveform relative to a reference value.

[0076] Peak detector 611 receives the AC LO output waveform of VCO 601. Depending on the embodiment, the LO output waveform can be a differential output, or a single-ended output referenced to ground. Peak detector 611 converts the AC amplitude of the VCO output waveform to a representative DC level. Figure 7 The embodiment of gives more details of the peak detector 611.

[0077] The DC level output from the peak detector 611 is compared to the DC voltage of the reference generator 621, representing the desired VCO amplitude, at the summing circuit 613, which can be any of a number of circuits for accomplishing this purpose. The reference value of the reference generator 621 and the output of the peak detector 611 are combined to provide a voltage difference that is a function of the difference between these values, as indicated by the + and – signs. For example, the reference value and the peak detector output can be connected to the – and + inputs, respectively, of a differential amplifier of the summing circuit. As described above, Figure 6 In the embodiment of FIG. 6 , the peak detector 611 is implemented as a negative peak detector for detecting a negative peak value and outputting a lower DC voltage as the amplitude of the output voltage increases.

[0078] Reference generator 621 provides a reference value that contains information about the desired amplitude of the LO output signal of VCO 601. According to an embodiment, the reference value can be fixed, such as set as part of an initial test of the device, or set to a programmable reference value. If the reference value is programmable, a controller 631, such as a microprocessor, can select the reference value based on user input, external monitoring, or some combination of these inputs and other inputs. For example, VCO system 600 can be used to provide local oscillator signals of different frequencies that will use different amplitudes of the LO output waveform. The controller can program the reference value based on the selected output waveform frequency based on a lookup table, etc. According to an embodiment, the reference value can be an analog voltage level, or, as shown below Fig. 9 In some embodiments, the reference generator 621 will also provide a zero reference value to the peak detector circuit, where the zero reference value corresponds to a zero amplitude LO output waveform. Figure 8A-8C An example of a reference generator is given.

[0079] The voltage difference of the summing circuit 613 is passed to the amplifier 615, where the voltage difference is multiplied by the gain of the amplifier 615. The amplifier 615 can be any of various designs known in the art. The amplifier 615 can have a relatively low gain and has no effect on the phase noise of the VCO 601. Using a low gain amplifier not only reduces the noise of the AGC loop, but also can make the total loop gain less than unity gain, thereby making the circuit unconditionally stable.

[0080] The output of amplifier 615 is passed to a "super filter" combination of a low pass filter 617 and a source follower 619. The low pass filter 617 reduces circuit noise in the AGC loop without changing the multiplied voltage difference. The source follower 619 is used to match the high impedance of the low pass filter output to the low impedance of the input voltage supply node of the VCO 601. Both the low pass filter 617 and the source follower 619 can be any of a variety of known implementations.

[0081] In some embodiments, switches SW1 and SW2 may be added to bypass the low-pass filter 617. For example, switches SW1 and SW2 may be implemented as transistors, but other embodiments may use mechanical or other types of switches to establish and disconnect these connections. Controller 631 or other control circuitry may control switches SW1 and SW2 to bypass the low-pass filter 617 during startup so that the AGC loop can reach the approximate input voltage more quickly. After the initial time period, the low-pass filter 617 may be switched back to the AGC loop to ensure normal operation. The initial time period may depend on the delay value or may be determined by the controller 631 monitoring the convergence of the difference of the summing circuit 613. In an alternative embodiment, the source follower 619 may be replaced with a unity gain amplifier, but the low-pass filter 617 will not subsequently remove any unity gain amplifier noise. If noise performance degradation is acceptable, the low-pass filter 617 and source follower 619 may be omitted, and the amplifier 615 may be used to drive the VCO 601.

[0082] VCO system 600 may be implemented in a CMOS process. Embodiments of peak detector 611 may be implemented using parasitic bipolar devices in a CMOS process. The term "parasitic device" as used herein is a transistor that is a byproduct of the CMOS process but is not intentionally designed in as in a Bi-CMOS process. In some cases, these parasitic devices may be detrimental to the design, become active, and cause the IC to lock in a state from which it cannot recover without powering down; however, in some embodiments described herein, they are used as components of VCO system 600.

[0083] Peak detector 611 is directly connected to VCO 601 and should not have a load that would impair its performance. When the transistors are implemented using Metal Oxide Semiconductor (MOS) transistors in a CMOS process, the physical size of these transistors should be small so that the gate capacitance of the MOS transistors does not affect the frequency range of VCO 601. Unfortunately, smaller MOS transistors have very high flicker noise and will degrade the close-in phase noise performance of VCO 601. Bipolar transistors do not have large capacitance at the input, and the flicker noise of bipolar transistors is much lower than that of MOS transistors, making them more suitable for peak detector 611.

[0084] Figure 7 An embodiment of a topology of a peak detector 611 having low noise and reduced loading of the VCO 601 is shown. Figure 7, resistors and capacitors labeled the same have the same resistance and capacitance values, respectively. More specifically, resistors 701a and 701b have the same resistance R2, resistors 705a and 705b have a resistance R1, and resistor 707 has a resistance of ½ R1. Capacitors 709a and 709b have the same capacitance C1, which need not be equal to the capacitance C2 of capacitor 707. The size of transistor Q3 713 is equal to the size of transistors Q1 715 and Q2 717 in parallel, and the size of resistor 707 connected to the base of transistor Q3 713 is equal to the size of resistors 705a and 705b connected to the bases of Q1 715 and Q2 717 in parallel. This makes the circuit of Q3 713 DC equivalent to the combination of the circuits of transistors Q1 715 and Q2 717. A zero reference input may be issued from reference generator 621 via a resistor divider, for example, as shown below in conjunction with Figure 8A-8C described.

[0085] Still reference Figure 7 , operational amplifier 711 maintains the DC emitter voltage of transistors Q1 715, Q2 717, and Q3 713 at a reference zero voltage regardless of process and temperature variations. Figure 7 The embodiment corresponds to a VCO 601 with a differential output, wherein the differential input signals VCOP and VCOM of the peak detector 611 are the differential outputs from the VCO 601. When the voltage swing of VCOP or VCOM is negative, transistor Q1 715 or Q2 717 will be turned on, respectively, and the common emitter voltage of Q1 715 and Q2 717 will swing below the DC zero reference to track the negative peak voltage of the VCO 601 and capacitor 707. This common emitter voltage is the peak detector output, which will be negative relative to the zero reference, providing an indication of the VCO amplitude when a lower voltage indicates a larger amplitude. When the voltage swing of VCOP or VCO is positive, transistor Q1 715 or Q2 717 will be turned off, respectively. When both transistors Q1 715 and Q2 717 are off, indicating no VCO amplitude, capacitor 707 will discharge through the common emitter resistor of Q1 715 and Q2 717 and return to a zero reference. The time constant of R2 and C2 determines how quickly the peak detector output tracks the VCO amplitude, and how quickly the AGC loop responds to changes in the VCO amplitude.

[0086] Figure 8A-8C shows the reference generator 621 (and below Fig. 9 921) of some embodiments. Fig. 8A In , the output of the reference generator 621 (which may include a programmable reference output and a zero reference output) may be derived through a voltage divider formed by series connected resistors connected to a stable voltage source V+. Fig. 8A In , both the zero reference and the programmable reference are taken from taps on the same resistor bank. Fig. 8A In the arrangement of FIG. 8 , the resistor array is grouped into a first resistor Ra 801, a second resistor Rb 803, and a third resistor Rc 805. The zero reference value is taken from a fixed tap between Ra 801 and Rb 803 plus Rc 805, where the ratio of Ra 801 to the sum of all the resistors will set the zero reference value. If desired, the reference value input to the summing circuit can be programmed by closing a selected one of the switches, such as SWi 807, so that the VCO amplitude can be programmed by the controller 631. Closing switch SWi 807 programs the reference value to the tap between Ra 801 plus Rb 803 and Rc 805, where the corresponding reference value is V+ multiplied by (Rc / (Ra+Rb+Rc)).

[0087] Figure 8B An embodiment similar to Fig. 8A but the zero reference has its own fixed resistor divider. Figure 8C is another embodiment, wherein, if Figure 8B The zero reference shown is provided by a fixed resistor divider, while the programmable reference value is set by a programmable voltage source Vth 821 in series with a programmable resistor Rth 823.

[0088] The AGC loop of the VCO system 600 has low noise, fast settling time, and unconditional stability. It should be noted that conventional AGC arrangements use an error integrator, which typically involves a high-gain amplifier. The low-frequency flicker noise of the high-gain CMOS amplifier is highly detrimental to the phase noise of the VCO, and even with a low-pass filter implemented in the IC, it is difficult to reduce the noise to an acceptable level. Figure 6 In the arrangement, the gain of amplifier 615 is relatively low and will not affect the phase noise of VCO 601. Figure 6 The arrangement also eliminates the need for an error integrator, which is a time-dependent function with a time constant (usually exponential in nature). This means that an AGC loop with an error integrator will only asymptotically approach the desired supply voltage over time, known as its settling time. For a VCO used in communications equipment, this settling time would cause the VCO frequency to slowly drift, thus introducing errors into the information being transmitted or received, until the VCO supply provides an input voltage very close to its final value. In contrast, in Figure 6 In the method, the differential amplifier 615 eliminates the settling time of the error integrator, thereby allowing the communication device to start sending or receiving information very quickly without generating errors. Figure 6In the arrangement of , the low gain of amplifier 615 not only reduces the noise of the AGC loop, but also makes the overall loop gain less than unity, making the circuit unconditionally stable. This is again in contrast to the case where a high loop gain is used, where the phase shift around the loop is important because an inadequate phase margin may cause the loop to oscillate. More generally, Figure 6 The arrangement has the following advantages: the power supply of the VCO system 600 is automatically adjusted to the optimal VCO amplitude over the process and temperature, thereby providing better frequency stability and noise performance for the communication device.

[0089] Fig. 9 An alternative embodiment of a VCO system 900 is shown in which the analog-to-digital converter A / D 933, controller 931 (typically a microprocessor) and digital-to-analog converter D / A 935 are part of the AGC loop of the power supply and perform Figure 6 The functions of the summing circuit 613 and the amplifier 615 in the embodiment. The peak detector 911 also monitors the amplitude of the VCO 901, and the A / D 933 sends the amplitude information to the controller 931. The controller 931 compares the A / D amplitude information with the programmable reference value of the reference generator 921, wherein the programmable reference value can be a digital value or an analog voltage value converted to a digital value. The reference value can be programmed by the controller 931.

[0090] Controller 931 sends information to D / A 935 and inputs the output voltage of D / A 935 to low-pass filter 917 and source follower 919 to generate a VCO input voltage. In the AGC loop, controller 931 compares the output of peak detector 911 with the reference value of reference generator 921; if the VCO amplitude is too low, controller 931 increases the voltage of D / A 935 to increase the VCO voltage and increase the VCO amplitude. If the VCO amplitude is too high, controller 931 decreases the voltage of D / A 935 to decrease the VCO input voltage and reduce the VCO amplitude. The voltage of D / A 935 can be increased and decreased with one code at a time so that the AGC loop can dynamically track changes in the VCO amplitude. The rate of change is controlled by the rate at which A / D 933 is polled to obtain new information. With Figure 6 As in the embodiment of FIG. 1 , controller 931 can bypass the low-pass filter during startup using switches SW1 and SW2; if reduced noise performance is acceptable, low-pass filter 917 and source follower 919 can be omitted and D / A 935 can be used to drive VCO 901.

[0091] for Fig. 9In the embodiment of the present invention, the noise of the peak detector 911 is insignificant because in this embodiment, the noise of the peak detector 911 does not affect the noise of the D / A 935 or the noise of the AGC loop, so that the peak detector 911 can be composed of a MOS device or a combination of the above. Figure 7 The output of peak detector 911 is essentially a linear function of the VCO amplitude so that the AGC loop can perform a simplified search algorithm in which only 2 measurements are made at the extremes of the VCO amplitude range and interpolation can then be used to determine the correct D / A settings for optimal VCO operation.

[0092] Fig. 9 Advantages of the embodiments of Figure 6 The advantages of the embodiments of the present invention are the same: if the response time of the controller is set appropriately, the AGC loop has low noise, fast settling time and unconditional stability. If linear interpolation is used to determine the settings of D / A 935 as described above, the response time of the AGC loop can be very fast to meet the needs of communication devices. Since the peak detector 911 does not contribute to the VCO noise, embodiments can use small MOS devices to minimize the loading of VCO 901. More generally, Fig. 9 The arrangement can also enable the input voltage supplied to the VCO 901 to be automatically adjusted to the optimal VCO amplitude as the process and temperature change, thereby providing better frequency stability and noise performance for the communication device.

[0093] Fig.10 1 is a high-level flow chart summarizing the operation of a power supply for a VCO provided by various embodiments of the present technology. Starting at 1001, the VCO 601, 901 begins operation to generate an AC LO oscillator waveform. At 1003, the summing circuit 613 or the controller 931 receives a reference value corresponding to the desired amplitude of the AC LO oscillator waveform from the reference generator 621, 921. At 1005, the AC LO oscillator waveform is received at the peak detector 611, 911. Although in Fig.10 1003 is shown first and then 1005, but these operations can be performed in any order and usually occur simultaneously when the AGC loop of the power supply is operating.

[0094] In 1007, the peak detector 611, 911 determines an indication of the amplitude of the LO output waveform of the VCO 601, 901. The indication may be a DC voltage level, which is then provided to the summing circuit 613 or digitized at the A / D 933 and provided to the controller 931. Then, in 1009, the summing circuit 613 or the controller 931 compares the reference level from 1003 with the amplitude indication from 1007 to determine a level difference. Then, in 1011, an input voltage for the VCO 601, 901 is generated based on the level difference. Figure 6 In the embodiment of FIG. 6 , the input voltage comes from amplifier 615. Fig. 9 In the embodiment of FIG. 9 , the input voltage is generated by D / A 935 according to the digital value of controller 931 .

[0095] In 1013, the input voltage is then provided to the VCO 601, 901 through the low pass filter 617, 917 and the source follower 619, 919. As described above in conjunction with Figure 6 and Fig. 9 As described above, the low pass filters 617, 917 may be bypassed first to speed up the operation at startup, and some embodiments may omit the low pass filters 617, 917 and the source followers 619, 919. If the VCO system continues to work using the AGC loop, then in 1015, the process will loop back to 1003. On the contrary, if the VCO is to be turned off in 1015, the process proceeds to 1017 and ends.

[0096] It should be understood that this theme can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. In fact, these embodiments are provided to make this theme thorough and complete, and to fully convey this theme to those skilled in the art. In fact, this theme is intended to cover substitutes, modifications and equivalents of these embodiments within the scope and spirit of this theme as defined by the appended claims. In addition, in the following detailed description of this theme, many specific details are set forth to provide a thorough understanding of this theme. However, it will be clear to those of ordinary skill in the art that this theme can be practiced without these specific details.

[0097] Various aspects of the present invention are described herein in conjunction with the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products provided in the embodiments of the present invention. It should be understood that each box of the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to form a machine, so that the instructions executed by the processor of the computer or other programmable instruction execution device create a mechanism for implementing the function / action specified in one or more boxes of the flowchart and / or block diagram.

[0098] The description of the present invention is presented for illustration and description and is not intended to be exhaustive or limited to the present invention in the disclosed form. Various modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present invention. Various aspects of the present invention are selected and described in order to better explain the principles and practical applications of the present invention and to enable those of ordinary skill in the art to understand the present invention and various modifications suitable for the intended specific use.

[0099] The present invention has been described in conjunction with various embodiments. Other changes and modifications to the disclosed embodiments may be understood and implemented by studying the drawings, the disclosure and the appended claims, and these changes and modifications should be interpreted as being covered by the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the term "a" or "an" does not exclude a plurality.

[0100] For ease of explanation, it should be noted that the dimensions of the various features depicted in the figures are not necessarily drawn to scale.

[0101] For purposes herein, the specification may refer to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" to describe different embodiments or the same embodiment.

[0102] For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., through one or more other parts). In some cases, when an element is described as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element through related elements. When an element is described as being directly connected to another element, there are no related elements between the element and the other element. Two devices "in communication" are connected directly or indirectly so that they can communicate electronic signals.

[0103] For purposes herein, the term "based on" may be understood as "based at least in part on."

[0104] For the purpose of this document, unless otherwise specified, the use of numerical terms such as a "first" object, a "second" object, and a "third" object is used to identify different objects for identification purposes and does not imply an ordering of the objects.

[0105] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the subject matter of the invention claimed herein to the precise form or forms disclosed. Many modifications and variations are possible in light of the above teachings. The various embodiments described are selected to better explain the principles of the disclosed technology and its practical application, thereby enabling those skilled in the art to best utilize the technology in various embodiments and with various modifications suitable for the intended specific use. The intended scope is defined by the appended claims.

[0106] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An oscillator system, characterized in that: include: Voltage controlled oscillator (VCO), used to generate an oscillator output waveform with a certain amplitude according to the input voltage; a peak detector for receiving the oscillator output waveform and determining an indication of an amplitude of the oscillator output waveform; A reference generator for providing a reference value; a gain control circuit for receiving the reference value and an indication of the amplitude of the oscillator output waveform and generating the input voltage based on a difference between the reference value and the indication of the amplitude of the oscillator output waveform; A source follower circuit, connected between the gain control circuit and the VCO, and providing the input voltage to the VCO; A low-pass filter is connected between the gain control circuit and the source follower circuit, wherein the low-pass filter is used to filter the input voltage received from the gain control circuit and provided to the source follower circuit.

2. The oscillator system according to claim 1, characterized in that Also includes: a bypass path connected in parallel with the low pass filter between the gain control circuit and the source follower circuit; One or more control circuits are connected to the bypass path for selectively connecting the bypass path during a startup mode.

3. The oscillator system according to any one of claims 1 to 2, characterized in that The gain control circuit comprises: an analog summing circuit for receiving the reference value and an indication of the amplitude of the oscillator output waveform and determining a difference between the reference value and the indication of the amplitude of the oscillator output waveform; An amplifier is provided for generating the input voltage based on a difference between the reference value and an indication of the amplitude of the oscillator output waveform.

4. The oscillator system according to claim 1, characterized in that The gain control circuit comprises: an analog-to-digital converter for receiving an indication of an amplitude of an output waveform of the oscillator and providing a digital representation of the indication; a digital controller for receiving said reference value and said digital representation of an indication of an amplitude of said oscillator output waveform and determining a digital value of said difference; A digital-to-analog converter is used to receive the digital value of the difference and generate the input voltage according to the digital value.

5. The oscillator system according to claim 1, characterized in that The reference generator includes a voltage divider.

6. The oscillator system according to claim 1, characterized in that The reference value is programmable, and the oscillator system further comprises: One or more control circuits are connected to the reference generator and are used to program the reference value.

7. The oscillator system according to claim 1, characterized in that The reference generator is further configured to provide a zero reference level corresponding to an oscillator output waveform having a zero amplitude, wherein the peak detector is configured to determine an indication of an amplitude of the oscillator output waveform relative to the zero reference level.

8. The oscillator system according to claim 1, characterized in that The peak detector, the reference generator and the gain control circuit are formed in an integrated circuit using CMOS technology, and the peak detector is implemented as a plurality of parasitic bipolar junction transistors.

9. The oscillator system according to claim 1, characterized in that The oscillator output waveform of the VCO is a differential signal.

10. A method for controlling the amplitude of a voltage controlled oscillator (VCO) output waveform, characterized in that: include: generating an output waveform by the VCO, wherein the amplitude of the output waveform depends on the input voltage; Receive reference level; receiving the output waveform of the VCO; determining an indication of an amplitude of the output waveform; determining a difference between the indication of the amplitude and the reference level; updating the input voltage according to the difference; providing the updated input voltage to the VCO; Providing the updated input voltage to the VCO comprises: filtering the updated input voltage through a low-pass filter; The filtered update input voltage is provided to the VCO through a source follower circuit.

11. The method according to claim 10, characterized in that The reference level is an analog voltage level, the indication of the amplitude of the output waveform is an analog voltage level, the difference is determined as an analog voltage level, wherein updating the input voltage comprises: The analog voltage level of the difference is amplified.

12. The method according to claim 10 or 11, characterized in that: The difference is calculated as a digital value, wherein updating the input voltage comprises: An analog voltage is generated according to the digital value.

13. The method according to claim 10, characterized in that Providing the updated input voltage to the VCO further comprises: The input voltage is provided to the VCO through the source follower circuit without filtering the updated input voltage through the low pass filter before the filtered updated input voltage is provided to the VCO through the source follower circuit.

14. A power supply for a voltage controlled oscillator (VCO), characterized in that: include: A reference generator for providing a reference value; Automatic gain control loop, including: a peak detector for receiving an oscillator output waveform of the VCO and determining an indication of an amplitude of the oscillator output waveform; An automatic gain control circuit, for receiving the reference value and an indication of the amplitude of the oscillator output waveform, and generating an input voltage of the VCO according to the reference value and the indication of the oscillator output waveform, the automatic gain control circuit comprising: a difference circuit for determining a difference between the reference value and an indication of an amplitude of the oscillator output waveform of the VCO; an analog voltage generating circuit, used for generating the input voltage according to the difference; A source follower circuit, connected between the analog voltage generating circuit and the VCO, and providing the input voltage to the VCO; A low-pass filter is connected between the analog voltage generating circuit and the source follower circuit, wherein the low-pass filter is used to filter the input voltage received from the analog voltage generating circuit and provided to the source follower circuit.

15. The power supply for VCO according to claim 14, characterized in that: The differential circuit includes an analog summing circuit, and the analog voltage generating circuit includes an amplifier for generating the input voltage according to the difference value.

16. The power supply for VCO according to claim 14 or 15, characterized in that: The differential circuit includes a digital controller, and the analog voltage generating circuit includes a digital-to-analog converter, and the digital-to-analog converter is used to receive the digital value of the difference and generate the input voltage according to the digital value.

17. The power supply for VCO according to claim 14, characterized in that: The automatic gain control circuit also includes: a bypass path connected in parallel with the low-pass filter between the analog voltage generating circuit and the source follower circuit; One or more control circuits are connected to the bypass path and are used to selectively connect the bypass path during a startup mode.

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