A narrow-pulse high-current constant current source and its control method

Abstract

The present invention relates to the technical field of semiconductor detection equipment, and particularly relates to a narrow-pulse high-current constant current source and its control method. The present invention sets a logic controller FPGA to drive the NMOS of the short-circuit branch through push-pull driving to improve the slope of the pulse rising and falling edges, uses an SPI interface to connect to a digital-to-analog converter DA to control the output voltage, outputs a current signal after passing through an operational amplifier of a mirror current source, controls the MOSFET drive to turn on or off the short-circuit branch through a multi-channel IO port, and at the same time, a clamping circuit is arranged in cooperation with the short-circuit branch to reduce the impact on the mirror current source and reduce the overshoot of the narrow pulse; finally, the current is output to the device under test through multi-channel parallel connection. The present invention disperses the load current to more components through parallel branches, which can effectively reduce the heat generation of the MOSFET tube; by setting the short-circuit branch, the limitation of the operational amplifier slew rate on the narrow pulse transition process is eliminated, and multi-channel parallel connection and a clamping circuit are set to achieve narrow-pulse high-current constant current control with an approximately ideal waveform.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor detection equipment, and particularly relates to a narrow pulse high-current constant current source and a control method thereof. Background Art

[0002] In the semiconductor component detection process, it is necessary to apply an instantaneous and controllable high current between two pins to test the impact resistance of the semiconductor component. Therefore, the detection equipment must provide a high-current signal with a narrow pulse width, constant current, and adjustable current.

[0003] Therefore, the detection equipment should first have a constant current characteristic and the current magnitude should be controlled by a program. Secondly, it can output a current signal with a narrow pulse width. Finally, it should be able to provide a high current of several amperes or more. Due to the slew rate limitations of the digital-to-analog converter and the operational amplifier, traditional design methods are difficult to increase the rise and fall speeds of the signal and are not easy to reduce the overshoot of the signal.

[0004] The present invention realizes the narrow pulse high-current constant current control with an approximately ideal waveform by designing a short-circuit branch, multiple parallel connections, and a clamping circuit. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention discloses a narrow pulse high-current constant current source and a control method thereof, which are used to solve the problems that due to the slew rate limitations of the digital-to-analog converter and the operational amplifier, traditional design methods are difficult to increase the rise and fall speeds of the signal and are not easy to reduce the overshoot of the signal.

[0006] The present invention is realized through the following technical solutions:

[0007] In a first aspect, the present invention discloses a narrow pulse high-current constant current source. The constant current source sets a logic controller FPGA to drive the NMOS of the short-circuit branch through push-pull driving to increase the slope of the pulse rising and falling edges, uses the SPI interface to connect to the digital-to-analog converter DA to control the output voltage, outputs a current signal after passing through the mirror current source operational amplifier, controls the MOSFET drive to turn on or off the short-circuit branch through multiple IO ports. At the same time, the short-circuit branch is provided with a clamping circuit to reduce the impact on the mirror current source and reduce the overshoot of the narrow pulse; finally, the current is output to the device under test through multiple parallel connections.

[0008] Furthermore, the digital-to-analog converter DA generates multiple analog voltage signals in the range of 0V to 5V and controls the output current of the mirror constant current source accordingly.

[0009] Furthermore, the clamping circuit group is composed of multiple groups of series diodes. The conduction voltage of each diode is set to Uon, and there is an NMOS transistor in each short-circuit branch group connecting the clamping circuit to GND.

[0010] Further, when none of the short - circuit branches are conducting, the currents I2_1 and I2_2 converge at point A and pass through the device under test. Therefore, UB = Uon+Uon_Test;

[0011] When the short - circuit branches Q_A1 and Q_B1 are conducting and Uon+Uon_Test>3Uon, the current I2_1 completely flows through the switch Q_A1, and the current I2_2 completely flows through the switch Q_B1, that is, UB = UC = 3Uon, UA = 0V.

[0012] Further, the conduction selection rule of the MOS transistors in the short - circuit branches is as follows:

[0013] The logic controller FPGA grounds and conducts the clamping circuits with the same conduction voltage, and disconnects other MOS transistors; the conducting clamping circuits satisfy n×Uon<Uon+Uon_Test and n×Uon≈Uon+Uon_Test, where n is the number of diodes connected in series in the clamping circuit.

[0014] Further, the push - pull drive converts the LVTTL level sent by the FPGA into levels of 0V and 12V to drive the NMOS in the short - circuit branches.

[0015] Further, the parallel branch distributes the load current to more components to reduce the heat generation of the MOSFET.

[0016] In a second aspect, the present invention discloses a control method for a narrow - pulse high - current constant - current source. When the control method is executed, the narrow - pulse high - current constant - current source described in the first aspect is used, and it includes the following steps:

[0017] S1 In the logic controller FPGA, use the IO port and the MOSFET drive circuit to turn on the set short - circuit branches to make the current of the device under test zero;

[0018] S2 Set DA1 and DA2 through the SPI interface of the logic controller FPGA, and make VDA1 = VDA2=(R1_1×R3_1×IΣ) / (2×R2_1), where IΣ is the desired device test current;

[0019] S3 Enter the transient process of VDA1 and VDA2 and the mirror current source, and finally make the currents I2_1 and I2_2 stable;

[0020] S4 Simultaneously turn off the short - circuit branches through the IO port of the FPGA to inject the currents I2_1 and I2_2 into the device under test;

[0021] S5 Simultaneously turn on the short - circuit branches through the IO port of the FPGA to turn off the current IΣ;

[0022] Finally, the FPGA sets VDA1 and VDA2 to 0 through the SPI interface.

[0023] Furthermore, in the control method, after the current is injected into the device under test and maintained for Δt, the short - circuit branch is simultaneously turned on through the IO port of the FPGA, thereby turning off the current IΣ, where the range of Δt is 0.8us to 1.2us.

[0024] Furthermore, in the control method, before the narrow pulse appears, stable currents I2_1 and I2_2 are obtained, and the two currents flow through the short - circuit branch. The instantaneous disconnection of the short - circuit branch results in the narrow - pulse current IΣ.

[0025] The beneficial effects of the present invention are as follows:

[0026] The present invention disperses the load current to more components through parallel branches, which can effectively reduce the heat generation of MOSFET tubes; by setting up a short - circuit branch, it gets rid of the limitation of the operational amplifier slew rate on the narrow - pulse transition process, and sets up multiple parallel connections and clamping circuits, realizing the constant - current control of narrow - pulse large current with an approximately ideal waveform, and having strong market application prospects. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following - described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0028] Figure 1 is the circuit diagram of the narrow - pulse large - current constant - current source in the specific implementation of the present invention;

[0029] Figure 2 is the control flow chart of the narrow - pulse large - current constant - current source in the embodiment of the present invention;

[0030] Figure 3 The control timing and key - point electrical signal waveform example diagram of the narrow - pulse large - current constant - current source in the embodiment of the present invention;

[0031] Figure 4 is the actual test curve diagram of the narrow - pulse large - current constant - current source in the embodiment of the present invention. Detailed Embodiment

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0033] Embodiment 1

[0034] This embodiment discloses a narrow-pulse high-current constant current source as shown in Figure 1 . The narrow-pulse high-current constant current source includes a logic controller FPGA that drives the NMOS of the short-circuit branch through push-pull driving to increase the slopes of the rising and falling edges of the pulse, uses an SPI interface to connect to a digital-to-analog converter DA to control the output voltage, outputs a current signal after passing through a mirror current source operational amplifier, controls the MOSFET driver to turn on or off the short-circuit branch through a multi-channel IO port. At the same time, a clamping circuit is arranged in cooperation with the short-circuit branch to reduce the impact on the mirror current source and reduce the overshoot of the narrow pulse; finally, the current is output to the device under test through multi-channel parallel connection.

[0035] In this embodiment, the FPGA adjusts the output voltage of the DA through the SPI interface, and also controls the MOSFET driver through a multi-channel IO port to turn on or off the short-circuit branch.

[0036] In this embodiment, the DA module generates multi-channel analog voltage signals in the range of 0V to 5V, and the output current value of the mirror constant current source is controlled by this voltage signal.

[0037] The mirror constant current source used in this embodiment is a publicly available and mature circuit. The FPGA can output a current signal through the SPI interface, passing through the DA module and then through the two operational amplifiers of the constant current source module. However, the transition process of the DA module and the operational amplifier is relatively long, which cannot meet the slope requirements of the rising and falling edges of the narrow pulse and cannot reach the pulse width index of less than 1 us.

[0038] Therefore, a short-circuit branch is designed at the output end of the constant current source in this embodiment to increase the slopes of the rising and falling edges of the pulse.

[0039] This embodiment uses push-pull driving to convert the LVTTL level sent by the FPGA into levels of 0V and 12V to drive the NMOS of the short-circuit branch.

[0040] Embodiment 2

[0041] This embodiment discloses a short - circuit branch. Traditional constant - current sources do not have a short - circuit branch. Therefore, analog - to - digital converters DA1 and DA2 are usually used to control the magnitude and pulse width of current IΣ. However, the slew - rate index of the digital - to - analog conversion module and the operational - amplifier circuit limits the rise and fall processes of currents I2_1 and I2_2, making it difficult to achieve a pulse - width current below 1 us.

[0042] Further analysis shows that as long as currents I2_1 and I2_2 change, their transient processes will be restricted by the slew - rate of the operational amplifier in the current source and an ideal transient process cannot be obtained. In the present invention, stable currents I2_1 and I2_2 have been obtained before the narrow pulse appears, and the two currents flow through the short - circuit branch. When the short - circuit branch is instantaneously disconnected, a narrow - pulse current IΣ can be obtained.

[0043] Therefore, the rise and fall edges of current IΣ are only affected by the driving of the MOSFET and the switching performance of the MOS tube in the short - circuit loop, and the switching performance of common components is better than 100 ns. Therefore, the short - circuit branch gets rid of the limitation of the operational - amplifier slew - rate on the transient process of the narrow pulse.

[0044] The following principles should be followed when selecting which MOS tubes in the short - circuit branch of this embodiment are turned on: ① The FPGA should make the clamping circuits with the same turn - on voltage conduct to the ground. For example, make Q_A1 and Q_B1 conduct simultaneously while other MOS tubes are turned off; ② The conducting clamping circuit should satisfy n×Uon < Uon+Uon_Test and n×Uon≈Uon+Uon_Test, where n is the number of diodes connected in series in the clamping circuit.

[0045] Based on the above principles, when the short - circuit branch is completely disconnected, the currents I2_1 and I2_2 of the two mirror current sources will converge at point A and completely pass through the device under test, and UB = UC = Uon+Uon_Test; when the short - circuit branch is connected, such as when Q_A1 and Q_B1 are conducting, since the turn - on voltage of the clamping circuit is lower, the currents of the two current sources will completely pass through MOS tubes Q_A1 and Q_B1.

[0046] Embodiment 3

[0047] This embodiment discloses a clamping circuit, which is composed of multiple groups of series - connected diodes. The turn - on voltage of each diode is set as Uon, and there is an NMOS tube in each short - circuit - branch group connecting the clamping circuit to GND.

[0048] When none of the short - circuit branches is conducting, the currents I2_1 and I2_2 converge at point A and pass through the device under test. Therefore, UB = Uon+Uon_Test. When the short - circuit branches Q_A1 and Q_B1 are conducting and Uon+Uon_Test>3Uon, the current I2_1 completely flows through the switch Q_A1, and the current I2_2 completely flows through the switch Q_B1. Therefore, UB = UC = 3Uon, and UA = 0V.

[0049] In this embodiment, the function of the clamping circuit group is that, as described above, the clamping circuit should satisfy n×Uon<Uon+Uon_Test and n×Uon≈Uon+Uon_Test. When the corresponding short - circuit branch is conducting, UB = n×Uon; when the short - circuit branch is disconnected, UB = Uon+Uon_Test.

[0050] If there is no clamping circuit, the change amount of UB, ΔUB≈Uon+Uon_Test; while the clamping circuit can reduce the change amount to ΔUB≈Uon_Test-(n - 1)×Uon. Therefore, the clamping circuit can make the change amount of UB smaller, reduce the impact on the mirror current source, and reduce the overshoot of the narrow pulse. When the model of the device under test changes and Uon_Test changes, this embodiment provides a multi - path clamping circuit group to satisfy n×Uon<Uon+Uon_Test and reduce ΔUB.

[0051] Embodiment 4

[0052] The control process of the narrow - pulse high - current constant - current source disclosed in this embodiment is as Figure 2 shown. First, the FPGA turns on the set short - circuit branches (such as turning on Q_A1 and Q_B1, or Q_A2 and Q_B2, or Q_A3 and Q_B3) through the IO port and the MOSFET drive circuit to make the current of the device under test zero.

[0053] Next, set DA1 and DA2 through the SPI interface of the FPGA, and make VDA1 = VDA2=(R1_1×R3_1×IΣ) / (2×R2_1), where IΣ is the expected device test current; after the transient processes of VDA1 and VDA2, and the mirror current source end, and the currents I2_1 and I2_2 are stable, turn off the short - circuit branches simultaneously through the IO port of the FPGA to inject the currents I2_1 and I2_2 into the device under test.

[0054] When the current injection into the device under test is maintained for Δt (about 1us), turn on the short - circuit branches simultaneously through the IO port of the FPGA to turn off the current IΣ; finally, the FPGA sets VDA1 and VDA2 to 0 through the SPI interface to reduce power consumption and the heat generation of the device.

[0055] Embodiment 5

[0056] This embodiment is described for a specific experiment. In this embodiment, two diodes are used to parallel two currents I2_1 and I2_2 into a test current IΣ, so IΣ = I2_1 + I2_2. Therefore, the parallel branch distributes the load current to more components, which can effectively reduce the heat generation of the MOSFET. By paralleling two current sources, the heat generation of the components in the mirror current source module, short - circuit module, and clamping circuit will be reduced to 1 / 4 of that of a single current source.

[0057] Figure 3 It is the control timing and key - point electrical signal waveforms of the narrow - pulse high - current constant - current source, where IΣ and UA have a good transient process, and the rising edge and falling edge are relatively ideal.

[0058] To test the control effect of the pulsed current, in Figure 1 a 0.25Ω resistor Rs is connected in series between the device under test and GND, and the voltage drop uRs across the resistor is measured. Figure 4 It is the voltage signal uRs corresponding to a current pulse. It can be seen that the peak value of the pulsed current is 2.16A, the pulse width is 1.25us, the top of the pulse is relatively flat, and the rise time and fall time are the same (about 0.32us), meeting the test requirements.

[0059] In summary, the present invention distributes the load current to more components through a parallel branch, which can effectively reduce the heat generation of the MOSFET; by setting up a short - circuit branch, it gets rid of the limitation of the operational amplifier slew rate on the transient process of narrow pulses, and by setting up multiple parallel connections and a clamping circuit, it realizes the narrow - pulse high - current constant - current control with an approximately ideal waveform, having a strong market application prospect.

[0060] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A narrow pulse high-current constant current source, characterized in that, the constant current source sets a logic controller FPGA to drive the NMOS of the short-circuit branch through push-pull drive to improve the slope of the pulse rise and fall edges, uses the SPI interface to connect to the digital-to-analog converter DA to control the output voltage, outputs a current signal after passing through the mirror current source operational amplifier, controls the push-pull drive to connect or disconnect the short-circuit branch through the multi-channel IO port of the FPGA, and at the same time, a clamping circuit is arranged in cooperation with the short-circuit branch to reduce the impact on the mirror current source and reduce the overshoot of the narrow pulse; finally, the current is output to the device under test through multiple parallel branches.

2. The narrow pulse high-current constant current source according to claim 1, characterized in that, the digital-to-analog converter DA generates multi-channel analog voltage signals in the range of 0V to 5V and controls the output current of the mirror current source accordingly.

3. The narrow pulse high-current constant current source according to claim 1, characterized in that, the clamping circuit group is composed of multiple groups of series diodes, and the conduction voltage of each diode is set to Uon, and there is an NMOS transistor in each short-circuit branch group connecting the clamping circuit to GND.

4. The narrow pulse high-current constant current source according to claim 3, characterized in that, when all the short-circuit branches are not conducting, the current I2_1 generated by the upper mirror current source and the I2_2 generated by the lower mirror current source converge to the parallel convergence point A of the upper mirror current source and the lower mirror current source and pass through the device under test, so UB = Uon + Uon_Test; when the switches Q_A1 and Q_B1 are conducting and satisfy Uon + Uon_Test > 3Uon, the current I2_1 completely flows through the switch Q_A1, and the current I2_2 completely flows through the switch Q_B1, that is, UB = UC = 3Uon, UA = 0V, where UB is the voltage of the upper mirror current source, UC is the lower mirror current source, UA is the voltage of the parallel convergence point A of the upper mirror current source and the lower mirror current source, and Uon_Test is the conduction voltage of the diode in the clamping circuit.

5. The narrow pulse high-current constant current source according to claim 1, characterized in that, the conduction selection rule of the short-circuit branch MOS transistor is as follows: the logic controller FPGA makes the clamping circuits with the same conduction voltage conduct to the ground, and other MOS transistors are disconnected; the conducting clamping circuits satisfy n×Uon < Uon + Uon_Test and n×Uon ≈ Uon + Uon_Test, where n is the number of series diodes in the clamping circuit, and Uon_Test is the conduction voltage of the diode in the clamping circuit.

6. The narrow pulse high-current constant current source according to claim 1, characterized in that, the push-pull drive converts the LVTTL level sent by the FPGA into levels of 0V and 12V to drive the NMOS of the short-circuit branch.

7. The narrow pulse high-current constant current source according to claim 1, characterized in that, the parallel branch disperses the load current to more components to reduce the heat generation of the MOSFET transistor.

8. A control method for a narrow-pulse high-current constant current source, which uses the narrow-pulse high-current constant current source according to any one of claims 1-7 when the control method is executed. Characterized in that: It includes the following steps: S1 The logic controller FPGA uses the IO port and the push-pull drive circuit to turn on the set short-circuit branch to make the current of the device under test 0. S2 Set DA1 and DA2 through the SPI interface of the logic controller FPGA, and make VDA1 = VDA2 = (R1_1 × R3_1 × IΣ) / (2 × R2_1), where IΣ is the expected device test current. S3 Enter the transient process of VDA1 and VDA2 and the mirror current source, and finally make the currents I2_1 and I2_2 stable. S4 Simultaneously turn off the short-circuit branch through the IO port of the FPGA to inject the currents I2_1 and I2_2 into the device under test. S5 Simultaneously turn on the short-circuit branch through the IO port of the FPGA, thereby turning off the current IΣ. S6 Finally, the FPGA sets VDA1 and VDA2 to 0 through the SPI interface. Wherein, DA1 and DA2 are multiplexed analog voltage signals generated by the digital-to-analog converter DA; VDA1 and VDA2 are the voltage values corresponding to DA1 and DA2; R1_1, R3_1, and R2_1 are the resistance values used by the upper current mirror source.

9. The control method for a narrow-pulse high-current constant current source according to claim 8. Characterized in that: In the control method, when the current is injected into the device under test and maintained for Δt, the short-circuit branch is simultaneously turned on through the IO port of the FPGA, thereby turning off the current IΣ, where the range of Δt is 0.8 us to 1.2 us.

10. The control method for a narrow-pulse high-current constant current source according to claim 8. Characterized in that: In the control method, before the narrow pulse appears, stable currents I2_1 and I2_2 are obtained, and the two currents flow through the short-circuit branch, and the instantaneous disconnection of the short-circuit branch obtains the narrow-pulse current IΣ.

Images