Structure and method of forming semiconductor device structure

Abstract

A structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a gate stack located above a semiconductor substrate and a covering element located above the gate stack. The covering element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element located above the sidewall of the covering element and the sidewall of the gate stack. Embodiments of the present invention relate to a structure and a method for forming a semiconductor device structure.

Description

[0001] This application is a divisional application of patent application entitled “Structure and Formation Method of Semiconductor Device Structure” filed on November 11, 2015, with patent application number 201510768135.7. Technical Field

[0002] Embodiments of the present invention relate to structures and methods of forming semiconductor device structures. Background Art

[0003] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation.

[0004] In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be manufactured using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0005] However, these advances have increased the complexity of processing and producing ICs. As component sizes continue to decrease, manufacturing processes continue to become more difficult to implement. Therefore, it is a challenge to form reliable semiconductor devices of increasingly smaller sizes. Summary of the invention

[0006] According to some embodiments of the present invention, a semiconductor device structure is provided, including: a gate stack located above a semiconductor substrate; a covering element located above the gate stack, wherein the covering element has an upper portion and a lower portion, and the upper portion is wider than the lower portion; and a spacer element located above the sidewalls of the covering element and the sidewalls of the gate stack.

[0007] According to some other embodiments of the present invention, a semiconductor device structure is also provided, including: a gate stack located above a semiconductor substrate; a covering element located above the gate stack, wherein the covering element has a first width close to the gate stack and a second width close to an upper portion of the covering element, and the second width is greater than the first width; and a spacer element located above the sidewalls of the covering element and the sidewalls of the gate stack.

[0008] According to some further embodiments of the present invention, a method for forming a semiconductor device structure is also provided, comprising: forming a gate electrode above a semiconductor substrate; forming a spacer element above the side wall of the gate electrode; partially removing the gate electrode and the spacer element to form a groove between the spacer elements, wherein the groove widens along a direction from the bottom of the groove toward the top of the groove; removing the remaining portion of the gate electrode so that the groove becomes deeper; after removing the remaining portion of the gate electrode, forming a metal gate stack in the groove; and forming a covering element above the metal gate stack and between the spacer elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When read in conjunction with the accompanying drawings, aspects of the present invention can be better understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figures 1A to 1G are cross-sectional views of various stages of a process for forming a semiconductor device structure according to some embodiments.

[0011] Figure 2 is a cross-sectional view of a semiconductor device structure according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the present invention may repeat reference numerals and characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the multiple embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative position terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] Several embodiments of the invention are described. Figures 1A to 1G is a cross-sectional view of various stages of a process for forming a semiconductor device structure according to some embodiments. Figures 1A to 1G Additional operations are provided before, during, and / or after the described stages. For different embodiments, some of the described stages may be replaced or eliminated. Additional components may be added to the semiconductor device structure. For different embodiments, some of the components described below may be replaced or eliminated.

[0015] like Figure 1A , a semiconductor substrate 100 is provided. In some embodiments, the semiconductor substrate 100 is a bulk semiconductor substrate such as a semiconductor wafer. For example, the semiconductor substrate 100 is a silicon wafer. The semiconductor substrate 100 may include silicon or other elemental semiconductor materials such as germanium. In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. The compound semiconductor may include gallium arsenide, silicon carbide, indium arsenide, indium phosphide, another suitable material, or a combination thereof.

[0016] In some embodiments, the semiconductor substrate 100 includes a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be manufactured using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof.

[0017] In some embodiments, one or more fin structures are formed. Figure 1A As shown, a fin structure (fin structure 101) is shown. In some embodiments, a plurality of recesses (or trenches) (not shown) are formed in the semiconductor substrate 100. As a result, a plurality of fin structures including the fin structure 101 are formed between the recesses. In some embodiments, one or more photolithography and etching processes are used to form the recesses.

[0018] like Figure 1A As shown, according to some embodiments, an isolation feature (not shown) is formed in the groove to surround the lower portion of the fin structure 101. The isolation feature is used to define and electrically isolate various device elements formed in and / or over the semiconductor substrate 100. In some embodiments, the isolation feature includes a shallow trench isolation (STI) feature, a local oxidation of silicon (LOCOS) feature, other suitable isolation features, or a combination thereof.

[0019] In some embodiments, each isolation component has a multilayer structure. In some embodiments, the isolation component is made of a dielectric material. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-K dielectric material, another suitable material, or a combination thereof. In some embodiments, an STI liner (not shown) is used to reduce crystal defects at the interface between the semiconductor substrate 100 and the isolation component. Similarly, the STI liner can also be used to reduce crystal defects at the interface between the fin structure and the isolation component.

[0020] In some embodiments, a dielectric material layer is deposited over the semiconductor substrate 100. The dielectric material layer covers the fin structure including the fin structure 101 and fills the grooves between the fin structures. In some embodiments, the dielectric material layer is deposited using a chemical vapor deposition (CVD) process, a spin coating process, another applicable process, or a combination thereof. In some embodiments, a planarization process is performed to thin the dielectric material layer until the fin structure 101 is exposed. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another applicable process, or a combination thereof. Thereafter, the dielectric material layer is etched back to below the top of the fin structure 101. As a result, an isolation component is formed. According to some embodiments, the fin structure including the fin structure 101 protrudes from the isolation component.

[0021] like Figure 1A According to some embodiments, a gate dielectric layer 104 is deposited over the isolation features and the fin structure 101. In some embodiments, the gate dielectric layer 104 is made of silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-K), another suitable dielectric material, or a combination thereof. Examples of high-K dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-K material, or a combination thereof. In some embodiments, the gate dielectric layer 104 is a dummy gate dielectric layer, which will be removed later. In some other embodiments, the gate dielectric layer 104 is not formed.

[0022] In some embodiments, the gate dielectric layer 104 is deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, a physical vapor deposition (PVD) process, another suitable process, or a combination thereof.

[0023] Afterwards, if Figure 1AAs shown, according to some embodiments, a gate electrode 106 is formed over the gate dielectric layer 104 to cover a portion of the fin structure 101. In some embodiments, the gate electrode 106 is a dummy gate electrode to be replaced by a metal gate electrode. In some embodiments, the gate electrode 106 is made of polysilicon. In some embodiments, the portion of the fin structure 101 located below the gate electrode 106 is used as a channel region of a transistor to be formed.

[0024] In some embodiments, a gate electrode layer is deposited over the gate dielectric layer 104 using a CVD process or another suitable process. In some embodiments, the gate electrode layer is made of polysilicon. Thereafter, according to some embodiments, a patterned hard mask layer (not shown) is formed over the gate electrode layer. The patterned hard mask layer can be used to pattern the gate electrode layer into a pattern including Figure 1A In some embodiments, the gate electrode 106 may be one or more gate electrodes. Figure 1A As shown, the gate dielectric layer 104 is also patterned. The gate electrode 106 and the gate dielectric layer 104 may together form a gate stack 109.

[0025] In some embodiments, the gate stack 109 is a dummy gate stack and will be replaced by a metal gate stack. In some embodiments, the gate stack 109 surrounds the side and top surfaces of the fin structure 101 and further extends above the semiconductor substrate 100 .

[0026] In some embodiments, the patterned hard mask layer includes a first hard mask layer and a second hard mask layer. The first hard mask layer is located between the gate electrode layer and the second hard mask layer. In some embodiments, the first hard mask layer is made of silicon nitride. In some embodiments, the second hard mask layer is made of silicon oxide. In some embodiments, the second hard mask layer is thicker than the first hard mask layer.

[0027] In some embodiments, a sealing element (not shown) is formed over the sidewalls of the gate stack 109. The sealing element may be used to protect the gate stack 109 and / or assist in a subsequent process for forming a lightly doped source / drain (LDS / D) region. In some embodiments, an ion implantation process is used to form the LDS / D region. In some other embodiments, a sealing element is not formed. In some other embodiments, the LDS / D region is not formed.

[0028] Afterwards, if Figure 1AAs shown, according to some embodiments, a spacer element 108 is formed over the sidewalls of the gate stack 109. The spacer element 108 can be used to protect the gate stack 109 and / or assist in subsequent processes for forming source / drain features. In some embodiments, the spacer element 108 is made of a dielectric material. The dielectric material may include silicon nitride, silicon oxynitride, silicon oxide, another suitable material, or a combination thereof.

[0029] In some embodiments, a dielectric material layer is deposited over the semiconductor substrate 100 and the gate stack 109. The dielectric material layer may be deposited using a CVD process, an ALD process, a spin coating process, another applicable process, or a combination thereof. Then, the dielectric material layer is partially removed using an etching process such as an anisotropic etching process. As a result, the remaining portion of the dielectric material layer located above the sidewalls of the gate stack 109 forms the spacer element 108.

[0030] like Figure 1A As shown, according to some embodiments, source / drain features 112 are formed over portions of the fin structure 101 near the gate stack 109. In some embodiments, the fin structure 101 is partially removed to form a recess near the spacer element 108. Figure 1A As shown, according to some embodiments, an epitaxial growth process is performed to form source / drain features 112. In some embodiments, source / drain features 112 also serve as stressors that can apply strain or stress to the channel region between source / drain features 112. Carrier mobility can be improved accordingly.

[0031] like Figure 1A As shown, according to some embodiments, a dielectric layer 114 is formed to surround the gate stack 109. In some embodiments, a dielectric material layer is deposited to cover the source / drain features 112, the spacer elements 108, and the gate stack 109. Thereafter, a planarization process is used to partially remove the dielectric material layer. The dielectric material layer may be partially removed until the gate electrode 106 is exposed. As a result, a dielectric layer 114 is formed.

[0032] In some embodiments, the dielectric material layer is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, another suitable material, or a combination thereof. In some embodiments, the dielectric material layer is deposited using a CVD process, an ALD process, a spin coating process, another suitable process, or a combination thereof. In some embodiments, the planarization process includes a CMP process, a grinding process, an etching process, another suitable process, or a combination thereof.

[0033] Thereafter, according to some embodiments, multiple etching operations are performed to remove the gate electrode 106. In some embodiments, these etching operations are performed in the same process chamber.

[0034] like Figure 1B As shown, according to some embodiments, a portion of the gate electrode 106 is removed in a first etching operation to form a recess 116a. The spacer element 108 and the gate electrode 106 remaining between the spacer elements 108 surround the recess 116a. In some embodiments, the depth of the recess 116a ranges from about 10 nm to about 20 nm. In some cases, after partially removing the gate electrode 106, the spacer element 108 may collapse slightly toward the recess 116a. As a result, the opening of the recess 116a becomes smaller.

[0035] In some embodiments, the first etching operation involves plasma. In some embodiments, the reactive gas used in the first etching operation includes HBr, Cl2, another similar gas, another suitable gas, or a combination thereof.

[0036] like Figure 1C As shown, in accordance with some embodiments, the second etching operation further removes portions of gate electrode 106 and laterally etches spacer element 108. In some embodiments, the first etching operation for spacer element 108 has a lower etching rate than the second etching operation for spacer element 108.

[0037] After the second etching operation, the groove (116a) becomes deeper and is indicated as 116b. In some embodiments, the depth of the groove 116b ranges from about 20 nm to about 35 nm. Figure 1C As shown, in some embodiments, the groove 116b becomes wider along a direction from the bottom of the groove 116b toward the top of the groove 116b.

[0038] In some embodiments, Figure 1C As shown, the conditions of the second etching operation are fine-tuned to laterally etch the upper portion of the spacer element 108. In some embodiments, the second etching operation involves plasma. In some embodiments, the reactive gas used in the second etching operation includes CHF3, HBr, O2, Ar, He, another similar gas, another suitable gas, or a combination thereof. In some embodiments, the volume concentration of CHF3 is in the range from about 50% to about 90%. In some embodiments, the volume concentration of HBr is in the range from about 20% to about 30%. In some embodiments, the volume concentration of O2 is in the range from about 10% to about 40%.

[0039] Due to the lateral etching of the spacer element 108, the groove 116b has a larger opening. In some embodiments, the groove 116b has an inclined sidewall. In some other embodiments, the groove 116b has a curved sidewall. In some embodiments, the width of the groove 116b gradually increases along the direction from the bottom of the groove 116b to the top of the groove 116b. In some embodiments, the groove 116b gradually becomes larger along the direction from the top of the gate electrode 106 toward the top of the groove 116b.

[0040] like Figure 1D As shown, according to some embodiments, in the third etching operation, the remaining portion of the gate electrode 106 is further removed. In some embodiments, the etching rate of the second etching operation on the spacer element 108 is higher than the etching rate of the third etching operation on the spacer element 108. In some embodiments, during the third etching operation, the spacer element 108 is not substantially removed.

[0041] After the third etching operation, the groove (116b) becomes deeper and is indicated as 116c. In some embodiments, the depth of the groove 116c is in the range from about 60nm to about 85nm. Thereafter, according to some embodiments, the gate dielectric layer 104 is removed. Figure 1D As shown, the recess 116 c exposes the fin structure 101 .

[0042] In some embodiments, the third etching operation involves plasma. In some embodiments, the reactive gas used in the second etching operation includes HBr, Cl2, another similar gas, another suitable gas, or a combination thereof. In some other embodiments, one or more other operations are performed before, during, between, and / or after the first, second, and third etching operations.

[0043] like Figure 1E As shown, according to some embodiments, a metal gate stack layer is deposited to fill the groove 116c (or trench) between the spacer elements 108. The metal gate stack layer may include a gate dielectric layer 118, a work function layer 120, and a conductive filling layer 122. One or more other layers may be formed between the metal gate stack layers. For example, a barrier layer may be formed between the gate dielectric layer 118 and the work function layer 120. A blocking layer may be formed between the work function layer 120 and the conductive filling layer 122. In some embodiments, since the groove 116c is widened (compared to before etching) after the above-mentioned etching operation, Figure 1B The groove 116a shown in FIG. 1 is a schematic diagram of a metal gate stack. Thus, filling of the metal gate stack layer becomes easier.

[0044] In some embodiments, the gate dielectric layer 118 is made of a dielectric material having a high dielectric constant (high K). The gate dielectric layer 118 may be made of hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-K material, or a combination thereof.

[0045] The work function layer 120 is used to provide a desired work function to the transistor to enhance device performance, such as increasing the threshold voltage. In some embodiments, the work function layer 120 is an n-type metal layer capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV. In some embodiments, the work function layer 120 is a p-type metal layer capable of providing a work function value suitable for the device, such as equal to or greater than about 4.8 eV.

[0046] The n-type metal layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type metal layer includes titanium nitride, tantalum, tantalum nitride, other suitable materials, or a combination thereof. The p-type metal layer may include a metal, a metal carbide, a metal nitride, other suitable materials, or a combination thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials, or a combination thereof.

[0047] The work function layer 120 may also be made of hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminum compounds, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the work function layer 120 may be fine-tuned to adjust the work function level. For example, the titanium nitride layer may be used as a p-type metal layer or an n-type metal layer, depending on the thickness and / or composition of the titanium nitride layer.

[0048] In some embodiments, the conductive fill layer 122 is made of a metal material. The metal material may include tungsten, aluminum, copper, another suitable material, or a combination thereof. The formation of the metal gate stack layer may involve a plurality of deposition processes. The deposition process may include a CVD process, an ALD process, a PVD process, an electroplating process, a chemical plating process, a spin coating process, another applicable process, or a combination thereof.

[0049] like Figure 1F As shown, according to some embodiments, a planarization process is performed to remove portions of the metal gate stack layer outside the recesses (or trenches) between the spacer elements 108. As a result, a metal gate stack 123 is formed. The metal gate stack 123 includes a gate dielectric layer 118, a work function layer 120, and a gate electrode 122' (such as a metal gate electrode), which is a portion of the conductive filling layer 122.

[0050] like Figure 1GAs shown, according to some embodiments, the metal gate stack 123 is etched back. In some embodiments, after the etch back process, the gate electrode 122' protrudes from the top surface of the work function layer 120 and / or the gate dielectric layer 118.

[0051] In some embodiments, because the spacer element 108 is laterally etched to provide a recess with a larger opening, the etching process for etching back the metal gate stack 123 can be well implemented due to the larger opening. The subsequent formation of the capping element and the subsequent process for forming a conductive contact to the metal gate stack 123 are significantly improved.

[0052] Afterwards, if Figure 1G As shown, according to some embodiments, a covering element 124 is formed over the etched-back metal gate stack 123. In some embodiments, the covering element 124 is in direct contact with the metal gate stack 123. In some embodiments, the covering element 124 is in direct contact with the gate electrode 122'. In some embodiments, the covering element 124 is in direct contact with the work function layer 120. In some embodiments, the covering element 124 is in direct contact with the gate dielectric layer 118. In some embodiments, the covering element 124 is in direct contact with the spacer element 108. In some embodiments, the gate electrode 122' penetrates into the covering element 124. In some embodiments, the covering element 124 surrounds the upper portion of the gate electrode 122'. In some embodiments, the covering element 124 continuously surrounds the upper portion of the gate electrode 122'.

[0053] In some embodiments, the covering element 124 is made of a dielectric material. The dielectric material may include silicon nitride, silicon oxynitride, another suitable material, or a combination thereof. In some embodiments, a protective material layer (such as a dielectric layer) is deposited over the dielectric layer 114, the spacer element 108, and the back-etched metal gate stack 123. In some embodiments, the protective material layer is made of a dielectric material. The dielectric material may include silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, oxide, another similar material, another suitable material, or a combination thereof. In some embodiments, the protective material layer is deposited using a CVD process, an ALD process, a spin coating process, another applicable process, or a combination thereof.

[0054] Thereafter, according to some embodiments, portions of the protective material layer outside the grooves between the spacer elements 108 are removed. Figure 1G As shown, the remaining portion of the protective material layer forms the capping element 124. In some embodiments, a planarization process is used to partially remove the protective material layer to achieve the formation of the capping element 124. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process, a grinding process, an etching process, another applicable process, or a combination thereof.

[0055] like Figure 1G As shown, the covering element 124 has a top portion 124t and a bottom portion 124b. The covering element 124 has a first width W1 near the metal gate stack 123 (or the bottom portion 124b) and a second width W2 near the top portion 124t of the covering element 124. The width W2 is greater than the width W1. In some embodiments, the first width W1 is in a range from about 25nm to about 35nm. In some embodiments, the second width W2 is in a range from about 27nm to about 37nm. In some embodiments, the covering element 124 has an upper portion and a lower portion. As shown in FIG. Figure 1G As shown, the upper portion is wider than the lower portion.

[0056] In some embodiments, the cover element 124 tapers along a direction from the top 124t toward the bottom 124b of the cover element 124. In some embodiments, the cover element 124 tapers along a direction from the top 124t toward the metal gate stack 123. In some embodiments, the spacer element 108 tapers along a direction from the bottom 124b of the cover element 124 toward the top 108t of the spacer element 108.

[0057] like Figure 1G As shown, there is an angle α between the bottom 125B and the sidewall 125V of the metal gate stack 123. In some embodiments, the angle α should be carefully controlled within an appropriate range. In some embodiments, the angle α is in a range from about 85 degrees to about 95 degrees. Figure 1G As shown, there is an angle θ between the sidewall 125S of the capping element 124 and the virtual plane L extending from the sidewall 125V of the metal gate stack 123 toward the top 124t of the capping element 124. In some embodiments, the angle θ should be carefully controlled within a suitable range. In some embodiments, the angle θ is in a range from about 1 degree to about 10 degrees.

[0058] Many variations and / or modifications may be made to the embodiments of the invention. Figure 2 1 is a cross-sectional view of a semiconductor device structure according to some embodiments of the present invention. The same reference numerals are used to represent the same elements. In some embodiments, the source / drain components are doped regions formed in the fin structure 101. In some other embodiments, the fin structure 101 is not formed. In these cases, the source / drain components are doped regions formed in the semiconductor substrate 100.

[0059] Embodiments of the present invention form a semiconductor device structure having a gate stack and a spacer element located above the sidewalls of the gate stack. The upper portion of the spacer element and the gate stack is partially removed to form a groove above the gate stack and between the spacer elements. The groove has an upper portion that is wider than the lower portion of the groove. Thereafter, the remaining portion of the gate stack is removed. Thereafter, a metal gate stack is formed in the groove and then the metal gate stack is etched back. A covering element is formed above the metal gate stack and between the spacer elements. Due to the profile of the groove, the quality of the process of removing the remaining portion of the gate stack, forming the metal gate stack, etching back the metal gate stack, and forming the covering element is improved.

[0060] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate stack located above a semiconductor substrate and a covering element located above the gate stack. The covering element has an upper portion and a lower portion, and the upper portion is wider than the lower portion. The semiconductor device structure also includes a spacer element located above the sidewall of the covering element and the sidewall of the gate stack.

[0061] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate stack located above a semiconductor substrate. The semiconductor device structure also includes a covering element located above the gate stack, and the covering element has a first width close to the gate stack and a second width close to an upper portion of the covering element. The second width is greater than the first width. The semiconductor device structure also includes a spacer element located above a sidewall of the covering element and a sidewall of the gate stack.

[0062] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes: forming a gate electrode above a semiconductor substrate and forming a spacer element above the sidewall of the gate electrode. The method also includes: partially removing the gate electrode and the spacer element to form a groove between the spacer elements. The groove widens along the direction from the bottom of the groove toward the top of the groove. The method further includes removing the remaining portion of the gate electrode, thereby making the groove deeper. In addition, the method includes forming a metal gate stack in the groove after removing the remaining portion of the gate electrode. The method also includes forming a covering element above the metal gate stack and between the spacer elements.

[0063] According to some embodiments of the present invention, a semiconductor device structure is provided, including: a gate stack located above a semiconductor substrate; a covering element located above the gate stack, wherein the covering element has an upper portion and a lower portion, and the upper portion is wider than the lower portion; and a spacer element located above the sidewalls of the covering element and the sidewalls of the gate stack.

[0064] In the above semiconductor device structure, the gate stack includes a work function layer and a gate electrode surrounded by the work function layer.

[0065] In the above semiconductor device structure, the covering element is in direct contact with the work function layer or the gate electrode.

[0066] In the above semiconductor device structure, the gate electrode protrudes from the top surface of the work function layer.

[0067] In the above semiconductor device structure, the gate electrode penetrates into the covering member.

[0068] In the above semiconductor device structure, the cover element gradually narrows along a direction from a top of the cover element toward the gate stack.

[0069] In the above semiconductor device structure, the spacer element gradually becomes narrower in a direction from a bottom of the cover element toward a top of the spacer element.

[0070] In the above semiconductor device structure, the cover element is in direct contact with the spacer element.

[0071] In the above semiconductor device structure, the gate stack includes a gate dielectric layer, and the gate dielectric layer is in direct contact with the cover element.

[0072] In the above semiconductor device structure, there is an angle between an upper portion of the sidewall of the cover element and an imaginary plane extending from the sidewall of the gate stack toward the top of the cover element, and the angle is in a range from about 1 degree to about 10 degrees.

[0073] According to some other embodiments of the present invention, a semiconductor device structure is also provided, including: a gate stack located above a semiconductor substrate; a covering element located above the gate stack, wherein the covering element has a first width close to the gate stack and a second width close to an upper portion of the covering element, and the second width is greater than the first width; and a spacer element located above the sidewalls of the covering element and the sidewalls of the gate stack.

[0074] In the above semiconductor device structure, the cover member is made of a dielectric material.

[0075] In the above semiconductor device structure, the capping element is in direct contact with the gate stack and the spacer element.

[0076] In the above semiconductor device structure, the gate stack includes a work function layer and a gate electrode surrounded by the work function layer.

[0077] In the above semiconductor device structure, the cover member surrounds an upper portion of the gate electrode.

[0078] According to some further embodiments of the present invention, a method for forming a semiconductor device structure is also provided, comprising: forming a gate electrode above a semiconductor substrate; forming a spacer element above the side wall of the gate electrode; partially removing the gate electrode and the spacer element to form a groove between the spacer elements, wherein the groove widens along a direction from the bottom of the groove toward the top of the groove; removing the remaining portion of the gate electrode so that the groove becomes deeper; after removing the remaining portion of the gate electrode, forming a metal gate stack in the groove; and forming a covering element above the metal gate stack and between the spacer elements.

[0079] In the above method, the method further includes: before forming the covering element, etching back the metal gate stack.

[0080] In the above method, the metal gate stack includes a work function layer and a gate electrode surrounded by the work function layer, and after etching back the metal gate stack, the gate electrode protrudes from a top surface of the work function layer.

[0081] In the above method, partial removal of the gate electrode and the spacer element is performed in a first etching operation, and removal of the remaining portion of the gate electrode is performed in a second etching operation, and an etching rate of the first etching operation for the spacer element is higher than an etching rate of the second etching operation for the spacer element.

[0082] In the above method, a portion of the gate electrode is removed before the first etching operation and after the spacer element is formed.

[0083] The components of several embodiments are summarized above so that those skilled in the art can better understand various aspects of the present invention. Those of ordinary skill in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for achieving the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device structure, comprising: a gate stack located above the semiconductor substrate, the gate stack comprising a gate electrode and a gate dielectric layer surrounding the gate electrode, the highest surface of the gate electrode being higher than the highest surface of the gate dielectric layer, the gate electrode having a uniform width from the bottommost surface of the gate electrode to the highest surface of the gate electrode; a cover element located above the gate stack, wherein the cover element has an upper portion and a lower portion, and the upper portion is wider than the lower portion, sidewalls of the upper portion are inclined and a spacing between the sidewalls gradually decreases in a direction from a top of the upper portion toward a bottom, and a spacing between the sidewalls of the lower portion is uniform; and a spacer element located above the sidewalls of the cover element and the sidewalls of the gate stack, wherein the lower portion at least partially extends between an outer surface of the gate stack and an inner surface of the spacer element, In a cross-sectional view of the semiconductor device structure, the spacer element has an inner sidewall closest to the sidewall of the gate stack, the inner sidewall has a lower portion and an upper portion, the upper portion of the inner sidewall is inclined relative to the lower portion of the inner sidewall, the lower portion of the inner sidewall has an upper end portion connected to the upper portion of the inner sidewall, and the covering element extends downward beyond the upper end portion of the spacer element, wherein a sidewall of the gate stack closest to the upper end is spaced apart from the upper end, and at least a portion of the lower portion and the upper end are above the highest surface of the gate electrode, wherein the gate stack has a portion extending above a lowermost surface of the cover element, An angle is formed between an upper portion of the inner sidewall and an imaginary plane extending from the sidewall of the gate stack toward the top of the spacer element, and the angle remains constant.

2. The semiconductor device structure according to claim 1, wherein: The gate stack includes a work function layer surrounding the gate electrode.

3. The semiconductor device structure according to claim 2, wherein: The cover element is in direct contact with the work function layer or the gate electrode.

4. The semiconductor device structure according to claim 2, wherein: The gate electrode protrudes from a top surface of the work function layer.

5. The semiconductor device structure according to claim 4, wherein: The gate electrode penetrates into the cover member.

6. The semiconductor device structure according to claim 1, wherein: The cover element gradually narrows in a direction from a top of the cover element toward the gate stack.

7. The semiconductor device structure according to claim 1, wherein: The spacing element gradually narrows in a direction from a bottom of the covering element toward a top of the spacing element.

8. The semiconductor device structure according to claim 1, wherein: The cover element is in direct contact with the spacing element. 9 . The semiconductor device structure according to claim 1 , wherein the gate dielectric layer is in direct contact with the capping element.

10. The semiconductor device structure according to claim 1, wherein: The angle is in the range from 1 degree to 10 degrees.

11. A semiconductor device structure, comprising: a gate stack located above the semiconductor substrate, the gate stack comprising a gate electrode and a gate dielectric layer surrounding the gate electrode, the highest surface of the gate electrode being higher than the highest surface of the gate dielectric layer, the gate electrode having a uniform width from the highest surface of the gate dielectric layer to the highest surface of the gate electrode; a covering element located above the gate stack, wherein the covering element has a first width close to the gate stack and a second width close to an upper portion of the covering element, and the second width is greater than the first width, the covering element has an upper portion and a lower portion, the sidewalls of the upper portion are inclined and the spacing between the sidewalls gradually decreases in a direction from the top of the upper portion toward the bottom, and the spacing between the sidewalls of the lower portion is uniform; and a spacer element located above the sidewalls of the cover element and the sidewalls of the gate stack, wherein a lower portion of the cover element at least partially extends between an outer surface of the gate stack and an inner surface of the spacer element, In a cross-sectional view of the semiconductor device structure, the spacer element has an inner sidewall closest to the sidewall of the gate stack, the inner sidewall has a lower portion and an upper portion, the upper portion of the inner sidewall is inclined relative to the lower portion of the inner sidewall, the lower portion of the inner sidewall has an upper end portion connected to the upper portion of the inner sidewall, and the covering element extends downward beyond the upper end portion of the spacer element, wherein a sidewall of the gate stack closest to the upper end is spaced apart from the upper end, and at least a portion of the lower portion and the upper end are above the highest surface of the gate electrode, wherein the gate stack has a portion extending above a lowermost surface of the cover element, There is an angle between the upper portion of the inner sidewall and a virtual plane extending from the sidewall of the gate stack toward the top of the spacer element, and the angle remains unchanged.

12. The semiconductor device structure according to claim 11, wherein: The cover element is made of a dielectric material.

13. The semiconductor device structure according to claim 11, wherein: The capping element is in direct contact with the gate stack and the spacer element.

14. The semiconductor device structure according to claim 11, wherein: The gate stack includes a work function layer surrounding the gate electrode.

15. The semiconductor device structure according to claim 14, wherein: The cover member surrounds an upper portion of the gate electrode.

16. A method for forming a semiconductor device structure, comprising: forming a gate electrode over the semiconductor substrate; forming a spacer element over a sidewall of the gate electrode; Partially removing the gate electrode and the spacer element to form a first groove between the spacer elements, wherein the first groove widens in a direction from a bottom of the first groove toward a top of the first groove; removing a remaining portion of the gate electrode so that the first groove becomes deeper to form a second groove; After removing the remaining portion of the gate electrode, forming a metal gate stack in the second groove; and forming a covering element on the metal gate stack and between the spacer elements, wherein the covering element is in direct contact with the side surface of the first groove, and before the covering element, etching back the metal gate stack, wherein the lower portion of the covering element at least partially extends between the outer surface of the metal gate stack and the inner surface of the spacer element, the covering element having an upper portion and a lower portion, the sidewalls of the upper portion are inclined and the spacing between the sidewalls gradually decreases in a direction from the top of the upper portion toward the bottom, and the spacing between the sidewalls of the lower portion is uniform, In a cross-sectional view of the semiconductor device structure, the spacer element has an inner sidewall closest to the sidewall of the metal gate stack, the inner sidewall has a lower portion and an upper portion, the upper portion of the inner sidewall is inclined compared to the lower portion of the inner sidewall, and the lower portion of the inner sidewall has an upper end portion connected to the upper portion of the inner sidewall, wherein a sidewall of the metal gate stack closest to the upper end is spaced apart from the upper end, and the upper end is above the highest surface of the metal gate stack, The metal gate stack has a portion extending above the lowest surface of the covering element, and the metal gate stack includes a gate dielectric layer, a work function layer, and a gate electrode formed by etching back. Before the gate dielectric layer and the work function layer are formed by etching back, the space between the inclined upper portions of the inner sidewalls of the spacer element is filled with the gate dielectric layer, the work function layer and the gate electrode before etching back. Wherein, in the filled state, the highest top surface of the gate electrode is higher than the highest top surface of the spacer element.

17. The method according to claim 16, further comprising: in, An angle is formed between an upper portion of the inner sidewall and an imaginary plane extending from the sidewall of the gate stack toward the top of the spacer element, and the angle remains constant.

18. The method according to claim 17, wherein: The metal gate stack includes the work function layer and the gate electrode surrounded by the work function layer, and after etching back the metal gate stack, the gate electrode protrudes from a top surface of the work function layer.

19. The method according to claim 16, wherein: Partial removal of the gate electrode and the spacer element is performed in a first etching operation, and removal of the remaining portion of the gate electrode is performed in a second etching operation, and an etching rate of the first etching operation for the spacer element is higher than an etching rate of the second etching operation for the spacer element.

20. The method according to claim 19, wherein: Prior to the first etching operation and after forming the spacer elements, a portion of the gate electrode is removed.

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