Deep trench capacitors embedded in the package substrate

Abstract

The present disclosure relates to deep trench capacitors embedded in a package substrate. In some aspects, a chip package includes an integrated circuit die having a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit, and the substrate has a first surface on which the integrated circuit die is mounted, and a second surface opposite to the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by a conductor.

Description

Technical Field

[0001] The present disclosure relates to deep trench capacitors embedded in a packaging substrate. Background Art

[0002] Dynamic noise (di / dt) in processor cores and application-specific integrated circuits (ASICs) is becoming increasingly problematic due to faster core clock frequencies and higher circuit current consumption. di / dt represents the rate of change of current with respect to a load (e.g., the core of an ASIC). Faster core clock frequencies cause more transient current to flow, and therefore more noise. Additionally, higher di / dt noise results in higher voltage losses in the power supplied to the circuit. Summary of the invention

[0003] This specification describes technology related to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted.

[0004] Generally, an innovative aspect of the subject matter described in this specification can be embodied in a chip package, the chip package comprising: an integrated circuit die, the integrated circuit die comprising a power distribution circuit, the power distribution circuit being used for one or more circuits in the integrated circuit; a substrate, the substrate being different from the integrated circuit and having (i) a first surface, on which the integrated circuit die is mounted, and (ii) a second surface, the second surface being opposite to the first surface, the substrate comprising one or more cavities, the one or more cavities being formed in at least one of the first surface or the second surface; and one or more deep trench capacitors, the one or more deep trench capacitors being disposed in at least one of the one or more cavities, each deep trench capacitor being connected to the power distribution circuit by a conductor.

[0005] These and other embodiments can each optionally include one or more of the following features. In some aspects, each cavity is formed on the first surface and extends from the first surface into the substrate.

[0006] In some aspects, each cavity is formed on the second surface and extends from the second surface into the substrate. In some aspects, each cavity and each deep trench capacitor is arranged below the power distribution circuit. In some aspects, the substrate includes a through hole for each conductor, and the conductor is arranged to pass from the deep trench capacitor through the substrate in the through hole to a contact of the integrated circuit die. In some aspects, the one or more cavities include a plurality of cavities, and the substrate includes a substrate wall between adjacent cavities.

[0007] In some aspects, each cavity is formed on the second surface and extends from the second surface into the substrate. The second surface may include a ball grid array with a plurality of interconnect pads, each interconnect pad extending from the second surface to an end of the interconnect pad. Each deep trench capacitor may extend out of a corresponding cavity without extending beyond an end of the interconnect pad.

[0008] Generally, another aspect of the subject matter described in this specification can be embodied in a method for manufacturing a chip package. The method includes: forming one or more cavities in a substrate, the substrate having (i) a first surface, the first surface configured to receive an integrated circuit die, and (ii) a second surface, the second surface opposite the first surface, each cavity formed in at least one of the first surface or the second surface; mounting one or more deep trench capacitors in each cavity; and mounting the integrated circuit die on the first surface.

[0009] These and other embodiments can optionally include one or more of the following features. In some aspects, each cavity is formed in the first surface. Forming the one or more cavities includes applying one or more substrate build-up pieces to the first surface after installing the one or more deep trench capacitors in each cavity.

[0010] In some aspects, each deep trench capacitor is electrically connected to the integrated circuit through a via formed in the substrate. In some aspects, forming the one or more cavities includes etching away a portion of the substrate.

[0011] In some aspects, each cavity is formed in the first surface, and before the integrated circuit is mounted on the first surface, the deep trench capacitor is connected to the integrated circuit die; mounting the integrated circuit die on the first surface and mounting the one or more deep trench capacitors in each cavity includes: mounting the integrated circuit die so that each deep trench capacitor is disposed within a cavity.

[0012] In some aspects, forming the one or more cavities includes: applying a release layer to the first surface; applying one or more buildup layers over the release layer; and removing the release layer and each portion of each buildup layer covering the release layer. Applying the release layer may include applying the release layer over the portion of the first surface where the cavity is to be formed.

[0013] Generally, another aspect of the subject matter described in this specification can be embodied in a chip package, the chip package comprising: an integrated circuit die; a substrate having (i) a first surface on which the integrated circuit die is mounted, and (ii) a second surface opposite to the first surface, the substrate comprising one or more cavities formed in at least one of the first surface or the second surface; and one or more capacitors disposed in at least one of the one or more cavities and connected to the integrated circuit die.

[0014] These and other embodiments may optionally include one or more of the following features. In some aspects, the one or more capacitors include deep trench capacitors. In some aspects, the one or more capacitors decouple one or more circuits of the integrated circuit die from a power supply circuit of the integrated circuit die.

[0015] In some aspects, each cavity is formed on the first surface and extends from the first surface into the substrate. In some aspects, each cavity is formed on the second surface and extends from the second surface into the substrate. In some aspects, each cavity and each deep trench capacitor is arranged below the power distribution circuit.

[0016] The subject matter described in this specification can be implemented in a specific embodiment to achieve one or more of the following advantages. By embedding deep trench capacitors in the substrate of the chip package, rather than on the integrated circuit die, the number of decoupling capacitors can be increased without increasing the size of the die. This can reduce dynamic noise (di / dt) to a greater extent without increasing the size of the die, and can reduce the voltage drop caused by noise to a greater extent. The deep trench capacitor can be embedded on the side of the substrate on which the die is mounted or on the opposite side, thereby providing flexibility based on the frequency of load changes that cause noise. For example, due to the shorter conductor between the capacitor and the die, the inductance increase relative to the farther capacitor is less, so the deep trench capacitor embedded closer to the die can be smaller and lower in capacitance to address higher frequency noise. Since higher capacitance and higher inductance lead to lower resonant frequencies, embedding the deep trench capacitor on the opposite side of the substrate can allow larger capacitors with higher capacitance to address lower frequency noise.

[0017] Various features and advantages of the foregoing subject matter are described below with reference to the accompanying drawings. Other features and advantages will be apparent from the subject matter described herein and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1is a cross-sectional view of an example integrated circuit (IC) package including the IC and a deep trench capacitor embedded in a substrate of the IC package.

[0019] Figure 2 is a diagram of an example process for manufacturing an IC package that includes an IC and a deep trench capacitor embedded in a substrate of the IC package.

[0020] Figure 3 is a cross-sectional view of another example IC package including an IC and a deep trench capacitor embedded in a substrate of the IC package.

[0021] Figure 4 is a diagram of an example process for manufacturing an IC package that includes an IC and a deep trench capacitor embedded in a substrate of the IC package.

[0022] Figure 5 is a cross-sectional view of another example IC package including an IC and a deep trench capacitor embedded in a substrate of the IC package.

[0023] Figure 6 is a diagram of an example arrangement of cavities for a deep trench capacitor.

[0024] Figure 7 is a diagram of an example arrangement of cavities for a deep trench capacitor.

[0025] Figure 8 is a diagram of another example arrangement of cavities for a deep trench capacitor.

[0026] Like reference numerals and designations in the various drawings refer to like elements. DETAILED DESCRIPTION

[0027] Generally, this document describes techniques involving deep trench capacitors embedded in a package substrate on which an integrated circuit (IC) is mounted. By adding decoupling capacitors to the chip package, di / dt noise caused by higher core clock frequencies and higher current consumption of high-performance ICs can be suppressed. However, due to the limited physical space of the die size of the chip, the ability to maintain decoupling capacitors added to the die to offset the additional noise generated by faster clock frequencies and higher current consumption is limited.

[0028] The chip package described in this document includes a decoupling capacitor in the form of a deep trench capacitor that is embedded in a package substrate on which an IC is mounted, rather than in the IC itself. For example, the IC can be mounted to one side of the substrate, and the other side of the substrate can include a ball grid array (BGA) for connecting the package to a printed circuit board (PCB). The package substrate can include one or more cavities on one or both sides of the package substrate. The deep trench capacitor can be disposed in a cavity, for example, and attached to the substrate or the die itself.

[0029] Typically, a trench capacitor is a capacitor formed by the following steps: etching one or more trenches into a substrate or wafer; forming an external or buried plate electrode around and below the trench; forming a dielectric layer by covering the external or buried plate electrode with a dielectric material; and forming an internal or upper electrode on the dielectric layer. A deep trench capacitor is a trench capacitor whose trench has an aspect ratio (ratio of depth to width) that meets or exceeds a threshold, or the depth of the trench meets or exceeds a threshold. For example, the aspect ratio of a deep trench capacitor can be about 5 to 10, but can vary. The height of a deep trench capacitor can also vary, but the height is typically about 64 microns (μm)-80 microns. Although the following description is primarily for deep trench capacitors, other types of capacitors can also be used.

[0030] Figure 1 1 is a cross-sectional view of an example IC package 100 including an IC 110 and a deep trench capacitor 170 embedded in a substrate 130 of the IC package 100. The IC package 100 includes: a substrate 130; an IC 110 mounted on the substrate 130; and a BGA ball 160 including interconnect pads with solder balls for connecting the IC package 100 to a PCB. The IC 110 may be an ASIC or other suitable type of IC.

[0031] In this example, IC package 100 is a flip chip package in which solder bumps 120 are used to connect interconnect pads of IC 110 to substrate 130. Solder bumps 120 include contact areas (e.g., pads) of IC 110 and solder balls that are used to connect the contact areas to corresponding contact areas (e.g., pads) of substrate 130. Figure 1 Although not shown, substrate 130 may include vias that connect contact areas of IC 110 to interconnect pads of BGA balls 160 .

[0032] The substrate 130 includes a substrate core 132 and substrate stacking pieces 131 and 133 on both sides of the substrate core 132. For example, when manufacturing the IC package 100, one or both of the substrate stacking pieces 131 and 133 can be added to the substrate core 132. In some embodiments, the substrate 130 includes only one of the substrate stacking pieces 131 or 133 or no substrate stacking piece. For example, the substrate 130 can include the substrate stacking piece 131 or 133 only on one side of the substrate core 132 that will include the cavity for the deep trench capacitor.

[0033] The substrate 130 includes a cavity 134 for a deep trench capacitor 170. In this example, the cavity 134 is formed in the substrate stack 131 on the top side of the substrate 130. After the deep trench capacitor 170 is mounted on the surface of the substrate 130 (e.g., on the surface of the substrate core 132 or the substrate stack 131), the cavity 134 can be formed by etching away a portion of the substrate stack 131 or by adding a laminate substrate around the deep trench capacitor 170. If etching is used, the deep trench capacitor 170 can be mounted in the cavity 134 after the cavity 134 is formed. The cavity 134 can also be formed using mechanical grinding or removing the stacked film after laser ablation. The deep trench capacitor 170 can be mounted in the cavity using, for example, pick and place and / or flip chip assembly techniques.

[0034] exist Figure 1 An example deep trench capacitor 170 is shown in FIG. However, many different types of deep trench capacitors may be used. In this example, the deep trench capacitor is a higher density silicon capacitor formed using a silicon wafer 173. The deep trench capacitor 170 includes two trenches 177A and 177B, but other deep trench capacitors may include a single trench or more than two trenches. The trenches 177A and 177B may be formed by etching away the silicon wafer 173.

[0035] The deep trench capacitor 170 includes an oxide liner 172 and four electrodes 171A-171D. The oxide liner 172 covers the walls and bottoms of the trenches 177A and 177B. The first electrode 171A covers the oxide liner 172. The first dielectric 176A covers the first electrode 171A, and the second electrode 171B covers the first dielectric 176A. That is, the first dielectric 176A is disposed between the first electrode 171A and the second electrode 171B and separates them.

[0036] The second dielectric 176B covers the second electrode 171B, and the third electrode 171C covers the second dielectric 176B, so that the second dielectric 176B is disposed between the second electrode 171B and the third electrode 171C and separates them. Similarly, the third dielectric 176C covers the third electrode 171C, and the fourth electrode 171D covers the third dielectric 176C, so that the third dielectric 176C is disposed between the third electrode 171C and the fourth electrode 171D and separates them. The electrodes 171A-171D are made of a conductive material, and the dielectrics 176A-176C are made of an insulating material.

[0037] The first electrode 171A and the third electrode 171C are both connected to the contact 174. Similarly, the second electrode 171B and the fourth electrode 171D are both connected to the contact 175. The contacts 174 and 175 of each deep trench capacitor 170 are electrically connected to the IC 110. For example, the contacts 174 and 175 of each deep trench capacitor 170 may be connected to the core power distribution circuit of the IC 110.

[0038] Each contact 174 and 175 may be connected to IC 110 using vias of substrate 130 and contact areas of IC 110. A via is a conductive hole in substrate 130. Since these conductive holes may add inductance to the circuits to which deep trench capacitor 170 is connected, deep trench capacitor 170 may be placed close to those circuits of IC 110 to reduce the amount of added inductance. In this example, deep trench capacitor 170 is located below core power distribution circuit 121 of IC 110, which distributes power to the core or other circuits of IC 110. Deep trench capacitor 170 may be connected in parallel with the core (or other circuits) of IC 110 in core power distribution circuit 121 to decouple these circuits from core power distribution circuit 121 and reduce di / dt noise applied to the circuits.

[0039] In order to make the deep trench capacitor 170 more efficient, the path connecting the deep trench capacitor 170 should be the path with the least resistance / inductance among the possible paths. The closest location with parallel vias / traces / planes may be preferred for capacitor mounting.

[0040] IC package 100 may include various numbers of deep trench capacitors 170. In this example, IC package 100 includes a single cavity 134 that includes three deep trench capacitors 170. In other examples, substrate 130 may include multiple cavities that each include one or more deep trench capacitors. Figures 6 to 8 Some example arrangements of substrate cavities are shown in and described below.

[0041] The number of deep trench capacitors 170, the size of the deep trench capacitors 170 (and therefore the size of the cavity 134), and the location of the deep trench capacitors 170 may be selected based on the IC 110 and its configuration or noise characteristics. These capacitors may be located on the bottom side of the substrate 130 (the side with the substrate stackup 133) because the bottom side of the substrate 130 may have more room for larger deep trench capacitors than the top side of the substrate 130 (the side with the stackup 131). For applications with higher noise frequencies, the deep trench capacitors may be located closer to the top side of the IC 110.

[0042] Figure 2 is a diagram illustrating an example process 200 for fabricating an IC package including an IC and a deep trench capacitor embedded in a substrate of the IC package. The example process 200 may be performed using IC package fabrication equipment.

[0043] A deep trench capacitor 270 is mounted on a substrate 230 (201). The substrate 230 includes a substrate core 232 and substrate stacks 231 and 233 on both sides of the substrate core 232. In this example, the deep trench capacitor 270 is mounted on the substrate stack 231 located on the top of the substrate core 232 and on the side of the substrate 230 where the IC is to be mounted.

[0044] A first buildup layer 280 is applied to a surface (202) of substrate buildup 231. The buildup layer 280 may be a laminate material. The buildup layer 280 may be applied to the entire surface of substrate buildup 231, including between adjacent deep trench capacitors 270.

[0045] A second buildup layer 282 is applied to the first buildup layer 280, and a through hole (203) is formed in the buildup layers 280 and 282. The second buildup layer 282 may also be a laminate. Through holes (including through holes 290 and 291) may be formed by drilling away (e.g., mechanically or using a laser) some laminate or other buildup material and adding a conductive material to the drilled hole. These through holes may be used to connect other through holes of the substrate 230 (e.g., through holes for arranging interconnect pads of a BGA) to contact areas of an IC mounted on the substrate 230. For example, each through hole may include a conductive pad on the top surface of the buildup layer 282, which will be connected to the contact area of ​​the IC using, for example, a solder ball of the IC. In this way, the surface of the substrate 230 is configured to receive the IC.

[0046] The vias may also include vias that connect the deep trench capacitor 270 to the IC. For example, a via may be disposed over the deep trench capacitor 270 to connect a contact of the deep trench capacitor 270 to the IC.

[0047] IC 210 is mounted on substrate 230 (204). IC 210 includes bumps 220 (e.g., controlled collapse chip connection (C4) bumps, solder bumps, or copper bumps) for mounting IC 210 on a surface of substrate 230 formed by second buildup layer 282. Bumps 220 include contact areas (e.g., pads) of IC 210 and solder or copper pillars for connecting the contact areas to corresponding contact areas (e.g., pads) of substrate 230. IC 210 may be placed onto the surface of substrate 230 such that bumps 220 are over corresponding contact areas on the surface of substrate 230. Bumps 220 may then be heated and cooled to form bonds between the contact areas of IC 210 and their corresponding contact areas of the surface of substrate 230.

[0048] Similar to Figure 1 The IC package 100 formed using the process 200 results in a flip chip package with a deep trench capacitor 270 located below the core power distribution circuit 221 of the IC 210 to reduce the inductance path of the via. Solder balls may also be formed on the BGA 260 on the bottom surface of the substrate 230.

[0049] Figure 3 3 is a cross-sectional view of another example IC package 300, which includes an integrated circuit 310 and a deep trench capacitor 370 embedded in a substrate 330 of the IC package 300. The IC package 300 includes: a substrate 330; an IC 310 mounted on the substrate 330; and a BGA ball 360, which includes an interconnect pad with a solder ball for connecting the IC package 300 to a PCB. The IC 310 may be an ASIC or other suitable type of IC.

[0050] In this example, IC package 300 is a flip chip package in which solder bumps 320 are used to connect interconnect pads of IC 310 to substrate 330. Solder bumps 320 include contact areas (e.g., pads) of IC 310 and solder balls that are used to connect the contact areas to corresponding contact areas (e.g., pads) of substrate 330. Figure 3 Not shown, but substrate 330 may include vias that connect contact areas of IC 310 to interconnect pads of BGA balls 360 .

[0051] Similar to Figure 11 , the substrate 330 includes a substrate core 332 and substrate stacking pieces 331 and 333 on both sides of the substrate core 332. For example, when manufacturing the IC package 300, one or both of the substrate stacking pieces 331 and 333 can be added to the substrate core 332. In some embodiments, the substrate 330 includes only one of the substrate stacking pieces 331 or 333 or no substrate stacking piece. For example, the substrate 330 can include the substrate stacking piece 331 or 333 only on one side of the substrate core 332 that will include the cavity for the deep trench capacitor.

[0052] Substrate 330 includes a cavity 334 for a deep trench capacitor 370. Cavity 334 is formed in substrate stack 331 on the top side of substrate 330. Cavity 334 may be formed by etching away a portion of substrate stack 331. In this example, deep trench capacitor 370 is mounted on IC 310, rather than being mounted in cavity 334 and connected to IC 310. Instead, cavity 334 provides space for deep trench capacitor 370 within substrate 330. Cavity 334 may be sized and shaped to accommodate deep trench capacitor 370 attached to IC 310.

[0053] Deep trench capacitor 370 (which may be Figure 1 The deep trench capacitor 370 (same or similar to the deep trench capacitor 170 of the IC 310) may include contacts electrically connected to contact areas (e.g., pads) of the IC 310. For example, the deep trench capacitor 370 may be soldered to the IC 310 using bumps 320 (e.g., C4 bumps) before the IC 310 is mounted on the substrate 310.

[0054] Figure 4 is a diagram of an example process 400 for manufacturing an IC package that includes an IC and a deep trench capacitor embedded in a substrate of the IC package. The example process 400 may be performed using IC package manufacturing equipment.

[0055] A release layer 435 is applied to substrate 430 (401). Substrate 430 includes a substrate core 432 and substrate stacks 431 and 433 on both sides of substrate core 432. Release layer 435 can be applied to each area of ​​the top surface of substrate stack 431 where a cavity will be formed. In this example, the cavity will be formed in the center of the top surface of substrate stack 431.

[0056] The release layer 435 may be made of a material that is less adhesive than other portions of the substrate 430. In this way, when the block is later removed from the substrate for the cavity structure, the release layer 435 may be easily peeled off.

[0057] Buildup layers 436 and 437 are applied to the surface (402) of substrate buildup 431. These buildup layers 436 and 437 can be laminated materials. Buildup layer 436 can be applied to the entire surface of substrate buildup 431 and above release layer 435. In addition, through holes are formed in buildup layers 436 and 437. These through holes (including through holes 490 and 491) can be formed by drilling away (e.g., mechanically or using a laser) some laminated materials or other buildup materials and adding conductive materials to the drilled holes. These through holes can be used to connect other through holes of substrate 430 (e.g., through holes for arranging interconnection pads of BGA) to contact areas of ICs mounted on substrate 430. For example, each through hole can include a conductive pad on the top surface of buildup layer 437, which will be connected to the contact area of ​​the IC using, for example, the solder ball of the IC.

[0058] A cavity 434 (403) is formed. The cavity 434 can be formed by removing the release layer 435 and portions 436A and 437A of the buildup layers 436 and 437 formed above the release layer 435, respectively. For example, laser ablation can be used to remove the release layer 435 and portions 436A and 437A of the buildup layers 436 and 437. A laser can be applied to the edges of the release layer 435 and between the edges to remove material. In another example, etching or another suitable technique can be used to remove the release layer 435 and portions 436A and 437A of the buildup layers 436 and 437.

[0059] IC 410 is mounted on substrate 430 (404). In this example, IC 410 includes a deep trench capacitor 470 attached to IC 410. IC 410 can be mounted such that deep trench capacitor 470 is disposed in cavity 434. Cavity 434 can be formed to be deep enough and wide enough to accommodate deep trench capacitor 470. Deep trench capacitor 470 can extend into cavity 434 and contact or not contact the bottom surface of cavity 434.

[0060] IC 410 also includes bumps 420 (e.g., C4 bumps) for mounting IC 410 to a surface of substrate 430 formed by second buildup layer 437. Bumps 420 include contact areas (e.g., pads) of IC 410 and solder balls for connecting the contact areas to corresponding contact areas (e.g., pads) of substrate 430. IC 410 may be placed onto the surface of substrate 430 such that bumps 420 are over corresponding contact areas on the surface of substrate 430. Bumps 420 may then be heated and cooled to form bonds between the contact areas of IC 410 and their corresponding contact areas on the surface of substrate 430.

[0061] Similar to Figure 3The IC package 300 formed using process 400 results in a flip chip package with a deep trench capacitor 470 attached to IC 410 and embedded in cavity 434 of the package substrate. Solder balls may also be formed on BGA balls 460 on the bottom surface of substrate 430.

[0062] Figure 5 5 is a cross-sectional view of another example IC package 500, which includes an IC 510 and a deep trench capacitor 570 embedded in a substrate 530 of the IC package 500. The IC package 500 is similar to Figure 1 IC package 100, except that deep trench capacitor 570 is embedded on the opposite side of the substrate. In this example, deep trench capacitor 570 is embedded in cavity 534 formed on the same side of substrate 530 as the interconnect pads of BGA ball 560. As described above, this configuration may be preferred when larger (e.g., higher) capacitors and higher capacitance are needed or desired for lower bandwidth (BW) requirements.

[0063] IC package 500 includes a substrate 530, an IC 510 mounted on substrate 530, and BGA balls 560 including interconnect pads with solder balls for connecting IC package 500 to a PCB. IC 510 may be an ASIC or other suitable type of IC.

[0064] In this example, IC package 500 is a flip chip package in which bumps 520 (e.g., C4 bumps) are used to connect interconnect pads of IC 510 to substrate 530. Solder bumps 520 include contact areas (e.g., pads) of IC 510 and solder balls that are used to connect the contact areas to corresponding contact areas (e.g., pads) of substrate 530. Figure 5 Not shown, but substrate 530 may include vias that connect contact areas of IC 510 to interconnect pads of BGA balls 560 .

[0065] Similar to Figure 1 130, the substrate 530 includes a substrate core 532 and substrate stacking pieces 531 and 533 on both sides of the substrate core 532. For example, when manufacturing the IC package 500, one or both of the substrate stacking pieces 531 and 533 can be added to the substrate core 532. In some embodiments, the substrate 530 includes only one of the substrate stacking pieces 531 or 533 or no substrate stacking piece. For example, the substrate 530 can include the substrate stacking piece 531 or 533 only on one side of the substrate core 532 that will include the cavity for the deep trench capacitor.

[0066] The substrate 530 includes a cavity 534 for a deep trench capacitor 570. The cavity 534 is formed in a substrate stack 533 on the bottom side of the substrate 530. The cavity 534 can be formed by etching away a portion of the substrate stack 533. The cavity 534 can be sized to fit the deep trench capacitor 570. For example, based on the BGA ball 560 and the PCB on which the IC package 500 is to be mounted, the distance that the capacitor 570 can extend from the bottom surface of the substrate 530 can be limited. The cavity 534 can have a depth that prevents the deep trench capacitor 570 from extending out of the cavity 534 and beyond the bottom surface of the substrate 530, or the depth can be such that the deep trench capacitor 570 does not extend beyond the depth allowed by the BGA ball 560 and PCB requirements.

[0067] The deep trench capacitor 570 can be connected with Figure 1 The substrate 530 may include through-holes that connect the deep trench capacitors 570 to conductive pads on the top surface of the substrate 530 that connect to contact areas of the IC 510. To reduce the length of such through-holes, the cavity and deep trench capacitors 570 may be located below (e.g., directly below) the core power distribution circuit 521 of the IC 510 that distributes power to the core or other circuits of the IC 510. In this way, the additional inductance caused by the through-holes is reduced, resulting in less high frequency di / dt noise and less corresponding voltage loss. However, because it allows for greater capacitance, it can address lower frequency di / dt noise and corresponding voltage loss.

[0068] Each of the above IC packages may include multiple cavities, for example, to embed more capacitors and offset more package inductance. In other cases, a single cavity may be used to embed a deep trench capacitor. Figures 6 to 8 Some example arrangements of cavities that may be formed in a substrate and used in the IC packages described above are shown in FIG.

[0069] Figure 6 6 is a diagram of an example arrangement 600 of a cavity 630 for a deep trench capacitor. In this example, the cavity 630 is located at the center of the surface of the substrate 610. The cavity 630 can be formed on the side of the substrate on which the IC is mounted, or on the side of the substrate that is connected to another component (e.g., to a PCB). The cavity 630 is also directly below the core power distribution circuit area 620 of the IC (or other circuit area to be decoupled). The cavity 630 can include one or more deep trench capacitors.

[0070] Figure 77 is a diagram of an example arrangement 700 of cavities 730A-730C for a deep trench capacitor. In this example, there are three cavities 730A-730C near the center of the surface of the substrate 710. However, other numbers of cavities may also be used.

[0071] The cavities 730A-730C may be formed on the side of the substrate on which the IC is mounted, or on the side of the substrate that is connected to another component (e.g., to a PCB). The cavities 730A-730C are also directly below the core power distribution circuit area 720 (or other circuit area to be decoupled) of the IC. Each cavity 730A-730C may include one or more deep trench capacitors.

[0072] Figure 8 is a diagram of another example arrangement 800 of cavities for a deep trench capacitor. In this example, there are six cavities 830A-830F near the center of the surface of the substrate 810. However, other numbers of cavities may also be used.

[0073] Cavities 830A-830F may be formed on the side of the substrate on which the IC is mounted, or on the side of the substrate that is connected to another component (e.g., to a PCB). Cavities 830A-830C are also located directly below the core power distribution circuit area 820 (or other circuit area to be decoupled) of the IC. Each cavity 830A-830C may include one or more deep trench capacitors.

[0074] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on any invention or the scope of protection that can be claimed, but rather as descriptions of specific features of specific embodiments of specific inventions. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination. Moreover, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features in the claimed combination may be removed from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0075] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a continuous order, or that all of the operations shown be performed to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of the various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0076] Thus, specific embodiments of the present subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired results. Additionally, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

Claims

1. A chip package, comprising: an integrated circuit die including a power distribution circuit configured to control distribution of power to one or more circuits of the integrated circuit die, the integrated circuit die including one or more capacitors extending from a surface of the integrated circuit die including interconnect pads, each capacitor connected to the power distribution circuit by a conductor in a manner that decouples the one or more circuits of the integrated circuit die from the power distribution circuit; as well as a substrate different from the integrated circuit die and having (i) a first surface on which the integrated circuit die is mounted via the interconnect pads of the integrated circuit die, and (ii) a second surface opposite the first surface, the substrate comprising one or more cavities formed in the first surface, each cavity extending from the first surface into the substrate to a third surface between the first surface and the second surface, and each cavity being configured to receive at least one of the one or more capacitors when the integrated circuit die is mounted on the first surface of the substrate, wherein each of the one or more cavities and each of the one or more capacitors are disposed below a core power distribution region of the integrated circuit die including the power distribution circuit, and The core power distribution area is a partial area of ​​the integrated circuit die that includes the power distribution circuit.

2. The chip package according to claim 1, wherein: Further comprising at least one additional cavity formed on the second surface and extending from the second surface into the substrate, wherein each additional cavity comprises an additional capacitor extending from a fourth surface of the substrate beyond the second surface, wherein the fourth surface is located between the first surface and the second surface.

3. The chip package according to claim 2, wherein: The substrate includes a through-hole in which a conductor is routed from at least one additional capacitor through the substrate to a contact of the integrated circuit die.

4. The chip package according to claim 1, wherein: The one or more cavities include a plurality of cavities; and The substrate includes substrate walls between adjacent cavities.

5. The chip package according to claim 1, further comprising: additional cavities formed on the second surface and extending from the second surface into the substrate to a fourth surface between the first surface and the second surface, wherein each additional cavity includes an additional capacitor extending from the fourth surface of the substrate beyond the second surface, wherein the fourth surface is located between the first surface and the second surface; The second surface includes a ball grid array with a plurality of interconnect pads, each interconnect pad extending from the second surface to an end of the interconnect pad; and Each additional capacitor extends out of the additional cavity without extending beyond ends of the plurality of interconnect pads.

6. The chip package according to claim 1, wherein: Each of the one or more capacitors is connected in parallel with the one or more circuits.

7. The chip package according to claim 1, wherein: The one or more circuits include a processor core.

8. The chip package according to claim 1, wherein: A conductor connects each capacitor to the power distribution circuit using a least resistance path among a plurality of available paths.

9. The chip package according to claim 1, wherein: The one or more capacitors are not coupled to the substrate.

10. The chip package according to claim 1, wherein: The one or more capacitors include an oxide liner covering a surface of the one or more cavities.

11. The chip package according to claim 10, wherein: The oxide liner of the one or more capacitors further includes a layer of conductive material disposed on the oxide liner.

12. The chip package according to claim 11, wherein: The conductive material layer disposed on the oxide liner further includes an insulating material layer disposed on the conductive layer.

13. The chip package according to claim 1, wherein: The substrate further includes one or more substrate buildup layers and a substrate core, wherein the one or more substrate buildup layers are disposed on both sides of the substrate core.

14. The chip package according to claim 13, wherein: The one or more cavities are formed in at least one of the one or more substrate buildup layers.

15. The chip package according to claim 1, wherein: The one or more capacitors are mounted into the one or more cavities using at least one of (i) flip chip assembly or (ii) pick and place assembly.

16. A chip package, comprising: An integrated circuit die comprising (i) a core power distribution region, the core power distribution region comprising a portion of the integrated circuit die having a power distribution circuit, the power distribution circuit configured to distribute power to one or more circuits of the integrated circuit die, (ii) an additional circuit region located outside the core power distribution region; a substrate having (i) a first surface on which the integrated circuit die is mounted, and (ii) a second surface opposite the first surface, the substrate comprising one or more cavities formed in the second surface, each cavity extending from the second surface into the substrate to a third surface between the first surface and the second surface; as well as one or more capacitors disposed in at least one of the one or more cavities and connected to the integrated circuit die, wherein the one or more capacitors decouple additional circuitry of the additional circuit area from the power distribution circuitry, and wherein each capacitor extends from the third surface beyond the second surface, Wherein each of the one or more cavities and each of the one or more capacitors are disposed below the core power distribution area of ​​the integrated circuit die.

17. The chip package according to claim 16, wherein: The one or more capacitors include deep trench capacitors.

18. The chip package of claim 17, wherein the conductor connects each capacitor to the power distribution circuit using a least resistance path among a plurality of available paths. 19 . The chip package of claim 16 , further comprising an additional cavity formed on the first surface and extending from the first surface into the substrate to a fourth surface between the first surface and the second surface.

20. The chip package according to claim 16, wherein: Each of the one or more capacitors is connected in parallel with the one or more circuits.

21. The chip package according to claim 16, wherein: The one or more circuits include a processor core.

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