Semiconductor devices

Abstract

The present invention prevents heat concentration. The arm portion (2) comprises: a first circuit pattern (5a) which is concave in a plan view and is provided with a back surface of a first semiconductor chip (6, 7); and a second circuit pattern (5b) which is at least partially provided in a first configuration area (5a1) formed by a depression of the first circuit pattern (5a) in a plan view, and is electrically connected to a first negative electrode (6b, 7b) in the first configuration area (5a1) through a connected first wiring component (8b, 8c). As a result, the first semiconductor chips (6, 7) provided in the first circuit pattern (5a) are not concentrated in the central portion of the laminated substrate (3), but are located in the outer periphery of the laminated substrate (3). Therefore, the heat generated in the laminated substrate (3) can be dispersed and the heat dissipation can be improved.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Semiconductor devices include semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), FWDs (Free Wheeling Diodes), and SBDs (Schottky Barrier Diodes). Such semiconductor devices have multiple semiconductor units comprising the aforementioned semiconductor elements and a heat sink disposed thereon. Such semiconductor devices can perform desired functions (e.g., see Patent Document 1).

[0003] The power conversion device is implemented by arranging, for example, IGBTs and FWDs on a substrate (see, for example, Patent Document 2). In this case, in order to make efficient use of the substrate area, IGBTs and FWDs with different chip sizes are arranged in the center of the substrate, and then the IGBTs and FWDs are arranged alternately vertically.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: US Patent No. 5,527,620

[0007] Patent Document 2: Japanese Patent Application Publication No. 2018-125494 Summary of the Invention

[0008] Technical issues

[0009] To effectively configure IGBTs and FWDs of different chip sizes as described above within a limited area of ​​the substrate, they need to be arranged in a concentrated manner to suppress ineffective areas. Furthermore, optimal configuration of external terminals and interconnects must be considered for the substrate. Therefore, the IGBTs and FWDs are necessarily located in the central portion of the substrate. However, this concentrated placement of IGBTs and FWDs in the central portion of the substrate leads to concentrated heat generation. Consequently, the rated current of the semiconductor device may be affected, making it difficult to enhance the characteristics of the semiconductor device.

[0010] The present invention was made in view of the following circumstances, and its object is to provide a semiconductor device capable of preventing heat concentration.

[0011] Technical solution

[0012] According to one aspect of the present invention, a semiconductor device is provided, having a first arm comprising: a first semiconductor chip having a first positive electrode on a back side and a first negative electrode and a first control electrode on a front side; a first circuit pattern having a concave shape when viewed from above and having the first positive electrode disposed thereon; and a second circuit pattern having at least a portion disposed in a first configuration area formed by the concavity of the first circuit pattern when viewed from above, and being electrically connected to the first negative electrode in the first configuration area via a connected first wiring member.

[0013] Invention Effects

[0014] According to the disclosed technology, heat concentration can be prevented and the characteristics of semiconductor devices can be improved.

[0015] The above and other objects, features and advantages of the invention will become clearer from the following description in conjunction with the accompanying drawings, which illustrate preferred embodiments as examples of the invention. Attached Figure Description

[0016] Figure 1 This is a diagram illustrating the arm portion included in the semiconductor device of the first embodiment.

[0017] Figure 2 This is a top view of the semiconductor device according to the second embodiment.

[0018] Figure 3 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0019] Figure 4 This is a circuit configuration diagram of the semiconductor device according to the second embodiment.

[0020] Figure 5 This is a diagram illustrating the flow of current in the semiconductor device according to the second embodiment.

[0021] Figure 6 It is a diagram used to illustrate a semiconductor device for reference and the flow of current in the semiconductor device.

[0022] Symbol Explanation

[0023] 1,10 Semiconductor devices

[0024] 2. Arm

[0025] 3-layer substrate

[0026] 4 substrate

[0027] 5a First Circuit Pattern

[0028] 5a1 First Configuration Area

[0029] 5b Second Circuit Pattern

[0030] 6,7 First Semiconductor Chip

[0031] 6a, 7a First control electrode

[0032] 6b, 7b First negative electrode

[0033] 8a~8e Wiring components

[0034] 20 First Arm

[0035] 21,31 Ceramic circuit board

[0036] 22,32 Insulation Board

[0037] Circuit patterns 23a~23d, 33a~33e

[0038] 23a1 First Configuration Area

[0039] 33a1 Second Configuration Area

[0040] 24,34 metal plates

[0041] 25, 26, 35, 36 Semiconductor chips

[0042] 25a, 26a, 35a, 36a gate electrodes

[0043] 25b, 26b, 35b, 36b Emitting Electrodes

[0044] 27a~27j, 37a~37i bond wires

[0045] 30 Second arm

[0046] 40 Housing

[0047] 41 Frame

[0048] 42 Storage Area

[0049] 43~45 External terminal section Detailed Implementation

[0050] [First Implementation Method]

[0051] The following, with reference to the attached diagram, uses Figure 1 The arm portion included in the semiconductor device of the first embodiment will be described. Figure 1 This is a diagram illustrating the arm portion included in the semiconductor device of the first embodiment. The semiconductor device 1 of the first embodiment includes... Figure 1The arm portion 2 is shown. Arm portion 2 has a laminated substrate 3 and first semiconductor chips 6 and 7 disposed on the laminated substrate 3. The first semiconductor chips 6 and 7 each have a first positive electrode (not shown) on their back side and a first negative electrode 6b and 7b and a first control electrode 6a and 7a on their front side. Such first semiconductor chips 6 and 7 can employ, for example, power MOSFETs or RC (Reverse-Conducting) IGBTs. RC-IGBTs are formed by including an IGBT and a FWD within a single chip.

[0052] The laminated substrate 3 also includes a substrate 4 and a first circuit pattern 5a and a second circuit pattern 5b formed on the front side of the substrate 4. The first circuit pattern 5a is concave when viewed from above. A first positive electrode is disposed on the back side of the first semiconductor chip 6,7. That is, the first circuit pattern 5a is U-shaped when viewed from above. The inner side of the first circuit pattern 5a has a recessed portion including a concave shape and is formed by… Figure 1 The first configuration area 5a1 is shown by the dashed line. It should be noted that the first circuit pattern 5a is concave. Therefore, the first semiconductor chips 6 and 7 are respectively disposed in the first circuit pattern 5a, separated by the first configuration area 5a1.

[0053] At least a portion of the second circuit pattern 5b is disposed in the first configuration region 5a1, and at least a portion of the second circuit pattern 5b is sandwiched by the first circuit pattern 5a. Furthermore, the second circuit pattern 5b is connected to one end of the first wiring components 8b and 8c in the first configuration region 5a1. The other end of the first wiring components 8b and 8c is connected to the first negative electrodes 6b and 7b of the first semiconductor chips 6 and 7. Therefore, the second circuit pattern 5b is electrically connected to the first negative electrodes 6b and 7b in the first configuration region 5a1 through the connected first wiring components 8b and 8c. It should be noted that the first circuit pattern 5a and the second circuit pattern 5b are composed of conductive components. Additionally, the wiring components 8b and 8c (and the wiring components 8a, 8d, and 8e described later) are composed of bonding wires, lead frames, or strip-shaped conductive components, etc.

[0054] In the arm 2 of such a semiconductor device 1, for example, the current flowing in from the wiring member 8a is split in the first circuit pattern 5a into the directions of the first semiconductor chip 6 and the first semiconductor 7, respectively. Thus, the current conducting in the first circuit pattern 5a flows into the first positive electrode on the back side of the first semiconductor chips 6 and 7, and output current is output from the first negative electrode 6b and 7b on the front side of the first semiconductor chips 6 and 7. The output current output from the first semiconductor chips 6 and 7 flows into the second circuit pattern 5b via the wiring members 8b and 8c. It should be noted that at this time, a control signal is input to the first control electrodes 6a and 7a of the first semiconductor chips 6 and 7 at a predetermined time via the wiring member 8e. Thus, the output current flowing into the second circuit pattern 5b is output to the outside of the arm 2 via the wiring member 8d.

[0055] At this time, in the arm portion 2 of the semiconductor device 1, the first semiconductor chips 6 and 7 that output current generate heat as they are driven. However, the first circuit pattern 5a is concave when viewed from above, and the second circuit pattern 5b is disposed in the recess of the first circuit pattern 5a. Therefore, the first circuit pattern 5a is disposed on the outer periphery of the laminated substrate 3, and the second circuit pattern 5b is disposed on the central portion of the laminated substrate 3. The first semiconductor chips 6 and 7 disposed in such a first circuit pattern 5a are not disposed on the central portion of the laminated substrate 3 but are located on the outer periphery of the laminated substrate 3. Therefore, heat generation can be dispersed to prevent heat from concentrating in one part of the laminated substrate 3, thereby improving heat dissipation. In addition, the output current from the first semiconductor chips 6 and 7 is collected in the second circuit pattern 5b at the central portion of the laminated substrate 3. Therefore, the control voltages on the first control electrodes 6a and 7a of the first semiconductor chips 6 and 7 can be made equal, and the first semiconductor chips 6 and 7 can be driven evenly among the first semiconductor chips 6 and 7. Therefore, the degradation of the characteristics of the semiconductor device 1 including such an arm portion 2 can be suppressed.

[0056] [Second Implementation]

[0057] In the second embodiment, the semiconductor device of the first embodiment will be described in more detail. First, using... Figure 2 and Figure 3 The semiconductor device is described. Figure 2 This is a top view of the semiconductor device according to the second embodiment. Figure 3 This is a cross-sectional view of the semiconductor device according to the second embodiment. It should be noted that... Figure 3 (A) is Figure 2 The cross-sectional view at the single-dotted dashed line X1-X1 in the diagram. Figure 3 (B) is Figure 2 The cross-sectional view at the single-dotted dashed line X2-X2 in the diagram.

[0058] Semiconductor device 10 has a first arm 20 and a second arm 30. The semiconductor device 10 has upper and lower arms formed by the first arm 20 and the second arm 30. It should be noted that the first arm 20 and the second arm 30 are electrically connected by bonding wires 27a and 27g. Furthermore, the semiconductor device 10 has a heat dissipation substrate (not shown) and a housing 40. The heat dissipation substrate has the first arm 20 and the second arm 30 disposed on it by solder (not shown). The housing 40 is disposed on the heat dissipation substrate and surrounds the first arm 20 and the second arm 30. The housing 40 is electrically connected to the first arm 20 and the second arm 30 by bonding wires 27f, 37a, and 37h. It should be noted that in this embodiment, only one bonding wire is used for the electrical connection of each part for simplicity. In practice, multiple bonding wires can be used instead of one. Alternatively, a plate-shaped lead frame or a thin ribbon-like wiring component can be used instead of bonding wires.

[0059] The first arm portion 20 has a ceramic circuit board 21 and semiconductor chips 25, 26 disposed on the front side of the ceramic circuit board 21. Furthermore, such a ceramic circuit board 21 is disposed on a heat dissipation substrate by means of solder or silver solder (not shown).

[0060] Semiconductor chips 25 and 26 (first semiconductor chips) are made of silicon. Such semiconductor chips 25 and 26 include an RC-IGBT switching element comprising an IGBT and a FWD within a single chip. The RC-IGBT chip is configured with a circuit formed by the IGBT and FWD connected in reverse parallel. Alternatively, semiconductor chips 25 and 26 are made of silicon carbide. Such semiconductor chips 25 and 26 include a switching element comprised of a MOSFET that effectively incorporates a body diode. For example, semiconductor chips 25 and 26 have a collector (positive electrode, drain electrode in a MOSFET) as the main electrode on the back side, and gate electrodes 25a and 26a (control electrodes) and emitter electrodes 25b and 26b (negative electrodes, source electrodes in a MOSFET) as the main electrodes on the front side. Furthermore, the gate electrodes 25a and 26a of semiconductor chips 25 and 26 are located at the center of the side portion of the front side, and the emitter electrodes 25b and 26b are located at the center portion. Note that the diagram of the collector on the back side is omitted. It should be noted that since the semiconductor device 10 uses switching elements including RC-IGBTs or MOSFETs made of silicon carbide, there is no need to connect diode elements in parallel. Therefore, the switching elements including RC-IGBTs or MOSFETs made of silicon carbide are suitable for being arranged on the concave circuit patterns 23a, 33a described later.

[0061] The ceramic circuit board 21 has an insulating plate 22 and a metal plate 24 formed on the back side of the insulating plate 22. Furthermore, the ceramic circuit board 21 has circuit patterns 23a to 23d formed on the front side of the insulating plate 22. The insulating plate 22 is made of a ceramic with high thermal conductivity, such as alumina, aluminum nitride, or silicon nitride. The metal plate 24 is made of a metal with high thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. The circuit patterns 23a to 23d are made of a metal with high electrical conductivity, such as copper or a copper alloy. Moreover, to improve corrosion resistance, a material such as nickel can be formed on the surface of the circuit patterns 23a to 23d through a plating process. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used. Additionally, the thickness of the circuit patterns 23a to 23d is, for example, 0.1 mm or more and 1 mm or less. As the ceramic circuit board 21 having this configuration, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate can be used. The ceramic circuit board 21 can transfer the heat generated by the semiconductor chips 25, 26 to the heat dissipation substrate side through the circuit pattern 23a, the insulating plate 22, and the metal plate 24. It should be noted that the ceramic circuit board 21 is an example, and it could also be a metal substrate and / or a lead frame formed by die pads.

[0062] Circuit pattern 23a (first circuit pattern) constitutes the collector pattern of the first arm 20. The circuit pattern 23a is soldered to the collector formed on the back side of the semiconductor chips 25, 26. Such circuit pattern 23a is concave when viewed from above. The inner side of the circuit pattern 23a has a recessed portion formed by the concave shape and... Figure 2 The dashed line indicates the configuration area 23a1 (first configuration area). The circuit pattern 23a can also be U-shaped when viewed from above. In the circuit pattern 23a, semiconductor chips 25 and 26 are separated by the configuration area 23a1 and arranged in a row along the configuration area 23a1. It should be noted that the semiconductor chips 25 and 26 are arranged such that their gate electrodes 25a and 26a are arranged in a row. Furthermore, the gate electrodes 25a and 26a are opposite each other. It should be noted that there can be three or more such semiconductor chips 25 and 26.

[0063] Circuit pattern 23b (second circuit pattern) constitutes the emitter pattern of the first arm 20. Circuit pattern 23b has a configuration region 23a1. Configuration region 23a1 is connected to the emitter electrodes 25b and 26b of semiconductor chips 25 and 26 via bonding lines 27b, 27c, 27d, and 27e. Such circuit pattern 23b in Figure 2When viewed from above, it appears L-shaped. That is, the circuit pattern 23b has a first part and a second part. The first part is disposed within the disposal area 23a1. The second part is located outside the disposal area 23a1, extending from the end of the first part in a direction perpendicular to the extending direction of the disposal area 23a1. Figure 2 (Extending to the lower side of the middle). It should be noted that circuit pattern 23b is in Figure 2 When viewed from above, it can also be T-shaped. That is, the second part of the circuit pattern 23b can also be located outside the configuration area 23a1, extending from the end of the first part in a direction orthogonal to the extending direction of the configuration area 23a1. Figure 2 (The upper and lower parts of the text are extended.)

[0064] Circuit patterns 23c and 23d constitute the sensing emitter pattern and gate pattern of the first arm 20, respectively. Circuit patterns 23c and 23d (the fifth circuit patterns) sandwich circuit pattern 23a with the arrangement region 23a1 and are arranged adjacent to circuit pattern 23a. That is, circuit patterns 23c and 23d are arranged adjacent to circuit pattern 23a parallel to the side separating them in the direction perpendicular to the opening direction of the concave opening of circuit pattern 23a when viewed from above. Furthermore, circuit patterns 23c and 23d are arranged parallel to the two opposite sides of the arrangement region 23a1 and adjacent to circuit pattern 23a. It should be noted that in... Figure 2 In the circuit diagram, circuit patterns 23c and 23d are arranged in the circuit pattern 23a. Figure 2 The lower side of the circuit pattern 23a. Circuit patterns 23c and 23d are not limited to this case; they can also be configured as needed within the circuit pattern 23a. Figure 2 The upper side of the insulating plate 22. Furthermore, to save space, circuit patterns 23c and 23d are configured to extend elongatedly along the edge of the insulating plate 22. Circuit pattern 23c is connected to the emitter electrode 25b of the semiconductor chip 25 via bonding wire 27j. Circuit pattern 23d is connected to the gate electrodes 25a and 26a of the semiconductor chips 25 and 26 via bonding wires 27h and 27i, respectively.

[0065] The second arm 30 has a ceramic circuit board 31 and semiconductor chips 35 and 36 disposed on the front side of the ceramic circuit board 31. Furthermore, the ceramic circuit board 31 is disposed on a heat dissipation substrate using solder or silver solder (not shown). It should be noted that the components of the second arm 30 are arranged in a manner approximately point-symmetrical with respect to the center point of the semiconductor device 10 when viewed from above.

[0066] Semiconductor chips 35 and 36 (the second semiconductor chips) are also made of silicon, just like semiconductor chips 25 and 26. Semiconductor chips 35 and 36 also include RC-IGBT switching elements, which are formed by combining an IGBT and a FWD within a single chip. Furthermore, semiconductor chips 35 and 36 are made of silicon carbide. Semiconductor chips 35 and 36 also include switching elements made of MOSFETs. Therefore, semiconductor chips 35 and 36 also have a collector (positive electrode, or drain electrode in a MOSFET) as the main electrode on the back side, and gate electrodes 35a and 36a (control electrodes) and emitter electrodes 35b and 36b (negative electrodes, or source electrodes in a MOSFET) as the main electrodes on the front side. Additionally, the gate electrodes 35a and 36a of semiconductor chips 35 and 36 are located at the center of the side portion of the front side, and the emitter electrodes 35b and 36b are located at the center portion. It should be noted that the diagram of the collector on the back side is omitted.

[0067] The ceramic circuit board 31 includes an insulating plate 32 and a metal plate 34 formed on the back side of the insulating plate 32. Furthermore, the ceramic circuit board 31 has circuit patterns 33a to 33e formed on the front side of the insulating plate 32. The insulating plate 32 is made of a ceramic with high thermal conductivity, such as alumina, aluminum nitride, or silicon nitride. The metal plate 34 is made of a metal with high thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. The circuit patterns 33a to 33e are made of a metal with high electrical conductivity, such as copper or a copper alloy. Moreover, to improve corrosion resistance, a material such as nickel can be formed on the surface of the circuit patterns 33a to 33e through a plating process. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used. Additionally, the thickness of the circuit patterns 33a to 33e is, for example, 0.1 mm or more and 1 mm or less. As a ceramic circuit board 31 with this configuration, for example, a DCB substrate or an AMB substrate can be used. The ceramic circuit board 31 can transfer the heat generated by the semiconductor chips 35, 36 to the heat dissipation substrate side via the circuit pattern 33a, the insulating plate 32, and the metal plate 34. It should be noted that the ceramic circuit board 31 is just one example, and it could also be a metal substrate and / or a lead frame formed by die pads.

[0068] Circuit pattern 33a (third circuit pattern) constitutes the collector pattern of the second arm 30. The circuit pattern 33a is soldered to the collector formed on the back side of the semiconductor chips 35, 36. Such circuit pattern 33a is concave when viewed from above. The inner side of the circuit pattern 33a has a recessed portion formed by the concave shape and... Figure 2The dashed line indicates the configuration area 33a1 (second configuration area). Furthermore, the circuit pattern 33a is adjacent to the circuit pattern 23a such that the configuration area 23a1 side of the circuit pattern 23a faces the configuration area 33a1 side of the circuit pattern 33a. That is, the circuit pattern 23a of the first arm 20 and the circuit pattern 33a of the second arm 30 are adjacent such that their respective recesses face each other. In the circuit pattern 33a, semiconductor chips 35 and 36 are separated by the configuration area 33a1 and are arranged in a row. It should be noted that the semiconductor chips 35 and 36 are arranged such that their gate electrodes 35a and 36a are arranged in a row. Furthermore, the gate electrodes 35a face each other, and the gate electrodes 36a face each other. It should be noted that there can be three or more such semiconductor chips 35 and 36.

[0069] Circuit pattern 33b (fourth circuit pattern) constitutes the emitter pattern of the second arm 30. Circuit pattern 33b has a configuration region 33a1. Configuration region 33a1 is connected to the emitter electrodes 35b and 36b of semiconductor chips 35 and 36 via bonding lines 37b, 37c, 37d, and 37e. Such circuit pattern 33b in Figure 2 When viewed from above, it appears L-shaped. That is, the circuit pattern 33b includes the entire surface area disposed in the configuration region 33a1 and the area in... Figure 2 The area above and orthogonal to this region. Circuit pattern 33b is electrically connected to circuit pattern 23a via bonding wire 27a. Such circuit pattern 33b in Figure 2 When viewed from above, it appears L-shaped. That is, circuit pattern 33b has a third part and a fourth part. The third part is disposed within the arrangement area 33a1. The fourth part extends outside the arrangement area 33a1 from the end of the third part in a direction perpendicular to the extending direction of the arrangement area 33a1, which is the direction along the extension of the circuit pattern 23b. Figure 2 The direction of the second part extending from the lower side of the middle is opposite to that of the middle part. It should be noted that circuit pattern 33b is in... Figure 2 When viewed from above, it can also be T-shaped. That is, the fourth part of the circuit pattern 33b can also be located outside the configuration area 33a1, extending from the end of the third part in a direction orthogonal to the extending direction of the configuration area 33a1. Figure 2 (The upper and lower parts of the text are extended.)

[0070] Circuit patterns 33c and 33d respectively constitute the sensing emitter pattern and gate pattern of the second arm 30. Circuit patterns 33c and 33d (sixth circuit patterns) are separated from and adjacent to the arrangement region 33a1 by circuit pattern 33a. Furthermore, circuit patterns 33c and 33d are positioned symmetrically to circuit patterns 23c and 23d with respect to the center point of the semiconductor device 10. It should be noted that, in this case, circuit patterns 33c and 33d are positioned on the edge of circuit pattern 33a. Figure 2 The upper side of the circuit pattern 33a. Circuit patterns 33c and 33d are not limited to this case; they can be arranged in relation to circuit pattern 33a depending on the position of circuit patterns 23c and 23d. Figure 2 The lower side of the insulating plate 32. Furthermore, to save space, circuit patterns 33c and 33d are configured to extend elongatedly along the edge of the insulating plate 32. Circuit pattern 33c is connected to the emitter electrode 36b of the semiconductor chip 36 via bonding wire 37i. Circuit pattern 33d is connected to the gate electrodes 35a and 36a of the semiconductor chips 35 and 36 via bonding wires 37f and 37g, respectively. Circuit pattern 33e is adjacent to circuit pattern 33a on the opposite side of the configuration region 33a1. Figure 2 It is configured on the lower side of the middle. In addition, circuit pattern 33e is electrically connected to circuit pattern 23b via bonding wire 27g.

[0071] The housing 40 is disposed on a heat dissipation substrate as described above and has a rectangular frame 41 when viewed from above. The frame 41 of this housing 40 is box-shaped, surrounding the perimeter. A storage area 42 is formed within the frame 41 for accommodating the first arm portion 20 and the second arm portion 30 described above. Furthermore, in the frame 41… Figure 2 External terminal portions 43 to 45 are formed at the left and right ends of the housing 40. External terminal portion 43 is electrically connected to circuit pattern 33a housed in the second arm portion 30 of the frame 41 via bonding wire 37a. External terminal portion 44 is electrically connected to circuit pattern 23a housed in the first arm portion 20 of the frame 41 via bonding wire 27f. External terminal portion 45 is electrically connected to circuit pattern 33e housed in the second arm portion 30 of the frame 41 via bonding wire 37h. Therefore, a positive terminal is connected to external terminal portion 43, a negative terminal is connected to external terminal portion 45, and an output is obtained from external terminal portion 44. It should be noted that, although not shown, the housing 40 has control terminals for receiving control signals on both sides of the frame 41 along its long side. These control terminals are electrically connected to circuit patterns 23c and 33c, respectively. Such a housing 40 includes, for example, external terminal portions 43 to 45, and is constructed using thermoplastic resin injection molding. Such resins include polyphenylene sulfide (PPS), polybutylene terephthalate (PBT) resin, polybutylene succinate (PBS) resin, polyamide (PA) resin, or acrylonitrile-butadiene-styrene (ABS) resin, etc.

[0072] It should be noted that the bonding wires 27a-27j and 37a-37i described above are made of metals with excellent electrical conductivity, such as aluminum and copper, or alloys containing at least one of these metals. Furthermore, the diameter of these bonding wires is preferably 100 μm or more and 1 mm or less. Additionally, the heat dissipation substrate (not shown) is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or alloys containing at least one of these metals. Furthermore, to improve corrosion resistance, materials such as nickel can be formed on the surface of the heat dissipation substrate through plating or other processes. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used. Such a heat dissipation substrate is appropriately formed with mounting holes for mounting to external machines, contact areas for allowing output current to flow into the first arm 20 and the second arm 30, etc.

[0073] Alternatively, a cooler (not shown) can be mounted on the back side of the heat dissipation substrate of such a semiconductor device 10. In this case, the cooler is mounted using thermally conductive grease such as silicone mixed with metal oxide filler. This also improves the heat dissipation of the semiconductor device 10. In this case, the cooler is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. Alternatively, a heat sink or a heat sink composed of multiple heat sinks, or a water-cooled cooling device can be used as the cooler. Furthermore, the heat dissipation substrate can be integrally formed with such a cooler. In this case, the heat dissipation substrate is made of materials with excellent thermal conductivity, such as aluminum, iron, silver, copper, or an alloy containing at least one of these metals. Moreover, to improve corrosion resistance, a material such as nickel can be formed on the surface of the heat dissipation substrate integrally formed with the cooler through a plating process. Specifically, in addition to nickel, nickel-phosphorus alloys, nickel-boron alloys, etc., are also used.

[0074] Next, use Figure 4 The circuit configuration implemented by such a semiconductor device 10 will be described. Figure 4 This is a circuit diagram of the semiconductor device according to the second embodiment. The semiconductor device 10 is thus constructed using semiconductor chips 25, 26, 35, 36, circuit patterns 23a-23d, 33a-33e, and bonding lines 27a-27j, 37a-37i. Figure 4 The inverter circuit shown.

[0075] The semiconductor device 10 includes a C1 terminal (corresponding to external terminal 43), an E2 terminal (corresponding to external terminal 45), and an E1C2 terminal (corresponding to external terminal 44). The high-potential terminal of the external power supply is connected to the C1 terminal, which serves as the input P terminal, and the low-potential terminal of the external power supply is connected to the E2 terminal, which serves as the input N terminal. Then, a load (not shown) is connected to the E1C2 terminal, which serves as the output U terminal of the semiconductor device 10. Thus, the semiconductor device 10 functions as an inverter.

[0076] For a semiconductor device 10 having such a configuration, for example, external connection terminals (not shown) can be connected to each of the external terminal portions 43-45, and the first arm portion 20 and the second arm portion 30 of the housing area 42 of the frame 41 can be encapsulated with an encapsulation component. In this case, a thermosetting resin such as epoxy resin, phenolic resin, or maleimide resin can be used.

[0077] Next, use Figure 5 The situation where current is input to make such a semiconductor device 10 work will be explained. Figure 5 This is a diagram illustrating the flow of current in the semiconductor device of the second embodiment. It should be noted that... Figure 5 The semiconductor device 10 shown is Figure 4 The semiconductor device shown. However, in Figure 5 In the diagram, thick arrows indicate the flow of current in the semiconductor device 10. It should be noted that dashed arrows indicate the flow of current in the area of ​​the circuit pattern 33a where the semiconductor chips 35 and 36 are disposed.

[0078] In such a semiconductor device 10, current input from the external terminal 43 flows into the circuit pattern 33a via the bonding wire 37a. The current flowing into the circuit pattern 33a is split along the shape of the circuit pattern 33a and directed toward the two regions where the semiconductor chips 35 and 36 are disposed.

[0079] In circuit pattern 33a, currents flowing in two directions enter semiconductor chips 35 and 36 from the collectors on the back side and exit from the emitter electrodes 35b and 36b on the front side. It should be noted that a gate voltage is applied to the gate electrodes 35a and 36a of semiconductor chips 35 and 36 at a predetermined time. The current exiting from the emitter electrodes 35b and 36b of semiconductor chips 35 and 36 flows into circuit pattern 33b via bonding lines 37b, 37c, 37d, and 37e. The output current flowing in this way circulates in circuit pattern 33b and then flows into circuit pattern 23a of the first arm 20 via bonding line 27.

[0080] In the second arm 30, where current flows, semiconductor chips 35 and 36 are positioned around the periphery of the concave circuit pattern 33a when viewed from above. Therefore, even when semiconductor chips 35 and 36 generate heat during energization, the heat is distributed throughout the second arm 30, preventing heat concentration in any one area. In particular, since semiconductor chips 35 and 36 are RC-IGBTs with the same chip size, the concave circuit pattern 33a can be implemented with a simpler shape rather than a complex shape when viewed from above. This shape of circuit pattern 33a allows for easy and space-saving placement of semiconductor chips 35 and 36. Furthermore, the output current from the emitter electrodes 35b and 36b of semiconductor chips 35 and 36 is collected in the centrally located circuit pattern 33b. Therefore, imbalances in the gate voltages of the gate electrodes 35a and 36a of semiconductor chips 35 and 36 can be suppressed. Moreover, semiconductor chips 35 and 36 can be driven evenly between semiconductor chips 35 and 36. Furthermore, the wiring length from the external terminal 43 to the semiconductor chip 35 is the same as the wiring length from the external terminal 43 to the semiconductor chip 36. Therefore, it is possible to suppress the current imbalance between the semiconductor chip 35 and the semiconductor chip 36.

[0081] Similarly, in the first arm 20, the current flowing into circuit pattern 23a flows from the collector on the back side of semiconductor chips 25, 26 into semiconductor chips 25, 26, and outputs current from the emitter electrodes 25b, 26b on the front side of semiconductor chips 25, 26. It should be noted that at this time, gate voltages are also applied to the gate electrodes 25a, 26a of semiconductor chips 25, 26 at predetermined times. The output current output from the emitter electrodes 25b, 26b of semiconductor chips 25, 26 flows into circuit pattern 23b via bonding lines 27b, 27c, 27d, 27e. The output current flowing in this way flows through circuit pattern 23b and into circuit pattern 33e of the second arm 30 via bonding line 27g. Therefore, the first arm 20 also achieves the same effect as the second arm 30 described above.

[0082] Here, for such a semiconductor device 10, using Figure 6 The semiconductor device used for reference is described. Figure 6 This is a diagram used to illustrate a semiconductor device for reference and the flow of current within the semiconductor device. It should be noted that... Figure 6 In the configuration of the semiconductor device 10a shown, the same symbols are used for configurations identical to those in the semiconductor device 10. Furthermore, only the symbols necessary for explanation are used.

[0083] Semiconductor device 10a has a first arm 60 and a second arm 70. The semiconductor device 10a forms upper and lower arms via the first arm 60 and the second arm 70. It should be noted that the first arm 60 and the second arm 70 are electrically connected via bonding wires 67a, etc. Furthermore, the semiconductor device 10a has a heat dissipation substrate (not shown) and a housing 40. The heat dissipation substrate has the first arm 60 and the second arm 70 disposed thereon via solder (not shown). The housing 40 is disposed on the heat dissipation substrate and surrounds the first arm 60 and the second arm 70. Additionally, the housing 40 is electrically connected to the first arm 60 and the second arm 70 via bonding wires 77a, etc.

[0084] The first arm 60 has a ceramic circuit board and semiconductor chips 651-653, 661-663 disposed on the front side of the ceramic circuit board. The ceramic circuit board is disposed on a heat dissipation substrate using solder or silver solder (not shown). Semiconductor chips 651-653 are FWD or SBDs made of silicon or silicon carbide. For example, these semiconductor chips 651-653 have a cathode electrode (negative electrode) as the main electrode on the back side and an anode electrode (positive electrode) as the main electrode on the front side. Additionally, semiconductor chips 661-663 are IGBTs made of silicon. These semiconductor chips 661-663 have a collector electrode (positive electrode) on the back side, a gate electrode at the center of the side portion of the front side, and an emitter electrode (negative electrode) at the center of the front side.

[0085] The ceramic circuit board has an insulating plate 62 and a metal plate formed on the back side of the insulating plate 62. Furthermore, the ceramic circuit board has circuit patterns 63a to 63c formed on the front side of the insulating plate 62. It should be noted that the circuit patterns 63a to 63c are arranged as follows: Figure 6 The shape configuration is shown. Furthermore, these semiconductor chips 651-653, 661-663 are respectively disposed in the center of the circuit pattern 63a described later.

[0086] The second arm 70 has a ceramic circuit board 71 and semiconductor chips 751-753, 761-763 disposed on the front side of the ceramic circuit board 71. Furthermore, this ceramic circuit board 71 is disposed on a heat dissipation substrate using solder or silver solder (illustration omitted).

[0087] Semiconductor chips 751-753 and 761-763 are also made of silicon or silicon carbide, just like semiconductor chips 651-653 and 661-663. Semiconductor chips 751-753 and 761-763 are also FWD and IGBT. Therefore, semiconductor chips 751-753, for example, have a cathode electrode (negative electrode) as the main electrode on the back side and an anode electrode (positive electrode) as the main electrode on the front side. Furthermore, semiconductor chips 761-763 have a collector electrode (positive electrode) on the back side, a gate electrode in the center of the side portion of the front side, and an emitter electrode (negative electrode) in the center of the front side. These semiconductor chips 751-753 and 761-763 are respectively arranged in the center of the circuit pattern 73a described later.

[0088] The ceramic circuit board 71 has an insulating plate 72 and a metal plate formed on the back side of the insulating plate 72. Furthermore, the ceramic circuit board 71 has circuit patterns 73a to 73d formed on the front side of the insulating plate 72. It should be noted that the circuit patterns 73a to 73d are... Figure 6 The shape configuration shown.

[0089] The situation regarding the input of current to operate the semiconductor device 10a having this configuration will be explained. It should be noted that, in Figure 6 The flow of current in the semiconductor device 10a is also indicated by thick arrows. It should be noted that the arrows indicate the flow of current in the area of ​​the circuit pattern 73a in which semiconductor chips 751-753, 761-763 are arranged.

[0090] In this semiconductor device 10a, current input from the external terminal 44 flows into circuit pattern 73a via bonding wire 77a. The current flowing into circuit pattern 73a diffuses within it. The current diffused within circuit pattern 73a flows from the collector on the back side of semiconductor chips 761-763 into semiconductor chips 761-763, and outputs current from the emitter on the front side of semiconductor chips 761-763. It should be noted that, at this time, a gate voltage is applied to the gate electrode of semiconductor chips 761-763 at a predetermined time.

[0091] The output current from the emitter electrodes of semiconductor chips 761 and 763 flows into circuit pattern 73b via bonding lines 77c and 77h. The output current from the emitter electrode of semiconductor chip 762 flows into circuit pattern 73b via bonding line 77d, semiconductor chip 752, and bonding line 77f. The output current flowing in this way flows through circuit pattern 73b and then into circuit pattern 63a of the first arm 60 via bonding line 67a.

[0092] In the second arm 70, where current flows, semiconductor chips 751-753 and 761-763 are arranged in the center of circuit pattern 73a. In particular, the semiconductor chips 751-753 and 761-763 are of different types and sizes. Therefore, circuit pattern 73a needs to cover a large area to ensure their placement. Furthermore, when arranging semiconductor chips 751-753 and 761-763 in circuit pattern 73a, it is necessary to arrange them in a staggered grid pattern in the center of circuit pattern 73a. Therefore, if semiconductor chips 761-763 generate heat during energization, heat concentration will occur in the center of the second arm 70. Additionally, the wiring lengths from the output current from the emitter electrodes of semiconductor chips 761-763 up to circuit pattern 73b are uneven. Therefore, uneven gate voltages occur at the gate electrodes of semiconductor chips 761-763, making it difficult to drive semiconductor chips 761-763 evenly. It should be noted that although a specific description of the first arm 60 that receives current from the second arm 70 is omitted, the current flows in the same way as in the second arm 70, and the same problems exist as in the second arm 70.

[0093] The semiconductor device 10 described above has a first arm 20 and a second arm 30, each having semiconductor chips 25, 26, 35, and 36. These semiconductor chips 25, 26, 35, and 36 have collector electrodes on their back surfaces and emitter electrodes 25b, 26b, 35b, and 36b and gate electrodes 25a, 26a, 35a, and 36a on their front surfaces. The first arm 20 and the second arm 30 also have circuit patterns 23a and 33a. When viewed from above, these circuit patterns 23a and 33a are concave, surrounding at least a portion of the configuration areas 23a1 and 33a1, and have the back surfaces of the semiconductor chips 25, 26, 35, and 36 disposed thereon. Furthermore, the first arm 20 and the second arm 30 are provided with circuit patterns 23b and 33b. These conductive patterns 23b and 33b are disposed in the placement regions 23a1 and 33a1, surrounding at least a portion of the circuit patterns 23a and 33a, and are electrically connected to the emitter electrodes 25b, 26b, 35b, and 36b of the semiconductor chips 25, 26, 35, and 36b via bonding lines 27b, 27c, 27d, 27e, 37b, 37c, 37d, and 37e. Therefore, the semiconductor chips 25, 26, 35, and 36 disposed in the circuit patterns 23a and 33a are not concentrated in the central portion of the ceramic circuit substrates 21 and 31, but are located on the outer periphery side of the ceramic circuit substrates 21 and 31. This allows for the dissipation of heat generated in the ceramic circuit substrates 21 and 31, improving heat dissipation. Furthermore, the emitter currents output from semiconductor chips 25, 26, 35, 36 are collected in circuit patterns 23b, 33b at the center of ceramic circuit substrates 21, 31. Therefore, the gate voltages of the gate electrodes 25a, 26a, 35a, 36a of semiconductor chips 25, 26, 35, 36 become equal, enabling balanced driving of semiconductor chips 25, 26, 35, 36 among them. Thus, it is possible to suppress the degradation of the characteristics of the semiconductor device 10, including such a first arm 20 and a second arm 30.

[0094] The above only illustrates the principles of the present invention. Furthermore, those skilled in the art can make numerous modifications and alterations. The present invention is not limited to the precise configuration and application examples shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the present invention as defined by the appended claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises a first arm portion, The first arm portion comprises: A first circuit pattern having a concave shape when viewed from above; a second circuit pattern, at least a portion of which is arranged in a first arrangement region formed by the recess of the first circuit pattern in a plan view; as well as a first semiconductor chip having a first positive electrode on the back surface and a first control electrode and a first negative electrode electrically connected to the second circuit pattern via a first wiring member on the front surface, wherein each of the first positive electrodes is arranged on the first circuit pattern via the first arrangement region. The first arm also has: an input wiring member connected to an input region of the first circuit pattern, the input region being parallel to an opening direction of the recess and facing the second circuit pattern; as well as An output wiring member is connected to an output region of the second circuit pattern on the opposite side to the input region.

2. The semiconductor device according to claim 1, wherein: The first semiconductor chip is an RC-IGBT.

3. The semiconductor device according to claim 1, wherein: The first semiconductor chip is a MOSFET having a built-in body diode.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The first control electrodes of the first semiconductor chips arranged across the first arrangement region are oriented toward the opening direction of the recess or the side opposite to the opening direction, and are arranged in a row perpendicular to the opening direction.

5. The semiconductor device according to claim 1, wherein: The first arm portion further includes a fifth circuit pattern that sandwiches the first circuit pattern together with the first arrangement region and is arranged adjacent to one side of the region of the first circuit pattern where the first semiconductor chip is arranged, and is electrically connected to the first control electrode via a first control wiring member.

6. The semiconductor device according to claim 5, wherein: The first control wiring member is arranged perpendicularly to the opening direction of the recess from the first control electrode. The first wiring member is arranged in parallel with the first control wiring member on the second circuit pattern from the first cathode electrode.

7. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a second arm portion, The second arm portion comprises: a third circuit pattern which is concave in a plan view and has a depression opposite to the side of the first circuit pattern where the depression is arranged; a fourth circuit pattern, at least a portion of which is arranged in a second arrangement region formed by the recess of the third circuit pattern in a plan view; and The second semiconductor chip has a second positive electrode on the back side and a second control electrode and a second negative electrode electrically connected to the fourth circuit pattern through a second wiring component on the front side, and each of the second positive electrodes is arranged in the third circuit pattern across the second arrangement area.

8. The semiconductor device according to claim 7, wherein: The second circuit pattern is L-shaped in a plan view and includes a first portion and a second portion, wherein the first portion is disposed in the first configuration region and the second portion extends in a direction perpendicular to an extending direction of the first configuration region.

9. The semiconductor device according to claim 8, wherein: The fourth circuit pattern is L-shaped when viewed from above and includes a third part and a fourth part, the third part is configured in the second configuration area, and the fourth part extends in a direction that is right angles to the extension direction of the second configuration area and opposite to the extension direction of the second part of the second circuit pattern.

10. The semiconductor device according to claim 7, wherein: The second circuit pattern is T-shaped in a plan view and includes a first portion and a second portion, wherein the first portion is arranged in the first arrangement region and the second portion extends in a direction orthogonal to an extending direction of the first arrangement region.

11. The semiconductor device according to claim 7, wherein: The fourth circuit pattern is T-shaped in a plan view and includes a third portion and a fourth portion, the third portion is arranged in the second arrangement region, and the fourth portion extends in a direction orthogonal to an extending direction of the second arrangement region.

12. The semiconductor device according to any one of claims 7 to 11, characterized in that The first arm portion further has a fifth circuit pattern, The fifth circuit pattern sandwiches the first circuit pattern together with the first arrangement region and is arranged adjacent to one side of the region of the first circuit pattern where the first semiconductor chip is arranged, and is electrically connected to the first control electrode via a first control wiring member. The second arm portion further has a sixth circuit pattern, The sixth circuit pattern sandwiches the third circuit pattern together with the second configuration area and is adjacent to a single side of the area of ​​the third circuit pattern where the second semiconductor chip is configured, and is configured on the opposite side of the fifth circuit pattern across the first configuration area and the second configuration area from the fifth circuit pattern, and is electrically connected to the second control electrode through a second control wiring component.

13. The semiconductor device according to claim 12, wherein: In the first arm, The first control wiring member is arranged perpendicularly to the opening direction of the recess from the first control electrode. The first wiring member is arranged in parallel with the first control wiring member on the second circuit pattern from the first cathode electrode. In the second arm, The second control wiring member is arranged perpendicularly to the opening direction of the recess from the second control electrode and on the opposite side of the first control wiring member. The second wiring member is arranged in parallel with the second control wiring member on the fourth circuit pattern from the second cathode electrode.

14. The semiconductor device according to claim 13, wherein: The first arm also has: a first input wiring member connected to a first input region of the first circuit pattern, the first input region being opposed to the second circuit pattern in parallel with an opening direction of the recess of the first circuit pattern; as well as a first output wiring member that connects a first output region of the second circuit pattern on the opposite side of the first input region and the third circuit pattern, The second arm also has: a second input wiring member connected to a second input region of the third circuit pattern, the second input region being opposed to the fourth circuit pattern in parallel with an opening direction of the recess of the third circuit pattern; as well as A second output wiring member is connected to a second output region of the fourth circuit pattern on the opposite side of the second input region.

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