Semiconductor devices, electronic equipment and electronic systems

Abstract

The present disclosure relates to a semiconductor device, an electronic device, and an electronic system. According to an embodiment, the semiconductor device includes: a holding circuit, a control circuit including an operation of determining a threshold, and a wireless communication circuit. The holding circuit includes a buffer and a stress counter. The buffer is configured to obtain thermal stress information with temperature dependence in each predetermined period, and the stress counter is configured to accumulate the thermal stress information and maintain the accumulated value as an accumulated stress count value. According to the semiconductor device of this embodiment, the accumulated thermal stress information can be wirelessly transmitted while reducing power consumption.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-168868 filed on September 17, 2019 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Background Art

[0003] The present disclosure relates to semiconductor devices, and is particularly applicable to semiconductor devices capable of transmitting stress information.

[0004] In order to detect the degradation of a semiconductor device, the inventors have proposed a technology of a stress detection circuit that converts the temperature of a semiconductor device into degradation stress intensity using a predetermined degradation model (e.g., an Arrhenius model), and performs predictive maintenance of a semiconductor device or a semiconductor system by an accumulated degradation stress amount obtained by integrating the degradation stress intensity.

[0005] There are technologies disclosed by the present inventors listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2017-118414

[0007] [Patent Document 2] Japanese Unexamined Patent Application Publication No. 2018-91804

[0008] [Patent Document 3] Japanese Unexamined Patent Application Publication No. 2019-95271 Summary of the invention

[0009] IoT (Internet of Things) has been studied to sense various states of devices, collect them via a network, and use them for predictive maintenance.

[0010] The present inventors have considered the form of a semiconductor device: simply mounted on the same semiconductor chip as the stress detection circuit, or mounted on an existing electronic system like a thermometer by installing a wireless function in the same package as the semiconductor chip, and have discovered the following new problem.

[0011] 1) When a semiconductor device including a stress detection circuit is mounted on an electronic system and an attempt is made to transmit the amount of accumulated degradation stress (the amount of thermal stress) measured by the stress detection system through wireless communication, electromagnetic waves and heat generated during the operation of the electronic system become noise, and the wireless communication may be hindered.

[0012] 2) Furthermore, in order to realize a configuration in which the stress detection circuit wirelessly transmits the amount of accumulated degradation stress while the electronic system is stopped, it is necessary to allow the stress detection circuit to recognize that the electronic system is stopped.

[0013] In this case, it is also conceivable that the semiconductor device receives the standby stop information issued by the control system of the electronic system, and the configuration for receiving the standby stop information may increase the power consumption of the semiconductor device.

[0014] 3) For the control system of the existing electronic system, it may also be necessary to change the design of sending system stop information to the stress detection circuit.

[0015] An object of the present disclosure is to provide a technology capable of wirelessly transmitting accumulated thermal stress information while reducing power consumption.

[0016] Other issues and novel features will become apparent from the description herein and from the accompanying drawings.

[0017] A brief summary of the present disclosure will be described below.

[0018] A semiconductor device according to an embodiment includes a holding circuit, including a control circuit for operating a threshold value; and a wireless communication circuit. The holding circuit includes a buffer and a stress counter. The buffer is configured to obtain thermal stress information having temperature dependence in each predetermined period, and the stress counter is configured to accumulate the thermal stress information and maintain the accumulated value as an accumulated stress count value; according to the semiconductor device of this embodiment, the accumulated thermal stress information can be wirelessly transmitted while reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a diagram showing a configuration example of a semiconductor device according to an embodiment.

[0020] Figure 2 are configuration diagrams illustrating an electronic device and an electronic system according to an embodiment.

[0021] Figure 3 is a diagram schematically showing a time course of thermal stress information of an electronic system.

[0022] Figure 4 It is a graphic application Figure 1 semiconductor device or Figure 2 An example diagram of an electronic system of an electronic device.

[0023] Figure 5 is a diagram illustrating a modified form of the operation determination threshold value.

[0024] Figure 6 is a diagram illustrating a first example of setting the operation determination threshold.

[0025] Figure 7 is a diagram illustrating a second example of setting the operation determination threshold.

[0026] Figure 8 is a diagram illustrating a third example of setting the operation determination threshold.

[0027] Fig. 9 It is a graphic Figure 1 FIG. 1 is a diagram showing an example of a configuration of a main portion of a stress detection circuit.

[0028] Fig.10 It is shown Figure 1 FIG. 1 is a diagram showing an example of a configuration of a main part of a circuit for maintaining cumulative degradation stress.

[0029] Fig.11 2 is a diagram showing a configuration example of a main part of an accumulated degradation stress amount holding circuit according to a first modification.

[0030] Fig.12 : is a diagram showing a configuration example of a main part of an accumulated degradation stress amount holding circuit according to a second modification.

[0031] Fig.13 is a diagram illustrating an operation process of a semiconductor device according to an embodiment.

[0032] Fig.14 is a diagram illustrating a configuration example of a stress detection circuit according to a first modification.

[0033] Fig.15 It is used to illustrate Figure 1 FIG. 1 is a diagram of a modified form of a switching count information holding circuit.

[0034] Fig.16 : is a diagram for explaining a state transition diagram of a switching count information holding circuit in a modified form.

[0035] Fig.17 is a diagram showing a stress detection circuit according to a second modification.

[0036] Fig.18 This is a diagram illustrating the lifespan of small batteries used in electronic devices and their interrelationship indicators. DETAILED DESCRIPTION

[0037] Semiconductor devices may suffer from wear and tear when they are used continuously for a long period of time.

[0038] When a product is continuously subjected to degradation stress during use and the accumulated amount reaches a certain value, failure will occur with a predetermined probability.

[0039] The lifetime before a fault occurs depends on the supply voltage and the ambient temperature.

[0040] Instead of directly capturing the wearout failure phenomenon, the inventors have studied predicting the wearout failure based on the degradation stress accumulation value of the power supply voltage and the ambient temperature received by the semiconductor device.

[0041] Based on the degradation stress accumulation value, the present disclosure applies the above discussion, which is a technical concept of making a prediction without detecting the ambient temperature and the power supply voltage received by the semiconductor device.

[0042] In the present disclosure, a semiconductor device having a stress detection circuit is mounted to an existing electronic system to utilize the semiconductor device having the stress detection circuit, such as a thermometer.

[0043] That is, the temperature of the electronic system is detected based on the accumulated degradation stress value. Alternatively, when a power supply voltage from a small battery or an ambient power generation device is supplied to a semiconductor device having a stress detection circuit, the life of the small battery and the output voltage of the ambient power generation device are predicted based on the accumulated degradation stress value.

[0044] First, the relationship between the amount of stress and the lifetime of a semiconductor device will be described.

[0045] The references are incorporated herein by reference.

[0046] “Failure Mechanisms and Models for Semiconductor Devices,” JEDEC Publication No. 122E.

[0047] As described in the reference, for the gate oxide wear failure factors of the device, such as time-dependent dielectric breakdown (Time-Dependent Dielectric Breakdown, hereinafter referred to as gate-TDDB) and negative bias temperature instability (hereinafter referred to as NBTI), the lifetime depends, for example, on the voltage V to the power of -n. -n (power law model), or the inverse of voltage (exp(-BV)) (V model), and at the same time depends on the exponential of the inverse of temperature (exp(Ea / kT)).

[0048] In the loss failure factors of electromigration and stress migration, the lifetime depends on the exponential of the inverse of temperature (exp(Ea / kT)) and has a small voltage dependence. Where n, B and Ea are coefficients specific to the loss failure factor, and k is the Boltzmann constant.

[0049] As shown in the following equations (1) and (2), the amount of stress can be expressed by the inverse of the life.

[0050] For gate-TDDB, NBTI:

[0051] 1 / τ(T,V)∝1(V -n exp(Ea / kT))=V n exp(-Ea / kT)…(1)

[0052] where τ(T,V) is a function of temperature (T), voltage (V), and is the wear failure lifetime that depends on T and V.

[0053] For electromigration and stress migration:

[0054] 1 / τ(T)∝1(V -n exp(Ea / kT))=exp(-Ea / kT)…(2)

[0055] where τ(T) is a function of temperature (T) and is the wear failure life.

[0056] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0057] However, in the following description, the same components are denoted by the same reference numerals, and repeated descriptions thereof are omitted.

[0058] It should be noted that for the sake of clarity of explanation, the drawings may be schematically represented compared to actual embodiments, but are only for examples and do not limit the interpretation of the present invention.

[0059] (Example of Configuration of Semiconductor Device)

[0060] Figure 1 is a diagram showing a configuration example of a semiconductor device according to an embodiment.

[0061] The semiconductor device 1 is a semiconductor integrated circuit device formed on a semiconductor substrate such as single crystal silicon (also referred to as a semiconductor chip) using, for example, a known method of manufacturing a CMOS transistor.

[0062] A semiconductor device 1 such as a thermometer is mounted on an electronic device or a device constituting an electronic system and is used to measure the temperature of the electronic device or device to be measured. The semiconductor device 1 includes a stress detection circuit 10, a wireless communication circuit 20, a first clock generation circuit CGH, a second clock generation circuit CGL, and a clock selection circuit SEL1.

[0063] The antenna ANT is connected to the wireless communication circuit 20 .

[0064] The semiconductor device 1 is provided inside a semiconductor package.

[0065] The semiconductor device 1 does not need to be formed of one semiconductor chip.

[0066] The stress detection circuit 10 , the first clock generation circuit CGH, the second clock generation circuit CGL, and the clock selection circuit SEL1 are preferably formed of one semiconductor chip.

[0067] The wireless communication circuit 20 , the stress detection circuit 10 , the first and second clock generation circuits CGH and CGL, and the clock selection circuit SEL1 formed in one semiconductor chip (first semiconductor chip) may be formed in another semiconductor chip (second semiconductor chip).

[0068] In this case, the first semiconductor chip and the second semiconductor chip are provided inside one semiconductor package. The stress detection circuit 10 converts the temperature of the electronic device or the apparatus to which the semiconductor device 1 is attached into the degradation stress intensity using a predetermined degradation model (for example, the Arrhenius model), and calculates the accumulated degradation stress amount obtained by integrating the degradation stress intensity. The stress detection circuit 10 includes a ring oscillator RO, a circuit for holding the accumulated degradation stress amount (accumulated degradation stress amount holding circuit) ST, an arithmetic circuit AC, and a control circuit CN.

[0069] The ring oscillator RO has a temperature dependency of its oscillation frequency.

[0070] The oscillation frequency of the ring oscillator RO is strongly correlated with the amount of degradation stress.

[0071] In this regard, the oscillation frequency of the ring oscillator RO may be regarded as thermal stress information HSI.

[0072] The accumulated degradation stress amount holding circuit ST includes a synchronous buffer (first synchronous buffer) SB and an accumulated stress counter SC.

[0073] The synchronization buffer SB acquires and temporarily holds the oscillation frequency (thermal stress information HSI) of the ring oscillator RO every unit count operation period.

[0074] The unit count operation period is a count sampling period of a constant period in which the temperature can be considered to be approximately constant.

[0075] The accumulated stress counter SC continues to add (accumulate) the oscillation frequency (thermal stress information HSI) of the ring oscillator RO output from the synchronization buffer SB, and holds the result as an accumulated stress count value CU.

[0076] The accumulated degradation stress amount holding circuit ST further includes a circuit (switching count information holding circuit) CST for holding the switching count information CSI.

[0077] The switching count information CSI will be described later.

[0078] The arithmetic circuit AC performs the following arithmetic operation: for calculating the thermal stress amount HSV based on the accumulated stress count value CU held by the accumulated stress counter SC.

[0079] The thermal stress magnitude HSV can also be called cumulative thermal stress information.

[0080] The arithmetic circuit AC may be configured by a hardware circuit, or may be configured by software executed by a central processing unit CPU provided in the semiconductor device 1 .

[0081] The controller CN maintains a plurality of operation determination thresholds OP1 , OP3 .

[0082] The plurality of operation determination threshold values ​​OP1 , OP3 are used as determination threshold values ​​for determining the operation state of an electronic instrument or device to which the semiconductor device 1 is attached.

[0083] The controller CN compares the thermal stress information HSI from the synchronization buffer SB with a plurality of operation determination thresholds OP1 , OP3 .

[0084] The control circuit CN generates a first control signal CC1 and a second control signal CC2 based on a comparison result of the thermal stress information HSI from the synchronization buffer SB and the first operation determination threshold OP1.

[0085] The first control signal CC1 is output to the wireless communication circuit 20 and the switching count information holding circuit CST, and the second control signal CC2 is output to the clock selection circuit SEL1.

[0086] When the thermal stress information HIS changes from a first state greater than the first operation determination threshold OP1 to a second state less than the first operation determination threshold OP1 , the control circuit CN outputs a control signal CC1 so that the thermal stress information HIS temporarily changes to an active level as a trigger condition.

[0087] When the thermal stress information HIS is in the first state greater than the first operation determination threshold OP1, the control circuit CN also outputs the second control signal CC2 as an active level.

[0088] On the other hand, when the thermal stress information HIS is in the second state less than the first operation determination threshold OP1, the control circuit CN outputs the second control signal CC2 as an inactive level.

[0089] The third operation determination threshold OP3 will be described later.

[0090] The thermal stress information HIS changes from a first state greater than the first operation determination threshold OP1 to a second state less than the first operation determination threshold OP1, indicating that the temperature of an electronic instrument or device to which the semiconductor device 1 is attached has dropped.

[0091] This is considered to indicate that the electronic equipment or device to which the semiconductor device 1 is attached has shifted from an operating state to a non-operating state.

[0092] Based on the activation level of the first control signal CC1 , the radio communication circuit 20 wirelessly transmits the thermal stress amount HSV from the antenna ANT.

[0093] The first control signal CC1 is used as a transmission trigger signal of the wireless communication circuit 20 .

[0094] The switching count information holding circuit CST increases the switching count by 1 based on the activation level of the control signal CC1 , thereby updating the switching count information CSI.

[0095] The switching count information CSI indicates the number of times the thermal stress information HIS has changed from a first state in which the thermal stress information HIS is greater than a first operation determination threshold OP1 to a second state in which the thermal stress information HIS is less than the first operation determination threshold OP1.

[0096] The first clock generating circuit CGH generates a first operation clock signal (first clock signal) of a high-speed frequency (first frequency) fH for the normal operation of the semiconductor device 1 .

[0097] On the other hand, the second clock generating circuit CGL generates a second operation clock signal (second clock signal) of a low-speed frequency (second frequency) fL compared to the high-speed frequency fH.

[0098] In one example, the frequency fL is a frequency such as (fH / 1000).

[0099] Based on the input of the second control signal CC2 to the switching circuit CK, the first operating clock signal of the high-speed frequency fH generated by the first clock generating circuit CGH and the second operating clock signal of the low-speed frequency fL generated by the clock generating circuit CGL are switched, and the clock selection circuit SEL1 outputs the operating clock CLK of the stress detection circuit 10.

[0100] When the thermal stress information HSI is equal to or greater than the first operation determination threshold OP1 , the first operation clock signal of the high speed frequency fH generated by the first clock generation circuit CGH is given as the operation clock CLK of the stress detection circuit 10 .

[0101] When the thermal stress information HSI is equal to or smaller than the first operation determination threshold OP1 , the second operation clock signal of the slow frequency fL generated by the second clock generation circuit CGL is given as the operation clock CLK of the stress detection circuit 10 .

[0102] That is, the clock selection circuit SEL1 selects the first operation clock signal of the high-speed frequency fH as the operation clock CLK based on the activation level of the second control signal CC2.

[0103] On the other hand, the clock selection circuit SEL1 selects the second operation clock signal of the low-speed frequency fL as the operation clock CLK based on the deactivated level of the second control signal CC2 .

[0104] The oscillation frequency of the ring oscillator RO will be described.

[0105] Due to the influence of temperature on degradation stress, in addition to the degradation factors according to the Arrhenius model, it is known that there are degradation factors that are affected by temperature rise and fall.

[0106] According to the reference, the degradation stress intensity is expressed as shown in Equations 3 and 4.

[0107] Degradation stress intensity of degradation factor according to Arrhenius model (= inverse of life (τ(T))):

[0108] Deterioration Stress Strength∝exp(-Ea / kT)…(3)

[0109] Degradation stress intensity of degradation factors affected by temperature rise and fall:

[0110] Deterioration Stress Strength∝ΔT n f m x exp(-Ea / kT)…(4)

[0111] Where n, m are coefficients specific to the wear-out failure factor, ΔT is the width of the temperature rise and fall, f is the frequency of the temperature rise and fall, Ea is the activation energy (temperature dependence coefficient), k is the Boltzmann constant, and T is the absolute temperature (K).

[0112] The switching count information CSI is information related to f in Equation 4.

[0113] Therefore, the degradation stress intensity can be calculated in consideration of the switching count information CSI.

[0114] The oscillation frequency of the ring oscillator RO can be expressed as a function of temperature (T).

[0115] Assuming that the oscillation frequency of the ring oscillator RO is F(T), F(T) is proportional to the exponent exp(Ea / kT) of the inverse of temperature.

[0116] Therefore, F(T) satisfies the following relationship (Equation 5) and depends largely on T.

[0117] F(T)∝exp(-Ea / kT)…(5)

[0118] The ring oscillator RO has the characteristic of Equation 5.

[0119] That is, by detecting the oscillation frequency of the ring oscillator RO, the temperature (T) can be measured.

[0120] The timing at which the thermal stress information HSI measured by the stress detection circuit 10 has dropped to a predetermined level (first operation determination threshold OP1 ) is regarded as the timing at which the electronic system (electronic device or apparatus) to be measured has stopped operating.

[0121] At the timing when the electronic system (electronic instrument or device) to be measured stops operating, the electromagnetic waves and heat generated by the electronic system to be measured are considered to be relatively low.

[0122] Therefore, the semiconductor device 1 is not affected by electromagnetic waves and heat generated by the electronic system to be measured, and can stably wirelessly transmit the thermal stress amount HSV as a measurement result to the outside from the wireless communication circuit 20 based on the first control signal CC1.

[0123] In addition, since it is not necessary for the semiconductor device 1 to receive standby stop information from the control system of the electronic system, the power consumption of the semiconductor device 1 can be reduced.

[0124] Alternatively, with respect to a control system of an existing electronic system, it is not necessary to perform a design change related to issuing system stop information to the stress detection circuit 10 , and the electronic system to be measured of the semiconductor device 1 is easy to implement.

[0125] Judging by the level of the thermal stress information HSI, at the timing when the electronic system is considered to have stopped, since the operating clock CLK of the stress detection circuit 10 switches from the high-speed frequency fH to the low-speed frequency fL, the stress detection circuit 10 is in a low power consumption state until the start of the next operation is detected.

[0126] (Configuration examples of electronic systems and electronic devices)

[0127] Figure 2 is a diagram illustrating a configuration example of an electronic system according to an embodiment.

[0128] like Figure 2 As shown, the electronic device ED includes: a semiconductor device 1 provided with an antenna ANT, a small battery BAT for supplying a power supply potential Vd and a ground potential Vs to the semiconductor device 1, and a circuit board CB on which the semiconductor device 1 and the battery BAT are mounted.

[0129] In one example, the battery BAT may be a coin cell, a button cell, or the like.

[0130] The electronic device ED is attached to an electronic device or apparatus whose temperature is to be measured.

[0131] exist Figure 2 In the figure, a motor control system is exemplarily shown as an electronic system SYS, which includes a motor MT and a motor control circuit MTC.

[0132] The motor MT corresponds to electronic equipment and devices as a temperature measurement object.

[0133] The electronic device ED is attached to the outer wall surface of the motor MT.

[0134] The motor control circuit MTC controls the rotation operation of the motor MT, controls the rotation stop of the motor MT, and performs control operations such as controlling the rotation speed of the motor MT.

[0135] The motor control circuit MTC receives the thermal stress HSV wirelessly transmitted from the antenna ANT of the electronic device ED, and can control the operation of the motor MT.

[0136] The receiving side of the thermal stress amount HSV wirelessly transmitted from the antenna ANT is not limited to the motor control circuit MTC.

[0137] The receiving side of the thermal stress amount HSV may be another network device (not shown).

[0138] like Figure 1 In the semiconductor device 1 described in the above, the power consumption of the semiconductor device 1 is reduced because the operation clock CLK of the stress detection circuit 10 is at the low speed frequency fL during the period when the electronic system SYS is considered to have stopped.

[0139] Therefore, the life or usage time of the small battery BAT for supplying power to the semiconductor device 1 can be extended.

[0140] Therefore, the replacement frequency of the small battery BAT can be reduced.

[0141] Wireless transmission of measurement results is also possible Figure 1 Stable execution as described in .

[0142] Furthermore, the existing electronic system has the effect of being simply added to the electronic device ED like a thermometer.

[0143] The power supply to the semiconductor device 1 is not limited to the small battery BAT.

[0144] Instead of the small battery BAT, an ambient power generation device that generates a voltage by light or vibration may be used as a power source for the semiconductor device 1 .

[0145] (Description of Thermal Stress Information HSI, First Operation Determination Threshold OP1, and Third Operation Determination Threshold OP3)

[0146] Figure 3 is a diagram schematically showing a time course of thermal stress information of an electronic system.

[0147] The vertical axis represents thermal stress information HSI, and the horizontal axis represents time t.

[0148] The electronic system SYS will repeat the operation state OP and a state different from the operation state OP.

[0149] exist Figure 3 , a state different from the operating state OP is shown as a standby state STB.

[0150] In the operating state OP, the thermal stress information HSI is large, whereas in the standby state STB, the thermal stress information HSI is smaller than the thermal stress information HSI in the operating state OP.

[0151] The control circuit CN of the semiconductor device 1 detects transition points of the thermal stress information HSI indicated by points A, B, and C to generate control signals CC1 , CC2 , and the like.

[0152] Point A is the time when the thermal stress information HSI changes from a first state in which the value of the thermal stress information HSI is greater than the first operation determination threshold OP1 to a second state in which the value of the thermal stress information HSI is less than the first operation determination threshold OP1.

[0153] The control signal CC1 triggers the radio transmission of the thermal stress level HSV and further triggers the updating of the switching count CSI.

[0154] The control signal CC2 causes the clock of the operation clock CLK of the stress detector 10 to switch from the fast frequency fH to the slow frequency fL.

[0155] Point B is the time when the thermal stress information HSI changes from a second state in which the value of the thermal stress information HSI is less than the first operation determination threshold OP1 to a first state in which the value of the thermal stress information HSI is greater than the first operation determination threshold OP1.

[0156] The control signal CC2 causes the operating clock CLK of the stress detector 10 to switch from the slow frequency fL to the fast frequency fH.

[0157] Point C is the timing at which the value of the thermal stress information HSI exceeds the third operation determination threshold OP3.

[0158] The third operation determination threshold OP3 is used as an abnormal thermal stress determination threshold for determining that the value of the thermal stress information HSI has become abnormal.

[0159] Since point C indicates an abnormality of the electronic system, the thermal stress amount HSV may be wirelessly transmitted by the wireless communication circuit 20 .

[0160] Alternatively, the abnormality occurrence information of the electronic system SYS may be wirelessly transmitted by the wireless communication circuit 20 .

[0161] Therefore, a person who performs operation management and maintenance of the electronic system SYS can perform maintenance such as stopping operation of the electronic system SYS and replacing components and devices of the electronic system SYS based on the thermal stress amount HSV and the abnormality occurrence information.

[0162] Therefore, the first state in which the value of the thermal stress information HSI is greater than the first operation determination threshold OP1 may be regarded as a duration of the operation state OP of the electronic system.

[0163] On the other hand, the second state in which the value of the thermal stress information HSI is less than the first operation determination threshold OP1 may be regarded as a duration of the standby state STB of the electronic system.

[0164] (Examples of applicable electronic systems)

[0165] Figure 4 It is an icon application Figure 1 semiconductor device or Figure 2 An example diagram of an electronic system of an electronic device.

[0166] Figure 4 A correspondence relationship between each electronic system and an operation state OP of each electronic system and a state other than the operation state OP (ie, a standby state STB) is shown.

[0167] Apart from Figure 2 In addition to the motor control system shown in , applicable systems include LED systems, TPMS systems, power line systems, etc.

[0168] The motor control system controls the rotation stop and rotation operation of the motor.

[0169] The motor rotation stop corresponds to the standby state STB, while the motor rotation corresponds to the operating state OP. When the motor rotates, the temperature of the motor rises. When the motor stops rotating, the temperature of the motor becomes low.

[0170] The electronic device ED is mounted on the outer wall of the motor, and the temperature of the motor is measured.

[0171] LED systems use light-emitting diodes (LEDs) to control the turning off and on of LED lighting.

[0172] The LED lighting being off corresponds to the standby state STB, while the LED lighting being on corresponds to the operating state OP.

[0173] When LED lighting is turned on, the temperature of the light emitting diode becomes high.

[0174] When the LED lighting is turned off, the temperature of the light emitting diode becomes low.

[0175] The conductor device 1 or the electronic device ED is mounted on the circuit board on which the light emitting diode is mounted, and the temperature of the circuit board on which the light emitting diode is mounted is measured.

[0176] TPMS (Tire Pressure Monitoring System: Tire Pressure Monitoring System) is a system that detects the pressure of automobile tires. The stopped state of the automobile corresponds to the standby state STB, and the running state of the automobile corresponds to the operating state OP.

[0177] When a car runs, the temperature of a gas such as air or nitrogen filled in the tire rises.

[0178] When the vehicle stops, the temperature of the gas filled in the tire drops.

[0179] The semiconductor device 1 or the electronic device ED is mounted on the pressure detection device mounted on the tire valve, and the temperature of the gas filled in the tire is measured.

[0180] The transmission line system transmits electricity from renewable energy sources (RE), such as wind and solar power, from power plants to the transmission lines.

[0181] The stop state of power transmission to the power line corresponds to the standby state STB, and the power transmission state to the power line corresponds to the operating state.

[0182] When electricity is transmitted to the transmission line, the temperature of the transmission line increases.

[0183] When the transmission of electricity to the power line stops, the temperature of the power line becomes low.

[0184] The electronic device ED is attached to the power line, and the temperature of the power line is measured.

[0185] In one example, the transmission line is a conductive line such as a copper line, and the conductive line is configured to be coated with an insulating cover made of an insulating material. When the temperature of the conductive line is higher than expected, the insulating cover may be burned off.

[0186] In order to prevent such a situation where the insulation covering burns, the temperature of the transmission line is preferably measured.

[0187] (Variation of the First Operation Determination Threshold)

[0188] Figure 5 is a diagram illustrating a modified form of the operation determination threshold value.

[0189] exist Figure 5 , the vertical axis represents thermal stress information HSI, and the horizontal axis represents time t.

[0190] exist Figure 3 In the example, the threshold OP1 is determined by the first operation to detect point A and point B.

[0191] exist Figure 5 In the embodiment, in addition to the first operation determination threshold OP1, a second operation determination threshold OP2 is newly provided.

[0192] In one embodiment, the second operation determination threshold OP2 is greater than the first operation determination threshold OP1.

[0193] Therefore, the control circuit CN is configured to maintain three operation determination thresholds: a first operation determination threshold OP1 , a second operation determination threshold OP2 , and a third operation determination threshold OP3 .

[0194] Three operation determination thresholds of a first operation determination threshold OP1 , a second operation determination threshold OP2 , and a third operation determination threshold OP3 are used as operation determination thresholds for determining an operation state of an electronic system (electronic device or apparatus) to be measured.

[0195] The first operation determination threshold OP1 is used to determine the Figure 3 Detect point A in the same way.

[0196] That is, the first operation determination threshold OP1 is used for the case where the value of the thermal stress information HSI drops from a first state to a second state, wherein in the first state, the value of the thermal stress information HSI is greater than the first operation determination threshold OP1, and in the second state, the value of the thermal stress information HSI is less than the first operation determination threshold OP1.

[0197] On the other hand, the second operation determination threshold OP2 is used to detect point B.

[0198] That is, the second operation determination threshold OP2 is used for the case where the value of the thermal stress information HSI drops from a first state to a second state, wherein in the first state, the value of the thermal stress information HSI is less than the second operation determination threshold OP2, and in the second state, the value of the thermal stress information HSI is greater than the second operation determination threshold OP2.

[0199] By giving hysteresis to the operation determination thresholds as in the first operation determination threshold OP1 and the second operation determination threshold OP2 , the problem of repeated or misjudged determination of the points A and B in a short period of time due to the influence of fluctuation or noise can be solved.

[0200] In addition to providing the first operation determination threshold OP1 and the second operation determination threshold OP2, a method is also provided such as performing a final determination after confirming that the thermal stress information HSI continues to decrease or increase through multiple unit count operations, preferably using a method that can eliminate the influence of fluctuations and noise.

[0201] (Example of setting an operation determination threshold)

[0202] Next, some examples of setting the operation determination threshold value will be described.

[0203] Figure 6 is a diagram illustrating a first example of setting the operation determination threshold.

[0204] like Figure 6 As shown, the control circuit CN includes a register REG for holding a plurality of operation determination thresholds OP1, OP2, and OP3.

[0205] exist Figure 1 A nonvolatile memory NVM such as a flash memory is provided in the solid-state device 1, and the nonvolatile memory NVM stores default values ​​OPD of a plurality of operation determination thresholds (OP1, OP2, and OP3).

[0206] The default value OPD is configured to be read into the register REG in response to a power-on reset of the semiconductor device 1 (for example, power is supplied to the semiconductor device 1 from a battery or the like).

[0207] In the default value OPD, in one example, the default value of the first operation determination threshold OP1 may be a value of thermal stress information HSI corresponding to a temperature (e.g., 50° C.) suitable for distinguishing between an operating state OP and a standby state STB of the electronic system SYS to which the semiconductor device 1 is attached.

[0208] The default value of the second operation determination threshold OP2 may be a value slightly higher than the default value of the first operation determination threshold OP1 , for example, a value corresponding to the thermal stress information HSI of 55° C.

[0209] The default value of the third operation determination threshold OP3 is set to a value of the thermal stress information HSI at which the thermal stress information HSI can determine the degree of failure or abnormality of the corresponding electronic system SYS.

[0210] A default value of the third operation determination threshold OP3 may be set based on the corresponding electronic system SYS.

[0211] (Example 2 of setting the motion judgment threshold)

[0212] Figure 7 is a diagram illustrating a second example of setting the operation determination threshold.

[0213] Figure 7 and Figure 6 The difference is: Figure 7 A rewrite circuit RWC for rewriting the contents of the register REG is provided.

[0214] Other configuration and operation Figure 6 The same, so redundant description will be omitted.

[0215] An administrator or user of the electronic system SYS can set an operation determination threshold value optimal for the use environment of the electronic system SYS by using the rewrite circuit RWC.

[0216] That is, when a power-on reset is performed, the default values ​​OPD of the plurality of operation determination thresholds OP1, OP2, OP3 stored in the register REG can be changed to operation determination thresholds optimal for the use environment of the electronic system SYS by using the rewriting circuit RWC.

[0217] This allows the operation of the electronic system to be determined more accurately.

[0218] (Example 3 of setting the operation judgment threshold)

[0219] Figure 8 is a diagram illustrating a third example of setting the operation determination threshold.

[0220] exist Figure 8 In the embodiment, the operation determination threshold value stored in the register REG is automatically adjusted or updated to an optimal operation determination threshold value based on the past thermal stress history.

[0221] The user sets the upper limit value UPL and the lower limit value LOL of the expected numerical value EXV of the switching count per elapsed time to the nonvolatile memory NVM.

[0222] The register value automatic correction circuit RAC automatically adjusts the operation determination threshold value OP1 during use of the semiconductor device 1 , for example.

[0223] That is, when the actual switching count CSR per elapsed time ET exceeds the upper limit value UPL of the expected switching count (EXV) ((CSR / ET) > UPL), the register value automatic correction circuit RAC decreases the value of the operation determination threshold OP1 stored in the register REG by a predetermined value N (-Ndown).

[0224] When the actual switching count CSR per elapsed time ET is lower than the lower limit LOL of the expected switching count (EXV) ((CSR / ET) < LOL), the register value automatic correction circuit RAC increases the value of the operation determination threshold OP1 stored in the register REG by a predetermined value N (+Nup).

[0225] The switching count is the frequency at which the operation state OP changes to the standby state STB, and the register value automatic correction circuit RAC is activated each time the switching count is updated.

[0226] Therefore, the value of the first operation determination threshold stored in the register REG of the control circuit CN can be automatically updated to the optimal determination threshold based on the previous thermal stress history, enabling more accurate operation determination of the electronic system SYS.

[0227] (Configuration example of stress detection circuit 10)

[0228] Fig. 9 is a diagram Figure 1 showing a configuration example of the main part of the stress detection circuit.

[0229] Fig. 9 Shows a configuration example of the operation clock CLK of the switching stress detection circuit 10.

[0230] In Fig. 9 the description of the switching count information holding circuit CST and the arithmetic circuit AC shown in Figure 1 is omitted.

[0231] The parts different from the stress detection circuit 10 in Figure 1 will be mainly described.

[0232] As Fig. 9 shown, the stress detection circuit 10 further includes a frequency divider circuit DIC and a selection circuit SEL2.

[0233] Furthermore, the cumulative degradation stress amount holding circuit ST further includes an intermittent operation control circuit IOC, and the operation circuit CN further includes a comparison circuit CPF.

[0234] The frequency divider circuit DIC divides the oscillation output Fout of the ring oscillator RO by 1 / N.

[0235] The selection circuit SEL2 selects the oscillation output Fout of the ring oscillator RO or the output of the frequency divider circuit DIC, and inputs it to the synchronous buffer SB.

[0236] The selection circuit SEL2 has its selection operation controlled by the output of the switching circuit CK in the clock selection circuit SEL1.

[0237] When the clock selection circuit SEL1 selects the first operation clock signal having the high-speed frequency fH as the operation clock CLK, the selection circuit SEL2 selects the oscillation output Fout of the ring oscillator RO and inputs it to the synchronous buffer SB.

[0238] On the other hand, when the clock selection circuit SEL1 selects the second operation clock signal having the low speed frequency fL as the operation clock CLK, the output of the switching circuit CK becomes 0, the selection circuit SEL2 selects the output of the frequency divider circuit DIC and inputs to the synchronous buffer SB.

[0239] The intermittent operation control circuit IOC receives the operation clock CLK to control the intermittent operation of the synchronous buffer and the accumulating stress counter SC.

[0240] The comparison circuit CPF performs a comparison operation between the thermal stress information HSI and the operation determination threshold in consideration of the frequency of the operation clock CLK.

[0241] As described above, the stress detection circuit 10 accumulates the oscillation output Fout of the ring oscillator RO in the accumulation stress counter SC.

[0242] The oscillation frequency of the ring oscillator RO is strongly correlated with the amount of degradation stress.

[0243] In other words, the oscillation frequency of the ring oscillator RO is related to (oscillation frequency of the ring oscillator RO∝degradation stress (thermal stress)∝exp(-Ea / kT)).

[0244] for Fig. 9 In order for the illustrated synchronous buffer to correctly capture the asynchronous oscillation of the ring oscillator RO, the frequency of the operating clock CLK of the stress detection circuit 10 must be faster than the frequency of the asynchronous oscillation of the ring oscillator RO.

[0245] If the frequency of the operation clock CLK is slower than the frequency of the asynchronous oscillation of the ring oscillator RO, a part of the asynchronous oscillation of the ring oscillator RO is lost, which causes the accumulated stress counter SC to acquire counts smaller than actual.

[0246] On the other hand, the oscillation frequency of the ring oscillator RO decreases logarithmically as the temperature decreases.

[0247] In the stress detection circuit 10, while correctly capturing the asynchronous oscillation of the ring oscillator RO, when the electronic system SYS is stopped (standby state STB), the frequency of the operating clock CLK (low-speed frequency fL) can be logarithmically slower than the frequency of the operating clock CLK (high-speed frequency fH) during operation of the electronic system (fL=fH / 1000).

[0248] Therefore, when the electronic system SYS stops, the stress detection circuit 10 can detect the next transition of the operation state for the electronic system SYS with low power consumption.

[0249] Incidentally, the asynchronous oscillation of the ring oscillator RO can be correctly captured by even further lowering the slow frequency fL, as Fig. 9 As shown, when operating at the slow frequency fL, the oscillation output Fout of the ring oscillator RO can be configured to be captured by the synchronous buffer SB after being slowed down to a 1 / N frequency by the frequency divider circuit DIC.

[0250] Therefore, during the standby state STB period of the electronic system, the power consumption of the semiconductor device 1 can be further reduced.

[0251] Fig. 9 The control circuit CN has a comparison circuit CPF that takes the frequency state of the operation clock CLK into consideration.

[0252] The comparison circuit CPF performs comparison in consideration of the operation of the stress detection circuit 10 in units of the number of clock counts.

[0253] That is, when the operation clock CLK switches from high-speed frequency fH to low-speed frequency fL, even if the count number is the same, in the case of real-time counting, the time of the low-speed operation clock (fL) is longer than the time of the high-speed operation clock (fH) (fH / fL).

[0254] Therefore, when the operation determination threshold OP1 is defined by the thermal stress count at the operation clock CLK of the high speed frequency fH, the operation determination threshold (OP1) is multiplied by (fH / fL) at the operation clock CLK of the low speed frequency fL.

[0255] Alternatively, the comparison is made by reducing the thermal stress information HSI by (1 / (fH / fL)).

[0256] Therefore, even if the frequency of the operation clock is switched, the comparison operation between the operation confirmation threshold value and the thermal stress information HSI can be correctly performed.

[0257] (Configuration Example and Modification Example of Accumulated Degradation Stress Holding Circuit)

[0258] Some configuration examples and modifications of the main part of the accumulated degradation stress amount holding circuit ST will be described.

[0259] Fig.10 It is shown Figure 1 FIG. 1 is a diagram showing an example of a configuration of a main part of a circuit for maintaining cumulative degradation stress.

[0260] like Fig.10 As shown, the accumulated stress counter SC of the accumulated degradation stress amount holding circuit ST holds the accumulated stress count value CU, and the switching count information holding circuit CST holds the switching count information CSI.

[0261] In this example, the accumulated stress count value CU is obtained by accumulating the accumulated stress count values ​​during the operation state OP period of the electronic system SYS and the accumulated stress count values ​​during the standby state STB period of the electronic system SYS without distinguishing them from each other.

[0262] Fig.11 2 is a diagram showing a configuration example of a main part of an accumulated degradation stress amount holding circuit according to a first modification.

[0263] like Fig.11 As shown, the accumulated degradation stress holding circuit STa includes an accumulated stress counter SC1 and an accumulated stress counter SC1a.

[0264] The accumulated stress counter SC1 holds an accumulated stress count value CU1 during the operating state OP of the electronic system SYS.

[0265] The accumulated stress counter SC1 a maintains an accumulated stress count value CU2 during the standby state STB of the electronic system SYS.

[0266] That is, the accumulated stress count value CU1 during the operation state OP period of the electronic system SYS and the accumulated stress count value CU2 during the standby state STB period of the electronic system SYS are distinguished from each other and held in the accumulated degradation stress amount holding circuit STa.

[0267] and Fig.10 The accumulated degradation stress force keeps the circuit ST compared to Fig.11 The accumulated degradation stress holding circuit STa has the advantage of increased information amount.

[0268] However, since two cumulative stress counters SC1 , SC1 a are required, it should be noted that the area of ​​the semiconductor chip forming the semiconductor device 1 and the power loss are increased.

[0269] Fig.12: is a diagram showing a configuration example of a main part of an accumulated degradation stress amount holding circuit according to a second modification.

[0270] Different from Fig.11 The accumulated degradation stress of the circuit STa is maintained, Fig.12 The accumulated degradation stress holding circuit STb does not have an accumulated stress counter SC1a in the accumulated degradation stress holding circuit STb, but only provides an accumulated stress counter SC1.

[0271] The accumulated stress counter SC1 holds an accumulated stress count value CU1 during the operating state OP of the electronic system SYS.

[0272] During the operating state OP of the electronic system SYS, the electronic system SYS is at a high temperature.

[0273] The amount of degradation stress in the period of the high temperature operation state OP is logarithmically larger than that in the period of the standby state STB within the same period.

[0274] Therefore, as long as the period of the standby state STB is not logarithmically greater than the period of the operating state OP, the amount of accumulated degradation stress during the period of the standby state STB can be ignored.

[0275] Accordingly, with Fig.10 Compared with the accumulated degradation stress level holding circuit ST, the accumulated degradation stress level holding circuit STb only performs a continuous monitoring operation (detection operation) for detecting the thermal stress intensity of the next transition for the period of the operating state OP during the period of the standby state STB, and does not perform a counter operation related to accumulation.

[0276] Therefore, this can reduce the power consumption of the accumulated degradation stress amount holding circuit STb during the period of the standby state STB.

[0277] (Operation process of semiconductor device)

[0278] Fig.13 is a diagram for explaining an operation process of a semiconductor device according to an embodiment.

[0279] A power on reset is performed to start up the semiconductor device 1 (step S1 ).

[0280] After power-on resetting (step S1 ), the stress detection circuit 10 in the semiconductor device 1 operates with the operation clock CLK of the low-speed frequency fL (step S2 ).

[0281] The stress detection circuit 10 determines whether the thermal stress information HSI is equal to or greater than the OP operation determination threshold value (OP1) for each predetermined period (step S3).

[0282] If the thermal stress information HSI is equal to or less than the OP operation determination threshold value (OP1) (No), the thermal stress information HSI repeats step S3.

[0283] When the thermal stress information HSI becomes larger than the OP operation determination threshold value (OP1) (Yes), the operation clock CLK of the stress detection circuit 10 is switched from the operation clock of the low speed frequency fL to the operation clock of the high speed frequency fH (step S4).

[0284] After switching to the operation clock CLK of the high speed frequency fH, the stress detection circuit 10 accumulates the thermal stress information HSI, and determines whether the thermal stress information HSI is less than the OP operation determination threshold value (OP1) for each predetermined period (step S5).

[0285] If the thermal stress information HSI is not equal to or less than the first operation determination threshold value OP1 (No), the thermal stress information HSI repeats step S5.

[0286] When the thermal stress information HSI becomes equal to or smaller than the first operation determination threshold OP1 (Yes), first, the switching count information CSI is updated (step S6 ).

[0287] Next, the wireless communication circuit 20 transmits the accumulated thermal stress information (thermal stress value HSV) including the updated switching count information CSI (step S7 ).

[0288] Subsequently, the operation clock CLK of the stress detection circuit 10 is switched from the operation clock of the high-speed frequency fH to the operation clock of the low-speed frequency fL (step S8 ).

[0289] Next, the stress detection circuit 10 continues to determine whether the thermal stress information HSI is equal to or greater than the first operation determination threshold OP1 for each predetermined period by the operation clock CLK of the low speed frequency fL (step S3 ).

[0290] According to the operation process of the semiconductor device, when the electronic system SYS is stopped (standby state STB), the stress detection circuit 10 operates with the operation clock CLK of the low speed frequency fL.

[0291] The operation clock CLK of the low speed frequency fL is used only for the stress detection circuit 10 to detect that the thermal stress information HSI has shifted higher than the predetermined level (the first operation determination threshold OP1 ) again.

[0292] Therefore, the timing design of the operation clock of the logic circuits other than the stress detection circuit 10 in the semiconductor device 1 can be implemented with respect to the operation clock CLK of the high-speed frequency fH for normal operation.

[0293] Therefore, the design of the semiconductor device 1 is facilitated.

[0294] (First Modification of Stress Detection Circuit)

[0295] Fig.14 is a diagram illustrating a configuration example of a stress detection circuit according to a first modification.

[0296] Fig.14 The stress detection circuit 10a shown in FIG. 1 has a timer TM, a selection circuit SEL3, and an accumulated degradation stress holding circuit STc.

[0297] compared to Fig. 9 In the accumulated degradation stress amount holding circuit ST shown in FIG, an accumulated degradation stress amount holding circuit STc is newly provided with an accumulated time holding circuit CT.

[0298] exist Fig.14 In the stress detection circuit 10a, the ring oscillator RO, the frequency divider circuit DIC, the selection circuit SEL2, the synchronous buffer SB, the intermittent operation control circuit IOC, and the comparison circuit CPF are not shown.

[0299] As reference Fig.10 As described, the accumulated stress count value CU of the accumulated stress counter of the accumulated degradation stress level holding circuit STc is assumed to be a count value obtained in the following manner: the accumulated stress count values ​​during the period of the operating state OP of the electronic system SYS and the accumulated stress count values ​​during the period of the standby state STB of the electronic system SYS are accumulated without distinguishing them from each other.

[0300] When the operation clock CLK of the high-speed frequency fH is used, the selection circuit SEL3 selects the control signal CTM1 to be output by the timer TM and input to the accumulated time holding circuit CT.

[0301] Further, when the operation clock CLK of the low speed frequency fL is used, the selection circuit SEL3 selects the control signal CTM2 to be output by the timer TM, and inputs to the accumulated time holding circuit CT.

[0302] The accumulated time holding circuit CT is a circuit for holding the number of realizations of the unit count operation as accumulated time information.

[0303] As in Fig. 9 As described in the comparison circuit CPF of FIG. 1 , the unit count operation of the stress detection circuit 10 a is performed for a predetermined period of the clock period of the operation clock CLK.

[0304] The accumulated time holding circuit CT holds the number of executions of the unit count operation as accumulated time information.

[0305] Therefore, when the operating clock CLK of the stress detection circuit 10a is switched from the operating clock CLK of the high-speed frequency fH to the operating clock CLK of the low-speed frequency fL, even if the number of executions of the unit counting operations in the accumulated time holding circuit CT is the same, the real time of the unit counting operation of the operating clock CLK of the low-speed frequency fL becomes longer by (fH / fL) compared to when the operating clock CLK is the high-speed frequency fH.

[0306] This difference in real time may cause a problem when the accumulated stress count value during the operation state OP of the electronic system SYS and the accumulated stress count value during the standby state STB of the electronic system SYS are accumulated in one accumulated stress counter SC without distinguishing them from each other.

[0307] That is, since it is impossible to distinguish between the accumulated stress count value during the operating state OP of the electronic system SYS and the accumulated stress count value during the standby state STB of the electronic system SYS, the degradation stress at the operating clock CLK with a low frequency fL is relatively misidentified as (fH / fL) times the operating clock CLK with a high frequency fH.

[0308] like Fig.14 As shown, control signals CTM1, CTM2 from the timer TM in units of the number of counts of the clock frequency of the operation clock are changed to match in real time.

[0309] That is, at the operation time CLK at the low speed frequency fL, the timer TM controls the count number 1 / (fH / fL) compared to the operation time CLK at the high speed frequency fH to generate the control signal CTM2.

[0310] In binary representation, the output bits are shifted right by log2(fH / fL).

[0311] For example, when fH = 32 [MHz] and fL = 32 [KHz], since log fH / fL is 10, when the operating clock CLK with a high-speed frequency of fH is used, the timer count value 2 20 The generated control signal CTM1 is generated as the timer count value 2 when the operation clock CLK of the low speed frequency fL is used. 10 of the control signal CTM2.

[0312] In this way, absolute time is adjusted.

[0313] According to the stress detection circuit 10a, the clock frequency of the stress detection circuit 10a is switched, and even in the following case: the accumulated stress count value during the period of the operating state OP of the electronic system SYS and the accumulated stress count value during the period of the standby state STB of the electronic system SYS are accumulated in one accumulated stress counter without distinguishing them, the stress detection circuit 10a can be operated correctly.

[0314] (Modification of the switching count information holding circuit)

[0315] Fig.15 It is used to illustrate Figure 1 FIG. 1 is a diagram of a modified form of a switching count information holding circuit.

[0316] Fig.16 : is a diagram for explaining a state transition diagram of a switching count information holding circuit of a modified form.

[0317] exist Fig.15 , the vertical axis shows thermal stress information HSI, and the horizontal axis shows time t.

[0318] The degradation stress associated with the frequency of temperature rise and fall shown in (Equation 4) is affected not only by the switching counts of the operation period OP and the standby period STB but also by the rise and fall of thermal stress during the operation period OP.

[0319] Since the change of thermal stress during the operation period OP is irregular, it is difficult to judge "up (rising)" or "down (falling)" during the operation period OP.

[0320] The median value m and standard deviation √(xm) of the thermal stress information HSI during the operation period OP 2 Can be used as a threshold for determining "up (rising)" and "down (falling)".

[0321] Here, the middle value m is the accumulated count / number of counts, and <> represents the average value of the enclosed values.

[0322] In the switching count information holding circuit CST, the threshold m1 which increases upward is set to m1=m+√(xm) 2 , and the downward decreasing threshold m2 is set to m2 = m-√(xm) 2 .

[0323] The median value m and the standard deviation √(xm) 2 is based on historical data. For example, the median and standard deviation of the thermal stress during the operating period OP from the previous operating state OP to the time of transition to the standby state STB may be used.

[0324] like Fig.15 and 16 As shown, when the thermal stress information HSI changes once below the intermediate value m and then changes to above the threshold value m1 of the rise Up, the “rise” is counted.

[0325] When the thermal stress information his transitions once below the intermediate value m and then transitions below the threshold value m2 of the down Down, the thermal stress information HSI is counted as “down”.

[0326] exist Fig.15 In the example, the rise is identified as five times Up1 to Up5.

[0327] exist Fig.15 In the example, the descent is determined as three times: Down1 to Down3.

[0328] In this way, the switching count information holding circuit CST holds five times of rising and three times of falling as the increment and decrement frequency information in the switching count information CSI.

[0329] According to the modified form of the switching count information holding circuit, by defining the number of rise and fall times of thermal stress during the operation period OP, it is possible to accurately obtain the number of rise and fall times of thermal stress. Therefore, by combining the switching count information CSI of the operation period OP and the standby period STB, it is possible to more accurately grasp the state of the degradation stress associated with the temperature rise and fall during the operation period OP.

[0330] (Second Modification of Stress Detection Circuit)

[0331] Fig.17 is a diagram showing a stress detection circuit according to a second modification.

[0332] like Fig.17 As shown, the stress detection circuit 10b includes a first ring oscillator RO, a second ring oscillator RO2 and an accumulated degradation stress holding circuit STd.

[0333] The accumulated degradation stress holding circuit STd includes a first synchronous buffer SB, a second synchronous buffer SB2, an accumulated time holding circuit CT, a first accumulated stress counter SC, a second accumulated stress counter SC2, and a switching count information holding circuit CST.

[0334] The first ring oscillator RO, the first synchronous buffer SB and the first accumulated stress counter SC correspond to Figure 1 The ring oscillator RO, synchronous buffer SB and accumulative stress counter SC shown in FIG.

[0335] The accumulated time holding circuit CT corresponds to Fig.14The accumulated time holding circuit CT shown in FIG.

[0336] In it Figure 1 and 14 In the combined configuration, the stress detection circuit 10b is further provided with a second ring oscillator RO2, a second synchronous buffer SB2 and a second accumulating stress counter SC2.

[0337] like Figure 1 As described in , the first ring oscillator RO is an oscillation circuit whose oscillation frequency varies according to temperature.

[0338] On the other hand, the second ring oscillator RO2 has both temperature- and voltage-dependent oscillation frequencies.

[0339] The oscillation output of the second ring oscillator RO2 is sent to the second synchronous buffer.

[0340] The second synchronization buffer SB2 acquires the oscillation frequency of the second ring oscillator RO2 for each unit count operation period, and temporarily holds it as the second thermal stress information.

[0341] The unit count operation period is a count sampling period of a constant period in which the temperature can be considered to be approximately constant.

[0342] The second accumulated stress counter SC2 continuously accumulates the second thermal stress information output from the second synchronization buffer SB2 and maintains the second thermal stress information as an accumulated stress count value CUVT.

[0343] Therefore, the first accumulated stress counter SC accumulates the first degradation stress amount (thermal stress information HSI) which significantly depends only on the temperature, and holds the accumulated stress count value (also referred to as the first accumulated stress count value) CU.

[0344] The second accumulated degradation stress counter SC2 accumulates the second degradation stress amount (voltage and thermal stress information) which significantly depends on both temperature and voltage, and holds the accumulated stress count value (also referred to as a second accumulated stress count value) CUTV.

[0345] The oscillation frequency of the second ring oscillator RO2 can be expressed as a function of temperature (T) and voltage (V).

[0346] Voltage (V) indicates the Figure 2 The small battery BAT provides a power supply potential Vd and a ground potential Vs as well as a potential difference (Vd-Vs) to the semiconductor device 1 .

[0347] Assuming that the oscillation frequency of the second ring oscillator RO2 is F(T, V), F(T, V) is proportional to the voltage dependence f(V) and the exponential of the inverse of temperature ((exp(-Ea2 / kT)), so that F(T, V) satisfies the following equation 6 and depends largely on T and V. Ea2 is the activation energy (temperature dependence coefficient).

[0348] F(T,V)∝f(V)exp(-Ea2 / kT)…(6)

[0349] The second ring oscillator RO2 has the property of Equation 6.

[0350] Assuming that the accumulated stress count value CU of the first accumulated stress counter SC is the count value Cnt1, the first accumulated stress counter SC is configured such that the count value Cnt1 for a predetermined period in which the temperature T is considered to be substantially constant is proportional to (exp(-Ea1 / kT).

[0351] The count number Cnt1 is expressed as Cnt1 = C1 exp(-Ea1 / kT).

[0352] Here, C1 is a constant related to the temperature dependence of the number of counts.

[0353] When the accumulated stress count value CUTV and count number Cnt2 of the second accumulated stress counter SC2, the second accumulated stress counter SC2, temperature T and voltage V are configured to be proportional to the count number Cnt2 of a predetermined period, which can be considered to be indicative of a constant f(V)exp(-Ea2 / kT).

[0354] The count Cnt2 is given by Cnt2 = f(V)C2 exp(-Ea2 / kT) = f(V)C2{exp(-Ea1 / kT)} q2 express.

[0355] Here, C2 is a constant related to the temperature dependency of the number of counts, and q2=Ea2 / Ea1.

[0356] Here, the variation range of the correlation index Kq2 considering the variation of the voltage dependency f(V) will be examined.

[0357] The correlation index between the accumulated value of the count number Cnt1 (hereinafter referred to as the Cnt1 accumulated value) and the accumulated value of the count number Cnt2 (hereinafter referred to as the Cnt2 accumulated value) is expressed by Equation 7 below.

[0358]

[0359] Here, the Cnt2 accumulated value and the Cnt1 accumulated value are actual measured values, N is the accumulated execution number of unit counting operations (counting operations for a predetermined period of time in which the temperature can be considered to be substantially constant), and the accumulated time for maintaining the accumulated execution number is the actual measured value of the circuit CT.

[0360] B(V) is an unknown value that depends on the voltage fluctuation history during the accumulation period.

[0361] Vchipmin and Vchipmax show the minimum value Vchipmin and the maximum value Vchipmax of the change in the power supply potential (Vd) of the semiconductor device 1 .

[0362] f(Vchipmin) shows the voltage dependence of the oscillation frequency of the second ring oscillator RO2 when the power supply potential (Vd) is the minimum value Vchipmin, and f(Vchipmax) shows the voltage dependence of the oscillation frequency of the second ring oscillator RO2 when the power supply potential (Vd) is the maximum value Vchipmax.

[0363] Therefore, the correlation index Kq2 is related to the average voltage dependency f(V) of the predetermined period held by the accumulated time holding circuit CT.

[0364] Further, the variation range of the correlation index Kq2d is obtained by considering the variation amount of the temperature T.

[0365] Here, ({exp(-Ea1 / kT)} in Equation 7 q2 Accumulated value) / [{exp(-Ea1 / kT) accumulated value} / N q2-1 ] is 1 or greater and less than Aq2.

[0366] Incidentally, Aq2 is a preset value when the worst case in the change of the temperature T is considered.

[0367] According to the above, the range of the correlation index Kq2 considering the change in temperature T is as follows:

[0368] f(Vchipmin)(C2 / C1 q2 )≤Kq2≤f(Vchipmax)Aq2(C2 / C1 q2 )Kq2 / (C2 / C1), and the power state of the power supply voltage (Vd) of the semiconductor device 1 changes between f(Vchipmin) and f(Vchipmax)Aq2).

[0369] Next, reference will be described Fig.17 The stress detection circuit 10b determines Figure 2 A method for evaluating the life of a small battery BAT used in electronic devices ED.

[0370] The correlation index Kq2 is used to determine the life of the small battery BAT.

[0371] Fig.18 This is a diagram illustrating the lifespan of small batteries used in electronic devices and their interrelationship indicators.

[0372] exist Fig.18 In the figure, the left vertical axis shows the ratio (Veff / Vtype) between the effective output voltage (Veff) of the actual output of the small battery BAT and the standard voltage (Vtype), the horizontal axis shows the time Time [h], and the right vertical axis shows the standardized cross-relationship index Kq2.

[0373] exist Fig.18 In the figure, line L1 schematically shows the ratio (Veff / Vtype) between the effective output voltage (Veff) of the small battery BAT and the standard voltage (Vtype). The output voltage of the small battery BAT decreases with the passage of usage time. When the life of the small battery BAT is approaching, the effective output voltage of the small battery BAT shows a significant decrease.

[0374] exist Fig.18 In the example shown in FIG. 2 , as shown by line L2 , the correlation index Kq2 associated with the voltage dependency f(V) changes.

[0375] Here, when calculating the normalized correlation index Kq2, the term involving temperature change in equation 7 ({exp(-Ea1 / kT)} q2 Accumulated value) / [{exp(-Ea1 / kT) accumulated value} / N q2-q ] is set to 1.

[0376] That is, Aq2 is set to 1.

[0377] As described above, due to the voltage dependence of the degradation stress amount f(V) from V n Or expressed as exp(BV), the normalized correlation index Kq2 decreases logarithmically as the output voltage of the miniaturized battery BAT decreases.

[0378] The correlation indicator Kq2 allows us to predict the lifetime of a small battery BAT relatively easily.

[0379] In the above explanation, the method of judging the life of the small battery BAT based on the time transition of the correlation index Kq2 has been described, but the time transition of the correlation index Kq2 may be regarded as the time transition of the second accumulated stress count.

[0380] Therefore, based on the time transition of the second accumulated stress count, it is possible to determine the life of the small-sized battery BAT.

[0381] If the temperature dependence of the oscillation frequency of the first ring oscillator RO and the temperature dependence of the oscillation frequency of the second ring oscillator RO2 are the same, the accumulated stress count value CU can be subtracted from the accumulated stress count value CUTV to calculate the change value related to the voltage dependence f(V), and based on the time transition of the change value, the life of the small battery BAT can be determined.

[0382] As in Figure 2 As described in the description of , even when an ambient power generation device that generates a voltage by light or vibration is used as a power source for the semiconductor device 1 instead of the small battery BAT, the correlation index Kq2 can be used to detect the voltage state.

[0383] Therefore, the correlation index Kq2 can be used to determine the stability of the voltage condition of the environmental power generation device.

[0384] That is, based on the temporal transition of the second accumulated stress counter value, the life of the small battery BAT or the stability of the voltage state of the ambient power generation device can be determined.

[0385] If the output voltage of the ambient power generation device is less than the predetermined voltage, the wireless transmission of the accumulated amount of degradation stress from the wireless communication circuit 20 is preferably delayed to wait for the voltage level of the output voltage of the ambient power generation device to recover above the predetermined voltage.

[0386] According to the second variation of the stress detection circuit, even if the power supply voltage of the small battery BAT is not continuously detected or monitored, the state of the output voltage of the small battery BAT or the environmental power generation device can be known based on the value of the degradation stress amount, thereby reducing the related storage area and the power consumption of the semiconductor device required for processing by continuously detecting or monitoring the large amount of data obtained.

[0387] Compared to the case where detection or monitoring of the output voltage of the small battery BAT or the ambient power generation device is performed once over a relatively long period of time, the risk of making false determinations due to erroneous measurements can be reduced by using the value integrated during the period, that is, the accumulated degradation stress amount.

[0388] The predetermined period for calculating the correlation index Kq2 may be a period after the standby state is changed to the operating state OP until the operating state OP is changed to the standby state STB (ie, a period of the operating state OP between the standby state STB and the standby state STB).

[0389] Therefore, the state of the output voltage (power supply potential (Vd)) of the small battery BAT can be detected at an appropriate frequency.

[0390] The correlation index Kq2 and other stress data are combined and wirelessly transmitted from the wireless communication circuit 20 .

[0391] Alternatively, the receiver may calculate the correlation index Kq2 based on the accumulated value of Cnt1 (the actual measured value of the first accumulated stress counter SC1), the accumulated value of Cnt2 (the actual measured value of the second accumulated stress counter SC2), and the actual measured value N of the accumulated time holding circuit CT.

[0392] In this case, other stress information, the Cnt1 accumulated value of the first accumulated stress counter SC1 and the Cnt2 accumulated value of the second accumulated stress counter SC2, and the measured value of the accumulated time holding circuit CT are wirelessly transmitted from the wireless communication circuit 20 to the receiving side together with other stress information.

[0393] This makes it possible to replace the small battery BAT with a stored new small battery BAT before the battery BAT reaches the end of its life.

[0394] Although the invention made by the present inventors has been described above specifically based on the embodiments, the present invention is not limited to the embodiments described above, and it goes without saying that the present invention can be modified in various ways.

Claims

1. A semiconductor device comprising: Holding circuit, including: a buffer configured to obtain thermal stress information having temperature dependency at each predetermined period; a stress counter configured to accumulate the thermal stress information and maintain the accumulated value as an accumulated stress count value; control circuitry including an operation determination threshold; clock selection circuit; and Wireless communication circuits, wherein the control circuit is configured to determine a state of thermal stress, the state of thermal stress being selected from: a first state in which the thermal stress information exceeds the operation determination threshold, or a second state in which the thermal stress information is lower than the operation determination threshold, wherein the wireless communication circuit is configured to transmit accumulated thermal stress information calculated according to the accumulated stress count value when the state of the thermal stress changes from the first state to the second state, wherein the holding circuit operates based on an operation clock, wherein the clock selection circuit is configured to change the frequency of the operating clock based on the state of the thermal stress, and The frequency of the operating clock in the second state is lower than the frequency of the operating clock in the first state.

2. The semiconductor device according to claim 1, wherein the control circuit further comprises an abnormal thermal stress threshold, The wireless communication circuit is further configured to transmit the accumulated thermal stress information when the thermal stress information exceeds the abnormal thermal stress threshold.

3. The semiconductor device according to claim 1, The holding circuit is further configured to hold switching information indicating the number of switchings between the first state and the second state.

4. The semiconductor device according to claim 1, The control circuit is further configured to perform detection of the thermal stress information exceeding the abnormal thermal stress threshold according to the operation clock of the second state.

5. The semiconductor device according to claim 1, wherein the control circuit is further configured to count the number of the operation clocks based on the count amount, wherein the count amount is configured to be set based on the frequency of the operating clock, and The holding circuit is further configured to input a count number of the operation clock.

6. The semiconductor device according to claim 3, wherein the switching information includes rise / fall information, and the rise / fall information indicates the number of rises and falls of the thermal stress information in the first state; The increase / decrease information is generated by determining an increase or decrease of the thermal stress information based on a median and a deviation of a transition history of the thermal stress information.

7. An electronic device comprising: The semiconductor device according to claim 1; an antenna connected to the wireless communication circuit of the semiconductor device; as well as a power generation device configured to supply a power supply voltage and a ground voltage to the semiconductor device, The power generation device comprises a battery or an environmental power generation device.

8. The electronic device according to claim 7, wherein the buffer of the holding circuit is further configured to obtain second thermal stress information having both temperature dependency and voltage dependency, wherein the holding circuit further comprises a second stress counter configured to accumulate the second thermal information into a second stress count value, and The control circuit is further configured to determine the remaining capacity of the battery or the voltage normality of the ambient power generation device.

9. An electronic system comprising: The electronic device according to claim 7; as well as An apparatus on which the electronic device is mounted.

10. An electronic system comprising: The electronic device according to claim 8; as well as An apparatus on which the electronic device is mounted.

11. A semiconductor device comprising: Stress detection circuit; Wireless communication circuits; A first clock generating circuit configured to generate a first clock signal having a first clock frequency; a second clock generating circuit configured to generate a second clock signal having a second clock frequency, the second clock frequency being slower than the first clock frequency; as well as A clock selection circuit implemented by a control circuit, The stress detection circuit comprises: a first ring oscillator, wherein the oscillation frequency of the first ring oscillator has temperature dependence; Accumulated degraded stress force holding circuit; and said control circuit having an operation determination threshold, The accumulated degradation stress holding circuit comprises: a first synchronous buffer configured to detect an oscillation frequency of the first ring oscillator for each unit count period and store the oscillation frequency as thermal stress information; and a first accumulated stress counter configured to accumulate the thermal stress information and keep the accumulated value as a first accumulated stress count value, The control circuit is configured as follows: determining a state of thermal stress, the state of thermal stress being selected from: a first state in which the thermal stress information exceeds the operation determination threshold, or a second state in which the thermal stress information is lower than the operation determination threshold, and When the state of the thermal stress changes from the first state to the second state, starting to transmit the accumulated thermal stress information calculated according to the first accumulated stress count value, wherein when the thermal stress information is in the first state, the clock selection circuit supplies the first clock signal as an operation clock to the stress detection circuit, and When the thermal stress information is in the second state, the clock selection circuit supplies the second clock signal as an operation clock to the stress detection circuit.

12. The semiconductor device according to claim 11, The stress detection circuit includes a frequency divider and a frequency divider selection circuit. wherein the frequency divider is configured to divide the frequency of the output of the first ring oscillator, and The frequency divider selection circuit is configured to select an output of the first ring oscillator or an output of the frequency divider and output the selected output to the first synchronous buffer.

13. The semiconductor device according to claim 11, The stress detection circuit includes a second ring oscillator, the oscillation frequency of the second ring oscillator has temperature dependence and voltage dependence, The accumulated degradation stress level holding circuit comprises: a second synchronization buffer configured to detect the oscillation frequency of the second ring oscillator for each unit count period and store the oscillation frequency as second thermal stress information; as well as The second accumulated stress counter is configured to accumulate the oscillation frequency of the second ring oscillator as second thermal stress information and keep the accumulated value as a second accumulated stress count value.

14. An electronic device comprising: The semiconductor device according to claim 11, an antenna connected to the wireless communication circuit of the semiconductor device; as well as A power generation device is configured to supply a power supply voltage and a ground voltage to the semiconductor device, wherein the power generation device includes a battery or an ambient power generation device.

15. An electronic system comprising: The electronic device according to claim 14; as well as An apparatus on which the electronic device is mounted.

16. An electronic device comprising: The semiconductor device according to claim 13, an antenna connected to the wireless communication circuit of the semiconductor device; as well as A power generation device is configured to supply a power supply voltage and a ground voltage to the semiconductor device, wherein the power generation device includes a battery or an ambient power generation device.

17. An electronic system comprising: The electronic device according to claim 16; as well as An apparatus on which the electronic device is mounted.

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