System and method for controlling plasma processing

Abstract

A plasma processing method includes: generating a first sequence of source power pulses; generating a second sequence of bias power pulses; combining the bias power pulses in the second sequence with the source power pulses in the first sequence to form a combined sequence of alternating source power pulses and bias power pulses; and generating a plasma including ions using the combined sequence and processing a substrate by delivering the ions to a major surface of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 718,454, filed on August 14, 2018, U.S. Provisional Application No. 62 / 724,879, filed on August 30, 2018, and U.S. Non-Provisional Application No. 16 / 221,971, filed on December 17, 2018, which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present invention relates generally to plasma processing and, in particular embodiments, to systems and methods for controlling plasma processing. Background Art

[0004] The formation of devices within a microelectronic workpiece may involve a range of fabrication techniques including the formation, patterning, and removal of multiple material layers on a substrate. In order to achieve the physical and electrical specifications of current and next generation semiconductor devices, process flows that reduce feature size while maintaining structural integrity are desired for various patterning processes.

[0005] Plasma processes are often used to form devices in microelectronic workpieces. For example, plasma etching and plasma deposition are common process steps during semiconductor device fabrication. During plasma processing, a combination of source power and bias power may be used to generate and direct the plasma. Fig.18 Conventional timing diagrams for applying source power and bias power during plasma processing are shown. In the top diagram, there are no distinct pulses in either the source power or the bias power. In the middle diagram, continuous bias power is applied without pulses while source pulses are applied. In the bottom diagram, continuous source power is applied without pulses while bias pulses are applied. Summary of the invention

[0006] According to an embodiment of the present invention, a plasma processing method includes: generating a first sequence of source power pulses; generating a second sequence of bias power pulses; combining the bias power pulses in the second sequence with the source power pulses in the first sequence to form a combined sequence of alternating source power pulses and bias power pulses; and generating a plasma including ions using the combined sequence and processing the substrate by transmitting the ions to a major surface of the substrate.

[0007] According to another embodiment of the present invention, a plasma processing method includes providing a source power to a plasma processing chamber to generate plasma. The source power includes a plurality of source power pulses. The method further includes providing a bias power including a plurality of bias power pulses to the plasma processing chamber. The plurality of source power pulses and the plurality of bias power pulses are combined to form a pulse train. Each pulse in the pulse train includes a source power pulse in the plurality of source power pulses, a bias power pulse in the plurality of bias power pulses, and a time interval in which a portion of the SP pulse or a portion of the BP pulse is in a high amplitude state.

[0008] According to yet another embodiment of the present invention, a plasma processing system includes a controller configured to generate a first sequence of source power pulses and a second sequence of bias power pulses. The controller is further configured to combine the bias power pulses in the second sequence with the source power pulses in the first sequence to form a combined sequence of alternating source power pulses and bias power pulses. The plasma processing system further includes a plasma processing chamber coupled to the controller and configured to generate a plasma including ions generated using the combined sequence. The plasma processing chamber is configured to support a substrate for receiving the generated ions. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A schematic timing diagram and corresponding qualitative graph illustrating a pulse sequence of an exemplary method of controlling plasma processing including source power pulses and bias power pulses according to an embodiment of the present invention;

[0011] Figure 2 A block diagram of an example plasma processing system including a source pulse modulation circuit and a pulse modulation timing circuit according to an embodiment of the present invention is shown;

[0012] Figure 3 A schematic timing diagram illustrating an example method of controlling plasma processing including anti-synchronous bias power pulses according to an embodiment of the present invention is shown;

[0013] Figure 4 A schematic timing diagram illustrating an example method of controlling plasma processing including high frequency radio frequency (RF) source power pulses and low frequency RF bias power pulses according to an embodiment of the present invention is shown;

[0014] Figure 5A schematic timing diagram illustrating an example method of controlling plasma processing including high frequency RF source power pulses and low frequency square wave bias power pulses according to an embodiment of the present invention is shown;

[0015] Figure 6 A schematic timing diagram illustrating an example method of controlling plasma processing including high frequency RF source power pulses and pulsed DC bias power pulses according to an embodiment of the present invention;

[0016] Figure 7 A schematic timing diagram illustrating an exemplary method of controlling plasma processing including high frequency RF source power pulses and alternating polarity pulsed DC bias power pulses according to an embodiment of the present invention;

[0017] Figure 8 A block diagram illustrating an example plasma processing system including a plasma potential coupling element in addition to a source pulse modulation circuit and a pulse modulation timing circuit in accordance with an embodiment of the present invention;

[0018] Fig. 9 A schematic timing diagram illustrating an example method of controlling plasma processing including potential control power pulses in addition to source power pulses and bias power pulses according to an embodiment of the present invention;

[0019] Fig.10 A block diagram illustrating an example plasma processing system including an electron beam source in addition to a source pulse modulation circuit and a pulse modulation timing circuit in accordance with an embodiment of the present invention is shown;

[0020] Fig.11 A schematic timing diagram illustrating an example method of controlling a plasma process including electron beam power pulses in addition to source power pulses and bias power pulses in accordance with an embodiment of the present invention;

[0021] Fig.12 A block diagram illustrating an example plasma processing system including a conductive grid in addition to a source pulse modulation circuit and a pulse modulation timing circuit in accordance with an embodiment of the present invention is shown;

[0022] Fig.13 A schematic timing diagram illustrating an example method of controlling plasma processing including grid control pulses in addition to source power pulses and bias power pulses according to an embodiment of the present invention;

[0023] Fig.14 A flow chart showing an example method of generating a control law that can be used to actively control an ion angular distribution function during plasma processing according to an embodiment of the present invention;

[0024] Fig.15 A flow chart showing an example method of feed-forward controlling a plasma process according to an embodiment of the present invention;

[0025] Fig.16 An example method of controlling during plasma processing according to an embodiment of the present invention is presented;

[0026] Fig.17 An example plasma processing method according to an embodiment of the present invention is presented; and

[0027] Fig.18 Several general timing diagrams including source power and bias power are shown.

[0028] Unless otherwise indicated, corresponding numerals and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate the relevant aspects of the embodiments, and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the range of the features. DETAILED DESCRIPTION

[0029] The making and use of various embodiments are discussed in detail below. However, it should be understood that the various embodiments described herein can be applied to a wide variety of specific situations. The specific embodiments discussed are merely illustrations of specific ways to make and use the various embodiments and should not be interpreted in a limited scope.

[0030] Ion energy and ion angle may affect the quality, uniformity, selectivity and predictability of various plasma processes. For example, in order to achieve anisotropic etching of high aspect ratio features, it may be desirable to generate a completely unidirectional vertical ion beam. In addition, it may also be desirable to be able to use an ion distribution with a manipulated angle to adjust, correct and control these directional ions. This ion distribution with a manipulated angle can be used, for example, to form contacts, fins, gate lines, other front-end or back-end processing and general patterning steps and other processes.

[0031] However, it is widely accepted that there is no active control mechanism in the art to control the angle of ions incident on topographical features of microelectronic devices during plasma processing. It may be beneficial to deliver ions to the substrate surface in an absolutely vertical or substantially vertical manner. Additionally, it may also be beneficial to control the angle of the ion beam delivered to the structure while accounting for and / or correcting for scattering on the sidewalls of the patterned structure. For example, such control of the ion distribution angle may be useful for high aspect ratio contact (HARC) type etching and patterning applications and other etching / deposition processes.

[0032] As described herein, embodiments of controlling ion angular distribution for plasma processing of a microelectronic workpiece (or substrate) are provided. The disclosed embodiments control the application of alternating current (AC) power and / or the application of pulsed direct current (DC) power to a microelectronic workpiece (e.g., a semiconductor wafer) during plasma processing. Through these techniques, the disclosed embodiments can provide various advantages (including controlling the angular distribution of ions delivered to the microelectronic workpiece). In view of the following description, additional embodiments and advantages may also be apparent to those skilled in the art.

[0033] In various embodiments, a method for processing a microelectronic workpiece includes providing source power to a plasma processing chamber to generate plasma. The plasma can be used, for example, for plasma processes such as etching, deposition, cleaning, ashing, etc. The source power provided to the plasma processing chamber is pulsed. Specifically, pulsing the power to the plasma processing chamber may include alternating the power between an on state and an off state, thereby forming a series of pulses that are different in time. The method further includes providing bias power to the plasma processing chamber. The bias power can accelerate charged particles in the generated plasma toward a microelectronic workpiece placed in the plasma processing chamber. The bias power provided to the plasma processing chamber is also pulsed. However, the source power pulses and the bias power pulses do not overlap at least partially in time.

[0034] Various embodiments described herein provide systems and methods for controlling ion angular distribution and ion energy for delivering ions to a surface for plasma processing, such as in reactive ion etching or plasma deposition. These control techniques for ion angular distribution can also contribute to atomic level etching (ALE) and atomic level deposition (ALD) as well as spatial ALE / ALD and / or other processes. Various embodiments as described herein provide for the application of inverted, anti-synchronous and / or out-of-phase source power and bias power pulses. In addition, these techniques can be further enhanced by incorporating one or more additional mechanisms for controlling the plasma potential. These additional mechanisms can also be pulsed in a delayed manner from the source plasma or at the same time as the source plasma. Embodiments as described herein can be used to modulate and control, for example, ion temperature (T i ), electron temperature (T e ), electron density (n e ), sheath voltage drop (V s ) and other plasma characteristics.

[0035] The embodiments provided below describe various systems and methods for operating a plasma processing system, and in particular, methods for controlling plasma processing including source power pulses and bias power pulses. The following description describes the embodiments. Figure 1Example schematic timing diagrams and qualitative graphs of example methods of controlling plasma processing including source power pulses and bias power pulses are described. Figure 2 Embodiment plasma processing systems including source pulse modulation circuits and pulse modulation timing circuits are described. Figure 3 Two example schematic timing diagrams of an embodiment method of controlling plasma processing including anti-synchronous bias power pulses are described. Figures 4 to 7 Several example schematic timing diagrams illustrating an embodiment method of controlling a plasma process including a single cycle of a source power pulse and a bias power pulse are described. Figure 8 and Fig. 9 An embodiment plasma processing system including a plasma potential coupling element and corresponding schematic timing diagrams of an embodiment method are described. Fig.10 and Fig.11 An embodiment plasma processing system including an electron beam source and corresponding schematic timing diagrams of an embodiment method are described. Fig.12 and Fig.13 An embodiment plasma processing system including a conductive grid and corresponding schematic timing diagrams of an embodiment method are described. Fig.14 An example flow chart of an embodiment method for generating a control law that can be used to actively control the ion angular distribution function (IADF) during plasma processing is described. Fig.15 An example flow chart of an embodiment method of feedforward controlling a plasma process is described. Fig.16 and Fig.17 Two example methods are described.

[0036] Figure 1 A schematic timing diagram and corresponding qualitative graphs of pulse sequences of an exemplary method of controlling plasma processing including source power pulses and bias power pulses according to an embodiment of the present invention are presented. The source power is coupled to a plasma processing chamber of a plasma processing system and is used to generate plasma for processing a microelectronic workpiece. The bias power is also coupled to the plasma processing chamber and can be used, among other functions, to accelerate ions toward a surface of a microelectronic workpiece.

[0037] refer to Figure 1, a timing diagram 100 includes a source power 1 and a bias power 2 that are pulsed to generate ions and transmit these ions to a microelectronic workpiece (e.g., a semiconductor wafer). Specifically, the timing diagram 100 includes a pulse sequence having one or more source power (SP) pulses 11 and bias power (BP) pulses 12 that are at least partially non-overlapping in time. For example, the source power 1 can be an AC power that switches between an on state and an off state to generate the SP pulses 11 (the frequency of the AC power is higher than the frequency of the SP pulses 11). Similarly, the bias power 2 can also be an AC power. For example, the bias power 2 can be implemented as an RF power and can have a DC self-bias. Alternatively, one or both of the source power 1 and the bias power 2 can be DC power.

[0038] In various embodiments, the pulse sequence is periodic (having a pulse modulation period 5) and includes a plurality of SP pulses 11 and BP pulses 12. However, in some cases, the pulse sequence may refer to a single SP pulse and a single BP pulse. Further, although periodicity may be beneficial, there is no strict requirement that the pulse sequence is periodic or that the SP pulses have the same period as the BP pulses.

[0039] As shown in the graph 102, the temperature curve 31 and the density curve 32 of the generated plasma change according to the applied source power 1 of the timing diagram 100. The SP pulse 11 generates a plasma whose electron density n is, for example, e , electron temperature T e and ion temperature T i The initial application of the SP pulse 11 may produce a plasma temperature (e.g., T e and T i ) peak 21, which relaxes to a pseudo-equilibrium state 23 for the remainder of the SP pulse. After the SP pulse ends, the plasma enters an afterglow phase during which the ions and electrons can cool down, resulting in T e , T i The electrons and ions diffuse to the wall through bipolar diffusion, resulting in n e In various embodiments, during the afterglow phase, a BP pulse is applied to accelerate ions toward the surface of the microelectronic workpiece.

[0040] As shown in graph 102, in the afterglow phase, T e and T i Can be compared to n e decreases more rapidly. Since the electron density n eDepending on the available ions, applying a BP pulse during the afterglow phase may be particularly effective in order to accelerate low temperature ions toward the surface of the microelectronic workpiece. During the afterglow phase, the plasma current may also be reduced. When bias power is applied (e.g., using a BP pulse), this current drop may allow the plasma sheath V in the afterglow phase to be reduced. DC (RF DC self-bias voltage) large voltage difference V p The increased voltage difference V p and the time average DC voltage drop V DC Together with lower ion temperature this can improve the directionality of the ion flux.

[0041] Thus, the SP pulses and the BP pulses are at least partially non-overlapping in time. In various embodiments, as illustrated by timing diagram 100, the SP pulses and the BP pulses are completely out of phase. In other embodiments, the SP pulses and the BP pulses may partially overlap. Thus, embodiments of the method include both a non-zero time interval for applying source power 1 without bias power 2 and a non-zero time interval for applying bias power 2 without source power 1.

[0042] In some cases, it can be considered advantageous to deliver substantially vertical ions to the processed surface. The average deviation of the angle of incidence of the ions at the surface can be referred to as the angular spread. The angular spread may be caused by the scattering of the ions in the plasma sheath and the random thermal motion of the ions in the plasma before they are accelerated toward the surface through the plasma sheath. The narrowing of the angular spread can be achieved by the directivity obtained from the electric field present in the plasma sheath, while the random thermal motion can cause the angular spread to widen. One method of generating an electric field in the plasma sheath can be to apply a bias power. In general, the angular spread <θ> of a given ion angular distribution can be described by the following proportional equation:

[0043]

[0044] From equation (1), we can see that as the ion temperature T i As the bias voltage V increases, the angular spread <θ> increases, thereby generating fewer vertical ions. Similarly, according to equation (1), as the bias voltage V DC As T increases, the angular spread <θ> decreases, resulting in more vertical ions. i It may be advantageous to apply a bias power 2 to the plasma processing chamber at a relatively low level to increase the verticality of the ions at the workpiece surface. It should be noted that in Equation 1, the ion temperature T i Usually expressed in electron volts (eV), the bias voltage V DC Expressed in volts (V), this conveniently allows the charge of the ion (+1) to be omitted from the denominator of equation (1).

[0045] Still refer to Figure 1 , the pulse sequence of the timing diagram 100 can be defined by pulse modulation process parameters. The pulse modulation process parameters may include SP pulse width 3 and SP pulse amplitude 4 corresponding to the source power 1 sequence and leading edge bias offset 6, BP pulse width 7, BP pulse amplitude 8, and trailing edge bias offset 9 corresponding to the bias power 2 sequence. Specifically, each SP pulse 11 includes SP pulse width 3 and SP pulse amplitude 4, and each BP pulse 12 includes BP pulse width 7 and BP pulse amplitude 8. It should be mentioned that, unless otherwise specified, the amplitude as used herein refers to the average peak-to-peak amplitude of a given pulse.

[0046] like Figure 1 As shown, the SP pulse 11 and the BP pulse 12 may not overlap at all in time. In this particular case, the SP pulse width 3 is the time interval during which the source power 1 is applied as the SP pulse without the bias power 2, and the BP pulse width 7 is the time interval during which the bias power 2 is applied as the BP pulse without the source power 1. In embodiments where the SP pulse 11 and the BP pulse 12 partially do not overlap, the non-overlapping time interval may include portions of the SP pulse width 3 and / or the BP pulse width 7.

[0047] For both the SP pulse 11 and the BP pulse 12, a specific pulse width can be implemented by selecting the duty cycle (%) of a given pulse modulation period 5. For example, if the pulse modulation period is set to 150 μs, a source power duty cycle (%) of 56% and a bias power duty cycle (%) of 28% will produce an 84 μs SP pulse width and a 42 μs BP pulse width. In one embodiment, the source power 1 and the bias power 2 have the same pulse modulation period. Alternatively, the source power 1 and the bias power 2 can be operated with separate pulse modulation periods.

[0048] The off time of the SP pulse 11 can be advantageously used to control the flux of ions and / or other free radicals to the surface of the microelectronic workpiece. For example, the inventors have found that when the SP off time (6 / 7 / 9) is set to less than L 2 / sD, a constant radical flux can be maintained, where L is a critical dimension of the plasma processing chamber, D is the diffusion coefficient of the species to maintain a constant flux, and s is the sticking coefficient of the species. For example, L can be the distance between the location where the ions / radicals are generated and the nearest wall. In one embodiment, L is the distance between the source region (i.e., the location where the ions / radicals appear) and the SP coupling element. In various embodiments, adjustments to the SP off time can increase or decrease the flux of ions and / or other radicals to the workpiece surface.

[0049] like Figure 1As shown, the delay between the SP pulse 11 and the BP pulse 12 can be referred to as the leading edge bias offset 6. The leading edge bias offset 6 can be implemented as a percentage of the pulse modulation period 5. For example, the leading edge bias offset can vary between -10% and +10% of the pulse modulation period 5. Alternatively, the leading edge bias offset 6 can be set to a specific time value. For example, continuing the above case where the source power 1 and the bias power 2 have the same pulse modulation period set to 150μs, a leading edge bias offset of 10% will result in a 15μs delay between the trailing edge of the SP pulse and the BP pulse. In the aforementioned example, the leading edge bias offset 6 is set to positive. However, the leading edge bias offset 6 can also be zero or negative.

[0050] Similarly, the delay between the BP pulse 12 and the SP pulse 11 can be referred to as the trailing edge bias offset 9 and can be implemented by a combination of the SP pulse width 3, the leading edge bias offset 6, and the BP pulse width 7. Continuing with the above example, a source power duty cycle (%) of 56%, a leading edge bias offset of 10%, and a bias power duty cycle (%) of 28% account for 94% of the entire pulse modulation period. Therefore, in this particular example, there is a delay between the trailing edge of the BP pulse and the leading edge of the SP pulse that is equal to 6% of the pulse modulation period. Since the pulse modulation period is 150 μs, this delay as the trailing edge bias offset 9 is equal to 9 μs. Similar to the leading edge bias offset 6, the trailing edge bias offset 9 does not need to be positive and can also be zero or negative.

[0051] The pulse amplitudes may be defined by corresponding high and low amplitude states. For example, the high and low amplitudes may be voltage levels. Specifically, each of the SP pulses 11 may oscillate between an SP low amplitude state 13 and an SP high amplitude state 14, and each of the BP pulses 12 may oscillate between a BP low amplitude state 17 and a BP high amplitude state 18. A positive DC bias or a negative DC bias may be applied to one or both of the source power 1 or the bias power 2 so that the corresponding high and low amplitudes reach a desired level.

[0052] It should be mentioned that both the temperature curve 31 and the density curve 32 are qualitative in nature. Therefore, although both the temperature curve and the density curve can indicate the relationship between the pulse sequence and the pulse sequence, the temperature curve 31 and the density curve 32 are qualitative in nature. e , T i and n e The temperature curve and the density curve are not intended to be drawn to a specific scale or to be quantitatively accurate. In addition, simplifications may be made for the sake of clarity. For example, the electron temperature T e and ion temperature T i has been shown as a single curve in graph 102 because the shape of the curves is similar, even though T e T in cold plasmai At least an order of magnitude larger.

[0053] Figure 2 A block diagram of an example plasma processing system including a source pulse modulation circuit and a pulse modulation timing circuit according to an embodiment of the present invention is presented. Figure 2 The plasma processing system can be used, for example, to perform any of the embodiment methods described herein, such as Figure 1 method.

[0054] refer to Figure 2 , the plasma processing system 200 includes an SP coupling element 15 coupled to a plasma processing chamber 210. The SP coupling element may allow source power to be applied to the plasma processing chamber 210, resulting in the generation of a plasma 60. In various embodiments, the SP coupling element 15 is a conductive coil positioned around the plasma processing chamber 210 and in one embodiment is a quarter-wave helical resonator. In another embodiment, the SP coupling element 15 is a half-wave helical resonator, which may be implemented as a planar helical coil positioned above the plasma processing chamber 210. Alternatively, other SP coupling elements such as antennas, plate electrodes, or waveguides may be employed, as examples.

[0055] The plasma processing system 200 further includes a BP coupling element 19 coupled to the plasma processing chamber 205. The BP coupling element 19 can enable the application of bias power to the microelectronic workpiece being processed. In various embodiments, the BP coupling element 19 is a substrate holder and in one embodiment is an electrostatic chuck.

[0056] The source power may be coupled to the plasma processing chamber 210 using an SP control path 201 including an SP pulse modulation circuit 51. The SP pulse modulation circuit 51 may modulate the source signal between the SP high amplitude state 14 and the SP low amplitude state 13. For example, as described with respect to Figure 1 As described, the modulated source signal may correspond to the SP pulse 11. The modulated source signal may be received by the SP function generator 20, which may superimpose a waveform onto the modulated source signal. The SP function generator 20 may also optionally include an amplification circuit configured to increase the amplitude of the modulated source signal.

[0057] The frequency of the superimposed waveform may be higher than the pulse modulation frequency. In various embodiments, the frequency of the superimposed waveform may be an RF frequency and in one embodiment is about 13.56 MHz. Thus, each of the resulting SP pulses may include several cycles of the superimposed waveform. The waveform shape may include periodic waveforms such as sine waves, square waves, sawtooth waves, etc. Alternatively, the waveform shape may include a non-periodic wave, such as a superposition of multiple sine waves of various frequencies to generate an arbitrary waveform shape.

[0058] The SP control path 201 may include an optional SP impedance matching network 25. The SP pulses generated by the SP function generator 20 may pass through the optional SP impedance matching network 25 before being coupled to the plasma processing chamber 210 through the SP coupling element 15. In certain plasma processing systems, such as when the SP coupling element 15 is a resonant structure that is inductively coupled to the plasma 60, the optional SP impedance matching network 25 may be omitted. Conversely, when the SP coupling element 15 is non-resonant, the optional SP impedance matching network 25 may be included. The optional SP impedance matching network 25 may be used to ensure that the source power is efficiently coupled to the plasma 60 by matching the impedance of the load to the impedance of the power source.

[0059] Still refer to Figure 2 , the bias power can be coupled to the plasma processing chamber 210 using the BP control path 202. The BP control path 202 can be coupled to the SP control path 201 through the pulse modulation timing circuit 252. The pulse modulation timing circuit 252 can determine the timing of the BP pulse relative to the timing of the SP pulse generated by the SP control path 201. The pulse modulation timing circuit 252 can receive a signal from the SP pulse modulation circuit 51 and introduce a delay triggered by the leading edge or trailing edge of the SP pulse. For example, if the leading edge bias offset parameter is set to 8% of the pulse modulation period, the pulse modulation timing circuit 252 can introduce a delay equal to 8% of the pulse modulation period after being triggered by the trailing edge of the SP pulse. Alternatively, if the pulse modulation timing circuit 252 is configured to be triggered by the leading edge of the SP pulse, a delay of 8% of the pulse modulation period plus the source power duty cycle (%) can be introduced by the pulse modulation timing circuit 252. Alternatively, the pulse modulation timing circuit 252 can determine the timing of the SP pulse relative to the timing of the BP pulse generated by the BP control path 202.

[0060] Similar to the SP control path 201, the BP control path 202 may include an optional BP pulse modulation circuit 53 triggered by the pulse modulation timing circuit 252. The optional BP pulse modulation circuit 53 may modulate the bias signal between a BP high amplitude state and a BP low amplitude state. Figure 1As described, the modulated bias signal may correspond to the BP pulse 12. Alternatively, the optional BP pulse modulation circuit 53 may be omitted and the delayed modulated source signal may correspond to the BP pulse.

[0061] The modulated bias signal can be received by an optional BP function generator 30. The optional BP function generator 30 can superimpose a waveform onto the modulated bias signal. The waveform can be similar or different to the waveform superimposed on the modulated source signal and can have any desired waveform shape as previously described. The optional BP function generator 30 can also optionally include an amplifier circuit for increasing the amplitude of the modulated bias signal. In one embodiment, the bias power transmitted to the plasma processing chamber 210 is DC power. In this case, the optional BP function generator 30 can be omitted. In some cases where amplification is required but function generation is not required, an amplifier circuit can be included instead of the optional BP function generator 30.

[0062] Also included in the BP control path 202 between the optional BP function generator 30 and the BP coupling element 19 is a BP impedance matching network 35. The BP impedance matching network can be used to ensure that the bias power is efficiently coupled to the plasma processing chamber 210 by matching the impedance of the load to the impedance of the power source.

[0063] One or more of the elements described above may be included in the controller. Figure 2 As shown, the SP pulse modulation circuit 51, the pulse modulation timing circuit 252, and the optional BP pulse modulation circuit 53 may be included in the controller 250. The controller 250 may be located locally relative to the plasma processing chamber 210. Alternatively, the controller 250 may be located remotely relative to the plasma processing chamber 210. The controller 250 may be capable of exchanging data with one or more of the elements included in the SP control path 201 and the BP control path 202. Each of the impedance matching networks may be controlled by the controller 250 or may include a separate controller.

[0064] The controller 250 can be configured to set, monitor and / or control various control parameters associated with generating the plasma and delivering ions to the surface of the microelectronic workpiece. The control parameters can include, but are not limited to, power levels, frequencies, and duty cycles (%) of both source power and bias power, and bias offset percentages. Other sets of control parameters can also be used. For example, the pulse widths of the SP and BP pulses and the bias offset can be directly input rather than being defined as the duty cycle (%) of the pulse modulation period.

[0065] Figure 3A schematic timing diagram of an example method of controlling plasma processing including anti-synchronous bias power pulses according to an embodiment of the present invention is shown. For example, Figure 3 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 100). Like labeled elements may be as previously described.

[0066] refer to Figure 3 , the timing diagram 300 includes a source power 1 and a bias power 2 that are pulsed to generate ions and deliver the ions to a microelectronic workpiece. Specifically, the timing diagram 300 includes a periodic pulse sequence having a shared pulse modulation period 305 of a series of 50% SP pulses 311 and 50% BP pulses 312. Both the 50% SP pulses 311 and the 50% BP pulses 312 are pulsed within half of the shared pulse modulation period 305, which corresponds to a 100% duty cycle (%). That is, the 50% SP pulse 311 has a 50% SP pulse width 303 with a 50% duty cycle (%), and the 50% BP pulse 312 has a 50% BP pulse width 307 with a 50% duty cycle (%).

[0067] In one embodiment, the shared pulse modulation period 305 is about 200 μs. Thus, in this embodiment, the 50% SP pulse width 303 is about 100 μs, and the 50% BP pulse width 307 is about 100 μs. In other embodiments, the shared pulse modulation period 305 can be any desired length. For example, the shared pulse modulation period 305 can be less than or greater than 200 μs. In various embodiments, the shared pulse modulation period 305 is about a few microseconds (μs). In other embodiments, the shared pulse modulation period 305 can be about a few milliseconds (ms) or seconds (s). In one embodiment, the shared pulse modulation period 305 is about 1 s.

[0068] Still refer to Figure 3 , the timing diagram 320 is similar to the timing diagram 300 including the source power 1 and the bias power 2 pulsed with the shared pulse modulation period 305. However, in the timing diagram 320, a non-zero leading edge bias offset 326 is included between the 50% SP pulse 311 and the <50% BP pulse 322. Since the off time of the 50% SP pulse 311 is equal to the 50% duty cycle (%), the <50% BP pulse width 327 of the <50% BP pulse 322 is equal to the duty cycle (%) less than 50%. Specifically, the <50% BP pulse width 327 is equal to the 50% duty cycle (%) minus the non-zero leading edge bias offset 326.

[0069] In one embodiment, the shared pulse modulation period 305 is about 200 μs, the non-zero leading edge bias offset 326 is about 20 μs and the <50% BP pulse width 327 is about 80 μs. Therefore, in this embodiment, the 50% SP pulse width 303 is about 100 μs. This corresponds to a non-zero leading edge bias offset 326 of about 10% duty cycle (%) and a <50% BP pulse width 327 of about 40% duty cycle (%). In other embodiments, the non-zero leading edge bias offset 326 can be any desired length less than the shared pulse modulation period 305. For example, the non-zero leading edge bias offset 326 can be less than or greater than 20 μs.

[0070] Since the 50% SP pulse 311 and the 50% BP pulse 312 do not overlap at all in time and share the shared pulse modulation period 305, the 50% SP pulse 311 and the 50% BP pulse 312 are anti-synchronous. That is, the 50% SP pulse 311 is out of phase with the 50% BP pulse 312 because the 50% SP pulse 311 is only in a high amplitude state when the 50% BP pulse 312 is in a low amplitude state. In addition, in the sense that the 50% SP pulse 311 and the 50% BP pulse 312 share the same modulation period, these 50% SP pulses and these 50% BP pulses are synchronized. This out-of-phase synchronization relationship can be referred to as an anti-synchronous relationship. Similarly, the 50% SP pulse 311 and the <50% BP pulse 322 are also anti-synchronous with each other.

[0071] Delivering anti-synchronous BP pulses to the plasma processing chamber can beneficially increase the effectiveness of the BP pulses. For example, during the high amplitude state of the SP pulse, energy is coupled to the plasma to generate ions. The thermal energy of the ions is increased, which can increase thermal motion. The random thermal motion of the ions can generally introduce a horizontal velocity component into the vertical velocity imparted by the bias power. In addition, during the high amplitude state of the SP pulse, the current to the substrate being processed can be larger, which can reduce the voltage to the substrate when the power is fixed. Therefore, applying the bias power during the high amplitude state of the SP pulse may be less effective in generating vertical or near-vertical ions than applying the BP pulse during the low amplitude state of the SP pulse.

[0072] The non-zero leading edge bias offset 326 may be determined based on, among other factors, the cooling rate of the plasma. For example, since the source power 1 is turned off during the delay between the SP pulse and the BP pulse, the generated plasma may lose power and the temperature and density of the charged particles may decrease. Thus, the sheath voltage V induced by the next BP pulse may be reduced. S In contrast, a non-zero leading edge bias offset 326 may advantageously allow the ion temperature T i Lower.

[0073] Timing diagrams 300 and 320 are specific cases of timing diagram 100 as previously described. For example, timing diagram 300 corresponds to a scenario where SP pulse width 3 is equal to 50% duty cycle (%) and both leading edge bias offset 6 and trailing edge bias offset 9 are equal to zero. Similarly, timing diagram 320 corresponds to a scenario where SP pulse width 3 is equal to 50% duty cycle (%), leading edge bias offset 6 is non-zero and positive, and trailing edge bias offset 9 is equal to zero. In view of the embodiments described herein, many other timing diagrams will be apparent to those skilled in the art by varying the pulse modulation process parameters. That is, different offsets, pulse widths, and pulse modulation periods may also be used while still utilizing the techniques described herein.

[0074] Figure 4 A schematic timing diagram of an example method of controlling plasma processing including high frequency RF source power pulses and low frequency RF bias power pulses according to an embodiment of the present invention is shown. As an example, Figure 4 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 The timing diagram of 100 or Figure 3 320). Like labeled elements may be as previously described.

[0075] refer to Figure 4 , the timing diagram 400 includes a source power 1 and a bias power 2 that are pulsed to generate ions and deliver the ions to a microelectronic workpiece. Specifically, the timing diagram 400 includes a pulse modulation period 5 having one or more SP pulses 11 and one or more BP pulses 12, the one or more SP pulses and the one or more BP pulses having an SP pulse width 3, a leading edge bias offset 6, and a BP pulse width 7. Each of the SP pulses 11 includes a SP frequency f SP The periodic waveform may be superimposed on the SP pulse 11 by a function generator. In one embodiment, the periodic waveform may be a sine wave and the source power may be AC ​​power. However, as previously described, other waveforms are also possible. Each of the BP pulses 12 may also include a BP frequency f BP The periodic waveform of the SP pulse 11 may be similar to or different from the periodic waveform of the SP pulse 11.

[0076] The inventors have discovered that, in some instances, applying high frequency pulses in the afterglow phase may result in undesirable electron heating and plasma generation (e.g., in a halogen plasma), which potentially may reduce and / or eliminate the effectiveness of the pulse sequence as described herein. This potential problem may be mitigated by applying low frequency AC power, DC power, or alternating polarity DC voltage during the afterglow phase. As previously described, the afterglow interval may begin when the source power is in a low amplitude state. Therefore, a BP pulse comprising low frequency AC power, DC power, or alternating polarity DC voltage may advantageously reduce or eliminate undesirable electron heating and plasma generation in the afterglow phase.

[0077] Therefore, in various embodiments, f BP Less than f SP In one embodiment, f BP In another embodiment, f BP Less than 400kHz. In one embodiment, f SP is about 13.56MHz and f BP Less than 400kHz. SP frequency f SP is any frequency such as RF, very high frequency (VHF), microwave (MW), etc. In one embodiment, f SP Greater than 10MHz and f BP In another embodiment, f SP Greater than 50MHz and f BP In yet another embodiment, f SP is between about 50 MHz and about 150 MHz, and f BP Between about 1 MHz and about 5 MHz.

[0078] Figure 5 A schematic timing diagram of an example method of controlling plasma processing including high frequency RF source power pulses and low frequency square wave bias power pulses according to an embodiment of the present invention is shown. As an example, Figure 5 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 The timing diagram of 100 or Figure 3 320). Like labeled elements may be as previously described.

[0079] refer to Figure 5, timing diagram 500 includes source power 1 and bias power 2 that are pulsed to generate ions and deliver the ions to a microelectronic workpiece. Specifically, timing diagram 400 includes a pulse modulation period 5 having one or more SP pulses 11 and one or more BP pulses 12, the one or more SP pulses and the one or more BP pulses having an SP pulse width 3, a leading edge bias offset 6, and a BP pulse width 7. In addition to each of the BP pulses 12 having a square wave frequency f SW and a periodic square wave with a square wave pulse width 517, the timing diagram 500 is similar to Figure 4 The timing diagram 400. The square wave frequency f SW Can be less than f SP and may be comparable in magnitude to the BP frequency f of the timing diagram 400 as previously described. BP In various embodiments, the periodic square wave may be generated by a function generator based on the superposition of harmonic sinusoidal waveforms.

[0080] Figure 6 A schematic timing diagram of an example method of controlling plasma processing including high frequency RF source power pulses and pulsed DC bias power pulses according to an embodiment of the present invention is shown. As an example, Figure 6 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 The timing diagram of 100 or Figure 3 320). Like labeled elements may be as previously described.

[0081] refer to Figure 6 , timing diagram 600 includes source power 1 and bias power 2 that are pulsed to generate ions and deliver the ions to a microelectronic workpiece. Specifically, timing diagram 400 includes a pulse modulation period 5 having one or more SP pulses 11 and one or more BP pulses 12, the one or more SP pulses and the one or more BP pulses having an SP pulse width 3, a leading edge bias offset 6, and a BP pulse width 7. In addition to each of the BP pulses 12 having a DC frequency f DC and one or more DC pulses 612 having a DC pulse width 617, the timing diagram 600 is similar to Figure 4 In addition to each of the DC pulses 612 being generated by switching the DC voltage off and on, the DC frequency f DC Similar to the square wave frequency f SW . DC frequency f DC Can be less than f SP and may be comparable in magnitude to the BP frequency f of the timing diagram 400 as previously described. BP similar.

[0082] SP pulses 11 may include AC power for plasma generation, while the microelectronic workpiece (e.g., wafer) being processed may be pulsed with BP pulses 12 including a DC voltage. The number of DC pulses 612 included in each of the BP pulses 12 may be relatively small. Thus, in various embodiments, the DC frequency f DC Much smaller than the SP frequency f SP For example, in one embodiment, each of the BP pulses 12 may include only one continuous DC pulse 612. Alternatively, each of the BP pulses 12 may include less than five DC pulses 612. However, any suitable number of DC pulses 612 may be included in each of the BP pulses 12.

[0083] Figure 7 A schematic timing diagram of an example method of controlling plasma processing including high frequency RF source power pulses and alternating polarity pulsed DC bias power pulses according to an embodiment of the present invention is shown. As an example, Figure 7 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 The timing diagram of 100 or Figure 3 320). Like labeled elements may be as previously described.

[0084] refer to Figure 7 , timing diagram 700 includes source power 1 and bias power 2 that are pulsed to generate ions and deliver the ions to a microelectronic workpiece. Specifically, timing diagram 400 includes a pulse modulation period 5 having one or more SP pulses 11 and one or more BP pulses 12, the one or more SP pulses and the one or more BP pulses having an SP pulse width 3, a leading edge bias offset 6, and a BP pulse width 7. In addition, each of the BP pulses 12 includes an alternating polarity (AP) frequency f AP AP DC pulse 712, the timing diagram 700 is similar to Figure 6 The AP DC pulse 712 is similar to the AP DC pulse 712 except that the AP DC pulse 712 is configured to alternate between a positive voltage level and a negative voltage level relative to a reference potential. Figure 6 DC pulse 612.

[0085] For example, alternating polarity DC voltages are useful when the substrate being processed includes a dielectric layer that can be charged (which can cause undesirable arcing). In some embodiments, the width and height of the positive AP DC pulse 712 can be different from the width and height of the negative AP DC pulse 712. For example, a positive DC pulse can attract ions to the surface of the workpiece. However, a subsequent negative DC pulse can repel ions away from the surface. Therefore, it can be advantageous to implement longer positive DC pulses and larger negative DC pulses. In one embodiment, the width of the positive DC pulse is greater than the width of the negative DC pulse.

[0086] In one embodiment, the height of the positive DC pulse is less than the height of the negative DC pulse. In one embodiment, the width of the positive DC pulse is greater than the width of the negative DC pulse, and the height of the positive DC pulse is less than the height of the negative DC pulse. In other embodiments, the height and or width of the positive DC pulse and the negative DC pulse may be the same. In various embodiments, each of the BP pulses 12 includes a single positive AP DC pulse and a single negative AP DC pulse. In one embodiment, the single positive AP DC pulse occurs when the source power is off (i.e., a low amplitude state), and the single negative AP DC pulse occurs when the source power is on (i.e., overlapping in time with the high amplitude state of the following SP pulse).

[0087] Figure 8 A block diagram of an example plasma processing system including a plasma potential coupling element in addition to a source pulse modulation circuit and a pulse modulation timing circuit according to an embodiment of the present invention is shown. For example, Figure 8 The plasma processing system may be other embodiment plasma processing systems (such as Figure 2 A specific embodiment of a plasma processing system 200). Figure 8 The plasma processing system can be used, for example, to perform any of the embodiment methods described herein, such as Fig. 9 Like labeled elements may be as described previously.

[0088] refer to Figure 8 , the plasma processing system 800 includes a BP control path 802 coupled to the SP control path 801 using the BP timing circuit 52, which provides source power and bias power to the plasma processing chamber 810. The SP control path 801 and the BP control path 802 can be similar to Figure 2The plasma processing system 800 further includes a potential controlled power (PCP) control path 803. The PCP control path 803 couples power to the plasma 60 using a plasma potential coupling element 816. In one embodiment, the plasma potential coupling element 816 is a plate electrode. However, any of the coupling elements previously described may be used.

[0089] The PCP control path 803 can be coupled to the SP control path 801 through an optional PCP timing circuit 854. The optional PCP timing circuit 854 can be coupled to the SP pulse modulation circuit 51 and / or the BP timing circuit 52. Similar to the BP timing circuit 52, the optional PCP timing circuit 854 can control the timing of applying potential control power to the plasma processing chamber 810 relative to the SP pulses and / or BP pulses delivered by the SP control path 801 and the BP control path 802. The PCP control path 803 can provide PCP pulses to the plasma potential coupling element 816 through the optional PCP pulse modulation circuit 855.

[0090] In various embodiments, one or more of the SP pulse modulation circuit 51, the BP timing circuit 52, the optional BP pulse modulation circuit 53, the optional PCP timing circuit 854, and the optional PCP pulse modulation circuit 855 may be included in the controller 850. As with the previously described controllers, the controller 850 may be located locally or remotely relative to the plasma processing chamber 810.

[0091] The power coupled to the plasma using the plasma potential coupling element 816 can advantageously reduce the potential of the plasma during the high amplitude state of the SP pulse. In one embodiment, a negative DC (-V PCP ) pulse. In this case, -V PCP The pulse can reduce the bulk potential of the plasma 60. For example, a negative potential at the plasma potential coupling element 816 can repel electrons from the plasma sheath into the plasma bulk. This negative charge injection can reduce the bulk potential, which can then reduce the plasma temperature (e.g., T e and T i ). Thus, applying a negative DC potential to the plasma during the plasma generation interval may advantageously allow the plasma to be generated at a reduced plasma temperature gain when compared to generating the plasma using only applied source power.

[0092] Power coupled to the plasma using plasma potential coupling element 816 may provide the additional benefit of increasing the ion velocity to the surface of the microelectronic workpiece during the BP pulse. In one embodiment, a positive DC (+V PCP ) pulse. +V PCP The pulses can repel ions toward the workpiece, thereby increasing the vertical velocity of the ions relative to the workpiece surface. Therefore, applying a positive DC potential to the plasma during the high amplitude state of the BP pulse can advantageously increase the verticality of the ions and the ion energy to the workpiece surface. It should be noted that although -V can be utilized in the same pulse sequence PCP and +V PCP pulses, but one or both may be omitted in some embodiments.

[0093] Fig. 9 A schematic timing diagram of an example method of controlling plasma processing including potential control power pulses in addition to source power pulses and bias power pulses according to an embodiment of the present invention is shown. For example, Fig. 9 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 100). Like labeled elements may be as previously described.

[0094] refer to Fig. 9 , timing diagram 900 includes source power 1, bias power 2, and potential control power 903 that are pulsed to generate ions and deliver these ions to a microelectronic workpiece. Timing diagram 900 includes -V PCP Pulse 911 and +V PCP Another pulse sequence of pulses 912. As with BP pulse 12, various offset parameters are used to delay the SP pulse 11 by -V PCP Pulse 911 and +V PCP Pulse 912. For example, -V PCP Pulse 911 includes an allowable PCP The timing and duration of pulse 911 are controlled by the leading edge-PCP offset 916, -V PCP Pulse width 917 and trailing edge-PCP offset 918. Similarly, +V PCP Pulse 912 includes an enable pulse for +V PCP The timing and duration of pulse 912 are controlled by the leading edge +PCP offset 926, +V PCP Pulse width 927 and trailing edge +PCP offset 928.

[0095] As with the previously described pulses, -V PCP Pulse 911 and +V PCPPulse 912 may include any suitable pulse width and offset as necessary to provide desired control of the generated plasma during plasma processing of the workpiece surface. PCP Pulse 911 and +V PCP Pulses 912 must not overlap in time. -V PCP Pulse 911 and +V PCP The pulse height of both pulses 912 can also be controlled. In one embodiment, -V PCP Pulse 911 and +V PCP The pulse heights of pulses 912 are substantially equal in magnitude. However, in other embodiments, -V PCP Pulse 911 and +V PCP The amplitude of the pulse height of pulse 912 may vary.

[0096] Fig.10 A block diagram of an example plasma processing system including an electron beam source in addition to a source pulse modulation circuit and a pulse modulation timing circuit according to an embodiment of the present invention is shown. For example, Fig.10 The plasma processing system may be other embodiment plasma processing systems (such as Figure 2 A specific embodiment of a plasma processing system 200). Fig.10 The plasma processing system can be used, for example, to perform any of the embodiment methods described herein, such as Fig.11 Like labeled elements may be as described previously.

[0097] refer to Fig.10 , the plasma processing system 1000 includes a BP control path 1002 coupled to the SP control path 1001 using a BP timing circuit 52, which provides source power and bias power to the plasma processing chamber 1010. The SP control path 1001 and the BP control path 1002 can be similar to Figure 2 1000. The plasma processing system 1000 also includes an electron beam (e-beam) control power (eCP) control path 1004. The eCP control path 1004 generates electrons 1065 and introduces these electrons into the plasma processing chamber 1010 at or near the plasma 60 using an e-beam source 1017. In various embodiments, the e-beam source 1017 generates a directional electron stream. In one embodiment, the directional electron stream generated by the e-beam source 1017 is directed inward toward the plasma 60, for example, in a direction perpendicular to the ion flux direction.

[0098] The eCP control path 1004 can be coupled to the SP control path 1001 through an optional eCP timing circuit 1056. The optional eCP timing circuit 1056 can be coupled to the SP pulse modulation circuit 51 and / or the BP timing circuit 52. Similar to the BP timing circuit 52, the optional eCP timing circuit 1056 can control the timing e-beam control power relative to the SP pulses and / or BP pulses transmitted by the SP control path 1001 and the BP control path 1002. The eCP control path 1004 can use the signal received from the optional eCP timing circuit 1056 to alternate the e-beam source 1017 between the on state and the off state through the optional eCP pulse modulation circuit 1057.

[0099] In various embodiments, one or more of the SP pulse modulation circuit 51, the BP timing circuit 52, the optional BP pulse modulation circuit 53, the optional eCP timing circuit 1056, and the optional eCP pulse modulation circuit 1057 may be included in the controller 1050. As with the previously described controllers, the controller 1050 may be located locally or remotely relative to the plasma processing chamber 1010.

[0100] Similar to the above Figure 8 and Fig. 9 Described -V PCP Pulse 911, the negative charge injected into the plasma 60 by the electrons 1065 can advantageously reduce the bulk potential and temperature of the plasma 60. Since the electrons 1065 are provided directly to the plasma 60 in the plasma processing chamber 1010, the eCP control path 1004 can advantageously achieve enhanced control of T compared to other methods. e and T i The electrons 1065 may be provided during the SP pulse and / or the BP pulse. In one embodiment, the electrons 1065 are provided during the SP pulse. In various embodiments, the electrons 1065 may be provided between the SP pulse and the BP pulse. Alternatively, the electrons 1065 may be pulsed such that they overlap only a small region of the tail end of the SP pulse and do not overlap with the BP pulse.

[0101] Fig.11 A schematic timing diagram of an example method of controlling plasma processing including electron beam power pulses in addition to source power pulses and bias power pulses according to an embodiment of the present invention is shown. For example, Fig.11 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 100). Like labeled elements may be as previously described.

[0102] refer to Fig.11, timing diagram 1100 includes source power 1, bias power 2, and e-beam control power 1104 that are pulsed to generate ions and transmit these ions to the microelectronic workpiece. Timing diagram 1100 includes an additional pulse sequence including an eCP pulse 1111. As with the BP pulse 12, the eCP pulse 1111 is delayed relative to the SP pulse 11 using various offset parameters. For example, the eCP pulse 1111 includes a leading edge eCP offset 1116, an eCP pulse width 1117, and a trailing edge eCP offset 1118 that allow the timing and duration of the eCP pulse 1111 to be controlled. As with the previously described pulses, the eCP pulse 1111 can include any suitable pulse width and offset as necessary to provide desired control of the generated plasma during plasma processing of the workpiece surface. Although timing diagram 1100 shows a synchronous eCP pulse 1111, an anti-synchronous eCP pulse can also be applied instead of or in addition to the synchronous pulse.

[0103] Fig.12 A block diagram of an example plasma processing system including a conductive grid in addition to a source pulse modulation circuit and a pulse modulation timing circuit in accordance with an embodiment of the present invention is shown. For example, Fig.12 The plasma processing system may be other embodiment plasma processing systems (such as Figure 2 A specific embodiment of a plasma processing system 200). Fig.12 The plasma processing system can be used, for example, to perform any of the embodiment methods described herein, such as Fig.13 Like labeled elements may be as described previously.

[0104] refer to Fig.12 , the plasma processing system 1200 includes a BP control path 1202 coupled to the SP control path 1201 using a BP timing circuit 52, which provides source power and bias power to the plasma processing chamber 1210. The SP control path 1201 and the BP control path 1202 can be similar to Figure 2 The SP control path 201 and the BP control path 202 of the plasma processing system 1200 are shown in FIG. 12. In addition, the plasma processing system 1200 further includes a grid control power (GCP) control path 1205. The GCP control path 1205 provides power to the plasma 60 using a conductive grid 1218.

[0105] In one embodiment, the conductive grid 1218 is a network of conductive plates with a major dimension substantially perpendicular to the surface of the workpiece to be processed. In one embodiment, the conductive grid 1218 is configured to increase the verticality of ions delivered to the workpiece surface. In some embodiments, the conductive grid can be an orifice plate, a charged particle filter, or a conduit. In some embodiments, the conductive grid 1218 is configured to filter out charged particles of the remote plasma.

[0106] The GCP control path 1205 can be coupled to the SP control path 1201 through an optional GCP timing circuit 1258. The optional GCP timing circuit 1258 can be coupled to the SP pulse modulation circuit 51 and / or the BP timing circuit 52. Similar to the BP timing circuit 52, the optional GCP timing circuit 1258 can control the timing of applying grid control power to the plasma processing chamber 1210 relative to the SP pulses and / or BP pulses delivered by the SP control path 1201 and the BP control path 1202. The GCP control path 1205 can provide GCP pulses to the conductive grid 1218 through an optional GCP pulse modulation circuit 1259.

[0107] In various embodiments, one or more of the SP pulse modulation circuit 51, the BP timing circuit 52, the optional BP pulse modulation circuit 53, the optional GCP timing circuit 1258, and the optional GCP pulse modulation circuit 1259 may be included in the controller 1250. As with the previously described controllers, the controller 1250 may be located locally or remotely relative to the plasma processing chamber 1210.

[0108] Similar to the above Figure 8 and Fig. 9 Described -V PCP Pulse 911, approaching the negative potential of plasma 60 can advantageously reduce the bulk potential and temperature of plasma 60. Figure 8 In contrast to the plasma potential coupling element 816 of BP coupling element 19, the conductive grid 1218 can be positioned between the plasma 60 and the workpiece surface. Therefore, any potential applied to the conductive grid 1218 during the BP pulse can be kept small compared to the potential of the BP coupling element 19, so that the dominant force on the ions is toward the workpiece surface.

[0109] Fig.13 A schematic timing diagram of an example method of controlling plasma processing including grid control pulses in addition to source power pulses and bias power pulses according to an embodiment of the present invention is shown. For example, Fig.13 The timing diagram may be a timing diagram of other embodiments (such as Figure 1 100). Like labeled elements may be as previously described.

[0110] refer to Fig.13 , timing diagram 1300 includes source power 1, bias power 2, and grid control power 1305 that are pulsed to generate ions and deliver these ions to a microelectronic workpiece. Timing diagram 1300 includes an additional pulse sequence including an SP GCP pulse 1311 and a BP GCP pulse 1312. As with BP pulse 12, SP GCP pulse 1311 and BP GCP pulse 1312 are delayed relative to SP pulse 11 using various offset parameters. For example, SP GCP pulse 1311 includes a leading edge SP GCP offset 1316, a SP GCP pulse width 1317, and a trailing edge SP GCP offset 1318 that allow control of the timing and duration of SP GCP pulse 1311. Similarly, BP GCP pulse 1312 includes a leading edge BP GCP offset 1326, a BP GCP pulse width 1327, and a trailing edge BP GCP offset 1328 that allow control of the timing and duration of BP GCP pulse 1312.

[0111] The SP GCP pulse 1311 includes an SP GCP pulse amplitude 1304, and the BP GCP pulse 1312 includes a BP GCP pulse amplitude 1314. The SP GCP pulse amplitude 1304 and the BP GCP pulse amplitude 1314 can be positive or negative relative to a reference potential. In one embodiment, both the SP GCP pulse amplitude 1304 and the BP GCP pulse amplitude 1314 are negative. Alternatively, the SP GCP pulse amplitude 1304 is negative and the BP GCP pulse amplitude 1314 is positive.

[0112] It may be advantageous for the SP GCP pulse amplitude 1304 to be greater in magnitude than the BP GCP pulse amplitude 1314. For example, during an SP pulse, the SP GCP pulse may be used to reduce the bulk potential of the plasma. Thus, the SP GCP pulse amplitude 1304 may be made large enough to affect the bulk of the plasma. In contrast, during a BP pulse, the BP GCP pulse may be used to make small adjustments to the velocity of ions passing through the conductive mesh toward a vertical line relative to the workpiece surface. Thus, the BP GCP pulse amplitude 1314 may be made small enough to not reflect ions back toward the plasma. In one embodiment, the SP GCP pulse amplitude 1304 is greater in magnitude than the BP GCP pulse amplitude 1314, but opposite in sign.

[0113] As with the previously described pulses, the SP GCP pulse 1311 and the BP GCP pulse 1312 may include any suitable pulse width and offset as necessary to provide desired control of the generated plasma during plasma processing of a workpiece surface.

[0114] Fig.14 A flow chart showing an example method for generating a control law that can be used to actively control the ion angular distribution function during plasma processing according to an embodiment of the present invention. Fig.14 Methods for determining appropriate delays and / or offsets for use in the embodiment methods described herein (e.g. Figure 1 In some embodiments, the ion angular distribution function (IADF) is measured by a control method (e.g., in order to achieve a desired angular spread during plasma processing). Since it is difficult to measure the ion angular distribution function (IADF), online control may not be an appropriate solution. Instead, model-based control of the IADF can be implemented as a solution to achieve active control of the IADF.

[0115] refer to Fig.14 , a flowchart 1400 for generating a control law includes step 1401 including determining an input array of pulse modulation process parameters. For example, the input array may include various delays, powers, pulse widths, duty cycles, etc. In step 1402, the input parameter array may be utilized, during which experiments may be conducted to determine empirical results for the input parameter array for a given plasma processing system. In step 1403, various plasma parameters may be measured. For example, the plasma parameters may include the maximum, minimum, and average energies of the plasma species, the ion energy distribution function (IEDF), the ion angular distribution function (IADF), the half maximum full width of the ion angular distribution (δθ fwhm ), development critical dimension (DCD), etch critical dimension (ECD) and other parameters at one or more locations in the plasma processing chamber. The measurements can be made by introducing a test wafer to best approximate the actual process conditions.

[0116] In step 1404, an array of input parameters may also be utilized in a plasma model. For example, the plasma model may be a one-dimensional (1D) model specific to a plasma processing system to predict plasma parameters given a set of input parameters. In some cases, the plasma model may also be a multi-dimensional model. The plasma model may be statistical and / or may include a physics-based model of the plasma in the plasma chamber. In step 1405, the plasma model may be used to calculate a set of simulated plasma parameters corresponding to the measured plasma parameters.

[0117] In step 1406, the calculated plasma parameters and the measured plasma parameters can be compared to determine the accuracy of the plasma model. For example, if certain preselected parameters are within a predetermined range, then it can be determined that there is consistency between the calculated parameters and the measured parameters. The identity of the preselected parameters and the predetermined range can depend on the specific design details of the plasma process. If it is determined in step 1406 that the calculated parameters and the measured parameters are inconsistent, the plasma model can be revised in step 1407. Model revisions can include adjusting proportional constants, changing boundary conditions and regression analysis, and replacing simple models with more complex models. After the plasma model has been revised, the method returns to step 1404.

[0118] If the measured plasma parameters are found to be consistent with the calculated plasma parameters, a control law may be generated in step 1408. The control law may be based on the change in one or more delay parameters f(Δt 延迟 ) to define the ion angular distribution δθ fwhm The change (expressed as Δδθ fwhm ). In particular, the control law may advantageously allow accurate prediction of the change in the angular spread of the ion distribution for a given change in one or more delay parameters.

[0119] Fig.15 A flow chart showing an example method of feedforward controlling a plasma process according to an embodiment of the present invention is shown. For example, Fig.15 The method may be performed by a plasma processing system to implement a control law (e.g., Fig.14 The feedforward control method can allow, for example, controlling a plasma processing system by determining a new pulse delay based on an expected and / or measured change in a desired value (such as a change in a critical dimension (CD), an angular distribution, etc.).

[0120] refer to Fig.15 , a flow chart 1500 of a feedforward control method includes a step 1501 of measuring a change in a critical dimension ΔCD. For example, CD may be an ECD of a DCD of a particular plasma process. In some embodiments, step 1501 may measure a plurality of ΔCDs, or step 1501 may be omitted. Step 1502 includes measuring a change in an angular distribution Δδθ fwhm Similar to step 1501, in some embodiments, changes in the angular distribution of multiple species may be measured in step 1502. Alternatively, step 1502 may be omitted.

[0121] In step 1503, a correction model may be applied using a control law. In one embodiment, the correction model is a linear correction model. As an example, for example, Fig.14 Based on the results of the linear correction model, one or more new delay parameters t can be determined. 延迟 .

[0122] Fig.16 An example method of controlling during plasma processing according to an embodiment of the present invention is presented. It should be noted that although Fig.14 and Fig.15 The flowchart is intended to show a specific sequence of events, but Fig.16 The method shown is not intended to limit the method steps to a particular order. Therefore, the following method steps can be performed in any suitable order as may be apparent to those skilled in the art.

[0123] Step 1601 of the method 1600 for controlling during plasma processing includes generating a first sequence of SP pulses. Step 1602 includes generating a second sequence of BP pulses. For example, any of the embodiment methods described herein (e.g., Figure 1 Further, for example, any embodiment system described in this article (such as Figure 2 In one embodiment, a pulse modulation circuit is used to generate the SP pulse. The pulse modulation circuit may be included in the controller.

[0124] Step 1603 of the method 1600 for controlling during plasma processing includes delaying BP pulses in the second sequence relative to the SP pulses in the first sequence to form a combined sequence of alternating SP pulses and BP pulses. For example, each SP pulse may be followed by a BP pulse, and each BP pulse may be followed by an SP pulse. In one embodiment, the BP pulses are delayed using a timing circuit. The timing circuit may be included in the controller.

[0125] Step 1604 includes generating a plasma including ions using the combined sequence, and step 1605 includes delivering the ions to a surface of a workpiece using the combined sequence. The combined sequence may be used to generate a plasma in a plasma processing chamber. The plasma may include ions, and the combined sequence may further be used to deliver the ions to a surface of a workpiece.

[0126] Fig.17 An exemplary plasma processing method according to an embodiment of the present invention is presented. It should be noted that although Fig.14 and Fig.15 The flowchart is intended to show a specific sequence of events, but Fig.17The method shown is not intended to limit the method steps to a particular order. Therefore, the following method steps can be performed in any suitable order as may be apparent to those skilled in the art.

[0127] Step 1701 of the plasma processing method 1700 includes providing source power to a plasma processing chamber to generate plasma. The source power includes a plurality of SP pulses. For example, any of the embodiment methods described herein (e.g., Figure 1 Further, for example, any of the embodiment systems described herein (such as Figure 2 system) to form SP pulses.

[0128] Step 1702 of the plasma processing method 1700 includes providing bias power to the plasma processing chamber. The bias power includes a plurality of BP pulses that are at least partially non-overlapping in time. In various embodiments, the SP pulses and the BP pulses are completely non-overlapping in time. For example, the plasma processing chamber may be provided according to any of the embodiment methods described herein (e.g., Figure 1 Further, for example, any embodiment system described in this article (such as Figure 2 system) forms BP pulses.

[0129] Embodiments as described herein can advantageously control the angle of incidence of ions at the surface of a microelectronic workpiece by controlling the timing between source pulses and bias pulses. For example, the angle of incidence of a given ion arriving at the surface of a microelectronic workpiece is a combination of the substantially vertical velocity imparted to the ion by the bias power and the random velocity due to the temperature of the ion. The temperature of the ion increases with the source power during plasma generation and decreases when the source power is turned off. Embodiments can also advantageously enable flexibility in applying source power and bias power to a plasma processing chamber such that the substantially vertical velocity increases and the random velocity decreases.

[0130] Embodiments described herein may also provide the benefit of limiting plasma generation to a specific time period. For example, applying high frequencies to the plasma afterglow phase may result in electron and ion heating and plasma generation. Further, embodiments may advantageously allow bias power pulses while source power is off, such that ions are accelerated in the afterglow phase without additional plasma generation or heating. This may also advantageously produce enhanced control over ion energy in addition to controlling the angular distribution of ions.

[0131] As an example, an additional advantage of the described embodiments can be the flexible application of bias power including low frequency RF power (e.g., <400kHz), DC power pulses, or alternating polarity DC voltage pulses. Since the source power is turned off, the effectiveness of the lower frequency bias power pulses and / or DC bias power pulses can be increased. The alternating polarity DC pulses can advantageously prevent charge accumulation on the substrate being processed. For example, if the substrate of the microelectronic workpiece includes a dielectric layer, the alternating polarity DC bias power pulses can reduce or eliminate undesirable charging of the substrate.

[0132] Another possible benefit of the described embodiments is maintaining a constant particle flux directed toward a microelectronic workpiece. For example, the source power pulse off time can be selected so that ions and other desired particles (such as free radicals) reach the surface of the microelectronic workpiece at a consistent rate. When selecting the source power off time, several parameters can be considered, including the diffusion coefficient and adhesion coefficient of specific species and the critical dimensions of the plasma processing chamber.

[0133] Example embodiments of the invention are summarized here. Other embodiments are also apparent from the overall description and claims presented herein.

[0134] Example 1. A plasma processing method, the method comprising: generating a first sequence of source power (SP) pulses; generating a second sequence of bias power (BP) pulses; combining the BP pulses in the second sequence with the SP pulses in the first sequence to form a combined sequence of alternating SP pulses and BP pulses; and using the combined sequence to generate a plasma including ions and process the substrate by transmitting the ions to a major surface of the substrate.

[0135] Example 2. The method of Example 1, further comprising adjusting an offset duration between trailing edges of the SP pulses and leading edges of the BP pulses.

[0136] Example 3. The method of one of Examples 1 and 2, further comprising adjusting the pulse width duration of the BP pulses in the second sequence.

[0137] Example 4. The method of one of Examples 1 to 3, further comprising adjusting an off-time duration between SP pulses in the first sequence.

[0138] Example 5. The method as described in one of Examples 1 to 4, further comprising generating a third sequence of potential-controlled power (PCP) pulses, wherein the PCP pulses in the third sequence overlap in time with the alternating SP pulses and BP pulses in the combined sequence.

[0139] Example 6. The method of Example 5, wherein the PCP pulses include negative direct current (DC) pulses, and wherein the negative DC pulses are provided to the plasma during the SP pulses.

[0140] Example 7. The method of Example 5, wherein the PCP pulses include positive direct current (DC) pulses, and wherein the positive DC pulses are provided to the plasma during the BP pulses.

[0141] Example 8. The method of one of Examples 1 to 7, further comprising providing an electron current at the plasma during the alternating SP pulses and BP pulses in the combined sequence.

[0142] Example 9. A plasma processing method, comprising: providing source power (SP) to a plasma processing chamber to generate plasma, the SP comprising a plurality of SP pulses; and providing a bias power (BP) comprising a plurality of bias power (BP) pulses to the plasma processing chamber, wherein the plurality of SP pulses and the plurality of BP pulses are combined to form a pulse sequence, wherein each pulse in the pulse sequence comprises an SP pulse among the plurality of SP pulses and a BP pulse among the plurality of BP pulses and a time interval in which a portion of the SP pulse or a portion of the BP pulse is in a high amplitude state.

[0143] Example 10. The method of Example 9, wherein the SP comprises alternating current (AC) power at a first frequency; the BP comprises AC power at a second frequency; and the second frequency is less than the first frequency.

[0144] Example 11. The method of Example 10, wherein the first frequency is greater than about 10 MHz and the second frequency is less than about 5 MHz.

[0145] Example 12. The method of Example 10, wherein the second frequency is less than about 400 kHz.

[0146] Example 13. The method of Example 9, wherein the SP comprises alternating current (AC) power; and the BP comprises direct current (DC) power.

[0147] Example 14. The method of Example 13, wherein providing SP and BP to the plasma processing chamber comprises alternating the SP pulses in the plurality of SP pulses with the BP pulses in the plurality of BP pulses; and wherein each of the plurality of BP pulses comprises a single DC pulse.

[0148] Example 15. The method of Example 13, wherein each of the plurality of BP pulses comprises alternating polarity DC pulses.

[0149] Example 16. A method as described in one of Examples 9 to 15, wherein the pulse sequence is a periodic sequence, wherein providing the SP and the BP to the plasma processing chamber includes transmitting the periodic sequence including the multiple SP pulses and the multiple BP pulses to the plasma processing chamber; each cycle of the periodic sequence includes exactly one SP pulse of the multiple SP pulses; and a duty cycle of each of the multiple SP pulses is approximately 50%.

[0150] Example 17. A method as described in Example 16, wherein each cycle of the periodic sequence includes exactly one BP pulse of the plurality of BP pulses; and providing the SP and the BP to the plasma processing chamber includes delaying each of the plurality of BP pulses so that a duty cycle of each of the plurality of BP pulses is less than 50%.

[0151] Example 18. A plasma processing system comprising: a controller configured to generate a first sequence of source power (SP) pulses and a second sequence of bias power (BP) pulses and to combine the BP pulses in the second sequence with the SP pulses in the first sequence to form a combined sequence of alternating SP pulses and BP pulses; and a plasma processing chamber coupled to the controller and configured to generate a plasma including ions generated using the combined sequence, the plasma processing chamber configured to support a substrate for receiving the generated ions.

[0152] Example 19. The system of Example 18, wherein the controller is further configured to adjust an offset duration between trailing edges of the SP pulses and leading edges of the BP pulses, adjust a pulse width duration of the BP pulses in the second sequence, or adjust an off-time duration between SP pulses in the first sequence.

[0153] Example 20. A system as described in one of Examples 18 and 19, wherein the controller is further configured to generate a third sequence of potential-controlled power (PCP) pulses, wherein the PCP pulses in the third sequence overlap in time with the alternating SP pulses and BP pulses in the combined sequence.

[0154] The power control techniques as described herein can be controlled by a controller. It should also be noted that the controller can be implemented using one or more programmable integrated circuits programmed to provide the functions described herein. For example, one or more processors (e.g., microprocessors, microcontrollers, central processing units, etc.), programmable logic devices (e.g., CPLD (complex programmable logic device), FPGA (field programmable gate array), etc.) and / or other programmable integrated circuits can be programmed with software or other programming instructions to implement any function described herein. It should be further noted that software or other programming instructions can be stored in one or more non-transient computer-readable media (e.g., memory storage devices, flash memory, DRAM memory, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), and software or other programming instructions when executed by programmable integrated circuits enable programmable integrated circuits to perform the processes, functions and / or capabilities described herein. Other variants of the above can also be implemented.

[0155] One or more deposition processes may be used to form the material layer described herein. For example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and / or other deposition processes may be used to implement one or more depositions. For plasma deposition processes, a precursor gas mixture (including but not limited to hydrocarbons, fluorocarbons or nitrogen-containing hydrocarbons) may be used in combination with one or more diluent gases (e.g., argon, nitrogen, etc.) under a variety of pressures, powers, flows and temperature conditions. Photolithography processes for photoresist (PR) layers may be implemented using optical lithography, extreme ultraviolet (EUV) lithography and / or other lithography processes. Etching processes may be implemented using plasma etching processes, discharge etching processes and / or other desired etching processes. For example, plasma etching processes may be implemented using plasmas containing fluorocarbons, oxygen, nitrogen, hydrogen, argon and / or other gases. In addition, the operating variables used for the process steps may be controlled to ensure that the CD target parameters of the through-holes are achieved during through-hole formation. The operating variables may include, for example, chamber temperature, chamber pressure, flow rate of gas, frequency and / or power applied to the electrode assembly when generating plasma, and / or other operating variables for the processing steps.Variations of the above may also be implemented while still utilizing the techniques described herein.

[0156] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the description. For example, Figure 8 , Fig.10 and Fig.12The embodiments of can be combined in other embodiments. Figure 2 The described embodiments (such as Figures 2 to 7 ) can be used with Fig. 9 , Fig.11 or Fig.13 It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. A plasma processing method, the method comprising: generating a first sequence of source power SP pulses; generating a second sequence of bias power BP pulses; combining the BP pulses in the second sequence with the SP pulses in the first sequence to form a combined sequence of alternating SP pulses and BP pulses; generating a plasma including ions using the combined sequence and processing the substrate by delivering the ions to a major surface of the substrate; adjusting the offset duration between the trailing edges of the SP pulses and the leading edges of the BP pulses; as well as generating a third sequence of potential-controlled power PCP pulses, wherein the PCP pulses in the third sequence overlap in time with the alternating SP pulses and BP pulses in the combined sequence, Wherein the PCP pulses comprise positive direct current (DC) pulses, and wherein the positive direct current (DC) pulses are provided to the plasma during the BP pulses.

2. The method of claim 1, further comprising: The pulse width duration of the BP pulses in the second sequence is adjusted.

3. The method of claim 1, further comprising: The off-time duration between SP pulses in the first sequence is adjusted.

4. The method of claim 1, wherein: The PCP pulses include negative direct current (DC) pulses, and wherein the negative DC pulses are provided to the plasma during the SP pulses.

5. The method of claim 1, further comprising: Electron current is provided at the plasma during the alternating SP pulses and BP pulses in the combined sequence.

6. A plasma processing method, comprising: providing a source power SP to a plasma processing chamber to generate a plasma, the SP comprising a plurality of SP pulses; as well as providing a BP including a plurality of bias power BP pulses to a plasma processing chamber, wherein the plurality of SP pulses and the plurality of BP pulses are combined to form a pulse train, wherein each pulse in the pulse train includes an SP pulse in the plurality of SP pulses and a BP pulse in the plurality of BP pulses and a time interval in which a portion of the SP pulse or a portion of the BP pulse is in a high amplitude state, Wherein, providing SP and BP to the plasma processing chamber comprises: alternating the SP pulses among the plurality of SP pulses with the BP pulses among the plurality of BP pulses, and adjusting the offset duration between the trailing edges of the SP pulses and the leading edges of the BP pulses; providing a potential controlled power PCP pulse to the plasma processing chamber, wherein the PCP pulse is temporally overlapped with alternating SP pulses and BP pulses, Wherein the PCP pulse comprises a positive direct current (DC) pulse, and wherein the positive direct current (DC) pulse is provided to the plasma during the BP pulse.

7. The method of claim 6, wherein: SP includes alternating current AC power of a first frequency; BP comprises AC power of a second frequency; and The second frequency is less than the first frequency.

8. The method of claim 7, wherein: The first frequency is greater than approximately 10 MHz, and the second frequency is less than approximately 5 MHz.

9. The method of claim 7, wherein: The second frequency is less than approximately 400 kHz.

10. The method of claim 6, wherein: SP includes alternating current (AC) power; and BP includes direct current DC power.

11. The method of claim 10, wherein: in, Each of the plurality of BP pulses includes a single DC pulse.

12. The method of claim 10, wherein: Each of the plurality of BP pulses comprises alternating polarity DC pulses.

13. The method of claim 6, wherein: A pulse train is a periodic sequence where: Providing the SP and the BP to the plasma processing chamber includes: delivering a periodic sequence including a plurality of SP pulses and a plurality of BP pulses to the plasma processing chamber; Each cycle of the periodic sequence includes exactly one SP pulse of the plurality of SP pulses; and The duty cycle of each of the plurality of SP pulses is about 50%.

14. The method of claim 13, wherein: Each cycle of the periodic sequence includes exactly one BP pulse from the plurality of BP pulses; and Providing the SP and the BP to the plasma processing chamber includes delaying each of the plurality of BP pulses such that a duty cycle of each of the plurality of BP pulses is less than 50%.

15. A plasma processing system comprising: A controller configured to: generating a first sequence of source power SP pulses and a second sequence of bias power BP pulses, combining the BP pulses in the second sequence with the SP pulses in the first sequence to form a combined sequence of alternating SP pulses and BP pulses, and generating a third sequence of potential controlled power PCP pulses, wherein the PCP pulses in the third sequence overlap in time with the alternating SP pulses and BP pulses in the combined sequence; and a plasma processing chamber coupled to the controller and configured to generate a plasma including ions generated using the combinatorial sequence, the plasma processing chamber configured to support a substrate for receiving the generated ions, wherein the controller is further configured to adjust an offset duration between the trailing edges of the SP pulses and the leading edges of the BP pulses, Wherein the PCP pulses comprise positive direct current (DC) pulses, and wherein the positive direct current (DC) pulses are provided to the plasma during the BP pulses.

16. The system of claim 15, wherein: The controller is further configured to: adjusting the pulse width duration of the BP pulses in the second sequence, or The off-time duration between the SP pulses in the first sequence is adjusted.

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