Non-volatile memory devices and methods of operating them

Abstract

A non-volatile memory device and a method of operating therefrom are provided. In the method of operating the non-volatile memory device, the non-volatile memory device includes a memory block comprising a plurality of memory cells connected to a plurality of word lines. A data write command is received. Based on the data write command, a first programming operation is performed on some of the word lines connected to the memory block. At least one of the word lines to which the first programming operation is performed is detected as an uncoupled word line. In the absence of a data write command, a second programming operation is performed on open word lines that have not undergone the first programming operation and are adjacent to the uncoupled word lines.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0116003, filed on September 20, 2019 with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The example embodiments generally relate to semiconductor memory devices, and more specifically, to methods of operating nonvolatile memory (NVM) devices, nonvolatile memory devices performing the methods, and methods of operating memory systems using the methods. Background Technology

[0004] Semiconductor memory devices can be broadly categorized into two types based on whether they retain stored data when disconnected from power. These categories include volatile memory devices and non-volatile memory devices. Volatile memory devices lose stored data when power is off, while non-volatile memory devices retain stored data when power is off. Volatile memory devices can perform read and write operations at high speeds, but the content stored in them may be lost when power is off. Non-volatile memory devices can retain their stored content even when power is off. Non-volatile memory devices can be used to store content that must be retained regardless of whether power is supplied. Recently, semiconductor memory devices with three-dimensionally stacked memory cells have been investigated to improve the integrity of semiconductor memory devices. Summary of the Invention

[0005] At least one example embodiment of this disclosure provides a method for operating a non-volatile memory device that can reduce or minimize firmware overhead and performance degradation in open blocks.

[0006] At least one example embodiment of this disclosure provides a non-volatile memory device for performing a method of operating a non-volatile memory device.

[0007] At least one example embodiment of this disclosure provides a method for operating a memory system using a method for operating a non-volatile memory device.

[0008] According to an example embodiment, in a method of operating a non-volatile memory device, the non-volatile memory device includes a memory block comprising a plurality of memory cells and connected to a plurality of word lines. A data write command is received. Based on the data write command, a first programming operation is performed on some of the word lines connected to the memory block. At least one of the word lines to which the first programming operation is performed is detected as an uncoupled word line. In the absence of a data write command, a second programming operation is performed on open word lines that have not undergone the first programming operation and are adjacent to uncoupled word lines.

[0009] According to an example embodiment, a non-volatile memory device includes a memory block, a line decoder, and control circuitry. The memory block includes a plurality of memory cells and is connected to a plurality of word lines. The line decoder selects the plurality of memory cells included in the memory block on a word-by-word-line basis. The control circuitry receives a data write command, performs a first programming operation on some of the word lines connected to the memory block based on the data write command, detects at least one of the word lines on which the first programming operation was performed as an uncoupled word line, and performs a second programming operation on open word lines that were not on which the first programming operation was performed and are adjacent to uncoupled word lines in the absence of a data write command.

[0010] According to an example embodiment, in a method of operating a memory system, the memory system includes a memory controller and a non-volatile memory device controlled by the memory controller. The non-volatile memory device includes a memory block comprising a plurality of memory cells connected to first word lines to Nth word lines, where N is a natural number greater than or equal to 2. The memory controller sends a data write command, a write address, and target data to be written to the non-volatile memory device. Based on the data write command, the write address, and the target data, the non-volatile memory device performs normal programming operations on the memory cells connected to the first to Xth word lines of the first to Nth word lines connected to the memory block, where X is a natural number greater than or equal to 1 and less than or equal to (N-1). The non-volatile memory device detects the Xth word line of the first to Nth word lines to which it performs normal programming operations as a decoupled word line. The Xth word line is the last programmed word line. In the absence of a data write command, the non-volatile memory device performs virtual programming operations on memory cells connected to the (X+1)th word line, which has not undergone normal programming operations and is adjacent to the Xth word line. The memory controller sends a data read command and a read address corresponding to the write address to the non-volatile memory device. Based on the data read command, read address, and read voltage of the same level, the non-volatile memory device performs a read operation on all memory cells connected to the first through Xth word lines to which it performs normal programming operations. The non-volatile memory device sends the target data to the memory controller as a result of the read operation.

[0011] In the method of operating a non-volatile memory device, the method of operating a memory system according to the example embodiments, after a memory block becomes an open block by performing a first programming operation (e.g., a normal programming operation) on a portion of the memory block, when an uncoupled word line is detected in the open block, the uncoupled word line in the open block can be pre-formed (e.g., changed to) a coupled word line by performing a second programming operation (e.g., a virtual programming operation) without external commands. Therefore, default read failures due to uncoupled word lines will not occur, performance degradation may not occur, and it may not be necessary to consider uncoupled word lines for all read operations. Thus, firmware complexity can be reduced, idle resources can be preserved, and firmware overhead and performance degradation due to uncoupled word lines can be reduced or minimized. Attached Figure Description

[0012] Illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 This is a flowchart illustrating a method of operating a non-volatile memory device according to an example embodiment.

[0014] Figure 2 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0015] Figure 3A and Figure 3B It is shown that it includes Figure 2 A diagram illustrating an example of a memory cell array in a non-volatile memory device.

[0016] Figure 4 This shows the operation. Figure 1 A flowchart illustrating an example of a method for using a non-volatile memory device.

[0017] Figure 5A and Figure 5B It is used to describe the operation Figure 4 A diagram illustrating a method for using a non-volatile memory device.

[0018] Figure 6 and Figure 7 Is to show execution Figure 1 The flowchart shows an example of the second programming operation.

[0019] Figure 8A and Figure 8B It is used to describe the operation Figure 4 A diagram illustrating a method for using a non-volatile memory device.

[0020] Figure 9 This shows the operation. Figure 1 A flowchart of another example of a method for non-volatile memory devices.

[0021] Figure 10A and Figure 10B It is used to describe the operation Figure 9 A diagram illustrating a method for using a non-volatile memory device.

[0022] Figure 11 This is a flowchart illustrating a method of operating a non-volatile memory device according to an example embodiment.

[0023] Figure 12 and Figure 13 It is shown Figure 11 A flowchart illustrating an example of performing a read operation.

[0024] Figure 14 This is a block diagram illustrating a memory system according to an example embodiment.

[0025] Figure 15 This is a block diagram illustrating a storage device including a non-volatile memory device according to an example embodiment. Detailed Implementation

[0026] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0027] Figure 1 This is a flowchart illustrating a method of operating a non-volatile memory device according to an example embodiment.

[0028] refer to Figure 1 A non-volatile memory device according to an example embodiment includes at least one memory block. The memory block includes a plurality of memory cells and is connected to a plurality of word lines. (Refer to...) Figure 2 , Figure 3A and Figure 3B Describe the configuration of non-volatile memory devices and memory blocks.

[0029] In a method of operating a non-volatile memory device according to an example embodiment, a data write command is received (operation S100). For example, the data write command may be provided from an external memory controller, and the write address and the data to be written (e.g., target data or write data) may be provided together with the data write command.

[0030] Based on a data write command, a first programming operation (operation S200) is performed on some of the word lines among the plurality of word lines connected to the memory block. For example, the first programming operation can be a normal (or conventional) programming operation. By performing the first programming operation, target data can be programmed (or stored) in some memory cells among the plurality of memory cells included in the memory block that are connected to the word lines. When the first programming operation is performed, the memory block can become an open block, wherein data is stored in some areas (e.g., the areas are in a programmed state), and data is not stored in other areas (e.g., the other areas are in an erased state).

[0031] At least one of the word lines to which the first programming operation is performed is detected as an uncoupled word line (operation S300). In the open block, the word lines to which the first programming operation is performed can be divided or classified as coupled word lines (or normal word lines) and uncoupled word lines. Coupled word lines and uncoupled word lines can have different characteristics. For example, coupled word lines and uncoupled word lines can have different threshold voltage distributions and different read levels. Therefore, it may be desirable, necessary, or required to manage (e.g., compensate) the uncoupled word lines included in the open block.

[0032] In the absence of a data write command, a second programming operation is performed on an open word line that has not undergone the first programming operation and is adjacent to an uncoupled word line (operation S400). For example, the second programming operation can be a dummy programming operation. When the second programming operation is performed, the uncoupled word line can be changed into a coupled word line.

[0033] In some example embodiments, operations S300 and S400 may be executed after the first programming operation in operation S200 is completed (e.g., terminated, completed, or successfully completed). As described above, the second programming operation may be executed without a data write command and may not be included in the first programming operation, or may not be executed consecutively with the first programming operation. Therefore, the second programming operation may be executed independently of the first programming operation after the first programming operation is executed.

[0034] In the method of operating a non-volatile memory device according to an example embodiment, after a memory block becomes an open block by performing a first programming operation (e.g., a normal programming operation) on a portion of the memory block, when an uncoupled word line is detected in the open block, the uncoupled word line in the open block can be pre-formed (e.g., changed to) a coupled word line by performing a second programming operation (e.g., a virtual programming operation) without external commands. Therefore, because default read failures due to uncoupled word lines do not occur, performance degradation may not occur, and it may not be necessary to consider uncoupled word lines for all read operations. Thus, firmware complexity can be reduced, idle resources can be preserved, and / or firmware overhead and performance degradation due to uncoupled word lines can be reduced or minimized.

[0035] Figure 2 This is a block diagram illustrating a non-volatile memory device according to an example embodiment.

[0036] refer to Figure 2 The non-volatile memory device 100 includes a memory cell array 110, a line decoder 120, a page buffer circuit 130, a data input / output (I / O) circuit 140, a voltage generator 150, and / or a control circuit 160.

[0037] The memory cell array 110 is connected to the line decoder 120 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The memory cell array 110 is also connected to the page buffer circuit 130 via multiple bit lines (BL).

[0038] The memory cell array 110 includes multiple memory cells (e.g., multiple non-volatile memory cells) connected to multiple word lines WL and multiple bit lines BL. The memory cell array 110 can be divided into multiple memory blocks BLK1, BLK2, ..., BLKz, each of which includes memory cells. Furthermore, each of the multiple memory blocks BLK1, BLK2, ..., BLKz can be divided into multiple pages. Reference will be made below. Figure 3A and Figure 3B As described, the plurality of memory cells can be arranged in a two-dimensional (2D) array structure or a three-dimensional (3D) vertical array structure.

[0039] Control circuit 160 receives data from memory controller (e.g., Figure 14 The memory controller 600 receives commands CMD and address ADDR, and controls erase, program, and read operations of the non-volatile memory device 100 based on the commands CMD and address ADDR. Erasing operations may include executing a series of erase cycles, and programming operations may include executing a series of programming cycles. Each programming cycle may include a programming operation and a programming verification operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations and data recovery read operations.

[0040] For example, control circuit 160 can generate control signal CON for controlling voltage generator 150 based on command CMD, and can generate control signal PBC for controlling page buffer circuit 130. It can also generate row address R_ADDR and column address C_ADDR based on address ADDR. Control circuit 160 can provide row address R_ADDR to row decoder 120 and column address C_ADDR to data I / O circuit 140.

[0041] Control circuit 160 can perform according to reference Figure 1 The method of the described example embodiment. For example, control circuit 160 receives a data write command, performs a first programming operation on some of a plurality of word lines connected to a memory block based on the data write command, detects at least one of the word lines on which the first programming operation was performed as an uncoupled word line, and performs a second programming operation on open word lines that were not on which the first programming operation was performed and which are adjacent to the uncoupled word lines in the absence of a data write command. Furthermore, control circuit 160 can perform operations according to [reference to...]. Figure 11 The method of the example embodiment described.

[0042] The row decoder 120 is connected to the memory cell array 110 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). The row decoder 120 selects multiple memory cells included in the memory cell array 110 on a word-by-word basis.

[0043] For example, in a data erase / write / read operation, the line decoder 120 can determine at least one of the plurality of word lines WL as the selected word line based on the line address R_ADDR, and can determine the remaining word lines in the plurality of word lines WL other than the selected word line as unselected word lines.

[0044] Furthermore, during data erase / write / read operations, the line decoder 120 can determine at least one of the plurality of string select lines SSL as the selected string select line based on the line address R_ADDR, and can determine the remaining string select lines other than the selected string select lines as unselected string select lines.

[0045] Furthermore, during data erase / write / read operations, the row decoder 120 can determine at least one of the plurality of ground select lines GSL as the selected ground select line based on the row address R_ADDR, and can determine the remaining ground select lines other than the selected ground select line in the plurality of ground select lines GSL as unselected ground select lines.

[0046] Voltage generator 150 can generate the voltage VS required for operation of the non-volatile memory device 100 based on power PWR and control signal CON. Voltage VS can be applied to the plurality of serial select lines SSL, the plurality of word lines WL, and the plurality of ground select lines GSL via row decoder 120. Furthermore, voltage generator 150 can generate the erase voltage VERS required for data erase operations based on power PWR and control signal CON. Eraser voltage VERS can be applied directly or via bit line BL to memory cell array 110.

[0047] For example, during an erase operation, voltage generator 150 can apply an erase voltage VERS to the common source line and / or bit line BL of the memory block (e.g., a selected memory block), and can apply an erase enable voltage (e.g., ground voltage) to all or some word lines of the memory block via row decoder 120. Furthermore, during an erase verification operation, voltage generator 150 can apply an erase verification voltage simultaneously to all word lines of the memory block, or sequentially to the word lines one after another.

[0048] For example, during programming operations, voltage generator 150 can apply a programming voltage to selected word lines via line decoder 120, and can apply a programming pass voltage to unselected word lines. Furthermore, during programming verification operations, voltage generator 150 can apply a programming verification voltage to selected word lines via line decoder 120, and can apply a verification pass voltage to unselected word lines.

[0049] Furthermore, during normal read operations, voltage generator 150 can apply a read voltage to the selected word line via line decoder 120, and can also apply a read voltage to unselected word lines. During data recovery read operations, voltage generator 150 can apply a read voltage to the word line adjacent to the selected word line via line decoder 120, and can also apply a recovery read voltage to the selected word line.

[0050] Page buffer circuitry 130 may be connected to memory cell array 110 via multiple bit lines BL. Page buffer circuitry 130 may include multiple page buffers. In some example embodiments, each page buffer may be connected to one bit line. In other example embodiments, each page buffer may be connected to two or more bit lines.

[0051] Page buffer circuit 130 can store data DAT to be programmed into memory cell array 110, or can read data DAT sensed from memory cell array 110. In other words, depending on the operating mode of non-volatile memory device 100, page buffer circuit 130 can operate as a write driver or a sense amplifier.

[0052] Data I / O circuit 140 can be connected to page buffer circuit 130 via data line DL. Based on column address C_ADDR, data I / O circuit 140 can transfer data DAT from outside the non-volatile memory device 100 (e.g., from...) via page buffer circuit 130. Figure 14 The memory controller 600 in the memory cell array 110 can provide data DAT from the memory cell array 110 to the outside of the non-volatile memory device 100.

[0053] Figure 3A and Figure 3B It is shown that it includes Figure 2 A diagram illustrating an example of a memory cell array in a non-volatile memory device. Figure 3A This is a circuit diagram illustrating an example of a memory cell array included in a NAND flash memory device. Figure 3B This is a circuit diagram illustrating an example of a memory cell array included in a vertical NAND flash memory device.

[0054] refer to Figure 3A The memory cell array 110a may include a string select transistor SST, a ground select transistor GST, and memory cells MC. The string select transistor SST may be connected to bit lines BL1, ..., BLm, and the ground select transistor GST may be connected to a common source line CSL. Memory cells arranged in the same column may be connected in series between one of the bit lines BL1 to BLm and the common source line CSL, and memory cells arranged in the same row may be connected together to one of the word lines WL1, WL2, ..., WL(n-1). In other words, the memory cell MC may be connected in series between the string select transistor SST and the ground select transistor GST, and 16, 32, or 64 word lines may be arranged between the string select line SSL connected to the string select transistor SST and the ground select line GSL connected to the ground select transistor GST.

[0055] The serial select transistor SST can be connected to the serial select line SSL, so that the serial select transistor SST is controlled according to the voltage level applied from the serial select line SSL. The ground select transistor GST can be connected to the ground select line GSL, so that the ground select transistor GST is controlled according to the voltage level applied from the ground select line GSL. The memory cell MC can be controlled according to the voltage levels applied to the word lines WL1 to WLn.

[0056] The non-volatile memory device including memory cell array 110a can perform data read and write (or program) operations in units of page 112 and data erase operations in units of block 113.

[0057] refer to Figure 3B The image shows a memory block 110b of a memory cell array. Figure 3B The memory block 110b can be formed on the substrate in a three-dimensional (or vertical) structure. For example, multiple cell strings included in the memory block 110b can be formed in a direction intersecting the substrate. For example, multiple cell strings included in the memory block 110b (e.g., vertical NAND strings) can be formed in a direction perpendicular to the substrate.

[0058] Memory block 110b may include multiple cell strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32, and NS33 connected between bit lines BL1, BL2, and BL3 and the common source line CSL. Each of cell strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground select transistor GST.

[0059] Each string select transistor (SST) can be connected to a corresponding string select line (SSL1, SSL2, and SSL3). Multiple memory cells MC1 through MC8 can be connected to corresponding word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, respectively. Each ground select transistor (GST) can be connected to a corresponding ground select line (GSL1, GSL2, and GSL3). Each string select transistor (SST) can be connected to a corresponding bit line (e.g., one of BL1 through BL3), and each ground select transistor (GST) can be connected to the common source line CSL.

[0060] Cell strings connected to a single bit line can form a column, and cell strings connected to a single string select line can form a row. For example, cell strings NS11, NS21, and NS31 connected to the first bit line BL1 can correspond to the first column, and cell strings NS11, NS12, and NS13 connected to the first string select line SSL1 can form the first row.

[0061] Word lines of the same height (e.g., WL1) can be connected together, and ground select lines GSL1-GSL3 and string select lines SSL1-SSL3 can be separate. Memory cells located on the same semiconductor layer can share word lines. Strings of cells in the same row can share the string select row. The common source line CSL can be connected to all string cells.

[0062] exist Figure 3B In the diagram, memory block 110b is shown connected to eight word lines WL1-WL8 and three bit lines BL1-BL3, and each of the cell strings NS11-NS33 is shown to include eight memory cells MC1-MC8. However, the inventive concept is not limited thereto. In some example embodiments, each memory block in the memory cell array 110 may be connected to any number of word lines and bit lines, and / or each cell string may include any number of memory cells.

[0063] A three-dimensional vertical array structure may include vertical NAND strings, wherein the vertical NAND strings are vertically oriented such that at least one memory cell is situated above another memory cell. The at least one memory cell may include a charge trapping layer. The following patent documents are incorporated herein by reference in their entirety, describing suitable configurations of memory cell arrays including 3D vertical array structures, wherein the three-dimensional memory array is configured as multiple levels and word lines and / or bit lines are shared between levels: U.S. Patent No. 7,679,133; U.S. Patent No. 8,553,466; U.S. Patent No. 8,654,587; U.S. Patent No. 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0064] Although the description of the memory cell array included in the non-volatile memory device according to the exemplary embodiments is based on NAND flash memory devices, the non-volatile memory device according to the exemplary embodiments can be any non-volatile memory device, such as phase random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), thyristor random access memory (TRAM), etc.

[0065] Figure 4 This shows the operation. Figure 1 A flowchart illustrating an example of a method for using a non-volatile memory device.

[0066] refer to Figure 1 and Figure 4 The plurality of word lines connected to a memory block included in a non-volatile memory device according to an example embodiment may include a first word line to an Nth word line, where N is a natural number greater than or equal to 2.

[0067] In the method of operating a non-volatile memory device according to the example embodiment Figure 4 Operation S100 in the middle can be with Figure 1 The operation S100 is basically the same.

[0068] When a first programming operation is performed on some word lines based on a data write command (operation S200), memory cells connected to the first to the Xth word lines among the first to Nth word lines can be sequentially programmed (operation S210), where X is a natural number greater than or equal to 1 and less than or equal to (N-1). For example, memory cells connected to the first word line can be sequentially programmed first, then memory cells connected to the second word line can be sequentially programmed, and finally memory cells connected to the Xth word line can be sequentially programmed. See reference... Figure 1 The first programming operation can be a normal programming operation.

[0069] When at least one of the word lines is detected as an uncoupled word line (operation S300), the programmed Xth word line among the programmed first to Xth word lines can be scanned as an uncoupled word line (operation S310). The programmed Xth word line can be the last programmed word line. In other words, the last programmed word line in an open block can be detected as an uncoupled word line.

[0070] When a second programming operation is performed on an open word line without a data write command (operation S400), a memory cell connected to the (X+1)th word line, which has not undergone a first programming operation and is adjacent to the Xth word line, can be programmed (operation S410). See reference... Figure 1 The second programming operation can be a virtual programming operation.

[0071] In the method of operating a non-volatile memory device according to the example embodiment, virtual programming operations may not be performed on all memory cells connected to all word lines (e.g., word lines (X+1) to N) that are not programmed in the open block, and virtual programming operations may be performed only on memory cells connected to the (X+1)th word line, which is an uncoupled word line. In other words, virtual programming operations can be performed to the extent that the effects of uncoupled word lines in the open block are eliminated. Therefore, while reducing or minimizing virtual programming operations, performance degradation due to uncoupled word lines can be reduced or prevented.

[0072] Figure 5A and Figure 5B It is used to describe the operation Figure 4 A diagram illustrating a method for using a non-volatile memory device. Figure 5A and Figure 5B It shows that it includes Figure 3A An example of a memory block in a NAND flash memory device is shown, and it is illustrated in... Figure 4 An example in which N=10 and X=4.

[0073] refer to Figure 5A and Figure 5B The memory block BLKa can be connected to word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8, and WL9, and can include memory cells MC0, MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, and MC9. Memory cell MC0 can be connected to word line WL0, and similarly, memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, and MC9 can be connected to word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8, and WL9, respectively.

[0074] like Figure 5A As shown, a first programming operation can be performed to sequentially program memory cells MC0, MC1, MC2, and MC3 connected to the first through fourth word lines WL0, WL1, WL2, and WL3 of the memory block BLKa. In this example, each of the programmed first through third word lines WL0, WL1, and WL2 can be a coupled word line, the last programmed fourth word line WL3 can be a decoupled word line, and each of the fifth through fourth word lines WL4, WL5, WL6, WL7, WL8, and WL9 (e.g., unprogrammed word lines) to which the first programming operation was not performed can be an open word line. Figure 5A In the diagram, memory cells MC0, MC1, and MC2 connected to the coupled word line are represented by solid shading, memory cell MC3 connected to the uncoupled word line is represented by dashed shading, and memory cells MC4, MC5, MC6, MC7, MC8, and MC9 connected to the open word line are not represented by shading. After the first programming operation is completed, the fourth word line WL3 can be detected as an uncoupled word line.

[0075] like Figure 5B As shown, a second programming operation can be performed to sequentially program the memory cell MC4 connected to the fifth word line WL4. The fifth word line WL4 can be one of the open word lines to which the first programming operation has not been performed, and can be adjacent to the fourth word line WL3, which is an uncoupled word line. Therefore, the fourth word line WL3 can be changed from an uncoupled word line to a coupled word line. Figure 5B In the diagram, memory cell MC3, connected to the fourth word line WL3 (which has been changed to a coupled word line), is indicated by a solid shaded line. Since the second programming operation is a virtual programming operation different from the first programming operation, memory cell MC4, connected to the fifth word line WL4, is indicated by a horizontal dashed shaded line. Even when the second programming operation is performed, memory cells MC0, MC1, MC2, MC5, MC6, MC7, MC8, and MC9 connected to the other word lines WL0, WL1, WL2, WL5, WL6, WL7, WL8, and WL9 can remain as described above. Figure 5A The same state as shown.

[0076] Figure 6 and Figure 7 Is to show execution Figure 1 The flowchart shows an example of the second programming operation.

[0077] refer to Figure 1 and Figure 6 When the second programming operation is performed (operation S400), the last programming time, which serves as the point in time when the first programming operation terminates, can be stored (operation S510). For example, see reference... Figure 4 , Figure 5A and Figure 5BAs stated above, when the memory cells connected to the first to the Xth word lines are programmed sequentially, the programming time of the memory cell connected to the last Xth word line can be stored (e.g., connected to...). Figure 5A The programming time of memory cell MC3 in the fourth word line WL3 (in the memory).

[0078] After the first programming operation is completed, the current time can be stored (operation S520), and the first time, which is the time difference between the current time and the last programming time, can be compared with a predetermined threshold time (operation S530). In other words, it can be determined whether the threshold time has elapsed since the last programming time.

[0079] When the first time is longer than the threshold time (operation S530: Yes), the memory cell connected to an open word line that has not undergone the first programming operation and is adjacent to an uncoupled word line can be programmed (operation S540). For example, as referenced Figure 4 , Figure 5A and Figure 5B As stated above, when the Xth word line is detected as an uncoupled word line, memory cells connected to the (X+1)th word line adjacent to the Xth word line (e.g., Figure 5B The memory cell MC4, which is connected to the fifth word line WL4, is used for programming.

[0080] When the first time is shorter than or equal to the threshold time (operation S540: No), the process can be terminated without executing operation S540.

[0081] In some example embodiments, the programming operation performed in operation S540 may be a virtual programming operation for programming dummy data in memory cells connected to open word lines. For example, the dummy data may include a random pattern. As described above, after performing the virtual programming operation, an uncoupled word line can be changed to a coupled word line.

[0082] Reference Figure 6 In the described method for operating a non-volatile memory device, the last programming time can be used as a primary parameter or factor to perform a virtual programming operation. In other words, regardless of the programming scheme, the write area in the memory block (e.g., the area where target data is stored via a first programming operation), or the host command (e.g., a data write command received from an external source), the last programming time is the most important parameter for the virtual programming operation. If no programming operation is performed after a certain period from the last programming time, a virtual programming operation can be performed on the word line adjacent to the last programmed word line to protect that last programmed word line.

[0083] refer to Figure 1 and Figure 7 When the second programming operation is performed (operation S400), it can be determined whether a programming failure occurred when the first programming operation was performed (operation S610).

[0084] When a programming failure occurs (operation S610: Yes), the memory cell connected to an open word line that has not undergone the first programming operation and is adjacent to an uncoupled word line can be programmed (operation S620). For example, when the programming cycle is repeated more than a predetermined (or alternatively, desired) number of times but the programming verification operation fails to complete successfully, it can be determined that a programming failure has occurred, and the word line where the programming failure occurred can correspond to a reference word line. Figure 6 The last word line of the program described. Figure 7 The operation of S620 can be combined with Figure 6 The operation is basically the same as that of S540.

[0085] If no programming failure occurs (operation S610: No), the process can be terminated without executing operation S620.

[0086] In some example embodiments, in Figure 6 Operation S540 and Figure 7 The second programming operation (e.g., virtual programming operation) performed in operation S620 can be performed when the non-volatile memory device is powered off. For example, the power outage of the non-volatile memory device can include a sudden power off (SPO) situation where the power to the non-volatile memory device is suddenly turned off, and a normal power off (NPO) situation where the power to the non-volatile memory device is turned off according to a predetermined (or alternatively, desired) process.

[0087] In other example embodiments, in Figure 6 Operation S540 and Figure 7 The second programming operation performed in operation S620 can be performed when the non-volatile memory device is powered on and the power of the non-volatile memory device is maintained.

[0088] However, the example embodiments are not limited thereto, and the second programming operation can be performed at any time the non-volatile memory device is driven.

[0089] Figure 8A and Figure 8B It is used to describe the operation Figure 4 A diagram illustrating a method for using a non-volatile memory device. Figure 8A and Figure 8B It shows that it includes Figure 3B An example of a memory block in a vertical NAND flash memory device is shown, and it is illustrated in... Figure 4Examples of N=10 and X=4 are shown in the embodiments. (The last part, "omitted," is a continuation of the previous sentence and doesn't need a direct translation.) Figure 5A and Figure 5B Repeated description.

[0090] refer to Figure 8A and Figure 8B The memory block BLKb can be connected to word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8 and WL9, and can be connected to serial select lines SSL0, SSL1, SSL2 and SSL3. It can also include memory cells MC00, MC01, MC02, MC03, MC04, MC05, MC06, MC07, MC08, MC09, MC10, MC11, MC12, MC13, MC14, MC15, MC16, MC17, MC18, MC19, MC20, MC21, MC22, MC23, MC24, MC25, MC26, MC27, MC28, MC29, MC30, MC31, MC32, MC33, MC34, MC35, MC36, MC37, MC38 and MC39. Memory cells MC00, MC10, MC20 and MC30 can be connected to word line WL0, and similarly, memory cells MC01, MC11, MC21, MC31, MC02, MC12, MC22, MC32, MC03, MC13, MC23, MC33, MC04, MC14, MC24, MC34, MC05, MC15, MC25, MC35, MC06, MC16, MC26, MC36, MC07, MC17, MC27, MC37, MC08, MC18, MC28, MC38, MC09, MC19, MC29 and MC39 can be connected to word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8 and WL9 respectively. Memory cells MC00, MC01, MC02, MC03, MC04, MC05, MC06, MC07, MC08, and MC09 can be connected to serial select line SSL0, and similarly, memory cells MC10, MC11, MC12, MC13, MC14, MC15, MC16, MC17, MC18, MC19, MC20, MC21, MC22, MC23, MC24, MC25, MC26, MC27, MC28, MC29, MC30, MC31, MC32, MC33, MC34, MC35, MC36, MC37, MC38, and MC39 can be connected to serial select lines SSL1, SSL2, and SSL3, respectively.

[0091] like Figure 8AAs shown, a first programming operation can be performed to sequentially program memory cells MC00, MC10, MC20, MC30, MC01, MC11, MC21, MC31, MC02, MC12, MC22, MC32, MC03, MC13, MC23, and MC33 connected to the first to fourth word lines WL0, WL1, WL2, and WL3 of the memory block BLKb. In this example, each of the programmed first to third word lines WL0, WL1, and WL2 can be a coupled word line, the last programmed fourth word line WL3 can be a decoupled word line, and each of the fifth to fourth cross lines WL4, WL5, WL6, WL7, WL8, and WL9, to which the first programming operation was not performed, can be an open word line.

[0092] like Figure 8B As shown, a second programming operation can be performed to sequentially program memory cells MC04, MC14, MC24, and MC34 connected to the fifth word line WL4. The fifth word line WL4 can be one of the open word lines to which the first programming operation has not been performed, and can be adjacent to the fourth word line WL3, which is an uncoupled word line. Therefore, the fourth word line WL3 can be changed from an uncoupled word line to a coupled word line.

[0093] Figure 9 This shows the operation. Figure 1 A flowchart of another example of a method for a non-volatile memory device. (The remaining text is omitted.) Figure 4 Repeated description.

[0094] refer to Figure 1 and Figure 9 The plurality of word lines connected to a memory block included in a non-volatile memory device according to an example embodiment may include first to Nth word lines. Furthermore, the memory block may be connected to a plurality of string select lines, which may include first to Mth string select lines, where M is a natural number greater than or equal to 2.

[0095] In the method of operating a non-volatile memory device according to the example embodiment Figure 9 Operation S100 in the middle can be with Figure 1 The operation S100 is basically the same.

[0096] When a first programming operation is performed on some word lines based on a data write command (operation S200), memory cells connected to the first to (Y-1) word lines among the first to N word lines, and memory cells connected to the Y word line among the first to N word lines and connected to the first to Z string select lines among the first to M string select lines, can be sequentially programmed (operation S220), where Y is a natural number greater than or equal to 2 and less than or equal to (N-1), and Z is a natural number greater than or equal to 1 and less than or equal to (M-1). For example, memory cells connected to the first word line and connected to the first to M string select lines can be sequentially programmed first, then memory cells connected to the second word line and connected to the first to M string select lines can be sequentially programmed, then memory cells connected to the (Y-1) word line and connected to the first to M string select lines can be sequentially programmed, and finally memory cells connected to the Y word line and connected to the first to Z string select lines can be sequentially programmed.

[0097] When at least one of the word lines is detected to be an uncoupled word line (operation S300), the programmed (Y-1) and Y-th word lines among the programmed first to Y-th word lines can be scanned as uncoupled word lines (operation S320). The programmed (Y-1) and Y-th word lines can be the last programmed word lines.

[0098] When a second programming operation is performed on an open word line without a data write command (operation S400), memory cells connected to the Y word line and connected to the (Z+1) string select line to the M string select line, and memory cells connected to the (Y+1) word line adjacent to the Y word line and connected to the first string select line to the Z string select line can be programmed (operation S420).

[0099] Figure 10A and Figure 10B It is used to describe the operation Figure 9 A diagram illustrating a method for using a non-volatile memory device. Figure 10A and Figure 10B It shows that it includes Figure 3B An example of a memory block in a vertical NAND flash memory device is shown, and it is illustrated in... Figure 9 Examples of N=10, M=4, Y=5, and Z=2 are shown in the embodiments. (The last part, "omitted," appears to be a fragment and doesn't translate directly.) Figure 5A , Figure 5B , Figure 8A and Figure 8B Repeated description.

[0100] refer to Figure 10A and Figure 10B The memory block BLKc can have the same as Figure 8A and Figure 8BThe memory block BLKb in the memory has a basically the same structure.

[0101] like Figure 10A As shown, a first programming operation can be performed on memory cells MC00, MC10, MC20, MC30, MC01, MC11, MC21, MC31, MC02, MC12, MC22, MC32, MC03, MC13, MC23, and MC33 of memory block BLKc, which are connected to the first to fourth word lines WL0, WL1, WL2, and WL3 and to the first to fourth string select lines SSL0, SSL1, SSL2, and SSL3, and on memory cells MC04 and MC14 of memory block BLKc, which are connected to the fifth word line WL4 and to the first and second string select lines SSL0 and SSL1. In this example, each of the first to third word lines WL0, WL1 and WL2 that have been programmed can be a coupled word line, each of the last programmed fourth and fifth word lines WL3 and WL4 can be a decoupled word line, and each of the sixth to the cross lines WL5, WL6, WL7, WL8 and WL9 that have not undergone the first programming operation can be an open word line.

[0102] like Figure 10B As shown, a second programming operation can be performed, sequentially programming memory cells MC24 and MC34 connected to the fifth word line WL4 and connected to the third and fourth string select lines SSL2 and SSL3, and sequentially programming memory cells MC05 and MC15 connected to the sixth word line WL5 adjacent to the fifth word line WL4 and connected to the first and second string select lines SSL0 and SSL1. Therefore, the fourth word line WL3 can be changed from an uncoupled word line to a coupled word line.

[0103] Figure 11 This is a flowchart illustrating a method of operating a non-volatile memory device according to an example embodiment. (The remaining text is incomplete and cannot be translated.) Figure 1 Repeated description.

[0104] refer to Figure 11 In the method of operating a non-volatile memory device according to the example embodiment, Figure 11 Operations S100, S200, S300, and S400 can be respectively connected with... Figure 1 The operations S100, S200, S300 and S400 are basically the same.

[0105] After operations S100, S200, S300, and S400 are executed, a data read command is received (operation S700). For example, similar to a data write command, the data read command can be provided from an external memory controller, and the read address can be provided along with the data read command. For example, the read address can correspond to the write address.

[0106] Based on the data read command, under the same conditions, a read operation is performed on all word lines of some word lines to which the first programming operation was performed (operation S800). For example, as referenced Figure 12 and Figure 13 The description indicates that a read operation can be performed based on a read voltage with the same level.

[0107] The target data can then be sent to an external memory controller as a result of the read operation.

[0108] In the method of operating a non-volatile memory device according to the example embodiment, the uncoupled word line storing valid data can be pre-formed (e.g., changed to) a coupled word line by performing a second programming operation (e.g., by performing a virtual programming operation to program virtual data into a word line following the uncoupled word line) without external commands. Therefore, read operations can be performed efficiently even using read voltages of the same level, without read errors or read retries.

[0109] Figure 12 and Figure 13 It is shown Figure 11 A flowchart illustrating an example of performing a read operation.

[0110] refer to Figure 11 and Figure 12 When a read operation is performed on all word lines of some word lines to which the first programming operation is performed under the same conditions (operation S800), the memory cells connected to the first to the Xth word lines among the first to the Nth word lines can be read sequentially based on the read voltages having the same level (operation S810). Figure 12 The operation S810 can be applied or adopted in it, as shown in the reference. Figure 4 , Figure 5A , Figure 5B , Figure 8A and Figure 8B As described Figure 11 Examples of operations S100, S200, S300, and S400 in the example.

[0111] refer to Figure 11 and Figure 13When a read operation is performed on all word lines of some word lines to which the first programming operation is performed under the same conditions (operation S800), the memory cells connected to the first to (Y-1) word lines in the first to N word lines and the memory cells connected to the Y word lines in the first to N word lines and the first to Z string selection lines in the first to M string selection lines can be read sequentially based on the read voltages with the same level (operation S820). Figure 13 The operation S820 can be applied to or used in it, as shown in the reference. Figure 9 , Figure 10A and Figure 10B As described Figure 11 Examples of operations S100, S200, S300, and S400 in the example.

[0112] As those skilled in the art will understand, the concept of the present invention can be implemented as a system, method, computer program product, and / or a computer program product implemented on one or more computer-readable media, wherein the computer-readable medium has computer-readable program code implemented thereon. The computer-readable program code can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus. Control circuitry 160, memory controller 600, and any other disclosed elements may include processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be any tangible medium capable of containing or storing a program used by or in connection with an instruction execution system, apparatus, or device. For example, a computer-readable medium can be a non-transitory computer-readable medium.

[0113] Figure 14 This is a block diagram illustrating a memory system according to an example embodiment.

[0114] refer to Figure 14The memory system 500 includes a memory controller 600 and at least one non-volatile memory device 700.

[0115] The non-volatile memory device 700 can correspond to the non-volatile memory device according to the example embodiment, and can perform the method of operating the non-volatile memory device according to the example embodiment, and can perform data erasure, programming (or writing) and / or read operations under the control of the memory controller 600. The non-volatile memory device 700 can receive commands CMD and addresses ADDR from the memory controller 600 via I / O lines to perform such operations, and can exchange data DAT with the memory controller 600 to perform such programming or read operations. Furthermore, the non-volatile memory device 700 can receive control signals CTRL from the memory controller 600 via control lines. Additionally, the non-volatile memory device 700 receives power PWR from the memory controller 600 via power lines.

[0116] Figure 15 This is a block diagram illustrating a storage device including a non-volatile memory device according to an example embodiment.

[0117] refer to Figure 15 Storage device 1000 includes multiple non-volatile memory (NVM) devices 1100 and a controller 1200. For example, storage device 1000 can be any storage device, such as an embedded multimedia card (eMMC), universal flash storage (UFS), solid-state drive (SSD), etc.

[0118] The controller 1200 can be connected to the non-volatile memory device 1100 via multiple channels CH1, CH2, CH3, ..., CHi. The controller 1200 may include one or more processors 1210, a buffer memory 1220, an error correction code (ECC) circuit 1230, a host interface 1250, and a non-volatile memory (NVM) interface 1260.

[0119] Buffer memory 1220 can store data used to drive controller 1200. ECC circuit 1230 can calculate the error correction code value of the data to be programmed during programming operations, and can use the error correction code value to correct errors in reading data during read operations. In data recovery operations, ECC circuit 1230 can correct errors in data recovered from non-volatile memory device 1100. Host interface 1250 can provide an interface with external devices. Non-volatile memory interface 1260 can provide an interface with non-volatile memory device 1100.

[0120] Each of the non-volatile memory devices 1100 may correspond to a non-volatile memory device according to an example embodiment, and may optionally be provided with an external high voltage VPP.

[0121] The concept of this invention can be applied to a variety of electronic devices and systems, including non-volatile memory devices. For example, the concept of this invention can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, portable camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, and the like.

[0122] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. While some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications to the exemplary embodiments are possible without substantially departing from the novel teachings and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments defined in the claims. Consequently, it should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A method of operating a non-volatile memory device, the non-volatile memory device comprising a memory block, the memory block including a plurality of memory cells and connected to a plurality of word lines, the method comprising: Receive data and write command; Based on the data write command, a first programming operation is performed on some of the multiple word lines connected to the memory block; At least one of the word lines to which the first programming operation is performed will be detected as an uncoupled word line; as well as In the absence of the data write command, perform a second programming operation on the open word line that has not undergone the first programming operation and is adjacent to the uncoupled word line. The second programming operation includes: Store the last programming time as the point in time when the first programming operation terminates. Store the current time. The first time is compared with a predetermined threshold time, where the first time is the time difference between the current time and the last programming time. When the first time is longer than the predetermined threshold time, the memory cell connected to the open word line that has not undergone the first programming operation and is adjacent to the uncoupled word line is programmed.

2. The method of claim 1, wherein the plurality of word lines includes a first word line to an Nth word line, wherein N is a natural number greater than or equal to 2, and Performing the first programming operation includes: The memory cells connected to the first word line to the X word line in the Nth word line are sequentially programmed, where X is a natural number greater than or equal to 1 and less than or equal to (N-1).

3. The method of claim 2, wherein detecting at least one of the word lines as the uncoupled word line comprises: The programmed Xth word line from the programmed first word line to the Xth word line is scanned as the uncoupled word line, and the programmed Xth word line is the last programmed word line.

4. The method of claim 3, wherein performing the second programming operation comprises: Program the memory cell connected to the (X+1)th word line adjacent to the Xth word line.

5. The method of claim 1, wherein performing the second programming operation comprises: Determine whether a programming failure occurred while performing the first programming operation; as well as When the programming failure occurs, the memory cell connected to the open word line that was not subjected to the first programming operation and is adjacent to the uncoupled word line is programmed.

6. The method of claim 1, wherein the second programming operation is a virtual programming operation for programming virtual data in a memory cell connected to the open word line.

7. The method of claim 6, wherein after performing the second programming operation, the uncoupled word line is changed to a coupled word line.

8. The method of claim 6, wherein the virtual data includes a random pattern.

9. The method of claim 1, wherein the plurality of word lines includes a first word line to an Nth word line, wherein N is a natural number greater than or equal to 2. The memory block is connected to the first select line to the Mth select line, where M is a natural number greater than or equal to 2. Performing the first programming operation includes: Sequential programming is performed on memory cells connected to the first word line to the (Y-1)th word line in the first word line to the Nth word line, and on memory cells connected to the Yth word line in the first word line to the Nth word line and the first string select line to the Zth string select line in the first string select line to the Mth string select line, where Y is a natural number greater than or equal to 2 and less than or equal to (N-1), and Z is a natural number greater than or equal to 1 and less than or equal to (M-1).

10. The method of claim 9, wherein detecting at least one of the word lines as the uncoupled word line comprises: The programmed (Y-1)th and Yth word lines from the first to the Yth word lines are scanned as the uncoupled word lines, wherein the programmed (Y-1)th and Yth word lines are the last programmed word lines.

11. The method of claim 10, wherein performing the second programming operation comprises: The memory cells connected to the Y-th word line and the (Z+1)th string select line to the M-th string select line, and the memory cells connected to the (Y+1)th word line and the first string select line to the Z-th string select line adjacent to the Y-th word line are programmed.

12. The method of claim 9, wherein the memory block is included in a three-dimensional memory cell array in which the plurality of memory cells are stacked in a direction intersecting the substrate.

13. The method according to claim 1, further comprising: Receive data read command; Based on the data read command, a read operation is performed on all word lines of the word lines to which the first programming operation was performed, under the same conditions.

14. The method of claim 13, wherein performing the read operation comprises: The memory cells connected to the word lines are read sequentially based on the read voltage having the same level.

15. The method of claim 1, wherein the second programming operation is performed when the non-volatile memory device is powered off.

16. The method of claim 15, wherein the power outage of the non-volatile memory device includes a sudden power outage (SPO) where the power to the non-volatile memory device is suddenly turned off, and a normal power outage (NPO) where the power to the non-volatile memory device is turned off according to a predetermined process.

17. The method of claim 1, wherein the second programming operation is performed when the non-volatile memory device is powered on and the power to the non-volatile memory device is maintained.

18. A non-volatile memory device, comprising: A memory block comprises multiple memory cells and is connected to multiple word lines; A line decoder is configured to select the plurality of memory cells included in the memory block on a word-by-word basis; and A control circuit is configured to receive a data write command, perform a first programming operation on some of the plurality of word lines connected to the memory block based on the data write command, detect at least one of the word lines on which the first programming operation has been performed as an uncoupled word line, and perform a second programming operation on open word lines that have not undergone the first programming operation and are adjacent to the uncoupled word lines in the absence of the data write command. The control circuit is further configured as follows: Store the last programming time as the point in time when the first programming operation terminates. Store the current time. The first time is compared with a predetermined threshold time, where the first time is the time difference between the current time and the last programming time. When the first time is longer than the predetermined threshold time, the memory cell connected to the open word line that has not undergone the first programming operation and is adjacent to the uncoupled word line is programmed.

19. A method of operating a memory system, the memory system including a memory controller and a non-volatile memory device controlled by the memory controller, the non-volatile memory device including a memory block, the memory block including a plurality of memory cells connected to a first word line to an Nth word line, wherein N is a natural number greater than or equal to 2, the method comprising: The memory controller sends a data write command, a write address, and the target data to be written to the non-volatile memory device. Based on the data write command, the write address, and the target data, the non-volatile memory device performs normal programming operations on the memory cells connected to the first word line to the X word line among the first word lines to the Nth word lines connected to the memory block, where X is a natural number greater than or equal to 1 and less than or equal to (N-1). The non-volatile memory device detects the Xth word line among the first word line to the Nth word line, which is the last word line programmed, as an uncoupled word line. The non-volatile memory device performs a virtual programming operation on a memory cell connected to the (X+1)th word line, which is adjacent to the Xth word line and for which the normal programming operation has not been performed, without the data write command. The memory controller sends a data read command and a read address corresponding to the write address to the non-volatile memory device; The non-volatile memory device performs a read operation on all memory cells connected to the first word line to the Xth word line to which the normal programming operation is performed, based on the data read command, the read address, and a read voltage of the same level. as well as The non-volatile memory device sends the target data to the memory controller as a result of the read operation.

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