Solid state drive device

Abstract

A solid state drive (SSD) device includes a substrate, a first buffer chip disposed on the substrate, a second buffer chip disposed on the first buffer chip, a plurality of first non-volatile memory chips connected to the second buffer chip through wire bonding, a controller configured to send a control signal to the plurality of first non-volatile memory chips through a first channel, and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer through flip chip bonding, and the second buffer chip is connected to the first redistribution layer through first wires.

Description

Technical Field

[0001] This disclosure relates to a solid-state drive (SSD) device and a method for manufacturing the solid-state drive device. Background Technology

[0002] Hard disks have traditionally been used as data storage devices in electronic systems such as computer systems. However, with the development of semiconductor technology, solid-state drives (SSDs) that use non-volatile memory (such as flash memory, e.g., NAND flash memory) instead of hard disks as data storage devices are increasingly being used in computer systems and portable devices.

[0003] Because solid-state drives (SSDs) do not include mechanical drive units, such as the motors required for hard disk drive (HDD) devices, they generate very little heat and noise during operation. Furthermore, due to their fast access speeds, high integration, and stability against external shocks, SSDs are ideal as data storage devices. In addition, the data transfer rates of SSDs can be significantly faster than those of hard disk drives.

[0004] Typically, a solid-state drive device can have multiple non-volatile memory chips connected to each of multiple channels. However, as the storage capacity of a solid-state drive device increases, the number of these multiple non-volatile memory chips connected to each of the multiple channels can also increase. However, this presents a problem: as the number of these multiple non-volatile memory chips connected to each of the multiple channels increases, the load to be driven for each channel increases, and the operating speed of the solid-state drive device decreases. Summary of the Invention

[0005] According to an embodiment, a solid-state drive (SSD) device includes: a substrate; a first buffer chip disposed on the substrate; a second buffer chip disposed on the first buffer chip; a plurality of first non-volatile memory chips connected to the second buffer chip via wire bonding; a controller configured to send control signals to the plurality of first non-volatile memory chips via a first channel; and a first redistribution layer disposed in the substrate and configured to electrically connect the first channel to the first buffer chip, wherein the first buffer chip is connected to the first redistribution layer via flip-chip bonding, and the second buffer chip is connected to the first redistribution layer via a first wire.

[0006] According to an embodiment, a solid-state driver device includes: a first buffer chip; a support film disposed on the first buffer chip; a second buffer chip disposed on the support film; a plurality of first non-volatile memory chips connected to the first buffer chip via wire bonding; a first redistribution layer connected to the first buffer chip and the second buffer chip via wire bonding; and a controller configured to send control signals to the plurality of first non-volatile memory chips via a first channel electrically connected to the first redistribution layer.

[0007] According to an embodiment, a solid-state driver device includes: a substrate; a first buffer chip on one side of the substrate; a second buffer chip disposed on the first buffer chip; a first redistribution layer, a second redistribution layer, and a third redistribution layer formed in the substrate and connected to the first buffer chip via flip-chip bonding, wherein the first redistribution layer is electrically connected to the first buffer chip via a first connection terminal, the second redistribution layer is electrically connected to the first buffer chip via a second connection terminal, and the third redistribution layer is electrically connected to the first buffer chip via a third connection terminal; a plurality of first non-volatile memory chips, including a bottom region of the first non-volatile memory chips and a top region of the first non-volatile memory chips, the bottom region of the first non-volatile memory chips being connected to the second buffer chip via a first lead, and the first non-volatile memory chips... A top region is connected to a second buffer chip via a second lead and disposed on the bottom region of a first non-volatile memory chip; a controller is connected to a first redistribution layer and configured to send control signals to the first buffer chip via a first channel; multiple external connection terminals are connected to the first channel and disposed on the opposite side of the substrate to the first side of the substrate; and multiple second non-volatile memory chips, including a bottom region of a second non-volatile memory chip and a top region of a second non-volatile memory chip, the bottom region of the second non-volatile memory chip being connected to a third redistribution layer via a third lead, the top region of the second non-volatile memory chip being connected to a second redistribution layer via a fourth lead and disposed on the bottom region of the second non-volatile memory chip, wherein the second buffer chip is electrically connected to the first redistribution layer via a fifth lead.

[0008] According to an embodiment, a method for manufacturing a solid-state driver device includes: forming a first redistribution layer in a substrate; forming a first connection pad connected to the first redistribution layer on an upper side of the substrate; forming a first connection terminal on the first connection pad; forming a plurality of external connection terminals on a lower side of the substrate opposite to the upper side; sequentially stacking a first buffer chip and a second buffer chip on the first connection terminal; sequentially stacking a plurality of first non-volatile memory chips on the upper side of the substrate in a first direction; connecting the second buffer chip and the first connection pad via a first lead; and connecting the plurality of first non-volatile memory chips to the second buffer chip via wire bonding. Attached Figure Description

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating an example of a solid-state drive system according to an embodiment.

[0011] Figure 2 This is a diagram illustrating an example of a solid-state drive device according to an embodiment.

[0012] Figure 3 According to the implementation method Figure 2 A circuit diagram of an example buffer chip.

[0013] Figure 4 This illustrates an embodiment. Figure 3 Circuit diagrams of the second and third receivers.

[0014] Figure 5 According to the implementation method Figure 2 A top view of an example solid-state drive device.

[0015] Figure 6 According to the implementation method Figure 5 A top view of an example of a buffer chip.

[0016] Figure 7 This illustrates an embodiment. Figure 2 A diagram showing an example of a non-volatile memory region.

[0017] Figure 8 This illustrates an embodiment. Figure 2 Another diagram showing an example of a non-volatile memory region.

[0018] Figure 9 This is a diagram illustrating an example of a solid-state drive device according to an embodiment.

[0019] Figure 10 This is a diagram illustrating an example of a solid-state drive device according to an embodiment.

[0020] Figures 11 to 13 This illustrates a method for manufacturing according to an embodiment. Figure 2 A diagram illustrating an intermediate stage of an example method for a solid-state driver device.

[0021] Figure 14 This is a block diagram illustrating a solid-state driver system according to an embodiment.

[0022] Figures 15 to 22 This is a block diagram illustrating an example of a solid-state drive device according to an embodiment. Detailed Implementation

[0023] The embodiments may provide solid-state drive devices with high capacity and improved operating speed. The embodiments may also provide methods for manufacturing solid-state drive devices with high capacity and improved operating speed. However, the embodiments are not limited to those set forth herein. These and other aspects of the embodiments will become more apparent to those skilled in the art to which this disclosure pertains from the following detailed description of the inventive concept. The embodiments described below are exemplary, and therefore the inventive concept is not limited to these disclosed embodiments, but may be implemented in various other forms. It will be understood that when an element or layer is referred to as being "on" another element or layer, "above" another element or layer, "on" another element or layer, "connected" to another element or layer, or "attached" to another element or layer, it may be directly on, directly above, directly on, directly connected to, or directly attached to the other element or layer, or there may be intervening elements. In contrast, when an element is referred to as "directly on" another element or layer, "directly above" another element or layer, "directly on" another element or layer, "directly connected" to another element or layer, or "directly linked to" another element or layer, there is no intermediate element or layer. Throughout the text, the same numbers refer to the same element.

[0024] Figure 1 This is a block diagram illustrating an example of a solid-state drive system according to an embodiment.

[0025] Reference Figure 1 The solid-state drive system 1000a may include a host 1100 and a solid-state drive device 1200.

[0026] The solid-state drive device 1200 may include a plurality of non-volatile memory (NVM) packages 100-1 to 100-n, including a first NVM package 100-1, a second NVM package 100-2 to an nth NVM package 100-n. The plurality of NVM packages may be used as storage media of the solid-state drive device 1200.

[0027] Each of the plurality of non-volatile memory packages 100-1 to 100-n according to the embodiments may include a plurality of non-volatile memory chips. Each of the plurality of non-volatile memory chips may include a flash memory device.

[0028] The controller 200 can be connected to each of the plurality of non-volatile memory packages 100-1 to 100-n via multiple channels CH1, CH2 to CHn. According to an embodiment, each of the plurality of non-volatile memory packages 100-1 to 100-n can be connected to the controller 200 via a single channel.

[0029] The controller 200 can send and receive control signals SGL to and from the host 1100 via signal connector 210. The control signals SGL may include commands, addresses, and / or data. Depending on the commands from the host 1100, the controller 200 can write data to or read data from the plurality of non-volatile memory packages 100-1 to 100-n.

[0030] The solid-state drive device 1200 may also include an auxiliary power supply 300. The auxiliary power supply 300 receives power input from the host 1100 via a power connector 310 and supplies power to the controller 200. The location of the auxiliary power supply 300 is not limited thereto; in some embodiments, the auxiliary power supply 300 may also be located outside the solid-state drive device 1200.

[0031] Figure 2 This is a diagram illustrating an example of a solid-state drive device according to an embodiment. Figure 3 According to the implementation method Figure 2 A circuit diagram of an example buffer chip. Figure 4 This illustrates an embodiment. Figure 3 The circuit diagrams of the second and third receivers are shown in the example. For ease of illustration, the first non-volatile memory package 100-1 connected to the controller 200 via the first channel CH1 is described as an example.

[0032] Reference Figure 2 The solid-state drive device may include: a controller 200; buffer chips (BCs) that can send data to and receive data from the controller 200 via a first channel CH1, such as a first buffer chip 160-1 and a second buffer chip 160-2 in a buffer region 160; and a non-volatile memory region 110 that sends data to and receives data from the controller 200 via, for example, the buffer chips 160-1 and 160-2.

[0033] The first channel CH1 and the buffer chips (e.g., first buffer chip 160-1 and second buffer chip 160-2) can be electrically connected to each other through a first redistribution layer 104-1 formed in the substrate 102-1. In an embodiment, the first redistribution layer 104-1 may be, for example, a wiring layer. Specifically, a plurality of external connection terminals 170 may be disposed below the substrate 102-1. That is, in order to electrically connect the first redistribution layer 104-1 and the first channel CH1 to each other, the plurality of external connection terminals 170 may be electrically connected to the first channel CH1. However, for the sake of illustration, in Figure 2 Only one external connection terminal is shown connected to the first channel CH1.

[0034] In the following figures, although the plurality of external connection terminals 170 are shown as solder balls, the invention is not limited thereto. For example, the plurality of external connection terminals 170 may be solder bumps, grid arrays, conductive connectors, etc. Furthermore, the number of the plurality of external connection terminals 170 is not limited to the number shown in the figures.

[0035] The first connection pad 105-1 can be formed on the upper part of the substrate 102-1 opposite to the lower part of the substrate 102-1, and can be electrically connected to the first connection terminal 106-1 of the first buffer chip 160-1, for example, in the form of a flip chip. In order to electrically connect the second buffer chip 160-2 and the first redistribution layer 104-1 to each other, the first connection pad 105-1 can also be connected to the first lead 107-1.

[0036] The second redistribution layer 104-2 may be further disposed within the substrate 102-1. The second redistribution layer 104-2 may extend in the fourth direction IV and may pass through the region of the substrate 102-1 below the non-volatile memory region 110. The second redistribution layer 104-2 may be connected to a second connection pad 105-21 located on the substrate 102-1 and on one side of the non-volatile memory region 110 in the fourth direction IV. The first buffer chip 160-1 may be connected to the second connection pad 105-21 via a second connection terminal 106-21 connected to the first buffer chip 160-1, for example, in a flip-chip configuration. The second redistribution layer 104-2 may be electrically connected to a fifth connection pad 105-32 disposed on the substrate 102-1 and on one side of the non-volatile memory region 110 in the fourth direction IV. The fifth connection pad 105-32 may be electrically connected via a fourth lead 107-4 to the top region 114-1 of the second non-volatile memory chip, which will be described later. That is, the controller 200 and the top region 114-1 of the second non-volatile memory chip can send and receive data through the second redistribution layer 104-2.

[0037] The third redistribution layer 104-3 may be further disposed within the substrate 102-1. The third redistribution layer 104-3 may extend in the fourth direction IV and may pass through the region of the substrate 102-1 below the non-volatile memory region 110. The third redistribution layer 104-3 may be connected to a third connection pad 105-31 located on the substrate 102-1 and on one side of the non-volatile memory region 110 in the fourth direction IV. The first buffer chip 160-1 may be connected to the third connection pad 105-31 via a third connection terminal 106-31 connected to the first buffer chip 160-1, for example, in a flip-chip configuration. The third redistribution layer 104-3 may also be further electrically connected to a fourth connection pad 105-22 in the fourth direction IV of the non-volatile memory region 110. The fourth connection pad 105-22 may be electrically connected via a fifth lead 107-5 to the bottom region 114-2 of the second non-volatile memory chip, which will be described later. That is, the controller 200 and the bottom region 114-2 of the second non-volatile memory chip can send and receive data through the third redistribution layer 104-3.

[0038] The first redistribution layers 104-1 to the third redistribution layers 104-3 and the first to fifth connection pads 105-1, 105-21, 105-31, 105-22 and 105-32 may include conductive materials. For example, the first redistribution layers 104-1 to the third redistribution layers 104-3 and the first to fifth connection pads 105-1, 105-21, 105-31, 105-22 and 105-32 may include gold (Au), silver (Ag), copper (Cu), nickel (Ni) and / or aluminum (Al). Furthermore, the first connection terminal 106-1, the second connection terminal 106-21 and / or the third connection terminal 106-31 may be, for example, solder balls, solder bumps or combinations thereof.

[0039] The second buffer chip 160-2 can be stacked on top of the first buffer chip 160-1. The first buffer chip 160-1 and the second buffer chip 160-2 can form a buffer region 160. The second buffer chip 160-2 can be electrically connected to the top region 112-1 of the first non-volatile memory chip (described later) via a second lead 107-2. Furthermore, the second buffer chip 160-2 can be electrically connected to the bottom region 112-2 of the first non-volatile memory chip (described later) via a third lead 107-3. That is, the top region 112-1 and the bottom region 112-2 of the first non-volatile memory chip can send data to and receive data from the controller 200 via the second buffer chip 160-2.

[0040] Will pass Figure 3 and Figure 4 An example describing the first buffer chip 160-1 and the second buffer chip 160-2 in buffer region 160.

[0041] Reference Figure 2 and Figure 3 The second buffer chip 160-2 may include a first port 161, a second port 162, a third port 163, and control logic 164.

[0042] The first port 161 can send data to and receive data from the controller 200 via the first lead 107-1, the first connection pad 105-1, the first redistribution layer 104-1, the external connection terminal 170, and the first channel CH1. The second port 162 can send data to and receive data from the top region 112-1 of the first non-volatile memory chip via the second lead 107-2. The third port 163 can send data to and receive data from the bottom region 112-2 of the first non-volatile memory chip via the third lead 107-3.

[0043] Control logic 164 can provide data received from the first port 161 to the top region 112-1 of the first non-volatile memory chip through the second port 162, or can provide the data to the bottom region 112-2 of the first non-volatile memory chip through the third port 163.

[0044] Control logic 164 can provide data received from the top region 112-1 of the first non-volatile memory chip to the first port 161 through the second port 162. Furthermore, control logic 164 can provide data received from the bottom region 112-2 of the first non-volatile memory chip to the first port 161 through the third port 163.

[0045] According to one embodiment, the first port 161 may include a first receiver 161-1 that receives data from the controller 200, and a first driver 161-2 that provides data to the controller 200. According to another embodiment, the second port 162 may include a second receiver 162-2 that receives data from the top region 112-1 of the first non-volatile memory chip, and a second driver 162-1 that provides data from the control logic 164 to the top region 112-1 of the first non-volatile memory chip. According to another embodiment, the third port 163 may include a third receiver 163-2 that receives data from the bottom region 112-2 of the first non-volatile memory chip, and a third driver 163-1 that provides data to the bottom region 112-2 of the first non-volatile memory chip. The operating parameters of the first ports 161 to the third ports 163 according to another embodiment may be different from each other.

[0046] The first buffer chip 160-1 may have the same configuration as the second buffer chip 160-2. In the first buffer chip 160-1 according to an embodiment, the first port 161 and the first connection terminal 106-1 can be connected to each other to send and receive data between the controller 200 and the control logic 164. Furthermore, in the first buffer chip 160-1 according to an embodiment, the second port 162 and the second connection terminal 106-21 can be connected to each other to send and receive data between the control logic 164 and the top region 114-1 of the second non-volatile memory chip. Furthermore, in the first buffer chip 160-1 according to an embodiment, the third port 163 and the third connection terminal 106-31 can be connected to each other to send and receive data between the control logic 164 and the bottom region 114-2 of the second non-volatile memory chip. Because the detailed send / receive operations are the same as those of the second buffer chip 160-2, repeated descriptions will not be provided.

[0047] Reference Figure 3 and Figure 4 The second receiver 162-2 may include on-die terminating (ODT) resistors R1 and R2 connected between the power supply voltage VDD and the ground voltage GND. Similarly, the third receiver 163-2 may include on-die terminating resistors R3 and R4 connected between the power supply voltage VDD and the ground voltage GND. That is, the sizes of the on-die terminating resistors R1 and R2 of the second receiver 162-2 and the sizes of the on-die terminating resistors R3 and R4 of the third receiver 163-2 can be set independently of each other.

[0048] Refer again Figure 2 According to the embodiment, the non-volatile memory region 110 may include a first non-volatile memory region 111-1 and a second non-volatile memory region 111-2.

[0049] The first non-volatile memory region 111-1 according to the embodiment may include a plurality of first non-volatile memory chips 112. The second non-volatile memory region 111-2 according to the embodiment may include a plurality of second non-volatile memory chips 114.

[0050] The plurality of first non-volatile memory chips 112 and / or the plurality of second non-volatile memory chips 114 according to the embodiments may include NAND flash memory, vertical NAND flash memory (VNAND), NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), etc. Furthermore, the plurality of first non-volatile memory chips 112 and / or the plurality of second non-volatile memory chips 114 according to the embodiments may include a three-dimensional array structure.

[0051] According to the embodiment, the first non-volatile memory region 111-1 may include a bottom region 112-2 of the first non-volatile memory chip and a top region 112-1 of the first non-volatile memory chip disposed on the bottom region 112-2. The number and stacking configuration of the first non-volatile memory chips 112 in the first non-volatile memory region 111-1 are not limited to the arrangement shown in this figure. The bottom region 112-2 of the first non-volatile memory chip may include a plurality of first non-volatile memory chips 112 electrically connected to each other. The top region 112-1 of the first non-volatile memory chip may also include a plurality of first non-volatile memory chips 112 electrically connected to each other.

[0052] As described above, the top region 112-1 of the first non-volatile memory chip can be electrically connected to the second buffer chip 160-2 via the second lead 107-2, and the bottom region 112-2 of the first non-volatile memory chip can be electrically connected to the second buffer chip 160-2 via the third lead 107-3. In this embodiment, each of the top region 112-1 and the bottom region 112-2 of the first non-volatile memory chip can send data to and receive data from the controller 200.

[0053] The second non-volatile memory region 111-2 according to the embodiment may include a bottom region 114-2 of the second non-volatile memory chip and a top region 114-1 of the second non-volatile memory chip disposed on the bottom region 114-2. The number and stacking configuration of the second non-volatile memory chips 114 in the second non-volatile memory region 111-2 are not limited to the number and stacking configuration shown in this figure. The bottom region 114-2 of the second non-volatile memory chip may include a plurality of second non-volatile memory chips 114 electrically connected to each other. The top region 114-1 of the second non-volatile memory chip may also include a plurality of second non-volatile memory chips 114 electrically connected to each other.

[0054] As described above, the top region 114-1 of the second non-volatile memory chip can be electrically connected to the first buffer chip 160-1 via the fourth lead 107-4. The bottom region 114-2 of the second non-volatile memory chip can be electrically connected to the first buffer chip 160-1 via the fifth lead 107-5. In summary, each of the top region 114-1 and the bottom region 114-2 of the second non-volatile memory chip can send data to and receive data from the controller 200.

[0055] To increase the storage capacity of a solid-state drive device, the number of multiple non-volatile memory chips (e.g., multiple first non-volatile memory chips 112 or multiple second non-volatile memory chips 114) connected to the same channel (e.g., first channel CH1) can be increased. However, as the number of non-volatile memory chips connected to the same channel increases, the parasitic capacitance of the multiple non-volatile memory chips formed in the same channel may increase. Therefore, it is highly likely that signals sent from the controller 200 to the multiple non-volatile memory chips will be reflected and returned.

[0056] However, in the solid-state drive device according to the embodiment, the plurality of non-volatile memory chips connected to the same channel can be divided into multiple regions, such as a first non-volatile memory region 111-1 and a second non-volatile memory region 111-2, which are formed to be connected to the same channel but spaced apart from each other. Therefore, the phenomenon of signals transmitted from the controller 200 being reflected can be prevented or reduced.

[0057] Furthermore, for the stacked plurality of buffer chips, such as the first buffer chip 160-1 and the second buffer chip 160-2, some buffer chips (e.g., the first buffer chip 160-1) can send signals to and receive signals from the controller 200 in flip-chip form, while the remaining buffer chips (e.g., the second buffer chip 160-2) can send signals to and receive signals from the controller 200 in wire-bonded form, thereby reducing parasitic capacitance components that may impede signal integrity.

[0058] In the following text, repeated parts of the above description will be omitted.

[0059] Figure 5 According to the implementation method Figure 2 A top view of an example solid-state drive device. Figure 6 According to the implementation method Figure 5 A top view of an example of a buffer chip.

[0060] Reference Figure 5 Each of the first buffer chip 160-1 and the second buffer chip 160-2 includes a first buffer chip pad 169-1, a second buffer chip pad 169-2, and a third buffer chip pad 169-3, each containing multiple pads. The number and arrangement of the buffer chip pads are not limited to those shown in this figure. Furthermore, in an embodiment, each of the first lead 107-1 to the fifth lead 107-5 may be one of multiple leads, or may include multiple leads. Furthermore, in an embodiment, each of the first to fifth connection pads 105-1, 105-21, 105-31, 105-22, and 105-32 may be one of multiple connection pads, or may include multiple connection pads. Furthermore, in an embodiment, each of the first buffer chip pad 169-1 to the third buffer chip pad 169-3 may be one of multiple buffer chip pads, or may include multiple buffer chip pads.

[0061] The first buffer chip pad 169-1 can be electrically connected to the first connection pad 105-1 via the first lead 107-1.

[0062] Each of the plurality of first non-volatile memory chips 112 in the top region 112-1 of the first non-volatile memory chip may include a top pad 122-1 of the first non-volatile memory chip. Furthermore, each of the plurality of first non-volatile memory chips 112 in the bottom region 112-2 of the first non-volatile memory chip may include a bottom pad 122-2 of the first non-volatile memory chip.

[0063] Similarly, each of the plurality of second non-volatile memory chips 114 in the top region 114-1 of the second non-volatile memory chip may include a top pad 124-1. Furthermore, each of the plurality of second non-volatile memory chips 114 in the bottom region 114-2 of the second non-volatile memory chip may include a bottom pad 124-2. Pads belonging to the same group among each of the pads 122-1, 122-2, 124-1, and 124-2 according to the embodiment may be electrically connected to each other. The number and form of the aforementioned pads 122-1, 122-2, 124-1, and 124-2 are not limited to those shown in this figure. For example, in the embodiment, each of the pads 122-1, 122-2, 124-1, and 124-2 may be one of a plurality of pads, or may include a plurality of pads.

[0064] The top pad 122-1 of the first non-volatile memory chip can be electrically connected to the second buffer chip pad 169-2 via the second lead 107-2. The bottom pad 122-2 of the first non-volatile memory chip can be electrically connected to the third buffer chip pad 169-3 via the third lead 107-3. The top pad 124-1 of the second non-volatile memory chip can be electrically connected to the fifth connection pad 105-32 via the fourth lead 107-4. The bottom pad 124-2 of the second non-volatile memory chip can be electrically connected to the fourth connection pad 105-22 via the fifth lead 107-5.

[0065] The first buffer chip pad 169-1 to the third buffer chip pad 169-3 can be positioned in the center of the buffer chip. (Refer to...) Figure 6 A detailed description of an example is provided. For reference, although the second buffer chip 160-2 will be described as an example, the description of the second buffer chip 160-2 also applies to the first buffer chip 160-1.

[0066] Reference Figure 5 and Figure 6 The second buffer chip 160-2 can extend from the first point P1 in the fifth direction V and can be formed up to the fourth point P4. In this case, each of the first buffer chip pads 169-1 to the third buffer chip pads 169-3 can include a plurality of pads arranged in the fifth direction V from the second point P2 to the third point P3 of the second buffer chip 160-2. The spacing (e.g., spacing G1) between the plurality of pads included in the first buffer chip pads 169-1 to the third buffer chip pads 169-3 can be constant.

[0067] Furthermore, if the position from the first buffer chip pad 169-1 to the third buffer chip pad 169-3, which is closest to the first point P1, is set as the second point P2, then the distance from the first point P1 to the second point P2 can be set as the first distance. Furthermore, if the position from the first buffer chip pad 169-1 to the third buffer chip pad 169-3, which is closest to the fourth point P4, is set as the third point P3, then the distance from the fourth point P4 to the third point P3 can be set as the second distance.

[0068] According to the embodiment, the first distance D1 and the second distance D2 in the second buffer chip 160-2 can be identical to each other. That is, each of the first buffer chip pads 169-1 to the third buffer chip pads 169-3 can be arranged symmetrically about the second buffer chip 160-2 along the fifth direction V in which it extends, i.e., symmetrically about an axis in the fourth direction IV perpendicular to the fifth direction V. Therefore, since the first buffer chip 160-1, which can be formed by inverting the second buffer chip 160-2, can also have a symmetrical arrangement of the first buffer chip pads 169-1 to the third buffer chip pads 169-3, pad stubs that may appear in the first buffer chip 160-1 and / or the second buffer chip 160-2 can be eliminated.

[0069] Figure 7 This illustrates an embodiment. Figure 2 A diagram showing an example of a non-volatile memory region. Figure 8 This illustrates an embodiment. Figure 2 Another diagram showing an example of a non-volatile memory region.

[0070] Reference Figure 7 According to the embodiment, the non-volatile memory region 110 includes a first non-volatile memory region 111-1 and a second non-volatile memory region 111-2 disposed on the first non-volatile memory region 111-1.

[0071] That is, as in the implementation method Figure 2 Unlike the example non-volatile memory region 110 shown, the second non-volatile memory region 111-2 can be disposed on the first non-volatile memory region 111-1. According to the embodiment... Figure 7The stacking direction (e.g., third direction III) of the plurality of first non-volatile memory chips 112 in the first non-volatile memory region 111-1 of the non-volatile memory region 110 may intersect with the stacking direction (e.g., first direction I) of the plurality of second non-volatile memory chips 114 in the second non-volatile memory region 111-2. Because the plurality of non-volatile memory chips in the non-volatile memory region 110 may collapse when the stacking directions of the plurality of first non-volatile memory chips 112 and the plurality of second non-volatile memory chips 114 are the same, in this embodiment, the plurality of non-volatile memory chips can be stacked in different directions.

[0072] Because the electrical connection type of each non-volatile memory chip can be related to... Figure 2 Since the electrical connection types are the same, no description will be provided.

[0073] Reference Figure 8 ,and Figure 7 Different, depending on the implementation method, such as Figure 8 Each of the examples of the first non-volatile memory region 111-1 and the second non-volatile memory region 111-2 of the non-volatile memory region 110 shown may have the form of the plurality of non-volatile memory chips stacked in two different orientations.

[0074] The plurality of first non-volatile memory chips 112 in the bottom region 112-2 of the first non-volatile memory chip can be stacked in the third direction III. The plurality of first non-volatile memory chips 112 in the top region 112-1 of the first non-volatile memory chip can be stacked in the first direction I. The plurality of second non-volatile memory chips 114 in the bottom region 114-2 of the second non-volatile memory chip can be stacked in the third direction III. The plurality of second non-volatile memory chips 114 in the top region 114-1 of the second non-volatile memory chip can be stacked in the first direction I.

[0075] That is, in the implementation method, Figure 8 The arrangement of the plurality of non-volatile memory chips in the non-volatile memory region 110 can be compared to Figure 7 The arrangement is slightly more stable.

[0076] Figure 9 This is a diagram illustrating an example of a solid-state drive device according to an embodiment.

[0077] As a reference, with Figure 2 The difference lies in the fact that, except for the buffer region 160 being located between the first non-volatile memory region 111-1 and the second non-volatile memory region 111-2, Figure 9 Operation and connection types and Figure 2 The operation and connection types are the same, so no description will be provided.

[0078] Figure 10 This is a diagram illustrating an example of a solid-state drive device according to an embodiment.

[0079] Reference Figure 10 The support film 168 can be disposed between the first buffer chip 160-1 and the second buffer chip 160-2 in the buffer region 160. The support film 168 can be, for example, but not limited to, a die attachment film (DAF).

[0080] and Figure 2 Different, depending on the implementation method, such as Figure 10 The example of the first buffer chip 160-1 shown can be connected to the first connection pad 105-1 via wire bonding to be electrically connected to the first redistribution layer 104-1.

[0081] In detail, the first buffer chip 160-1 can be connected to the first connection pad 105-1 via the second lead 107-2, and can be electrically connected to the first non-volatile memory region 111-1 via the third lead 107-3, so as to send and receive data between the controller 200 and the first non-volatile memory region 111-1.

[0082] According to the implementation method Figure 10 The second non-volatile memory region 111-2 of the non-volatile memory region 110 can be disposed on the first non-volatile memory region 111-1, and a spacer can be disposed between the first non-volatile memory region 111-1 and the second non-volatile memory region 111-2. The spacer according to the embodiment can be a silicon material.

[0083] When the first non-volatile memory region 111-1 and the second non-volatile memory region 111-2 on the first non-volatile memory region 111-1 are stacked consecutively in the third direction III, the plurality of non-volatile memory chips (e.g., the first non-volatile memory chip 112 and / or the second non-volatile memory chip 114) may collapse. Therefore, spacers can be provided on the first non-volatile memory region 111-1, and the second non-volatile memory region 111-2 can be formed from a position further moved in the opposite direction of the fourth direction IV than the position of the first non-volatile memory chip 112 at the uppermost layer portion of the first non-volatile memory region 111-1 in the second direction II. This allows for improved stability of the plurality of non-volatile memory chips in the non-volatile memory region 110.

[0084] The spacer can be attached to the first non-volatile memory chip 112 and / or the second non-volatile memory chip 114 using an insulating adhesive. Furthermore, the spacer can be formed to be larger than the width of the first non-volatile memory chip 112 and / or the second non-volatile memory chip 114 in the fourth direction IV and / or in the fifth direction V, so that the second non-volatile memory region 111-2 can be stably formed.

[0085] The second non-volatile memory region 111-2 can be connected to the second buffer chip 160-2 via the fourth lead 107-4. The second buffer chip 160-2 can be connected to the first connection pad 105-1 via the first lead 107-1. Therefore, data can be sent and received between the controller 200 and the second non-volatile memory region 111-2 via the second buffer chip 160-2.

[0086] To increase the storage capacity of a solid-state drive device, the number of multiple non-volatile memory chips (e.g., multiple first non-volatile memory chips 112 or multiple second non-volatile memory chips 114) connected to the same channel (e.g., first channel CH1) can be increased. However, as the number of non-volatile memory chips connected to the same channel increases, the parasitic capacitance of the multiple non-volatile memory chips formed in the same channel may increase. Therefore, it is highly likely that signals sent from the controller 200 to the multiple non-volatile memory chips will be reflected and returned.

[0087] However, in the solid-state drive device according to the embodiment, the regions of the plurality of non-volatile memory chips connected to the same channel can be divided into, for example, a first non-volatile memory region 111-1 and a second non-volatile memory region 111-2, and can be configured to be connected to the same channel but spaced apart from each other. Therefore, the phenomenon of signals transmitted from the controller 200 being reflected can be prevented.

[0088] Furthermore, for the stacked plurality of buffer chips, such as the first buffer chip 160-1 and the second buffer chip 160-2, some buffer chips (e.g., the first buffer chip 160-1) can send signals to and receive signals from the controller 200 in flip-chip form, while the remaining buffer chips (e.g., the second buffer chip 160-2) can send signals to and receive signals from the controller 200 in wire-bonded form. This allows for the reduction of parasitic capacitance components that may impede signal integrity.

[0089] Figures 11 to 13 This illustrates a method for manufacturing according to an embodiment. Figure 2 A diagram illustrating an intermediate stage of an example method for a solid-state driver device.

[0090] Reference Figure 11 A first redistribution layer 104-1 to a third redistribution layer 104-3 can be formed in the substrate 102-1, and a plurality of external connection terminals 170 can be formed on the lower part (i.e., the lower surface) of the substrate 102-1. A first connection pad 105-1 connected to the first redistribution layer 104-1, a second connection pad 105-21 and a fifth connection pad 105-32 connected to the second redistribution layer 104-2, and a third connection pad 105-31 and a fourth connection pad 105-22 connected to the third redistribution layer 104-3 can be formed on the upper part of the substrate 102-1 opposite to the lower part. A first connection terminal 106-1 can be formed on the first connection pad 105-1, a second connection terminal 106-21 can be formed on the second connection pad 105-21, and a third connection terminal 106-31 can be formed on the third connection pad 105-31.

[0091] Next, refer to Figure 12 The first buffer chip 160-1 and the second buffer chip 160-2 can be stacked sequentially on the first connection terminal 106-1 to the third connection terminal 106-31 to form a buffer region 160.

[0092] In addition, refer to Figure 13 A non-volatile memory region 110 can be formed on the substrate 102-1. Although only the method for manufacturing according to an embodiment has been described... Figure 2 This method applies to solid-state drives, but it is equally applicable to the other examples. For ease of explanation, descriptions of other implementations will be omitted.

[0093] Figure 14 This is an exemplary block diagram illustrating a solid-state drive system according to an embodiment.

[0094] Reference Figure 14 The solid-state drive system 1000b includes a host 1100 and a solid-state drive device 1200. The solid-state drive device 1200 may include a plurality of non-volatile memory packages 100-1 to 100-n. The plurality of non-volatile memory packages 100-1 to 100-n may be used as storage media of the solid-state drive device 1200.

[0095] Each of the plurality of non-volatile memory packages 100-1 to 100-n according to the embodiments may include a plurality of non-volatile memory chips. The plurality of non-volatile memory chips may include, but are not limited to, flash memory devices.

[0096] The controller 200 can be connected to multiple non-volatile memory packages 100-1 to 100-n via multiple channels CH1, CH2, CH3, CH4, ..., CH(2n-1) and CH2n, where n is an integer greater than or equal to 3. (Except according to the embodiment...) Figure 1 Each of the plurality of non-volatile memory packages 100-1 to 100-n included in the solid-state drive device 1200 can be connected to the controller 200 via a channel, according to an embodiment. Figure 14 Each of the plurality of non-volatile memory packages 100-1 to 100-n included in the solid-state drive device 1200 can be connected to a controller 200 via two channels, and the solid-state drive device 1200 can be connected to... Figure 1 The example shown is the same. Therefore, repeated parts of the above description will be omitted. In the following text, the internal configuration of the non-volatile memory region will be omitted to utilize the space in the accompanying drawings.

[0097] Figures 15 to 22 This is a block diagram illustrating an example of a solid-state drive device according to an embodiment.

[0098] Reference Figure 15 and Figure 16 According to the embodiments, the solid-state drive device may include an upper first non-volatile memory package 100-1a connected to a first channel CH1 and a lower first non-volatile memory package 100-1b connected to a second channel CH2.

[0099] That is, the upper first non-volatile memory package 100-1a can send data to and receive data from the controller 200 through the first channel CH1, and the lower first non-volatile memory package 100-1b can send data to and receive data from the controller 200 through the second channel CH2.

[0100] In the implementation, Figures 15 to 18 The lower first non-volatile memory package 100-1b may include a lower substrate 102-1a, a lower external connection terminal 170a, lower first to third redistribution layers 104-1a to 104-3a, lower first to fifth connection pads 105-1a, 105-21a, 105-31a, 105-22a and 105-32a, lower first to fifth leads 107-1a, 107-2a, 107-3a, 107-4a and 107-5a, and lower first to third connection terminals 106-1a, 106-21a and 106-31a.

[0101] exist Figure 15 and Figure 16In the illustrated embodiment, the buffer region 160 and / or the lower buffer region 160a may have the same characteristics as... Figure 2 The configuration of buffer region 160 is the same. Non-volatile memory region 110 and / or lower non-volatile memory region 110a can be with... Figure 2 Non-volatile memory region 110 Figure 7 Non-volatile memory region 110 or Figure 8 The non-volatile memory region 110 is the same. For example... Figure 15 and Figure 16 As shown, the substrate side of the first and second buffer chips in buffer region 160 and the plurality of first non-volatile memory chips in non-volatile memory region 110 can face the lower substrate side of the lower first and second buffer chips in lower buffer region 160a and the plurality of lower first non-volatile memory chips in lower non-volatile memory region 110a. Here, substrate side refers to the side closer to substrate 102-1, and lower substrate side refers to the side closer to lower substrate 102-1a.

[0102] Reference Figure 17 and Figure 18 The solid-state drive device includes an upper first non-volatile memory package 100-1a connected to a first channel CH1 and a lower first non-volatile memory package 100-1b connected to a second channel CH2.

[0103] That is, the upper first non-volatile memory package 100-1a can send data to and receive data from the controller 200 through the first channel CH1, and the lower first non-volatile memory package 100-1b can send data to and receive data from the controller 200 through the second channel CH2.

[0104] Buffer region 160 and / or lower buffer region 160a may have the same Figure 10 The configuration of buffer region 160 is the same. Non-volatile memory region 110 and / or lower non-volatile memory region 110a can be with... Figure 10 The non-volatile memory region 110 is the same. For example... Figure 17 and Figure 18 As shown, the substrate side of the first buffer chip, the support film and the second buffer chip of the buffer region 160 and the plurality of first non-volatile memory chips of the non-volatile memory region 110 can face the lower substrate side of the lower first buffer chip, the lower support film and the lower second buffer chip of the buffer region 160a and the plurality of lower first non-volatile memory chips of the lower non-volatile memory region 110a.

[0105] Reference Figure 19 and Figure 20 The solid-state drive device may include a left-side first non-volatile memory package 100-1c connected to a first channel CH1 and a right-side first non-volatile memory package 100-1d connected to a second channel CH2.

[0106] That is, the left-side first non-volatile memory package 100-1c can send data to and receive data from the controller 200 through the first channel CH1, and the right-side first non-volatile memory package 100-1d can send data to and receive data from the controller 200 through the second channel CH2.

[0107] In the implementation, Figures 19 to 22 The right-side first non-volatile memory package 100-1b may include the right-side portion of the substrate 102-1, the right-side portion of the external connection terminal 170, the right-side first to third redistribution layers 104-1b to 104-3b, the right-side first to fifth connection pads 105-1b, 105-21b, 105-31b, 105-22b and 105-32b, the right-side first to fifth leads 107-1b, 107-2b, 107-3b, 107-4b and 107-5b, and the right-side first to third connection terminals 106-1b, 106-21b and 106-31a.

[0108] exist Figure 19 and Figure 20 In the illustrated embodiment, the left buffer region 160 and / or the right buffer region 160b may have the same characteristics as... Figure 10 The configuration of buffer region 160 is the same. The left non-volatile memory region 110 and / or the right non-volatile memory region 110b can be configured with... Figure 10 The non-volatile memory region 110 is the same.

[0109] Reference Figure 21 and Figure 22 According to the embodiments, the solid-state drive device may include a left-side first non-volatile memory package 100-1c connected to a first channel CH1 and a right-side first non-volatile memory package 100-1d connected to a second channel CH2.

[0110] That is, the left-side first non-volatile memory package 100-1c can send data to and receive data from the controller 200 through the first channel CH1, and the right-side first non-volatile memory package 100-1d can send data to and receive data from the controller 200 through the second channel CH2.

[0111] The left buffer region 160 and / or the right buffer region 160b may have the same characteristics as... Figure 2 The configuration of buffer region 160 is the same. The left non-volatile memory region 110 and / or the right non-volatile memory region 110b can be configured with... Figure 2 Non-volatile memory region 110 Figure 7 Non-volatile memory region 110 Figure 8 Non-volatile memory region 110 or Figure 9 The non-volatile memory region 110 is the same.

[0112] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the disclosed embodiments of the invention are used only in a general and descriptive sense and not for limiting purposes.

[0113] This application is based on and claims priority to Korean Patent Application No. 10-2019-0116505, filed on September 23, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A solid-state drive device, comprising: substrate; A first buffer chip is disposed on the substrate; The second buffer chip is disposed on the first buffer chip; Multiple first non-volatile memory chips are connected to the second buffer chip via wire bonding; The controller is configured to send control signals to the plurality of first non-volatile memory chips via a first channel; as well as A first redistribution layer is disposed in the substrate and configured to electrically connect the first channel to the first buffer chip. The first buffer chip is connected to the first redistribution layer via flip-chip bonding, and the second buffer chip is connected to the first redistribution layer via a first lead.

2. The solid-state drive device of claim 1, wherein the plurality of first non-volatile memory chips includes a bottom region of the first non-volatile memory chips and a top region of the first non-volatile memory chips disposed on the bottom region of the first non-volatile memory chips; and The top region of the first non-volatile memory chip is connected to the second buffer chip via a second lead, and the bottom region of the first non-volatile memory chip is connected to the second buffer chip via a third lead.

3. The solid-state driver device according to claim 1, further comprising: A second redistribution layer is disposed in the substrate and connected to the first buffer chip by flip-chip bonding; as well as Multiple second non-volatile memory chips are connected to the second redistribution layer via wire bonding.

4. The solid-state driver device according to claim 3, further comprising: A third redistribution layer is disposed in the substrate and connected to the first buffer chip via flip-chip bonding. The plurality of second non-volatile memory chips include a bottom region of the second non-volatile memory chip and a top region of the second non-volatile memory chip disposed on the bottom region of the second non-volatile memory chip, and The top region of the second non-volatile memory chip is connected to the second redistribution layer via a fourth lead, and the bottom region of the second non-volatile memory chip is connected to the third redistribution layer via a fifth lead.

5. The solid-state drive device according to claim 3, wherein the first buffer chip and the second buffer chip are disposed between the plurality of first non-volatile memory chips and the plurality of second non-volatile memory chips.

6. The solid-state driver device of claim 1, further comprising: Multiple second non-volatile memory chips are disposed on the multiple first non-volatile memory chips; as well as A second redistribution layer is disposed in the substrate and connected to the first buffer chip via flip-chip bonding. The plurality of second non-volatile memory chips are connected to the second redistribution layer by wire bonding.

7. The solid-state drive device of claim 6, wherein the plurality of first non-volatile memory chips are arranged continuously in a first direction, and the plurality of second non-volatile memory chips are arranged continuously in a second direction intersecting the first direction.

8. The solid-state driver device of claim 6, further comprising: A third redistribution layer is disposed in the substrate and connected to the first buffer chip via flip-chip bonding. The plurality of first non-volatile memory chips include a bottom region of the first non-volatile memory chips continuously disposed in a first direction, and a top region of the first non-volatile memory chips disposed on the bottom region of the first non-volatile memory chips and continuously disposed in a second direction intersecting the first direction. The plurality of second non-volatile memory chips include a bottom region of second non-volatile memory chips continuously disposed in the first direction, and a top region of second non-volatile memory chips disposed on the bottom region of the second non-volatile memory chips and continuously disposed in the second direction. The top region of the first non-volatile memory chip is connected to the second buffer chip via a second lead. The bottom region of the first non-volatile memory chip is connected to the second buffer chip via a third lead. The top region of the second non-volatile memory chip is connected to the second redistribution layer via a fourth lead, and The bottom region of the second non-volatile memory chip is connected to the third redistribution layer via a fifth lead.

9. The solid-state driver device of claim 1, further comprising: lower base plate; The lower first buffer chip is disposed on the lower substrate; The lower second buffer chip is disposed on the lower first buffer chip; Multiple lower first non-volatile memory chips are connected to the lower second buffer chip via wire bonding; The second channel is configured to send the control signal to the plurality of lower first non-volatile memory chips; as well as The lower first redistribution layer is configured to electrically connect the second channel and the lower first buffer chip. The lower first buffer chip is connected to the lower first redistribution layer via flip-chip bonding, and the lower second buffer chip is connected to the lower first redistribution layer via a lower first lead.

10. The solid-state driver device of claim 9, wherein the substrate sides of the first buffer chip, the second buffer chip, and the plurality of first non-volatile memory chips face the lower substrate sides of the lower first buffer chip, the lower second buffer chip, and the plurality of lower first non-volatile memory chips.

11. The solid-state driver device of claim 1, wherein the second buffer chip extends from the first point to the second point in a first direction. The second buffer chip includes a plurality of buffer chip pads arranged continuously in the first direction. The plurality of buffer chip pads are spaced apart at regular intervals. The minimum distance between the first point and the pads of the plurality of buffer chips is the first distance. The minimum distance between the second point and the plurality of buffer chip pads is the second distance. Wherein the first distance is equal to the second distance.

12. A solid-state drive device, comprising: The first buffer chip is mounted on the substrate; A support membrane is disposed on the first buffer chip; A second buffer chip is disposed on the support membrane; Multiple first non-volatile memory chips are connected to the first buffer chip via wire bonding; The first redistribution layer is connected to the first buffer chip and the second buffer chip by wire bonding; as well as The controller is configured to send control signals to the plurality of first non-volatile memory chips via a first channel electrically connected to the first redistribution layer.

13. The solid-state driver device of claim 12, wherein the support film comprises a die attachment film.

14. The solid-state driver device of claim 12, further comprising: Spacers are disposed on the plurality of first non-volatile memory chips; as well as Multiple second non-volatile memory chips are disposed on the spacer.

15. The solid-state driver device of claim 14, wherein the spacer comprises silicon.

16. The solid-state driver device of claim 14, wherein the plurality of first non-volatile memory chips and the plurality of second non-volatile memory chips are respectively disposed sequentially in a first direction.

17. The solid-state driver device of claim 12, further comprising: The lower first buffer chip is disposed on the lower substrate; The lower support membrane is disposed on the lower first buffer chip; The lower second buffer chip is disposed on the lower support membrane; Multiple lower first non-volatile memory chips are connected to the lower second buffer chip via wire bonding; The lower first redistribution layer is connected to the lower first buffer chip and the lower second buffer chip by wire bonding; as well as The second channel is electrically connected to the lower first redistribution layer and configured to send the control signal to the plurality of lower first non-volatile memory chips.

18. The solid-state driver device of claim 17, wherein the substrate sides of the first buffer chip, the support film, the second buffer chip, and the plurality of first non-volatile memory chips face the lower substrate sides of the lower first buffer chip, the lower support film, the lower second buffer chip, and the plurality of lower first non-volatile memory chips.

19. A solid-state drive device, comprising: substrate; The first buffer chip is located on one side of the substrate; The second buffer chip is disposed on the first buffer chip; A first redistribution layer, a second redistribution layer, and a third redistribution layer are formed in the substrate and connected to the first buffer chip by flip-chip bonding, wherein the first redistribution layer is electrically connected to the first buffer chip via a first connection terminal, the second redistribution layer is electrically connected to the first buffer chip via a second connection terminal, and the third redistribution layer is electrically connected to the first buffer chip via a third connection terminal. A plurality of first non-volatile memory chips, including a bottom region of the first non-volatile memory chip and a top region of the first non-volatile memory chip, wherein the bottom region of the first non-volatile memory chip is connected to a second buffer chip via a first lead, and the top region of the first non-volatile memory chip is connected to the second buffer chip via a second lead and disposed on the bottom region of the first non-volatile memory chip; A controller, connected to the first redistribution layer, is configured to send control signals to the first buffer chip via a first channel; Multiple external connection terminals are connected to the first channel and are disposed on the opposite side of the substrate to the first side of the substrate; as well as A plurality of second non-volatile memory chips, including a bottom region of a second non-volatile memory chip and a top region of a second non-volatile memory chip, wherein the bottom region of the second non-volatile memory chip is connected to the third redistribution layer via a third lead, and the top region of the second non-volatile memory chip is connected to the second redistribution layer via a fourth lead and is disposed on the bottom region of the second non-volatile memory chip. The second buffer chip is electrically connected to the first redistribution layer via a fifth lead.

20. The solid-state drive device of claim 19, wherein the first buffer chip and the second buffer chip are disposed between the plurality of first non-volatile memory chips and the plurality of second non-volatile memory chips.

Images