Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate having a plurality of mutually separated core layers, and the top surface of the core layer having an isolation layer; forming a sacrificial layer on the substrate to expose the top surface of the isolation layer; after forming the sacrificial layer, removing the isolation layer; after removing the isolation layer, removing the sacrificial layer; after removing the sacrificial layer, forming a mask layer on the side wall surface of the core layer; after forming the mask layer, removing the core layer. The method can improve the uniformity of the spacing between adjacent mask layers, so that the performance of the formed semiconductor structure is better.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the rapid development of semiconductor technology, the feature size of semiconductor devices continues to shrink, making the integration of integrated circuits higher and higher, which also puts higher requirements on semiconductor manufacturing processes. Etching is an important process in semiconductor manufacturing. It is the process of transferring the pattern on the mask to the material layer. As the feature size continues to decrease, the etching process encounters a bottleneck due to the wavelength limit in the photolithography process, and it is unable to provide etching of smaller grooves.

[0003] In order to increase the integration density of semiconductor memory devices, many different methods are used in the prior art. Self-aligned multi-patterning technology is a solution that is widely accepted and applied in the process of preparing semiconductor devices. Currently, commonly used self-aligned multi-patterning technologies include self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). Self-aligned multi-patterning technology can prepare devices with smaller nodes under existing photolithography technology to provide smaller process fluctuations.

[0004] However, the existing self-aligned multiple patterning technology must introduce complex film layer stacking to achieve pattern transfer. When etching the film layer to form the target pattern on the semiconductor substrate, it is prone to poor graphic transfer quality and distortion of the target pattern, which has a negative impact on the robustness of the device.

[0005] Therefore, the performance of semiconductor structures formed using the existing self-aligned multi-patterning technology needs to be improved. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the uniformity of the distance between adjacent mask layers, so that the formed semiconductor structure has better performance.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate having a plurality of mutually discrete core layers, and the top surface of the core layer having an isolation layer; forming a sacrificial layer on the substrate to expose the top surface of the isolation layer; after forming the sacrificial layer, removing the isolation layer; after removing the isolation layer, removing the sacrificial layer; after removing the sacrificial layer, forming a mask layer on the side wall surface of the core layer; after forming the mask layer, removing the core layer.

[0008] Optionally, the material of the isolation layer includes silicon oxide, silicon nitride or silicon oxynitride.

[0009] Optionally, the method for forming the sacrificial layer includes: forming a sacrificial film on the substrate, the sacrificial film covering the top surface and side wall surface of the isolation layer; etching back the sacrificial film to form a sacrificial layer, and the top surface of the sacrificial layer is flush with or lower than the bottom surface of the isolation layer.

[0010] Optionally, the material of the sacrificial film includes: a photoresist material or an organic material containing carbon and oxygen.

[0011] Optionally, the method for forming the mask layer includes: forming a mask material layer on the surface of the substrate, and the mask material layer covers the top surface and side wall surface of the core layer; etching back the mask material layer until the substrate surface and the top surface of the core layer are exposed to form the mask layer.

[0012] Optionally, the material of the core layer includes: amorphous silicon, amorphous carbon or polycrystalline silicon.

[0013] Optionally, the method further includes: before forming the sacrificial layer, forming a first protective layer on the side wall surface of the core layer, wherein the material of the mask layer is different from that of the first protective layer; and after removing the core layer, removing the first protective layer.

[0014] Optionally, it also includes: after forming the mask layer and before removing the core layer, forming a second protective layer on the side wall surface of the mask layer, and the material of the second protective layer is different from that of the mask layer; after removing the core layer, removing the second protective layer.

[0015] Optionally, a first etching process is used to remove the first protective layer and the second protective layer; the etching rate of the first etching process on the first protective layer is greater than the etching rate of the mask layer, and the etching rate of the first etching process on the second protective layer is greater than the etching rate of the mask layer.

[0016] Optionally, the material of the first protective layer includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0017] Optionally, the thickness of the first protective layer ranges from 10 angstroms to 20 angstroms.

[0018] Optionally, the process for forming the first protective layer includes: an in-situ water vapor generation process, a chemical vapor deposition process or a physical vapor deposition process.

[0019] Optionally, the material of the second protective layer includes: silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0020] Optionally, the thickness of the second protective layer is greater than 20 angstroms and less than half of the distance between adjacent mask layers.

[0021] Optionally, the process for forming the second protective layer includes: a furnace process, a chemical vapor deposition process or a physical vapor deposition process.

[0022] Optionally, the method for removing the core layer includes: using a second etching process to remove the core layer; after removing the core layer, using a third etching process to remove etching byproducts generated during the second etching process.

[0023] Optionally, the second etching process is a dry etching process; and the third etching process is a wet etching process.

[0024] Optionally, the base includes a substrate and a hard mask layer located on a surface of the substrate.

[0025] Optionally, the method further includes: after removing the first protective layer and the second protective layer, etching the substrate using the mask layer as a mask.

[0026] Correspondingly, the technical solution of the present invention also provides a semiconductor structure formed by any of the above methods.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the isolation layer located on the top surface of the core layer is removed before the mask layer is formed, thereby avoiding etching damage to the mask layer caused by the etching process, which is conducive to the mask layer maintaining a good morphology. In addition, after removing the isolation layer, the sacrificial layer is removed, so that the process of removing the sacrificial layer is also completed before the mask layer is formed, thereby avoiding further etching damage to the mask layer caused by the etching process, which is further conducive to the mask layer maintaining a good morphology. Therefore, the uniformity of the distance between adjacent mask layers can be improved, so that the performance of the formed semiconductor structure is better.

[0029] Furthermore, since the mask layer is located on the side wall surface of the first protective layer, and the second protective layer is located on the side wall surface of the mask layer, that is, the first protective layer and the second protective layer are respectively located on both sides of the mask layer. Moreover, the material of the first protective layer is different from the material of the mask layer, and the material of the second protective layer is different from the material of the mask layer. Furthermore, in the process of removing the core layer, the first protective layer and the second protective layer can protect the side wall surface of the mask layer to avoid etching damage to the mask layer. At the same time, since the etching rate of the first etching process on the first protective layer is greater than the etching rate on the mask layer, and the etching rate of the first etching process on the second protective layer is greater than the etching rate on the mask layer, the first etching process can avoid etching damage to the mask layer in the process of removing the first protective layer and the second protective layer by using the first etching process. In summary, the method is conducive to improving the uniformity of the spacing between adjacent mask layers, and thus is conducive to improving the performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 6 It is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0031] Figures 7 to 17 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, the performance of existing semiconductor structures is poor.

[0033] The following is a detailed description of the reasons for the poor performance of the semiconductor structure with reference to the accompanying drawings. Figures 1 to 6 The present invention is a structural schematic diagram of each step of a semiconductor structure forming method.

[0034] Please refer to Figure 1 A substrate 100 is provided, on which a plurality of mutually independent core layers 110 are provided, and an isolation layer 120 is provided on the top surface of the core layer 110 .

[0035] Please refer to Figure 2 A mask material layer 130 is formed on the surface of the substrate 100, the top surface of the core layer 110, and the sidewall surface.

[0036] Please refer to Figure 3 , the mask material layer 130 is etched back until the surface of the substrate 100 and the top surface of the isolation layer 120 are exposed, and a mask layer 140 is formed on the side wall surface of the core layer 110 and the side wall surface of the isolation layer 120 .

[0037] Please refer to Figure 4A sacrificial film 150 is formed on the substrate 100 , and the sacrificial film 150 covers the sidewall surface of the mask layer 140 and the top surface and sidewall surface of the isolation layer 120 .

[0038] Please refer to Figure 5 , the sacrificial film 150 is etched back to form a sacrificial layer 160 , and the top surface of the sacrificial layer 160 is flush with the bottom surface of the isolation layer 120 .

[0039] Please refer to Figure 6 After forming the sacrificial layer 160 , the isolation layer 120 is removed; after removing the isolation layer 120 , the sacrificial layer 160 and the core layer 110 are removed.

[0040] In the above method, the process for forming the mask material layer 130 includes an atomic layer deposition process, and the use of the atomic layer deposition process is conducive to forming a thinner mask material layer 130, so that after the subsequent back etching process, the thickness of the mask layer 140 formed is thinner. Then, the substrate 100 is etched using the thinner mask layer 140 as a mask to achieve pattern transfer, which is conducive to forming semiconductor devices with shrinking feature sizes.

[0041] However, in the process of removing the isolation layer 120, not only the isolation layer 120 is etched at a certain rate, but the mask layer 140 is also etched at a certain rate, which will cause certain etching damage to the mask layer 140, resulting in poor morphology of the mask layer 140, which is not conducive to stable transfer of the pattern and makes the uniformity of the distance between adjacent mask layers poor.

[0042] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of mutually separated core layers, and the top surface of the core layer having an isolation layer; forming a sacrificial layer on the substrate to expose the top surface of the isolation layer; after forming the sacrificial layer, removing the isolation layer; after removing the isolation layer, removing the sacrificial layer; after removing the sacrificial layer, forming a mask layer on the side wall surface of the core layer; after forming the mask layer, removing the core layer. The method can improve the uniformity of the spacing between adjacent mask layers, so that the performance of the formed semiconductor structure is better.

[0043] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0044] Figures 7 to 17 It is a structural schematic diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0045] Please refer to Figure 7, providing a substrate 200, wherein the substrate 200 has a plurality of mutually separate core layers 210, and the top surface of the core layer 210 has an isolation layer 220.

[0046] In this embodiment, the base 200 includes a substrate 201 and a hard mask layer 202 located on a surface of the substrate 201 .

[0047] The material of the initial substrate 201 is a semiconductor material. In this embodiment, the material of the initial substrate 201 is silicon. In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP. The function of the hard mask layer is, on the one hand,

[0048] The material of the hard mask layer 202 includes silicon, silicon oxide, silicon nitride, titanium nitride, silicon oxynitride or silicon oxycarbide.

[0049] In this embodiment, the hard mask layer 202 is a stacked structure, and the hard mask layer 202 includes a first hard mask portion (not shown in the figure) located on the substrate and a second hard mask portion (not shown in the figure) located on the surface of the first hard mask portion, and the material of the first hard mask portion is nitrogen-doped silicon carbide, and the material of the second hard mask portion is silicon nitride.

[0050] In other embodiments, the hard mask layer may also be a single-layer structure.

[0051] The core layer 210 provides support for the subsequent formation of a mask layer.

[0052] The material of the core layer 210 includes: amorphous silicon, amorphous carbon or polycrystalline silicon.

[0053] In this embodiment, the material of the core layer 210 is amorphous silicon.

[0054] The material of the isolation layer 220 includes silicon oxide, silicon nitride or silicon oxynitride.

[0055] In this embodiment, the material of the isolation layer 220 is silicon oxide.

[0056] Please refer to Figure 8 , forming a first protective layer 230 on the side wall surface of the core layer 210 .

[0057] The first protection layer 230 is made of different materials from a mask layer to be formed subsequently, so as to protect the mask layer subsequently.

[0058] The material of the first protection layer 230 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0059] The thickness of the first protection layer 230 is in the range of 10 angstroms to 20 angstroms.

[0060] The significance of selecting the thickness range is that: if the thickness of the first protective layer 230 is less than 10 angstroms, the first protective layer 230 with a thickness that is too thin still cannot fully protect the mask layer during the subsequent removal of the core layer 210, and cannot effectively reduce the etching loss of the mask layer, so that the performance of the formed semiconductor structure is still relatively low; if the thickness of the first protective layer 230 is greater than 20 angstroms, while being able to fully protect the mask layer, on the one hand, forming a first protective layer 230 with a thickness that is too thick will increase the process cost and process time accordingly, and on the other hand, after the subsequent removal of the core layer 210, the time and cost of removing the first protective layer 230 will also increase accordingly, which is not conducive to improving efficiency and saving process costs.

[0061] In this embodiment, the thickness of the first protection layer 230 is 12 angstroms.

[0062] The process of forming the first protective layer 230 includes: an in-situ water vapor generation process, a chemical vapor deposition process or a physical vapor deposition process.

[0063] In this embodiment, the core layer 210 is oxidized by adopting the in-situ water vapor generation process. Since the material of the core layer 210 is amorphous silicon, the material of the formed first protective layer 230 is silicon oxide.

[0064] In this embodiment, the significance of using the in-situ water vapor generation process to form the first protective layer 230 is that, on the one hand, it is conducive to the generation of silicon oxide with higher density, so that the first protective layer 230 has higher density, which is beneficial to the subsequent protection of the mask layer; on the other hand, it is conducive to accurately controlling the thickness of the generated film layer, that is, it can generate a thinner first protective layer 230, reduce the impact on the thickness of the subsequent mask layer, and meet the process requirements.

[0065] Through the in-situ water vapor generation process, it is possible to form the thin first protective layer 230 only on the side wall surface of the core layer 210 without the need for further processing by other processes. Therefore, the steps are simple and easy to operate, thereby saving process time.

[0066] In this embodiment, the first protective layer is formed before the sacrificial layer is subsequently formed; in other embodiments, the first protective layer may not be formed before the sacrificial layer is subsequently formed.

[0067] Next, a sacrificial layer is formed on the substrate to expose the top surface of the isolation layer. For details on the process of forming the sacrificial layer, please refer to Figures 9 and 10 .

[0068] Please refer to Fig. 9 A sacrificial film 240 is formed on the substrate 200 , and the sacrificial film 240 covers the top surface and the sidewall surface of the isolation layer 220 .

[0069] The sacrificial film 240 provides material for subsequently forming a sacrificial layer.

[0070] In this embodiment, the top surface of the sacrificial film 240 is higher than the top surface of the isolation layer 220 .

[0071] The material of the sacrificial film 240 includes: a photoresist material or an organic material containing carbon and oxygen.

[0072] In this embodiment, the material of the sacrificial film 240 is an organic material containing carbon and oxygen; the process of forming the sacrificial film 240 is a spin coating process.

[0073] Please refer to Fig.10 , the sacrificial film 240 is etched back to form a sacrificial layer 241 , and the top surface of the sacrificial layer 241 is flush with or lower than the bottom surface of the isolation layer 220 .

[0074] In this embodiment, the top surface of the sacrificial layer 241 is flush with the bottom surface of the isolation layer 220 .

[0075] Since the sacrificial layer 241 is formed by etching back the sacrificial film 240 , the material of the sacrificial layer 241 includes: a photoresist material or an organic material containing carbon and oxygen.

[0076] In this embodiment, the material of the sacrificial layer 241 is an organic material containing carbon and oxygen.

[0077] The process of etching back the sacrificial film 240 includes: one of a wet etching process and a dry etching process or a combination of the two.

[0078] In this embodiment, the process of etching back the sacrificial film 240 is a dry etching process.

[0079] Please refer to Fig.11 After forming the sacrificial layer 241 , the isolation layer 220 is removed.

[0080] The process of removing the isolation layer 220 includes: a dry etching process and a wet etching process, or a combination of the two.

[0081] In this embodiment, the process for removing the isolation layer 220 is a dry etching process; the dry etching process parameters include: the etching gas used includes ammonia and hydrogen fluoride, wherein the volume ratio of ammonia to hydrogen fluoride is 100:80 to 100:100, and the temperature is 20 degrees Celsius to 45 degrees Celsius.

[0082] Due to the process of removing the isolation layer 220 located on the top surface of the core layer 210 before forming the mask layer, the etching process is prevented from causing etching damage to the mask layer formed subsequently, which is conducive to the mask layer maintaining a good morphology. Therefore, the uniformity of the distance between adjacent mask layers can be improved, so that the performance of the formed semiconductor structure is better.

[0083] In this embodiment, the sacrificial layer 241 covers the side wall surface of the first protective layer 230, thereby avoiding etching damage to the first protective layer 230 caused by the process of removing the isolation layer 220, which is beneficial to the morphology of the mask material layer subsequently formed on the side wall surface of the first protective layer 230.

[0084] Please refer to Fig.12 After removing the isolation layer 220 , the sacrificial layer 241 is removed.

[0085] The process of removing the sacrificial layer 241 includes: a dry etching process, a wet etching process or an ashing process.

[0086] In this embodiment, the material of the sacrificial layer 241 is an organic material containing carbon and oxygen, and an ashing process can be used to remove the sacrificial layer 241. The ashing process can easily completely remove the sacrificial layer 241 and is easy to operate, thereby saving process time.

[0087] After removing the isolation layer 220, the sacrificial layer 241 is removed, so that the process of removing the sacrificial layer 241 is also completed before the subsequent formation of the mask layer, thereby avoiding further etching damage to the mask layer by the etching process, which is further conducive to the mask layer maintaining a good morphology. Therefore, the uniformity of the distance between adjacent mask layers can be improved, so that the performance of the formed semiconductor structure is better.

[0088] After removing the sacrificial layer, a mask layer is formed on the sidewall surface of the core layer. For the specific process of forming the mask layer, please refer to Figure 13 to Figure 14 .

[0089] Please refer to Fig.13 A mask material layer 250 is formed on the surface of the substrate 200 , and the mask material layer 250 covers the top surface and the side wall surface of the core layer 210 .

[0090] The mask material layer 250 provides material for subsequently forming a mask layer.

[0091] In this embodiment, the mask material layer 250 is located on the sidewall surface and the top surface of the first protection layer 230 , and the top surface of the core layer 210 .

[0092] The material of the mask material layer 250 is different from the material of the first protection layer 230 .

[0093] The material of the mask material layer 250 includes titanium nitride, silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0094] In this embodiment, the mask material layer 250 is made of silicon nitride.

[0095] The process of forming the mask material layer 250 includes: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0096] In this embodiment, the process for forming the mask material layer 250 is an atomic layer deposition process. The atomic layer deposition process is a process of depositing at a thickness of an atomic mass, and has good step coverage, so that the thickness uniformity of the formed mask material layer 250 is good, and thus the thickness uniformity of the mask layer formed subsequently is good, which is conducive to improving the uniformity of the distance between adjacent mask layers, and further conducive to improving the performance of the formed semiconductor structure.

[0097] Please refer to Fig.14 , the mask material layer 250 is etched back until the surface of the substrate 200 and the top surface of the core layer 210 are exposed, thereby forming the mask layer 260 .

[0098] The mask layer 260 is used as a mask for subsequent etching of the substrate 200 to achieve pattern transfer.

[0099] In this embodiment, the mask layer 260 is located on the sidewall surface of the first protection layer 230 on the sidewall surface of the core layer 210 .

[0100] Since the mask layer 260 is formed by etching back the mask material layer 250 , correspondingly, the material of the mask layer 260 includes: titanium nitride, silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

[0101] In this embodiment, the material of the mask layer 260 is silicon nitride.

[0102] Please refer to Fig.15 After the mask layer 260 is formed, a second protective layer 270 is formed on the sidewall surface of the mask layer 260 , and the material of the second protective layer 270 is different from that of the mask layer 260 .

[0103] In this embodiment, the second protection layer 270 is also located on the surface of the substrate 200 , the top surface of the core layer 210 , the top surface of the first protection layer 230 , and the top surface of the mask layer 260 .

[0104] The material of the second protection layer 270 includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

[0105] The thickness of the second protection layer 270 is greater than 20 angstroms and less than half of the distance between adjacent mask layers 260 .

[0106] The significance of selecting the thickness range is that: if the thickness of the second protective layer 270 is less than 20 angstroms, the second protective layer 270 with a thickness that is too thin still cannot fully protect the mask layer 260 during the subsequent removal of the core layer, and cannot effectively reduce the etching loss of the mask layer 260, so that the performance of the formed semiconductor structure is still low; if the thickness of the second protective layer 270 is greater than one-half of the spacing between adjacent mask layers 260, while being able to fully protect the mask layer 260, on the one hand, in the process of forming the second protective layer 270, adjacent second protective layers 270 are easily merged together, which is not conducive to the subsequent removal of the merged second protective layers 270, thereby affecting the accuracy of pattern transfer using the mask layer 260 as a mask; on the other hand, forming a second protective layer 270 with a thickness that is too thick will increase the process cost and process time accordingly, and is therefore not conducive to improving efficiency and saving process costs.

[0107] The process of forming the second protection layer 270 includes: a furnace process, a chemical vapor deposition process or a physical vapor deposition process.

[0108] In this embodiment, the process for forming the second protective layer 270 is a furnace tube process. The second protective layer 270 formed by the furnace tube process can be easily removed later.

[0109] In this embodiment, the material of the second protective layer 270 is the same as that of the first protective layer 230 , so that the subsequent etching process can easily remove the first protective layer 230 and the second protective layer 270 at the same time, thereby saving process steps.

[0110] Please refer to Fig.16 , forming the second protection layer 270 , and removing the core layer 210 .

[0111] Since the mask layer 260 is located on the side wall surface of the first protective layer 230, and the second protective layer 270 is located on the side wall surface of the mask layer 260, that is, the first protective layer 230 and the second protective layer 270 are respectively located on both sides of the mask layer 260. In addition, the material of the first protective layer 230 is different from that of the mask layer 260, and the material of the second protective layer 270 is different from that of the mask layer 260. Furthermore, in the process of removing the core layer 210, the first protective layer 230 and the second protective layer 270 can protect the side wall surface of the mask layer 260 to avoid etching damage to the mask layer 260, thereby facilitating the improvement of the uniformity of the spacing between adjacent mask layers 260, and further facilitating the improvement of the performance of the formed semiconductor structure.

[0112] The method for removing the core layer 210 includes: using a second etching process to remove the core layer 210; after removing the core layer 210, using a third etching process to remove etching byproducts generated during the second etching process.

[0113] In this embodiment, the second etching process further etches the second protection layer 270 located on the top surface of the core layer 210 , thereby exposing the top surface of the core layer 210 .

[0114] The second etching process is a dry etching process; and the third etching process is a wet etching process.

[0115] Please refer to Fig.17 , using a first etching process to remove the first protective layer 230 and the second protective layer 270.

[0116] The etching rate of the first etching process on the first protective layer 230 is greater than the etching rate of the mask layer 260, and the etching rate of the first etching process on the second protective layer 270 is greater than the etching rate of the mask layer 260, so that when the first etching process is used to remove the first protective layer 230 and the second protective layer 270, etching damage to the mask layer 260 can be avoided. Therefore, it is beneficial to improve the uniformity of the distance between adjacent mask layers 260, and further to improve the performance of the formed semiconductor structure.

[0117] The first etching process includes: one of a dry etching process and a wet etching process, or a combination of the two.

[0118] In this embodiment, the first etching process is a wet etching process; the parameters of the first etching process include: the etching solution used is a mixed solution of dilute hydrofluoric acid and ozone water, wherein the volume ratio of hydrofluoric acid to water in the dilute hydrofluoric acid is 200:1, the concentration of ozone in the ozone water is 30ppm, and the volume mixing range of dilute hydrofluoric acid and ozone water is 1:3 to 1:5.

[0119] In this embodiment, after removing the first protective layer 230 and the second protective layer 270 , the method further includes: using the mask layer 260 as a mask to etch the substrate 200 , thereby achieving pattern transfer.

[0120] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method.

[0121] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of mutually separate core layers, and the top surface of the core layer has an isolation layer; forming a sacrificial layer on the substrate to expose the top surface of the isolation layer; After forming the sacrificial layer, removing the isolation layer; After removing the isolation layer, removing the sacrificial layer; After removing the sacrificial layer, forming a mask layer on the side wall surface of the core layer; After forming the mask layer, removing the core layer; After forming the mask layer and before removing the core layer, a second protective layer is formed on the side wall surface of the mask layer, and the material of the second protective layer is different from that of the mask layer; after removing the core layer, the second protective layer is removed.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the isolation layer includes silicon oxide, silicon nitride or silicon oxynitride.

3. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the sacrificial layer comprises: forming a sacrificial film on the substrate, the sacrificial film covering the top surface and side wall surface of the isolation layer; etching back the sacrificial film to form a sacrificial layer, wherein the top surface of the sacrificial layer is flush with or lower than the bottom surface of the isolation layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The material of the sacrificial film includes: a photoresist material or an organic material containing carbon and oxygen.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the mask layer includes: forming a mask material layer on the surface of the substrate, and the mask material layer covers the top surface and side wall surface of the core layer; etching back the mask material layer until the substrate surface and the top surface of the core layer are exposed to form the mask layer.

6. The method for forming a semiconductor structure according to claim 1, wherein: The material of the core layer includes: amorphous silicon, amorphous carbon or polycrystalline silicon.

7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the sacrificial layer, forming a first protective layer on the side wall surface of the core layer, and the material of the mask layer is different from that of the first protective layer; After removing the core layer, the first protective layer is removed.

8. The method for forming a semiconductor structure according to claim 7, wherein: The first protective layer and the second protective layer are removed by a first etching process; the etching rate of the first etching process on the first protective layer is greater than the etching rate on the mask layer, and the etching rate of the first etching process on the second protective layer is greater than the etching rate on the mask layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: The material of the first protective layer includes silicon oxide, silicon nitride, silicon carbide nitride, silicon boron nitride, silicon carbon nitride oxide or silicon nitride oxide.

10. The method for forming a semiconductor structure according to claim 7, wherein: The thickness of the first protective layer ranges from 10 angstroms to 20 angstroms.

11. The method for forming a semiconductor structure according to claim 7, wherein: The process of forming the first protective layer includes: an in-situ water vapor generation process, a chemical vapor deposition process or a physical vapor deposition process.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second protective layer includes silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon carbonitride oxide or silicon nitride oxide.

13. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the second protection layer is greater than 20 angstroms and less than half of the distance between adjacent mask layers.

14. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the second protective layer includes: a furnace process, a chemical vapor deposition process or a physical vapor deposition process.

15. The method for forming a semiconductor structure according to claim 1, wherein: The method for removing the core layer comprises: using a second etching process to remove the core layer; after removing the core layer, using a third etching process to remove etching byproducts generated during the second etching process.

16. The method for forming a semiconductor structure according to claim 15, wherein: The second etching process is a dry etching process; and the third etching process is a wet etching process.

17. The method for forming a semiconductor structure according to claim 7, wherein: The base comprises a substrate and a hard mask layer located on the surface of the substrate.

18. The method for forming a semiconductor structure according to claim 17, wherein: Also includes: After removing the first protective layer and the second protective layer, the substrate is etched using the mask layer as a mask.

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