Three-dimensional semiconductor memory device

Abstract

Disclosed is a three-dimensional semiconductor memory device, which includes: a substrate including a cell array region and a connection region; a stack including a first stack and a second stack sequentially stacked on the substrate, the stack having a stepped structure on a stack connection region, and each of the first stack and the second stack includes conductive patterns vertically stacked on the substrate; and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. The bottom surface of each contact plug is located between the top surface and the bottom surface of the corresponding conductive pattern. In each stack, when measured from the top surface of the corresponding conductive pattern, the recess depth of each contact plug monotonically changes in the stacking direction of the conductive patterns. The contact plugs coupled to the uppermost conductive pattern of the first stack and the lowermost conductive pattern of the second stack have discrete recess depths.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the priority of Korean Patent Application No. 10 - 2019 - 0119075, filed with the Korean Intellectual Property Office on September 26, 2019, the entire content of which is incorporated herein by reference. Technical field

[0003] The present inventive concept relates to a three - dimensional semiconductor memory device, and more particularly, to a three - dimensional semiconductor memory device having high reliability and high integration density. Background art

[0004] There is a desire / need for semiconductor devices with higher integration to meet consumers' demands for excellent performance and / or low prices. In the case of semiconductor devices, since their integration density is an important factor in determining the product price, increasing the integration density is particularly desired / needed. Accordingly, three - dimensional semiconductor memory devices including three - dimensionally arranged memory cells have been proposed recently. Summary of the invention

[0005] Some example embodiments of the present inventive concept provide a three - dimensional semiconductor memory device having improved reliability.

[0006] According to some example embodiments of the present inventive concept, a three - dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region; a stack including a first stack and a second stack, the first stack and the second stack being sequentially stacked on the substrate, the stack having a stepped structure on the connection region, a plurality of steps of the stepped structure decreasing in a first direction, each of the first stack and the second stack including conductive patterns vertically stacked on the substrate; and contact plugs on the connection region and respectively coupled to the conductive patterns of the first stack and the second stack. A bottom surface of each contact plug is between a top surface and a bottom surface of a corresponding one of the conductive patterns. In the first stack, a depression depth of adjacent contact plugs monotonically varies in the first direction, the depression depth being measured from the top surface of a corresponding one of the conductive patterns. In the second stack, a depression depth of adjacent contact plugs monotonically varies in the first direction, the depression depth being measured from the top surface of a corresponding one of the conductive patterns. The depression depth changes to have a bend between contact plugs adjacent to each other in the first stack and the second stack.

[0007] According to some example embodiments of the inventive concept, a three-dimensional semiconductor memory device includes: a substrate including a cell array region and a connection region; a stack including a first stack and a second stack sequentially stacked on the substrate, the stack having a stepped structure on the connection region, each of the first stack and the second stack including insulating patterns and conductive patterns vertically and alternately stacked on the substrate; a planarization insulating layer covering the stepped structure of the stack and having a substantially flat top surface, a portion of the insulating pattern being in direct contact with the planarization insulating layer; first contact plugs on the connection region and penetrating the planarization insulating layer and respectively coupled to the conductive patterns of the first stack; and second contact plugs on the connection region and respectively coupled to the conductive patterns of the second stack. A bottom surface of each of the first contact plugs and the second contact plugs is located between a top surface and a bottom surface of a corresponding one of the conductive patterns. A recess depth of each of the first contact plugs monotonically varies in a stacking direction of the conductive patterns, the recess depth being measured from a top surface of a corresponding one of the conductive patterns of the first stack. A recess depth of each of the second contact plugs monotonically varies in a stacking direction of the conductive patterns, the recess depth being measured from a top surface of a corresponding one of the conductive patterns of the second stack. A change in the recess depth of adjacent contact plugs among the first contact plugs and the second contact plugs has a bend, the recess depth of the adjacent contact plugs among the first contact plugs and the second contact plugs being measured from a top surface of a corresponding one of the conductive patterns.

[0008] According to some example embodiments of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region; a stack including a first stack, a second stack, and a third stack sequentially stacked on the substrate, the stack having a stepped structure on the connection region, each of the first stack, the second stack, and the third stack including insulating patterns and conductive patterns vertically and alternately stacked on the substrate; contact plugs respectively connected to the conductive patterns of the stack. A bottom surface of each contact plug is between a top surface and a bottom surface of a corresponding one of the conductive patterns. The contact plugs include: a first contact plug coupled to the uppermost conductive pattern of the first stack; a second contact plug coupled to the lowermost conductive pattern of the first stack; a third contact plug coupled to the uppermost conductive pattern of the second stack; a fourth contact plug coupled to the lowermost conductive pattern of the second stack; a fifth contact plug coupled to the uppermost conductive pattern of the third stack; and a sixth contact plug coupled to the lowermost conductive pattern of the third stack. A difference between recess depths of bottom surfaces of the third contact plug and the fourth contact plug is less than a difference between recess depths of bottom surfaces of the first contact plug and the second contact plug or a difference between recess depths of bottom surfaces of the fifth contact plug and the sixth contact plug, wherein each recess depth is measured from a top surface of a corresponding one of the conductive patterns.

[0009] According to some example embodiments of the inventive concept, a three-dimensional semiconductor memory device may include: a substrate including a cell array region and a connection region; a stack including a first stack and a second stack sequentially stacked on the substrate, the stack having a stepped structure on the connection region, each of the first stack and the second stack including insulating patterns and conductive patterns vertically and alternately stacked on the substrate; contact plugs respectively connected to the conductive patterns of the stack. A bottom surface of each contact plug is between a top surface and a bottom surface of a corresponding one of the conductive patterns, a recess depth of each contact plug is defined by a difference between the top surface of the conductive pattern and the bottom surface of the contact plug, and the contact plugs include: a first contact plug coupled to the uppermost conductive pattern of the first stack; a second contact plug coupled to the lowermost conductive pattern of the first stack; a third contact plug coupled to the uppermost conductive pattern of the second stack; and a fourth contact plug coupled to the lowermost conductive pattern of the second stack. A difference between recess depths of adjacent contact plugs between the first contact plug and the second contact plug is less than a difference between recess depths of adjacent contact plugs between the third contact plug and the fourth contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting example embodiments described herein.

[0011] Figures 1A to 1G is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0012] Figure 2A and Figure 2B is a cross-sectional view showing a part of a connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figures 1A to 1G is a cross-sectional view showing a part of a connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method of

[0013] Figure 2C is a cross-sectional view showing a change in recess depth of contact plugs provided in a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figures 1A to 1G is a graph showing a change in recess depth of contact plugs provided in a three-dimensional semiconductor memory device manufactured by the manufacturing method of

[0014] Figure 3A is a cross-sectional view showing a part of a connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figures 1A to 1G is a cross-sectional view showing a part of a connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method of

[0015] Figure 3B is a cross-sectional view showing a change in recess depth of contact plugs provided in a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figure 3A is a graph showing a change in recess depth of contact plugs provided in a three-dimensional semiconductor memory device manufactured by the manufacturing method of

[0016] Figure 4 is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0017] Figure 5 is a cross-sectional view showing a part of a connection region of a three-dimensional semiconductor memory device manufactured by a manufacturing method of Figure 4 .

[0018] Figure 6 is a graph showing changes in the depression depth of a contact plug provided in a three-dimensional semiconductor memory device manufactured by a manufacturing method of Figure 4 .

[0019] Figure 7 is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some exemplary embodiments of the inventive concept.

[0020] Figure 8 is a cross-sectional view showing a part of a connection region of a three-dimensional semiconductor memory device manufactured by a manufacturing method of Figure 7 .

[0021] Figure 9A , Figure 9B and Figure 9C are cross-sectional views showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0022] Figure 10A and Figure 10B are cross-sectional views showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0023] Figure 11 is a graph showing changes in the depression depth of a contact plug provided in a three-dimensional semiconductor memory device manufactured by a manufacturing method of Figure 10A and Figure 10B .

[0024] Figure 12A , Figure 12B , Figure 12C and Figure 12D are cross-sectional views showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0025] Figure 13 is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0026] Figure 14A and Figure 14B are cross-sectional views showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0027] Figure 15 and Figure 16is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0028] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in certain example embodiments and supplement the written description provided below. However, these drawings are not or may not be drawn to scale and cannot precisely reflect the exact structural or performance characteristics of any given embodiment, and should not be construed as defining or limiting the scope of the values or characteristics included in the example embodiments. For example, for clarity, the relative thicknesses and positions of molecules, layers, regions, and / or structural elements may be reduced or exaggerated. The use of like or identical reference numerals in the various drawings is intended to indicate the presence of like or identical elements or features. Detailed Description

[0029] Example embodiments of the inventive concept will now be described more fully with reference to the drawings showing exemplary embodiments.

[0030] Figures 1A to 1G is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept.

[0031] Referring to Figure 1A , a substrate 100 including a cell array region CAR and a connection region CNR may be provided. The connection region CNR may include an upper connection region CNR1 and a lower connection region CNR2, and the upper connection region CNR1 may be adjacent to the cell array region CAR.

[0032] A molding structure MS may be formed on the substrate 100, and the molding structure MS may include sacrificial layers SL and insulating layers ILD that are vertically and alternately stacked on the substrate 100. The molding structure MS may be deposited, for example, using a chemical vapor deposition (CVD) process and / or an atomic layer deposition (ALD) process. The sacrificial layers SL and the insulating layers ILD may be alternately and repeatedly formed in one CVD chamber or, alternatively, in multiple CVD chambers. Here, the sacrificial layer SL may be formed of a material that can be etched with a high etch selectivity relative to the insulating layer ILD. For example, the sacrificial layer SL may be formed of or include or consist of silicon nitride, and the insulating layer ILD may be formed of or include or consist of silicon oxide. In some example embodiments, the sacrificial layer SL may be formed of or include or consist of a conductive material, and in this case, the subsequent replacement process may be omitted.

[0033] The molded structure MS may have a stepped structure on the connection region CNR. The formation of the molded structure MS may include vertically and alternately stacking a sacrificial layer SL and an insulating layer ILD on a substrate 100 to form a layered structure (not shown), and then performing a stepped patterning process on the layered structure. The stepped patterning process may include a single lithographic patterning process, or alternatively, may include a plurality of lithographic patterning processes. When observed in a cross-sectional view taken along the first direction D1, the stepped patterning process may be performed to form a stepped structure in the molded structure MS and on the connection region CNR. In the stepped patterning process, the slope of the stepped structure observed in the cross-sectional view taken along the first direction D1 may vary according to the number of sacrificial layers SL etched during the process of etching a part of the layered structure. In the case where two or more sacrificial layers SL are etched when etching a part of the layered structure, such a stepped structure may also be formed in the second direction D2.

[0034] After the molded structure MS is formed, a planarized insulating layer 110 may be formed to cover the stepped structure of the molded structure MS. The planarized insulating layer 110 may be deposited by a CVD process, and the planarized insulating layer 110 may be planarized by a chemical mechanical planarization process and / or by an etch-back process; however, the exemplary embodiments are not limited thereto. The planarized insulating layer 110 may have a flat top surface that is located at substantially the same level as the top surface of the molded structure MS. The planarized insulating layer 110 may be formed by forming an insulating gap-fill layer that is thicker than the molded structure MS and then performing a planarization process on the insulating gap-fill layer.

[0035] After the planarized insulating layer 110 is formed, a vertical structure VS may be formed to penetrate the molded structure MS. The vertical structure VS may be formed on the cell array region CAR and the connection region CNR, and in this case, the vertical structure VS on the connection region CNR may be formed to penetrate the planarized insulating layer 110 and the molded structure MS.

[0036] The formation of the vertical structure VS may include forming a vertical hole to penetrate the molded structure MS and expose the substrate 100, and then forming a vertical insulating pattern DP and a vertical semiconductor pattern VP in each vertical hole.

[0037] The vertical insulating pattern DP may be formed to surround the sidewall of the vertical semiconductor pattern VP. The vertical insulating pattern DP may be formed by a CVD process and / or an ALD process. The vertical insulating pattern DP may include one or more layers. The vertical insulating pattern DP may be a part of a data storage layer. As an example, the vertical insulating pattern DP may be a data storage layer of a NAND flash memory device and may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer; however, the exemplary embodiments are not limited thereto.

[0038] The vertical semiconductor pattern VP can be in direct contact with the substrate 100, for example, and can have a cross-section shaped like a cylindrical tube with a closed bottom end or the letter "U". The internal space of the vertical semiconductor pattern VP can be filled with an insulating material and / or air, such as clean dry air (CDA). The vertical semiconductor pattern VP can be formed of or include at least one of semiconductor materials such as silicon (Si), germanium (Ge), or a mixture thereof.

[0039] Reference Figure 1B , a first interlayer insulating layer 120 can be formed on the molded structure MS and the planarized insulating layer 110. Thereafter, a replacement process can be performed to replace the sacrificial layer SL with the conductive patterns CPa and CPb.

[0040] The replacement process can include: forming trenches to penetrate the first interlayer insulating layer 120 and the molded structure MS and expose the substrate 100; removing the sacrificial layer SL exposed through the trenches to form gate regions between the insulating patterns ILD; and forming the conductive patterns CPa and CPb in each gate region. Here, the formation of the gate regions can include isotropically etching the sacrificial layer SL using an etching recipe such as a wet etching recipe that has an etching selectivity with respect to the planarized insulating layer 110, the insulating pattern ILD, the vertical structure VS, and the substrate 100. For example, the sacrificial layer SL can have an etching selectivity such that in the presence of a wet chemical, the sacrificial layer SL is etched faster than any of the planarized insulating layer 110, the insulating pattern ILD, the vertical structure VS, and the substrate 100. The conductive patterns CPa and CPb can be formed of or include at least one of metal nitrides (e.g., TiN, TaN, and / or WN) or metals (e.g., W, Al, Ti, Ta, Co, and / or Cu). In addition, before forming the conductive patterns CPa and CPb in the gate regions, a horizontal insulating pattern HP (e.g., see Figure 2A and Figure 2B ) can be formed to conformally cover the inner surfaces of each gate region. The horizontal insulating pattern HP can be part of the data storage layer of a NAND FLASH memory device.

[0041] As a result of the replacement process, a stack ST can be formed on the substrate 100, the stack ST including the conductive patterns CPa and CPb and the insulating patterns ILD that are vertically and alternately stacked on the substrate 100. In some example embodiments, the stack ST can include: a lower stack ST1 including the conductive pattern CPa, the end of the lower stack ST1 being located on the lower connection region CNR2; and an upper stack ST2 including the conductive pattern CPb, the end of the upper stack ST2 being located on the upper connection region CNR1.

[0042] After forming the stacked ST, an impurity region (not shown) can be formed by doping an impurity into a portion of the substrate 100 exposed through the trench. The impurity region can be formed by an ion implantation process, such as a beam line implantation process and / or a plasma-assisted doping process. Thereafter, an insulating spacer SS can be formed in the trench to cover side surfaces of the conductive patterns CPa and CPb, and a common source conductive pattern CSP coupled to the impurity region or the substrate 100 can be formed in the trench.

[0043] After forming the common source conductive pattern CSP, a second interlayer insulating layer 130 can be formed on the first interlayer insulating layer 120. Thereafter, an etch stop pattern 140 can be formed on the second interlayer insulating layer 130. The etch stop pattern 140 can be formed by depositing an etch stop layer on the second interlayer insulating layer 130 and patterning the etch stop layer. As an example, the etch stop pattern 140 can be formed to cover a region of the second interlayer insulating layer 130 on the stepped structure of the stacked ST, for example, a part of the region of the second interlayer insulating layer 130 in the upper connection region CNR1.

[0044] The etch stop pattern 140 can have a uniform thickness on the flat top surface of the second interlayer insulating layer 130. The etch stop pattern 140 can include a single layer or multiple layers. The etch stop pattern 140 can be formed of a material having an etch selectivity with respect to the second interlayer insulating layer 130. For example, the etch stop pattern 140 can be formed of at least one of a metal (e.g., doped or undoped polysilicon, W, Al, and / or Ti) or a metal nitride (e.g., TiN, TaN, and / or WN). The etch stop pattern 140 can be formed of a material that etches slower than the material of the second insulating layer 130, for example, etches slower during an anisotropic etching process.

[0045] After forming the etch stop pattern 140, a mask pattern MP can be formed to have an opening OP on an end of the stacked ST. The mask pattern MP can be a photoresist pattern and / or a hard mask pattern.

[0046] Referring to Figure 1C , the etch stop pattern 140, the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110 can be subjected to a first anisotropic etching process using the mask pattern MP as an etch mask.

[0047] A first anisotropic etching process can be performed using an etching recipe that anisotropically and sequentially etches the etch stop pattern 140, the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110. The first anisotropic etching process can be or include a dry etching process using plasma, and in this case, etch ions or etch plasma generated from an etch gas can be supplied through the openings of the mask pattern MP.

[0048] As a result of the first anisotropic etching process, a first preliminary contact hole PH1 can be formed to penetrate the etch stop pattern 140, and optionally, a portion of the insulating layer 130, the insulating layer 120, and the planarization layer 110, and a second preliminary contact hole PH2 can be formed to penetrate at least a portion of the planarization layer 110, the insulating layer 120, and the insulating layer 130 that is spaced apart from the etch stop pattern 140.

[0049] According to some embodiments, the first preliminary contact hole PH1 and the second preliminary contact hole PH2 can be formed simultaneously, but depending on the presence or absence of the etch stop pattern 140, the processes of forming the first preliminary contact hole PH1 and the second preliminary contact hole PH2 can have an etch rate difference. For example, the etch rate of the first preliminary contact hole PH1 can be slower than the etch rate of the second preliminary contact hole PH2. Therefore, the height of the first preliminary contact hole PH1 can be greater than the height of the second preliminary contact hole PH2. For example, the bottom surface of the second preliminary contact hole PH2 can be located at a level lower than the bottom surface of the first preliminary contact hole PH1. Alternatively or additionally, due to the etch rate difference between the first preliminary contact hole PH1 and the second preliminary contact hole PH2, the diameter of the second preliminary contact hole PH2 can be greater than the diameter of the first preliminary contact hole PH1.

[0050] Thereafter, as Figure 1D shown, a second anisotropic etching process using the mask pattern MP as an etch mask can be performed to expose the ends of the conductive patterns CPa and CPb of the stack ST.

[0051] In some exemplary embodiments, the second anisotropic etching process can be continuously performed under the same conditions as those in the first anisotropic etching process. Thus, each of the first contact hole H1 and the second contact hole H2 can be formed to have a sidewall profile that monotonically connects to the corresponding one of the first preliminary contact hole PH1 and the second preliminary contact hole PH2.

[0052] For example, as a result of a second anisotropic etching process, the first contact hole H1 may be formed to expose the ends of the conductive patterns CPa and CPb at the upper region of the stack ST located on the upper connection region CNR1, and the second contact hole H2 may be formed to expose the ends of the conductive patterns CPa and CPb at the lower region of the stack ST located on the lower connection region CNR2. Since the conductive patterns CPa and CPb are at different levels from the substrate 100, the first contact hole H1 and the second contact hole H2 may have bottom surfaces at different levels.

[0053] During the second anisotropic etching process, the top surface of each of the conductive patterns CPa and CPb may be partially recessed. For example, when the first contact hole H1 and the second contact hole H2 are formed, the portions of the conductive patterns CPa and CPb exposed through the first contact hole H1 and the second contact hole H2 may be physically over-etched by plasma. Accordingly, the bottom surface of each of the first contact hole H1 and the second contact hole H2 may be located between the top surface and the bottom surface of the corresponding one of the conductive patterns CPa and CPb.

[0054] In the region having the etch stop pattern 140 (e.g., the upper connection region CNR1), the depth of the first contact hole H1 from the top surface of each conductive pattern CPb may vary continuously or monotonically in the stacking direction of the conductive pattern CPb. As used herein, monotonically means that a dimension increases or remains the same, or alternatively, a dimension decreases or remains the same. For example, the portions of the conductive pattern CPb exposed through the first contact hole H1 may have different thicknesses from each other. As an example, the depth of the first contact hole CH1 may decrease as the distance from the substrate 100 increases. Additionally, in the region without the etch stop pattern 140 (e.g., the lower connection region CNR2), the depth of the second contact hole H2 from the top surface of each conductive pattern CPa may vary monotonically in the stacking direction of the conductive pattern CPa. For example, the portions of the conductive pattern CPa exposed through the second contact hole H2 may have different thicknesses from each other. As an example, the depth of the second contact hole CH2 may decrease as the distance from the substrate 100 increases. Further, the portions of the conductive patterns CPa and CPb exposed through adjacent contact holes among the first contact hole H1 and the second contact hole H2 may have discontinuous or discrete recessed depths. For example, the difference in the recessed depth between a portion of the conductive pattern CPa and an adjacent portion of the conductive pattern CPb may be greater than the difference in the recessed depth between a portion of the conductive pattern CPa and an adjacent portion of the conductive pattern CPa, and may also be greater than the difference in the recessed depth between a portion of the conductive pattern CPb and an adjacent portion of the conductive pattern CPb. Additionally, there may be a bend IFX between the recessed depths R1d and R2a.

[0055] After forming the first contact hole H1 and the second contact hole H2, the mask pattern MP may be removed.

[0056] After that, as Figure 1E shown, a contact conductive layer 145 may be formed to fill the first contact hole H1 and the second contact hole H2. The contact conductive layer 145 may completely fill the first contact hole H1 and the second contact hole H2, and may be deposited on the etch stop pattern 140 and the second interlayer insulating layer 130. The contact conductive layer 145 may be formed of or include at least one of metals (e.g., W, Al, and / or Ti), and may be deposited by a CVD process.

[0057] Referring to Figure 1F , a planarization process may be performed to expose the second interlayer insulating layer 130, and thus, a first contact plug CT1 and a second contact plug CT2 may be formed in the first contact hole H1 and the second contact hole H2, respectively.

[0058] A chemical mechanical polishing (CMP) process and / or an etch-back process may be performed as the planarization process. The contact conductive layer 145 and the etch stop pattern 140 may also be removed during the planarization process. For example, during the planarization process, the polishing selectivity and / or etch selectivity between the contact conductive layer 145 and the etch stop pattern 140 may be about 1:1.

[0059] Referring to Figure 1G , a source contact plug CCT may be formed on the cell array region CAR and may be coupled to the common source conductive pattern CSP. A cell interconnection line CCL and connection interconnection lines CL1 and CL2 may be formed on the second interlayer insulating layer 130. The cell interconnection line CCL may be coupled to the source contact plug CCT, and the connection interconnection lines CL1 and CL2 may be connected to the first contact plug CT1 and the second contact plug CT2, respectively.

[0060] A third interlayer insulating layer 150 may be formed on the second interlayer insulating layer 130, and a bit line contact plug BCT coupled to the vertical semiconductor pattern VP and a bit line BL coupled to the bit line contact plug BCT may be formed on the cell array region CAR.

[0061] Hereinafter, with reference to Figure 1G , Figure 2A , Figure 2B and Figure 2C a three-dimensional semiconductor memory device manufactured by a manufacturing method according to some exemplary embodiments of the present inventive concept will be described in more detail.

[0062] Figure 2A and Figure 2B are diagrams illustrating through Figures 1A to 1GCross-sectional view of a part of a connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method. Figure 2C is a graph showing changes in the recess depth of a contact plug provided in a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figures 1A to 1G the manufacturing method.

[0063] Referring to Figure 1G and Figure 2A , the stack ST may include insulating patterns ILD and conductive patterns CPa and CPb that are vertically and alternately stacked on the substrate 100. The stack ST may have a stepped structure on the connection region CNR.

[0064] In some example embodiments, the stack ST may include a lower stack ST1 and an upper stack ST2 on the lower stack ST1, and each of the lower stack ST1 and the upper stack ST2 may include insulating patterns ILD and conductive patterns CPa and CPb that are vertically and alternately stacked on the substrate 100. The number of layers of the insulating pattern ILD and the conductive pattern CPb on the upper stack ST2 may be the same as or different from the number of layers of the insulating pattern ILD and the conductive pattern CPa on the lower stack ST1.

[0065] The conductive pattern CPa of the lower stack ST1 may have an end portion located on the lower connection region CNR2, and the conductive pattern CPb of the upper stack ST2 may have an end portion located on the upper connection region CNR1. In some example embodiments, the upper connection region CNR1 may correspond to the region where the etch stop pattern 140 described with reference to Figures 1A to 1G the manufacturing method is provided, and the lower connection region CNR2 may correspond to the region where the etch stop pattern 140 is not provided.

[0066] The horizontal insulating pattern HP may cover the top surface and the bottom surface of each of the conductive patterns CPa and CPb. The horizontal insulating pattern HP may include a barrier insulating layer that serves as part of the data storage layer of the NAND flash memory device. In some example embodiments, the horizontal insulating pattern HP may extend horizontally from the cell array region CAR to the connection region CNR. A part of the horizontal insulating pattern HP may be provided between the planarization insulating layer 110 and the top surface of the conductive pattern.

[0067] The planarized insulating layer 110 may cover the stepped structure of the stacked STs on the substrate 100. The planarized insulating layer 110 may be in contact with the side surface of the insulating pattern ILD, and the side surface of the insulating pattern ILD may be vertically aligned with the side surfaces of the conductive patterns CPa and CPb located on the insulating pattern ILD. The planarized insulating layer 110 may be in contact with (e.g., directly contact) a portion of the horizontal insulating pattern HP that is disposed on the connection region CNR and covers the top and bottom surfaces of the conductive pattern.

[0068] The planarized insulating layer 110 may be a single layer made of a single insulating material. As an example, the planarized insulating layer 110 may be formed of or include or consist of silicon oxide. The planarized layer 110 may be a homogenous layer. The planarized insulating layer 110 may have a substantially flat top surface and may have a thickness that decreases as the distance from the cell array region CAR decreases.

[0069] The first interlayer insulating layer 120 and the second interlayer insulating layer 130 may be sequentially stacked on the planarized insulating layer 110. The first contact plug CT1 may be disposed to penetrate the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarized insulating layer 110 and may be coupled to the conductive pattern CPb of the upper stacked ST2, respectively. The second contact plug CT2 may be disposed to penetrate the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarized insulating layer 110 and may be coupled to the conductive pattern CPa of the lower stacked ST1, respectively. In some example embodiments, a plurality of first contact plugs CT1 and a plurality of second contact plugs CT2 may be arranged in the first direction D1, and the first contact plugs CT1 and the second contact plugs CT2 may be coupled to the conductive patterns CPa and CPb disposed on even-numbered layers, respectively. The top surfaces of the first contact plug CT1 and the second contact plug CT2 may be at substantially the same height from the top surface of the substrate 100. As an example, the top surfaces of the first contact plug CT1 and the second contact plug CT2 may be substantially coplanar with the top surface of the second interlayer insulating layer 130. The height of the first contact plug CT1 and the second contact plug CT2 in the third direction D3 may decrease as the distance from the cell array region CAR decreases.

[0070] According to some embodiments of the inventive concept, each of the first contact plug CT1 and the second contact plug CT2 may extend to a level lower than the top surface of the corresponding one of the conductive patterns CPa and CPb. For example, each of the first contact plug CT1 and the second contact plug CT2 may have a bottom surface that is located between the top and bottom surfaces of the corresponding one of the conductive patterns CPa and CPb.

[0071] When measuring the position of the bottom surface of each first contact plug CT1 from the top surface of a corresponding one of the conductive patterns CPb, the positions of the bottom surfaces of the first contact plugs CT1 on the upper stack ST2 may be different from each other. For example, when measuring the recess depth of each first contact plug CT1 from the top surface of a corresponding one of the conductive patterns CPb, the recess depths of the first contact plugs CT1 may be different from each other. Here, the recess depth of the first contact plug CT1 may vary monotonically in the stacking direction of the conductive pattern CPb. In some example embodiments, the recess depth of each contact plug CT1 or CT2 may correspond to the distance between the top surface of the corresponding conductive pattern CPa or CPb and the bottom surface of the contact plug CT1 or CT2. When measuring the position of the bottom surface of each second contact plug CT2 from the top surface of a corresponding one of the conductive patterns CPa, the positions of the bottom surfaces of the second contact plugs CT2 on the lower stack ST1 may be different from each other. For example, when measuring the recess depth of each second contact plug CT2 from the top surface of a corresponding one of the conductive patterns CPa, the recess depths of the second contact plugs CT2 may be different from each other. Here, the recess depth of the second contact plug CT2 may vary monotonically in the stacking direction of the conductive pattern CPa.

[0072] The height of the stepped structure of the stack ST may increase in the stacking direction. For example, the stacking direction may be a direction opposite to the first direction D1 (e.g., see Figure 2A , Figure 2B and Figure 2C ), and may be perpendicular to the surface of the substrate.

[0073] Referring to Figure 2A and Figure 2C , as the level of the conductive pattern CPa of the lower stack ST1 increases, the recess depth of the second contact plug CT2 coupled to the conductive pattern CPa may increase monotonically (e.g., R2a > R2b... > R2c > R2d or R2a >= R2b... >= R2c >= R2d). As the level of the conductive pattern CPb of the upper stack ST2 increases, the recess depth of the first contact plug CT1 coupled to the conductive pattern CPb may decrease monotonically (e.g., R1a < R1b... < R1c < R1d or R1a <= R1b... <= R1c <= R1d). Compared with the difference between adjacent contact plugs CT1 or adjacent contact plugs CT2, the recess depths of adjacent first contact plugs CT1 and second contact plugs CT2 may have discrete values (e.g., R1d < R2a), or may have a large jump. As an example, the difference between R2a and R1d may be greater than the difference between R1d and R1c. The recess depths of the first contact plug CT1 and the second contact plug CT2 may be in the range of about to (or 0.1 nm to 35 nm).

[0074] Specifically, the distance between the top surface of the uppermost conductive pattern CPb of the upper stack ST2 and the bottom surface of a corresponding first contact plug CT1 may be or correspond to a first recess depth R1a. The distance between the top surface of the lowermost conductive pattern CPb of the upper stack ST2 and the bottom surface of a corresponding first contact plug CT1 may be or correspond to a second recess depth R1d greater than the first recess depth R1a. In the upper stack ST2, the recess depths R1b and R1c of the first contact plugs CT1 coupled to the conductive patterns CPb located between the uppermost conductive pattern CPb and the lowermost conductive pattern CPb may be greater than the first recess depth R1a and may be less than the second recess depth R1d.

[0075] The distance between the top surface of the uppermost conductive pattern CPa of the lower stack ST1 and the bottom surface of a corresponding second contact plug CT2 may be a third recess depth R2a. Here, the third recess depth R2a may be greater than the second recess depth R1d. The distance between the top surface of the lowermost conductive pattern CPa of the lower stack ST1 and the bottom surface of a corresponding second contact plug CT2 may be a fourth recess depth R2d greater than the third recess depth R2a. In the lower stack ST1, the recess depths R2b and R2c of the second contact plugs CT2 coupled to the conductive patterns CPa located between the uppermost conductive pattern CPa and the lowermost conductive pattern CPa may be greater than the third recess depth R2a and may be less than the fourth recess depth R2d. The first difference in the recess depths between adjacent first contact plugs CT1 (e.g., the difference between R1a and R1b, the difference between R1b and R1c, or the difference between R1c and R1d) may be different from the second difference in the recess depths between adjacent first contact plugs CT1 and second contact plugs CT2 (e.g., the difference between R1d and R2d). As an example, the first difference may be in the range of 0.1 nm to 5 nm, and the second difference may be in the to range (e.g., 3 nm to 10 nm).

[0076] The first variation amount DD1 of the recess depth of the first contact plugs CT1 on the upper stack ST2 may be different from the second variation amount DD2 of the recess depth of the second contact plugs CT2 on the lower stack ST1. As an example, the first variation amount DD1 of the recess depth of the first contact plugs CT1 on the upper stack ST2 may be less than the second variation amount DD2 of the recess depth of the second contact plugs CT2 on the lower stack ST1. The first variation amount DD1 may correspond to the difference between the maximum value R1d and the minimum value R1a of the recess depth of the first contact plugs CT1, and the second variation amount DD2 may correspond to the difference between the maximum value R2d and the minimum value R2a of the recess depth of the second contact plugs CT2. In some example embodiments, the first variation amount DD1 may be about to about ranges from, for example, 3 nm to 8 nm, and the second variation amount DD2 can be from about to about ranges from, for example, about 4 nm to 10 nm.

[0077] In some example embodiments, the first contact plug CT1 can have a first average upper diameter A, and the second contact plug CT2 can have a second average upper diameter B, which is different from, for example, less than the first upper diameter A. For example, the diameters of adjacent contact plugs among the first contact plug CT1 and the second contact plug CT2 can be different from each other. The difference in diameter between the first contact plug CT1 and the second contact plug CT2 can be from about to about ranges from, for example, about 5 nm to 10 nm.

[0078] In addition, the diameter of the first contact plug CT1 coupled to the lowermost conductive pattern CPb of the upper stack ST2 can be greater than the diameter of the first contact plug CT1 coupled to the uppermost conductive pattern CPb of the upper stack ST2. Similarly, the diameter of the second contact plug CT2 coupled to the lowermost conductive pattern CPa of the lower stack ST1 can be greater than the diameter of the second contact plug CT2 coupled to the uppermost conductive pattern CPa of the lower stack ST1.

[0079] Referring to Figure 2B , the first contact plug CT1 coupled to the uppermost conductive pattern CPb of the upper stack ST2 can have a bottom surface that is located at substantially the same level as the top surface of the uppermost conductive pattern CPb. The first contact plug CT1 coupled to the lowermost conductive pattern CPb of the upper stack ST2 can have a bottom surface that is located at substantially the same level as the bottom surface of the lowermost conductive pattern CPb. In other words, the first contact plug CT1 can penetrate the lowermost conductive pattern CPb.

[0080] Similarly, the second contact plug CT2 coupled to the uppermost conductive pattern CPa of the lower stack ST1 can penetrate the uppermost conductive pattern CPa. The second contact plug CT2 coupled to the uppermost conductive pattern CPa of the lower stack ST1 can have a bottom surface that is located at substantially the same level as the bottom surface of the uppermost conductive pattern CPa. The second contact plug CT2 coupled to the lowermost conductive pattern CPa of the lower stack ST1 can have a bottom surface that is located at substantially the same level as the top surface of the lowermost conductive pattern CPa.

[0081] Figure 3A is a cross-sectional view showing a part of the connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figures 1A to 1G . Figure 3Bis a graph showing the variation in the recess depth of contact plugs provided in a three-dimensional semiconductor memory device in Figure 3A The vertical length of the first contact plug CT1 is higher, the recess depths R2a, R2b, R2c, and R2d of the first contact plug CT1 are smaller. This may be true for the second contact plug CT2 coupled to the upper stack ST2. In addition, as described above, the difference in recess depth between adjacent contact plugs in the first contact plug CT1 or the second contact plug CT2.

[0082] Referring to Figure 1G , Figure 3A and Figure 3B , the recess depths R2a, R2b, R2c, and R2d of the first contact plug CT1 of the conductive pattern CPa coupled to the lower stack ST1 may gradually decrease in the direction from the uppermost conductive pattern CPa to the lowermost conductive pattern CPa. For example,

[0083] Figure 4 is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Figure 5 is a cross-sectional view showing a part of a connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figure 4 . Figure 6 is a graph showing the variation in the recess depth of contact plugs provided in a three-dimensional semiconductor memory device manufactured by the manufacturing method of Figure 4 . For brevity of description, the elements previously described with reference to Figures 1A to 1G may be identified by the same reference numerals and will not be described again.

[0084] Referring to Figure 4 , the connection region CNR of the substrate 100 may include a lower connection region CNR3, an upper connection region CNR1, and an intermediate connection region CNR2 between the lower connection region CNR3 and the upper connection region CNR1.

[0085] The stacked ST may include a lower stack ST1, an intermediate stack ST2, and an upper stack ST3 sequentially stacked on a substrate 100, and each of the lower stack ST1, the intermediate stack ST2, and the upper stack ST3 may include insulating patterns ILD and conductive patterns CPa, CPb, and CPc vertically and alternately stacked on the substrate 100. The number of layers of the insulating pattern ILD in each of the lower stack ST1, the intermediate stack ST2, and the upper stack ST3 may be the same as or different from each other. When observed in a cross-sectional view taken along a first direction D1, the conductive patterns CPa, CPb, and CPc of the lower stack ST1, the intermediate stack ST2, and the upper stack ST3 may be formed to form a stepped structure on a connection region CNR. An end of the conductive pattern CPa of the lower stack ST1 may be disposed on a lower connection region CNR3, an end of the conductive pattern CPb of the intermediate stack ST2 may be disposed on an intermediate connection region CNR2, and an end of the conductive pattern CPc of the upper stack ST3 may be disposed on an upper connection region CNR1.

[0086] As described in the reference Figure 1B The planarized insulating layer 110 and the first interlayer insulating layer 120 and the second interlayer insulating layer 130 may be formed to cover the stacked ST, and an etch stop pattern 140 may be formed on a flat top surface of the second interlayer insulating layer 130. In some example embodiments, the etch stop pattern 140 may be formed on the intermediate connection region CNR2.

[0087] Similar to the reference Figure 1C and Figure 1D the method described, after forming the etch stop pattern 140, contact holes H1, H2, and H3 may be formed to penetrate the etch stop pattern 140, the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarized insulating layer 110.

[0088] As described above, the contact holes H1, H2, and H3 may be formed to expose ends of the conductive patterns CPa, CPb, and CPc of the stacked ST, respectively, and the top surfaces of the conductive patterns CPa, CPb, and CPc may be recessed by an anisotropic etching process to form the contact holes H1, H2, and H3. In some example embodiments, the contact holes H1, H2, and H3 may include a first contact hole H1 that exposes the conductive pattern CPc of the upper stacked ST2, a second contact hole H2 that exposes the conductive pattern CPb of the intermediate stacked ST2, and a third contact hole H3 that exposes the conductive pattern CPa of the lower stacked ST1, respectively.

[0089] According to some example embodiments of the inventive concept, when the first through third contact holes H1, H2, and H3 are formed simultaneously, an etch stop pattern 140 may be present on the intermediate connection region CNR2. Accordingly, the recess depth of the conductive pattern CPb exposed through the second contact hole H2 on the intermediate connection region CNR2 may be less than the recess depth of the conductive pattern CPa exposed through the first contact hole H1 on the lower connection region CNR1 and the recess depth of the conductive pattern CPc exposed through the third contact hole H3 on the upper connection region CNR3.

[0090] In the case where the first through third contact holes H1, H2, and H3 are formed simultaneously, when measured from the top surface of a corresponding one of the conductive patterns CPa, CPb, and CPc, the recess depth of the first contact hole H1 may monotonically vary in the stacking direction of the conductive pattern CPc of the upper stack ST3, the recess depth of the second contact hole H2 may vary to obtain a local maximum in the stacking direction of the conductive pattern CPb of the intermediate stack ST2, and the recess depth of the third contact hole H3 may monotonically vary in the stacking direction of the conductive pattern CPb of the intermediate stack ST2. Here, the recess depths of adjacent contact holes among the first contact hole H1 and the second contact hole H2 may have discrete values (e.g., may have discrete jumps), and the recess depths of adjacent contact holes among the second contact hole H2 and the third contact hole H3 may have discrete values (e.g., may have discrete jumps). As an example, the difference between the recess depth of the second contact hole H2 and the recess depth of the adjacent first contact hole H1 may be greater than the difference between the recess depth of the first contact hole H1 and the recess depth of the adjacent first contact hole H1. Additionally or alternatively, the difference between the recess depth of the third contact hole H3 and the recess depth of the adjacent second contact hole H2 may be greater than the difference between the recess depth of the second contact hole H2 and the recess depth of the adjacent second contact hole H2.

[0091] As Figure 5 shown, after the first through third contact holes H1, H2, and H3 are formed, first through third contact plugs CT1, CT2, and CT3 may be respectively formed in the first through third contact holes H1, H2, and H3. As described above, after the first through third contact plugs CT1, CT2, and CT3 are formed, the etch stop pattern 140 on the second interlayer insulating layer 130 may be removed.

[0092] Referring to Figure 5 and Figure 6, the first contact plug CT1 coupled to the uppermost conductive pattern CPc of the upper stack ST3 may have a first recess depth R1a, and the first contact plug CT1 coupled to the lowermost conductive pattern CPc of the upper stack ST3 may have a second recess depth R1d greater than the first recess depth R1a. The recess depth of the first contact plug CT1 may vary monotonically in the stacking direction of the conductive patterns CPc of the upper stack ST3 and may be within a range between the first recess depth R1a and the second recess depth R1d.

[0093] The second contact plug CT2 coupled to the uppermost conductive pattern CPb of the middle stack ST2 may have a third recess depth R2a, and the second contact plug CT2 coupled to the lowermost conductive pattern CPb of the middle stack ST2 may have a fourth recess depth R2d equal to or different from the third recess depth R2a. One of the second contact plugs CT2 may have a recess depth R2d that is the maximum value of the recess depths of the second contact plugs CT2. The recess depth of the second contact plug CT2 may vary to obtain a local maximum in the stacking direction of the conductive patterns CPb of the middle stack ST2 and may be within a range from the third recess depth R2a to the maximum recess depth R2d.

[0094] The third contact plug CT3 coupled to the uppermost conductive pattern CPa of the lower stack ST1 may have a fifth recess depth R3a, and the third contact plug CT3 coupled to the lowermost conductive pattern CPa of the lower stack ST1 may have a sixth recess depth R3d less than the fifth recess depth R3a. The recess depth of the third contact plug CT3 may vary monotonically according to the level of the conductive pattern CPa of the lower stack ST1 and may be within a range between the fifth recess depth R3a and the sixth recess depth R3d.

[0095] According to Figure 5 and Figure 6 the embodiments of, between the upper connection region CNR1 and the middle connection region CNR2 and between the middle connection region CNR2 and the lower connection region CNR3, the recess depths of the contact plugs CT1, CT2, and CT3 may vary discontinuously.

[0096] The variation amount DD2 of the recess depth of the second contact plug CT2 on the middle connection region CNR2 may be less than the variation amount DD1 of the recess depth of the first contact plug CT1 on the upper connection region CNR1 or the third contact plug CT3 on the lower connection region CNR3.

[0097] Figure 7 is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some example embodiments of the inventive concept. Figure 8 is shown byFigure 7 Cross-sectional view of a portion of a connection region of a three-dimensional semiconductor memory device manufactured by the manufacturing method. For the sake of brevity of description, the elements previously referred to Figures 1A to 1G The elements described above may be identified by the same reference numerals and will not be described again.

[0098] Referring to Figure 7 , the connection region CNR of the substrate 100 may include a lower connection region CNR3, an upper connection region CNR1, and an intermediate connection region CNR2 between the lower connection region CNR3 and the upper connection region CNR1.

[0099] Etch stop patterns 140 may be formed (e.g., deposited and patterned) on the flat top surface of the second interlayer insulating layer 130 to be spaced apart from each other. Here, the etch stop patterns 140 may be formed on the upper connection region CNR1 and the lower connection region CNR3, respectively.

[0100] Similar to the method described with reference to Figure 1C and Figure 1D , after forming the etch stop patterns 140, contact holes H1, H2, and H3 may be formed to penetrate the etch stop patterns 140, the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110. Here, the first contact hole H1 may be formed to expose the conductive pattern CPc of the upper stack ST3 accordingly, the second contact hole H2 may be formed to expose the conductive pattern CPb of the intermediate stack ST2 accordingly, and the third contact hole H3 may be formed to expose the conductive pattern CPa of the lower stack ST1 accordingly.

[0101] In some example embodiments, when the first through third contact holes H1, H2, and H3 are formed simultaneously by the same process, there may be an etch stop pattern 140 on the intermediate connection region CNR2, and there may be an etch stop pattern 140 on each of the upper connection region CNR1 and the lower connection region CNR3. Therefore, the recess depth of the first contact hole H1 on the upper connection region CNR1 and the third contact hole H3 on the lower connection region CNR3 may be less than the recess depth of the second contact hole H2.

[0102] As Figure 8 shown, after forming the first through third contact holes H1, H2, and H3, the first through third contact plugs CT1, CT2, and CT3 may be formed in the first through third contact holes H1, H2, and H3, respectively. As described above, after forming the first through third contact plugs CT1, CT2, and CT3, the etch stop pattern 140 on the second interlayer insulating layer 130 may be removed.

[0103] Referring to Figure 8, the recess depth R1d of the first contact plug CT1 coupled to the lowermost conductive pattern CPc of the upper stack ST3 may be less than the recess depth R2a of the second contact plug CT2 coupled to the uppermost conductive pattern CPb of the middle stack ST2. The recess depth R2d of the second contact plug CT2 coupled to the lowermost conductive pattern CPb of the middle stack ST2 may be greater than the recess depth R3a of the third contact plug CT3 coupled to the uppermost conductive pattern CPa of the lower stack ST1.

[0104] Figure 9A , Figure 9B and Figure 9C is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Figures 1A to 1G The elements described above may be identified by the same reference numerals without repeated description.

[0105] Reference Figure 9A , the etch stop pattern 140 may be formed on a portion of the flat top surface of the second interlayer insulating layer 130 located on the upper connection region CNR1. Figure 9B As shown, the etch stop pattern 140 may be formed on the intermediate connection region CNR2, and as shown in FIG. Figure 9C As shown, the etch stop patterns 140 may be formed on the upper connection region CNR1 and the lower connection region CNR3 , respectively.

[0106] Reference Figure 9A , Figure 9B and Figure 9C , the etch stop pattern 140 may include a lower etch stop pattern 141 and an upper etch stop pattern 143 made of different materials. In the anisotropic etching process, the lower etch stop pattern 141 and the upper etch stop pattern 143 may have different etching rates from each other. As an example, the lower etch stop pattern 141 may be formed of a conductive material, and the upper etch stop pattern 143 may be formed of an insulating material. As an example, during the anisotropic etching, the lower etch stop pattern 141 may be etched faster than the upper etch stop pattern 143.

[0107] Figure 10A and Figure 10B is a cross-sectional view illustrating a method of fabricating a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Figure 11 It is shown in the Figure 10A and Figure 10B A graph showing a change in a recess depth of a contact plug provided in a three-dimensional semiconductor memory device manufactured by the manufacturing method.

[0108] Reference Figure 10A and Figure 10B, an etch stop pattern 140 may be formed on the flat top surface of the second interlayer insulating layer 130, and the etch stop pattern 140 may include portions having different thicknesses and / or widths from each other.

[0109] For example, as Figure 10A shown, the etch stop pattern 140 may include a lower etch stop pattern 141 and an upper etch stop pattern 143. The lower etch stop pattern 141 has a first width, and the upper etch stop pattern 143 is disposed on the lower etch stop pattern 141 and has a second width smaller than the first width. Here, the lower etch stop pattern 141 and the upper etch stop pattern 143 may be formed of the same material or different materials.

[0110] Alternatively or additionally, as Figure 10B shown, the etch stop pattern 140 may include a first etch stop pattern 142 having a first thickness and a second etch stop pattern 144 having a second thickness greater than the first thickness. Here, the second etch stop pattern 144 may be disposed between the first etch stop patterns 142.

[0111] Similar to the method described with reference to Figure 1C and Figure 1D , after forming the etch stop pattern 140, contact holes H1, H2a, H2b, and H3 may be formed to penetrate the etch stop pattern 140, the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110, as Figure 10A and 10B shown.

[0112] When the first contact hole to the third contact holes H1, H2a, H2b, and H3 are formed simultaneously (e.g., anisotropic etching simultaneously), the etch stop pattern 140 may exist on the intermediate connection region CNR2. Therefore, the recess depths of the second contact holes H2a and H2b on the intermediate connection region CNR2 may be smaller than the recess depths of the first contact hole H1 on the lower connection region CNR1 and the third contact hole H3 on the upper connection region CNR3. In addition, since the etch stop pattern 140 on the intermediate connection region CNR2 has at least two different thicknesses, the recess depths of the second contact holes H2a and H2b may be different from each other.

[0113] Thereafter, first contact plugs to third contact plugs CT1, CT2, and CT3 may be respectively formed in the first contact hole to the third contact holes H1, H2a, H2b, and H3. As described above, after forming the first contact plug to the third contact plugs CT1, CT2, and CT3, the etch stop pattern 140 on the second interlayer insulating layer 130 may be removed.

[0114] Referring to Figure 10A ,Figure 10B and Figure 11 As compared with the recess depth of the second contact plug in the thinner portion of the etch stop pattern 140, the recess depth of the second contact plugs H2a and H2b formed in the second contact plug penetrating the thicker portion of the etch stop pattern 140 can be reduced. The variation amount DD3 of the recess depth of the second contact plug penetrating the thicker portion of the etch stop pattern 140 can be less than the variation amount DD2 of the recess depth of the second contact plug in the thinner portion of the etch stop pattern 140.

[0115] Figure 12A 、 Figure 12B 、 Figure 12C and Figure 12D are cross-sectional views showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. For the sake of brevity of description, the elements described previously with reference to Figures 1A to 1G may be identified by the same reference numerals and will not be described again.

[0116] Referring to Figure 12A and Figure 12B , the etch stop pattern 140 may be disposed on the upper connection region CNR1 and may include a lower etch stop pattern 141 having a first length and / or width and an upper etch stop pattern 143 having a second length and / or width smaller than the first length and / or width. The upper etch stop pattern 143 may be formed on the upper connection region CNR1 and may be locally formed on the lower etch stop pattern 141.

[0117] The first contact holes H1a and H1b may include a first contact hole H1a penetrating the lower etch stop pattern 141 and the upper etch stop pattern 143, and a first contact hole H1b penetrating the lower etch stop pattern 141. When the first contact holes Hla and Hlb are formed, the recess depth of the first contact plug formed in the first contact holes Hla and Hlb may depend on the thickness of the etch stop pattern 140.

[0118] Referring to Figure 12C , the etch stop pattern 140 may include a first etch stop pattern 142 having a first thickness and a second etch stop pattern 144 having a second thickness greater than the first thickness. Since the etch stop pattern 140 on the upper connection region CNR1 is formed to have two different thicknesses, the diameter of the first contact hole H1b penetrating the first etch stop pattern 142 may be greater than the diameter of the first contact hole H1a penetrating the second etch stop pattern 144. In addition, the diameter of the second contact hole H2 formed in the lower connection region CNR2 without the etch stop pattern 140 may be greater than the diameter of the first contact hole H1b penetrating the second etch stop pattern 144.

[0119] Reference Figure 12D As shown in Figure 12D , etch stop patterns 140 may be formed on upper connection region CNR1 and lower connection region CNR3, respectively, and each etch stop pattern 140 may include a lower etch stop pattern 141 and an upper etch stop pattern 143 shorter than the lower etch stop pattern 141.

[0120] Figure 13 FIG. Figure 12D is a cross-sectional view showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. For the sake of brevity in description, elements previously described with reference to Figures 1A to 1G may be identified by the same reference numerals and will not be described in detail again.

[0121] Reference Figure 13 As shown in Figure 13 , etch stop patterns 140 may be formed on the flat top surface of the second interlayer insulating layer 130, and then a mask pattern MP having openings OP may be formed on the etch stop patterns 140 and the second interlayer insulating layer 130, as previously referenced Figure 1B In some example embodiments, the diameter R of the openings OP formed in the mask pattern MP may be substantially the same regardless of the presence or absence of the etch stop patterns 140.

[0122] Thereafter, contact holes H1 and H2 may be formed to penetrate the etch stop patterns 140, the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110, as previously referenced Figure 1C and Figure 1D Here, contact holes H1 and H2 may include a first contact hole H1 formed to expose a conductive pattern CPb of the upper stack ST2 and a second contact hole H2 formed to expose a conductive pattern CPa of the lower stack ST1.

[0123] When forming the contact holes H1 and H2, the etching rate in the upper connection region CNR1 having the etch stop pattern 140 may be less than the etching rate in the lower connection region CNR2. Since the etch stop pattern 140 is formed of a material having an etching selectivity with respect to the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110 when forming the first contact hole H1, the sidewall profile of the first contact hole H1 in the etch stop pattern 140 may be different from the sidewall profile of the first contact hole H1 in the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110.

[0124] As an example, the diameter A of the first contact hole H1 in the planarization insulating layer 110 may be less than the diameter in the etch stop pattern 140.

[0125] The second contact hole H2 formed on the lower connection region CNR2 without the etch stop pattern 140 may have a substantially uniform sidewall profile. The difference between the upper diameter B of the second contact hole H2 and the diameter R of the opening OP of the mask pattern MP may be less than the difference between the upper diameter A of the first contact hole H1 and the diameter R of the opening OP of the mask pattern MP.

[0126] Thereafter, as described above, the first contact plug CT1 and the second contact plug CT2 may be formed in the first contact hole H1 and the second contact hole H2, respectively, and then the etch stop pattern 140 may be removed. The first contact plug CT1 and the second contact plug CT2 formed by the above method may have different diameters at their top levels. As an example, the diameter of the first contact plug CT1 coupled to the conductive pattern CPb of the upper stack ST2 may be smaller than the diameter of the second contact plug CT2 coupled to the conductive pattern CPa of the lower stack ST1. The difference in diameter between the first contact plug CT1 and the second contact plug CT2 may range from about 5 nm to 10 nm.

[0127] Figure 14A and Figure 14B are cross-sectional views showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. For brevity of description, the elements previously referred to Figures 1A to 1G may be identified by the same reference numerals and will not be described again.

[0128] Referring to Figure 14A , the etch stop pattern 140 may be formed on the flat top surface of the second interlayer insulating layer 130, and then the mask pattern MP having an opening may be formed on the etch stop pattern 140 and the second interlayer insulating layer 130, as previously referred to Figure 1B above. In some exemplary embodiments, the diameter of the opening of the mask pattern MP may be substantially the same regardless of the presence or absence of the etch stop pattern 140.

[0129] Thereafter, a first anisotropic etching process may be performed to form a first preliminary contact hole PH1 and a second preliminary contact hole PH2, the first preliminary contact hole PH1 penetrating the etch stop pattern 140, and the second preliminary contact hole PH2 spaced apart from the etch stop pattern 140 and penetrating a portion of the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarization insulating layer 110, as previously referred to Figure 1C above. The first preliminary contact hole PH1 and the second preliminary contact hole PH2 may be formed simultaneously, but the length of the first preliminary contact hole PH1 may be greater than the length of the second preliminary contact hole PH2.

[0130] Thereafter, referring to Figure 14B, a second anisotropic etching process may be performed on the planarized insulating layer 110 exposed through the first preliminary contact hole PH1 and the second preliminary contact hole PH2. An etching recipe different from the etching recipe in the first anisotropic etching process may be used in the second anisotropic etching process. Therefore, after the first preliminary contact hole PH1 and the second preliminary contact hole PH2 are formed, the sidewall profiles of the first contact hole H1 and the second contact hole H2 exposing the ends of the conductive patterns CPa and CPb may change discontinuously.

[0131] As an example, the first contact hole H1 and the second contact hole H2 may have a first diameter A1 and B1, respectively, at their top horizontal levels, and may have second diameters A2 and B2 smaller than the first diameters A1 and B1, respectively, at their bottom horizontal levels. The sidewall profile of each of the first contact hole H1 and the second contact hole H2 may have an inflection point at which the width or slope changes discontinuously. For example, the difference between the sidewall profiles of adjacent contact holes in the first contact hole H1 may be significantly different from the difference between the sidewall profiles of adjacent contact holes in the first contact hole H1 or the difference between the sidewall profiles of adjacent contact holes in the second contact hole H2. In addition, the first contact hole H1 and the second contact hole H2 may be different from each other in terms of the vertical length of the upper part having the first diameters A1 and B1.

[0132] Figure 15 and Figure 16 are cross-sectional views showing a method of manufacturing a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. For the sake of brevity of description, the elements described previously with reference to Figures 1A to 1G may be identified by the same reference numerals and will not be described again.

[0133] Referring to Figure 15 , the etching stop pattern 140 may extend from the upper connection region CNR1 to the cell array region CAR. After the etching stop pattern 140 is formed, the contact holes H1 and H2 may be formed to penetrate the etching stop pattern 140, the first interlayer insulating layer 120, the second interlayer insulating layer 130, and the planarized insulating layer 110, as described with reference to Figure 1C and Figure 1D , and in some exemplary embodiments, when the contact holes H1 and H2 are formed, a cell contact hole CH may be formed on the cell array region CAR. As an example, the cell contact hole CH may be formed to expose the common source conductive pattern CSP.

[0134] Referring to Figure 16 , the substrate 100 may include a cell array region CAR, a connection region CNR, and a peripheral circuit region PCR.

[0135] The peripheral transistor PT may be formed on the peripheral circuit region PCR of the substrate 100 before or after forming the stacked ST on the substrate 100, and the planarized insulating layer 110 and the first and second interlayer insulating layers 120 and 130 may be formed to cover the peripheral transistor PT.

[0136] In some example embodiments, during formation of the contact holes H1 and H2 that expose the conductive patterns CPa and CPb of the stacked ST, the cell contact hole CH in the cell array region CAR and the peripheral contact hole PH in the peripheral circuit region PCR may be formed simultaneously (e.g., may be etched).

[0137] According to some example embodiments of the inventive concept, contact plugs respectively coupled to the conductive patterns may be formed simultaneously while preventing or reducing the possibility that the etch stop pattern remains on the stacked stepped structure.

[0138] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional semiconductor memory device, comprising: A substrate including a cell array region and a connection region; A stack including a first stack and a second stack, the first stack and the second stack being sequentially stacked on the substrate, the stack having a stepped structure on the connection region, a plurality of steps of the stepped structure decreasing in a first direction, and each of the first stack and the second stack including conductive patterns vertically stacked on the substrate; And Contact plugs on the connection region and respectively coupled to the conductive patterns of the first stack and the second stack, Wherein, the bottom surface of each contact plug is between the top surface and the bottom surface of a corresponding one of the conductive patterns, In the first stack, the recess depths of adjacent contact plugs vary monotonically in the first direction, and the recess depth is measured from the top surface of a corresponding one of the conductive patterns, In the second stack, the recess depths of adjacent contact plugs vary monotonically in the first direction, and the recess depth is measured from the top surface of a corresponding one of the conductive patterns, and The recess depth changes to have a bend between contact plugs adjacent to each other in the first stack and the second stack.

2. The device according to claim 1, wherein, The contact plugs include a first contact plug and a second contact plug, the first contact plug being coupled to the uppermost conductive pattern of the first stack, the second contact plug being coupled to the lowermost conductive pattern of the second stack, and In each of the first stack and the second stack, a first difference in recess depth between adjacent contact plugs is less than a second difference in recess depth between the first contact plug and the second contact plug.

3. The device according to claim 2, wherein, The first difference ranges from 0.1 nm to 5 nm, and the second difference ranges from 3 nm to 10 nm.

4. The device according to claim 1, wherein, The recess depth of the contact plugs ranges from 0.1 nm to 35 nm.

5. The device according to claim 1, wherein, A first total change in recess depth of the contact plugs on the first stack is different from a second total change in recess depth of the contact plugs on the second stack, The first total change corresponds to the difference between the maximum value and the minimum value of the recess depth of the contact plugs on the first stack, and The second total change corresponds to the difference between the maximum value and the minimum value of the recess depth of the contact plugs on the second stack.

6. The device according to claim 5, wherein, The second total change is less than the first total change.

7. The device according to claim 1, wherein, The contact plugs include: A plurality of first contact plugs on the connection region and respectively coupled to the conductive patterns of the first stack, the recess depths of the first contact plugs varying monotonically in the first direction; and A plurality of second contact plugs on the connection region and respectively coupled to the conductive patterns of the second stack, the recess depths of the second contact plugs varying monotonically in the first direction, Wherein, the recess depths of adjacent contact plugs among the first contact plugs and the second contact plugs vary in a monotonic manner different from the monotonic variation of the recess depth of the first contact plugs.

8. The device according to claim 7, wherein, The bottom surface of the first contact plug coupled to the top conductive pattern of the first stack is at a first recess depth from the top surface of the top conductive pattern of the first stack, and the bottom surface of the second contact plug coupled to the bottom conductive pattern of the second stack is at a second recess depth from the top surface of the bottom conductive pattern of the second stack, and the second recess depth is less than the first recess depth.

9. The device according to claim 8, wherein, The bottom surface of the first contact plug coupled to the bottom conductive pattern of the first stack is at a third recess depth from the top surface of the bottom conductive pattern of the first stack, and the third recess depth is less than the first recess depth, the bottom surface of the second contact plug coupled to the top conductive pattern of the second stack is at a fourth recess depth from the top surface of the top conductive pattern of the second stack, and the fourth recess depth is less than the second recess depth, a first total change in the recess depth of the contact plugs on the first stack is different from a second total change in the recess depth of the contact plugs on the second stack, the first total change corresponds to the difference between the first recess depth and the third recess depth, and the second total change corresponds to the difference between the second recess depth and the fourth recess depth.

10. The device according to claim 7, wherein, The first contact plug has a first average upper diameter, and the second contact plug has a second average upper diameter different from the first average upper diameter.

11. The device according to claim 7, wherein, Each of the first contact plug and the second contact plug includes an upper portion having a first diameter and a lower portion having a second diameter different from the first diameter, the sidewall profile of each of the first contact plug and the second contact plug has a varying slope and an inflection point located at the boundary between the upper portion and the lower portion, and the height of the upper portion of the first contact plug is different from the height of the upper portion of the second contact plug.

12. The device according to claim 1, further comprising: a planarized insulating layer covering the stepped structure of the stack; and a horizontal barrier insulating layer covering the top and bottom surfaces of each conductive pattern, wherein, on the connection region, a portion of the horizontal barrier insulating layer is in direct contact with the planarized insulating layer.

13. The device according to claim 12, wherein, The planarized insulating layer has a flat top surface on the cell array region and the connection region and has a decreasing thickness in a direction from the connection region to the cell array region.

14. The device according to claim 1, wherein, The stack further includes a third stack including third conductive patterns vertically stacked on the second stack, the contact plug further includes upper contact plugs on the connection region and respectively coupled to the third conductive patterns, when measured from the top surface of a corresponding one of the third conductive patterns, the recess depth of each upper contact plug varies monotonically in the first direction, a first total change in the recess depth of the contact plugs on the first stack is different from a second total change in the recess depth of the contact plugs on the second stack, the second total change is less than the first total change and a third total change in the recess depth of the upper contact plugs, The first total variation corresponds to the difference between the maximum and minimum values of the depression depth of the contact plugs on the first stack, the second total variation corresponds to the difference between the maximum and minimum values of the depression depth of the contact plugs on the second stack, and the third total variation corresponds to the difference between the maximum and minimum values of the depression depth of the contact plugs on the third stack.

15. The device according to claim 14, wherein, the bottom surface of the first contact plug coupled to the uppermost conductive pattern of the first stack is at a first depression depth, which is measured from the top surface of the uppermost conductive pattern of the first stack, the bottom surface of the second contact plug coupled to the lowermost conductive pattern of the second stack is at a second depression depth greater than the first depression depth, which is measured from the top surface of the lowermost conductive pattern of the second stack, the bottom surface of the second contact plug coupled to the uppermost conductive pattern of the second stack is at a third depression depth less than the second depression depth, which is measured from the top surface of the uppermost conductive pattern of the second stack, and the bottom surface of one of the upper contact plugs coupled to the lowermost conductive pattern of the third stack is at a fourth depression depth less than the third depression depth, which is measured from the top surface of the lowermost conductive pattern of the third stack.

16. The device according to claim 14, wherein, The upper contact plugs include: a first upper contact plug coupled to the lowermost conductive pattern of the third stack; a second upper contact plug coupled to the uppermost conductive pattern of the third stack; and a third upper contact plug coupled to one of the third conductive patterns between the lowermost and uppermost conductive patterns of the third stack, wherein the depression depth of the third upper contact plug is greater than the average depression depth of the first upper contact plug and the second upper contact plug.

17. A three-dimensional semiconductor memory device, comprising: a substrate including a cell array region and a connection region; a stack including a first stack and a second stack sequentially stacked on the substrate, the stack having a stepped structure on the connection region, and each of the first stack and the second stack including insulating patterns and conductive patterns vertically and alternately stacked on the substrate; a planarization insulating layer covering the stepped structure of the stack and having a flat top surface, and a part of the insulating pattern is in direct contact with the planarization insulating layer; a first contact plug on the connection region and penetrating the planarization insulating layer, and respectively coupled to the conductive patterns of the first stack; and a second contact plug on the connection region and respectively coupled to the conductive patterns of the second stack, wherein the bottom surface of each of the first contact plug and the second contact plug is located between the top surface and the bottom surface of a corresponding one of the conductive patterns, the depression depth of each of the first contact plugs varies monotonically in the stacking direction of the conductive patterns, and the depression depth is measured from the top surface of a corresponding one of the conductive patterns of the first stack, The depression depth of each of the second contact plugs varies monotonically in the stacking direction of the conductive patterns, the depression depth being measured from the top surface of the corresponding one of the conductive patterns of the second stack, and the depression depth changes of adjacent contact plugs among the first contact plugs and the second contact plugs have a bend, the depression depths of the adjacent contact plugs among the first contact plugs and the second contact plugs being measured from the top surface of the corresponding one of the conductive patterns.

18. The device according to claim 17, wherein, A first difference between the depression depths of adjacent first contact plugs among the first contact plugs is less than a second difference between the depression depths of adjacent contact plugs among the first contact plugs and the second contact plugs.

19. The device according to claim 18, wherein, The first difference ranges from 0.1 nm to 5 nm, and the second difference ranges from 3 nm to 10 nm.

20. The device according to claim 17, wherein, The depression depths of the first contact plugs and the second contact plugs range from 0.1 nm to 35 nm.

21. The device according to claim 17, wherein The planarized insulating layer comprises a single material.

22. The device according to claim 17, wherein The planarized insulating layer has a decreasing thickness in a direction from the connection region to the cell array region.

23. The device according to claim 17, wherein, The bottom surface of one of the first contact plugs coupled to the uppermost conductive pattern of the first stack is at a first depression depth, the first depression depth being measured from the top surface of the uppermost conductive pattern of the first stack, and the bottom surface of one of the second contact plugs coupled to the lowermost conductive pattern of the second stack is at a second depression depth, the second depression depth being measured from the top surface of the lowermost conductive pattern of the second stack, the second depression depth being less than the first depression depth.

24. The device according to claim 17, wherein, The first total change in the depression depth of the first contact plugs is different from the second total change in the depression depth of the second contact plugs.

25. A three-dimensional semiconductor memory device, comprising: a substrate including a cell array region and a connection region; a stack including a first stack, a second stack, and a third stack sequentially stacked on the substrate, the stack having a stepped structure on the connection region, each of the first stack, the second stack, and the third stack including insulating patterns and conductive patterns vertically and alternately stacked on the substrate; and contact plugs respectively connected to the conductive patterns of the stack, wherein the bottom surface of each of the contact plugs is between the top surface and the bottom surface of the corresponding one of the conductive patterns, the contact plugs include: a first contact plug coupled to the uppermost conductive pattern of the first stack, a second contact plug coupled to the lowermost conductive pattern of the first stack, a third contact plug coupled to the uppermost conductive pattern of the second stack, a fourth contact plug coupled to the lowermost conductive pattern of the second stack, a fifth contact plug coupled to the uppermost conductive pattern of the third stack, and a sixth contact plug coupled to the lowermost conductive pattern of the third stack, and The difference between the recess depths of the bottom surfaces of the third contact plug and the fourth contact plug is less than the difference between the recess depths of the bottom surfaces of the first contact plug and the second contact plug or the difference between the recess depths of the bottom surfaces of the fifth contact plug and the sixth contact plug, wherein each of the recess depths is measured from the top surface of the corresponding one of the conductive patterns.

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