Operational Amplifier Circuit

Abstract

An operational amplifier circuit includes: an input stage circuit for receiving an input voltage signal; a gain stage circuit coupled to the input stage circuit; an output stage circuit coupled to the gain stage circuit for providing an output voltage signal; a compensation circuit coupled to the input stage circuit and the output stage circuit; and a feedforward capacitor circuit coupled to the output stage circuit and the gain stage circuit. The output stage circuit includes a P-type output transistor and an N-type output transistor, and the drains of the P-type output transistor and the N-type output transistor are connected together; the feedforward capacitor circuit includes a first capacitor and a second capacitor, which are used to drive the gain stage circuit to quickly turn on the P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal rises instantly, and to drive the gain stage circuit to quickly turn on the N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage signal drops instantly.

Description

Technical Field

[0001] The present invention relates to an operational amplifier circuit, and more particularly to an amplifier circuit with a feedforward capacitor for accelerating transient response speed. Background Art

[0002] In today's flat panel displays, an operational amplifier (OP) is usually used as a source driver to drive the data line. An input voltage signal representing a color is applied to the non-inverting input terminal and the inverting input terminal of the operational amplifier. After differential amplification by the operational amplifier, the amplified color signal is transmitted to the flat panel display such as an LCD panel through the data line for display operation.

[0003] As the current display is developing towards high resolution and large area, the resistance and capacitance of the source drive operational amplifier load are also increasing. Under the limited area and power consumption of the source drive operational amplifier, its instantaneous response speed is also limited. However, due to the rapid progress of industry today, the requirements for display resolution and panel size have also increased dramatically, resulting in a faster requirement for the instantaneous response speed of the source drive operational amplifier, while avoiding increasing the overall static power consumption.

[0004] However, the existing operational amplifier cannot speed up its instantaneous response speed without increasing static power consumption, and thus it is difficult to meet the requirements of today's displays for high resolution and low static power consumption. Therefore, it is still necessary to improve it. Summary of the invention

[0005] The main purpose of the present invention is to provide an operational amplifier circuit, which accelerates the transient response of the operational amplifier output by adding a feedforward capacitor without increasing the static power consumption of the entire operational amplifier.

[0006] To achieve the aforementioned objectives, the present invention provides an operational amplifier circuit, comprising: an input stage circuit, receiving an input voltage signal; a gain stage circuit, coupled to the input stage circuit; an output stage circuit, coupled to the gain stage circuit, providing an output voltage signal, wherein the output stage circuit comprises a P-type output transistor and an N-type output transistor, and the drains of the P-type output transistor and the N-type output transistor are connected together; a compensation circuit, coupled to the input stage circuit and the output stage circuit; and a feed-forward capacitor circuit, coupled to the output stage circuit and the gain stage circuit, wherein the feed-forward capacitor circuit comprises a first capacitor and a second capacitor, for driving the gain stage circuit to quickly turn on the P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal rises instantaneously, and for driving the gain stage circuit to quickly turn on the N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage signal drops instantaneously.

[0007] The above summary and the following detailed description are exemplary in nature and are intended to further illustrate the claims of the present invention. Other objects and advantages of the present invention will be described in the subsequent description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an operational amplifier circuit of the present invention.

[0009] Figure 2 A circuit diagram showing a first embodiment of an operational amplifier circuit of the present invention.

[0010] Figure 3 A circuit diagram showing a second embodiment of the operational amplifier circuit of the present invention.

[0011] Figure 4 A simulation example of the operational amplifier circuit of the present invention is shown.

[0012] Figure 5 A schematic diagram showing a third embodiment of an operational amplifier circuit of the present invention.

[0013] Explanation of symbols:

[0014] Input stage circuit 11 Gain stage circuit 13

[0015] Compensation circuit 15 Output stage circuit 17

[0016] Feedforward capacitor circuit 19

[0017] The first current mirror 111 and the second current mirror 112

[0018] P-type differential input circuit 113 N-type differential input circuit 114

[0019] First active load 115 Second active load 116

[0020] Input voltage signal VIN,VIP Output voltage signal Vout

[0021] NMOS transistors 1151 to 1154 PMOS transistors 1161 to 1164

[0022] Node VP2 Node VN2

[0023] First gain circuit 131 Second gain circuit 132

[0024] Floating Class AB Control Circuit 133

[0025] PMOS transistors 1311, 1312 NMOS transistors 1321, 1322

[0026] Node VP1 Node VN1

[0027] The first compensation capacitor 151 and the second compensation capacitor 152

[0028] P-type output transistor 171 N-type output transistor 172

[0029] The first capacitor 191 and the second capacitor 192

[0030] The third capacitor 193 and the fourth capacitor 194

[0031] First component 195 Second component 196

[0032] Third component 197 Fourth component 198

[0033] Gate connection PP Gate connection NN

[0034] The first current mirror 211 and the second current mirror 212

[0035] Rail-to-rail differential input circuit 213

[0036] Input voltage signal INP, INN

[0037] PMOS transistors 2131, 2132 NMOS transistors 2133, 2134

[0038] First gain circuit 231 Second gain circuit 232

[0039] Floating Class AB Control Circuit 233

[0040] PMOS transistors 2311, 2312 NMOS transistors 2321, 2322

[0041] The first compensation capacitor 251 and the second compensation capacitor 252

[0042] P-type output transistor 271 N-type output transistor 272

[0043] First capacitor 291 Second capacitor 292

[0044] First component 295 Second component 296

[0045] Operational amplifier 41,51 Load 43

[0046] Measuring point MP Auxiliary operational amplifier 52

[0047] Waveform 53,55,57 DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0049] Figure 1 1 is a block diagram of an operational amplifier circuit of the present invention, wherein the operational amplifier circuit includes an input stage circuit 11, a gain stage circuit 13, a compensation circuit 15, an output stage circuit 17 and a feed-forward capacitor circuit 19. As shown in the figure, the input stage circuit 11 receives an input voltage signal, the gain stage circuit 13 is coupled to the input stage circuit 11 to increase the output current of the input stage circuit 11, the compensation circuit 15 is coupled to the input stage circuit 11 and the output stage circuit 17, or is further coupled to the gain stage circuit 13, to provide frequency compensation to maintain the stability of the operational amplifier circuit and increase the phase margin, the output stage circuit 17 is coupled to the gain stage circuit 13 to provide a gain output voltage signal, and the feed-forward capacitor circuit 19 is coupled to the output stage circuit 17 and the gain stage circuit 13, or is further coupled to the input stage circuit 11, to detect the output voltage response and use positive feedback to accelerate the transient response speed of the operational amplifier circuit.

[0050] Figure 2The circuit diagram of the first embodiment of the operational amplifier circuit of the present invention is further shown. The operational amplifier of this embodiment is a Class AB operational amplifier. In this embodiment, the input stage circuit 11 includes a first current mirror 111, a second current mirror 112, a P-type differential input circuit 113, an N-type differential input circuit 114, a first active load 115 and a second active load 116, wherein the first current mirror 111, the P-type differential input circuit 113 and the first active load 115 are coupled together in sequence and connected between a power supply voltage (VDD) and a ground voltage (VSS), and the second active load 116, the N-type differential input circuit 114 and the second current mirror 112 are coupled together in sequence and connected between a power supply voltage (VDD) and a ground voltage (VSS); the first current mirror 111 and the second current mirror 112 provide a constant current for circuit operation, wherein the current mirror is a circuit known in circuit design. Figure 2 The current mirror can be formed by two PMOS transistors or two NMOS transistors. The P-type differential input circuit 113 and the N-type differential input circuit 114 are used to receive input voltage signals VIN, VIP, wherein the differential input circuit is a circuit known in circuit design. Figure 2 exemplarily shows that the P-type differential input circuit 113 can be formed by two PMOS transistors, and the N-type differential input circuit 114 can be formed by two NMOS transistors. The first active load 115 and the second active load 116 exhibit a current-stabilizing nonlinear resistance characteristic to serve as a load for the differential input signal, wherein the active load is a circuit known in circuit design. Figure 2 It is exemplarily shown that the first active load 115 can be composed of four NMOS transistors 1151~1154, and the gates of these four NMOS transistors 1151~1154 are all connected to a node VN2, and the gate and drain of the NMOS transistor 1151 are connected together, and the second active load 116 can be composed of four PMOS transistors 1161~1164, and the gates of these four PMOS transistors 1161~1164 are all connected to a node VP2, and the gate and drain of the PMOS transistor 1162 are connected together.

[0051] The gain stage circuit 13 of the present embodiment includes a first gain circuit 131, a second gain circuit 132 and a floating AB class control circuit 133. The first gain circuit 131, the floating AB class control circuit 133 and the second gain circuit 132 are coupled together in sequence and connected between a power supply voltage (VDD) and a ground voltage (VSS). The first gain circuit 131 is used to increase the current output by the second active load 116 of the input stage circuit 11, and the second gain circuit 132 is used to increase the current output by the first active load 115 of the input stage circuit 11, so as to provide a driving current for the operational amplifier. The gain circuit is a circuit known in circuit design. Figure 2 exemplarily shows that the first gain circuit 131 can be composed of two PMOS transistors 1311 and 1312, and the gates of the two PMOS transistors 1311 and 1312 are both connected to the node VP1, and the gate and drain of the PMOS transistor 1311 are connected together, and the second gain circuit 132 can be composed of two NMOS transistors 1321 and 1322, and the gates of the two NMOS transistors 1321 and 1322 are both connected to the node VN1, and the gate and drain of the NMOS transistor 1321 are connected together. The floating AB class control circuit 133 is coupled to the first gain circuit 131 and the second gain circuit 132 to provide a floating current source to drive the first gain circuit 131 and the second gain circuit 132, wherein the floating AB class control circuit is a circuit known in circuit design. Figure 2 FIG. 4 exemplarily shows that the floating class AB control circuit 133 can be composed of four PMOS transistors and four NMOS transistors.

[0052] The compensation circuit 15 of the present embodiment includes a first compensation capacitor 151 and a second compensation capacitor 152, wherein the first compensation capacitor 151 is coupled between the second active load 116 of the input stage circuit 11 and the output stage circuit 17, and the second compensation capacitor 152 is coupled between the first active load 115 of the input stage circuit 11 and the output stage circuit 17. The first compensation capacitor 151 and the second compensation capacitor 152 are used to implement a cascoded Miller frequency compensation scheme. A compensating driving current is provided by using a first compensation capacitor 151 to enhance the phase margin and reduce the oscillation, thereby maintaining the stability of the operational amplifier circuit. As shown in the figure, one end of the first compensation capacitor 151 is connected to the connection point of the drain of the PMOS transistor 1163 of the second active load 116 and the source of the PMOS transistor 1164, and the other end of the first compensation capacitor 151 is connected to the connection point of the drain of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17. One end of the second compensation capacitor 152 is connected to the connection point of the source of the NMOS transistor 1153 of the first active load 115 and the drain of the NMOS transistor 1154, and the other end of the second compensation capacitor 151 is connected to the connection point of the drain of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17.

[0053] The output stage circuit 17 of the present embodiment includes a P-type output transistor 171 and an N-type output transistor 172 coupled together to provide a gained output voltage signal Vout according to a compensated driving current, wherein the output stage circuit 17 is configured as follows: the drain of the P-type output transistor 171 is connected to the drain of the N-type output transistor 172, the gate of the P-type output transistor 171 is connected to the drain of the PMOS transistor 1312 of the first gain circuit 131 and the drain of the PMOS transistor 1164 of the second active load 116, the source of the P-type output transistor 171 is connected to the power supply voltage (VDD), the gate of the N-type output transistor 172 is connected to the drain of the NMOS transistor 1322 of the second gain circuit 132 and the drain of the NMOS transistor 1153 of the first active load 115, and the source of the N-type output transistor 172 is connected to the ground voltage (VSS).

[0054] The feedforward capacitor circuit 19 of the present embodiment includes a first capacitor 191, a second capacitor 192, a third capacitor 193 and a fourth capacitor 194, wherein one end of the first capacitor 191 is connected to the drain connection point of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the first capacitor 191 is connected to the node VP1 of the first gain circuit 131 via a first component 195; one end of the second capacitor 192 is connected to the drain connection point of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the second capacitor 192 is connected to the node VP1 of the first gain circuit 131 via a first component 195. The second component 196 is connected to the node VN1 of the second gain circuit 132; one end of the third capacitor 193 is connected to the drain connection point of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the third capacitor 193 is connected to the node VP2 of the second active load 116 via a third component 197; one end of the fourth capacitor 194 is connected to the drain connection point of the P-type output transistor 171 and the N-type output transistor 172 in the output stage circuit 17, and the other end of the fourth capacitor 194 is connected to the node VN2 of the first active load 115 via a fourth component 198. The first component 195, the second component 196, the third component 197 and the fourth component 198 are impedances in the circuit, which can be wiring, resistors, diodes or metal oxide semiconductors (MOS), etc.

[0055] By means of the first capacitor 191 and the second capacitor 192, when the waveform of the output voltage signal Vout rises instantaneously, the gain stage circuit 13 can be driven to quickly turn on the P-type output transistor 171 of the output stage circuit 17 to charge the output voltage signal Vout, and when the waveform of the output voltage signal Vout drops instantaneously, the gain stage circuit 13 can be driven to quickly turn on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout. In detail, when the waveform of the output voltage Vout rises instantaneously, the high voltage is coupled to the node VP1 via the first capacitor 191 and the first component 195, and is coupled to the node VN1 via the second capacitor 192 and the second component 196, so that the voltage of the node VP1 rises due to voltage coupling, and the voltage of the node VN1 rises due to voltage coupling, causing the PMOS transistor 1312 of the first gain circuit 131 to be turned off, and the NMOS transistor 1322 of the second gain circuit 132 to be turned on, indirectly causing the voltage on the gate connection PP of the P-type output transistor 171 to drop, and the voltage on the gate connection NN of the N-type output transistor 172 to drop, so as to quickly turn on the P-type output transistor 171 of the output stage circuit 17 to charge the output voltage signal Vout, thereby accelerating the rising time of the output voltage signal Vout. On the contrary, when the waveform of the output voltage signal Vout drops instantaneously, since the low voltage is coupled to the node VP1 via the first capacitor 191 and the first component 195, and is coupled to the node VN1 via the second capacitor 192 and the second component 196, the voltage of the node VP1 drops due to voltage coupling, and the voltage of the node VN1 drops due to voltage coupling, causing the PMOS transistor 1312 of the first gain circuit 131 to be turned on, and the NMOS transistor 1322 of the second gain circuit 132 to be turned off, indirectly causing the voltage on the gate connection PP of the P-type output transistor 171 to rise, and the voltage on the gate connection NN of the N-type output transistor 172 to rise, so as to quickly turn on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout, thereby accelerating the time for the output voltage signal Vout to fall.

[0056] Similarly, by means of the third capacitor 193 and the fourth capacitor 194, when the waveform of the output voltage signal Vout rises instantaneously, the input stage circuit 11 can be driven to quickly turn on the P-type output transistor 171 of the output stage circuit 17 to charge the output voltage signal Vout, and when the waveform of the output voltage signal Vout drops instantaneously, the input stage circuit 11 can be driven to quickly turn on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout. In detail, when the waveform of the output voltage Vout rises instantaneously, the high voltage is coupled to the node VP2 via the third capacitor 193 and the third component 197, and is coupled to the node VN2 via the fourth capacitor 194 and the fourth component 198, so that the voltage of the node VP2 rises due to voltage coupling, and the voltage of the node VN2 rises due to voltage coupling, causing the PMOS transistor 1164 of the second active load 116 to be turned off, and the NMOS transistor 1153 of the first active load 115 to be turned on, indirectly causing the voltage on the gate connection PP of the P-type output transistor 171 to drop, and the voltage on the gate connection NN of the N-type output transistor 172 to drop, so as to quickly turn on the P-type output transistor 171 of the output stage circuit 17 to charge the output voltage signal Vout, thereby accelerating the rising time of the output voltage signal Vout. On the contrary, when the waveform of the output voltage signal Vout drops instantaneously, since the low voltage is coupled to the node VP2 via the third capacitor 193 and the third component 197, and is coupled to the node VN2 via the fourth capacitor 194 and the fourth component 198, the voltage of the node VP2 drops due to voltage coupling, and the voltage of the node VN2 drops due to voltage coupling, causing the PMOS transistor 1164 of the second active load 116 to be turned on, and the NMOS transistor 1153 of the first active load 115 to be turned off, indirectly causing the voltage on the gate connection PP of the P-type output transistor 171 to rise, and the voltage on the gate connection NN of the N-type output transistor 172 to rise, so as to quickly turn on the N-type output transistor 172 of the output stage circuit 17 to discharge the output voltage signal Vout, thereby accelerating the time for the output voltage signal Vout to fall.

[0057] In the circuit of the present embodiment, the transient response speed of the operational amplifier can be accelerated by only the first capacitor 191 and the second capacitor 192. However, when the operational amplifier is configured into a unity gain mode, when the difference between the output voltage signal Vout and the input voltage signal VIN,VIP is too large, the input stage circuit 11 and the gain stage circuit 13 will pull each other, resulting in the occurrence of spike interference (glitch) in the output waveform and not smooth. Therefore, the third capacitor 193 and the fourth capacitor 194 are required to accelerate the transient response speed of the operational amplifier at the same time, and the third capacitor 193 and the fourth capacitor 194 are designed to be larger than the first capacitor 191 and the second capacitor 192 to avoid the phenomenon of uneven output voltage.

[0058] Figure 3 is a circuit diagram of a second embodiment of the operational amplifier circuit of the present invention. The operational amplifier of this embodiment is a folded AB class operational amplifier. In this embodiment, the input stage circuit 11 includes a first current mirror 211, a second current mirror 212 and a rail-to-rail differential input circuit 213, wherein the first current mirror 211, the rail-to-rail differential input circuit 213 and the second current mirror 212 are coupled together in sequence and connected between a power supply voltage (VDD) and a ground voltage (VSS); the first current mirror 211 and the second current mirror 212 provide a constant current for circuit operation, wherein the current mirror is a circuit known in circuit design. Figure 3 The current mirror can be formed by a PMOS transistor or an NMOS transistor. The rail-to-rail differential input circuit 213 is used to receive input voltage signals INP, INN, wherein the rail-to-rail differential input circuit is a circuit known in circuit design. Figure 3 exemplarily shows that the rail-to-rail differential input circuit 213 can be composed of two PMOS transistors 2131 , 2132 and two NMOS transistors 2133 , 2134 .

[0059] The gain stage circuit 13 of the present embodiment includes a first gain circuit 231, a second gain circuit 232 and a floating AB class control circuit 233, wherein the first gain circuit 231, the floating AB class control circuit 233 and the second gain circuit 232 are coupled together in sequence and connected between a power supply voltage (VDD) and a ground voltage (VSS). The first gain circuit 231 is used to increase the current outputted by the rail-to-rail differential input circuit 213 of the input stage circuit 11, and the second gain circuit 232 is used to increase the current outputted by the rail-to-rail differential input circuit 213 of the input stage circuit 11, so as to provide a driving current of the operational amplifier. The gain circuit is a circuit known in circuit design. Figure 3exemplarily shows that the first gain circuit 231 can be composed of two PMOS transistors 2311 and 2312, and the gates of the two PMOS transistors 2311 and 2312 are both connected to a node VP1, and the gate and drain of the PMOS transistor 2311 are connected together, and the second gain circuit 231 can be composed of two NMOS transistors 2321 and 2322, and the gates of the two NMOS transistors 2321 and 2322 are both connected to a node VN1, and the gate and drain of the NMOS transistor 2321 are connected together. The floating AB class control circuit 233 is coupled to the first gain circuit 231 and the second gain circuit 232 to provide a floating current source to drive the first gain circuit 231 and the second gain circuit 232, wherein the floating AB class control circuit is a circuit known in circuit design. Figure 3 FIG. 2 exemplarily shows that the floating class AB control circuit 233 may be composed of four PMOS transistors and four NMOS transistors.

[0060] The compensation circuit 15 of the present embodiment includes a first compensation capacitor 251 and a second compensation capacitor 252, wherein the first compensation capacitor 251 is coupled between the rail-to-rail differential input circuit 213 of the input stage circuit 11 and the first gain circuit 231 of the gain stage circuit 13, and the output stage circuit 17, and the second compensation capacitor 252 is coupled between the rail-to-rail differential input circuit 213 of the input stage circuit 11 and the second gain circuit 232 of the gain stage circuit 13, and the output stage circuit 17. A cascoded Miller frequency compensation scheme is implemented by the first compensation capacitor 251 and the second compensation capacitor 252 to provide a compensated driving current, so as to enhance the phase margin and reduce oscillation, thereby maintaining the stability of the operational amplifier circuit. As shown in the figure, one end of the first compensation capacitor 251 is connected to the drain of the NMOS transistor 2133 of the rail-to-rail differential input circuit 213 and the drain of the PMOS transistor 2312 of the first gain circuit 231, and the other end of the first compensation capacitor 251 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17, one end of the second compensation capacitor 252 is connected to the drain of the PMOS transistor 2131 of the rail-to-rail differential input circuit 213 and the drain of the NMOS transistor 2322 of the second gain circuit 232, and the other end of the second compensation capacitor 252 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17.

[0061] The output stage circuit 17 of the present embodiment includes a P-type output transistor 271 and an N-type output transistor 272 coupled together to provide a gained output voltage signal Vout according to a compensated driving current, wherein the output stage circuit 17 is configured as follows: the drain of the P-type output transistor 271 is connected to the drain of the N-type output transistor 272, the gate of the P-type output transistor 271 is connected to the drain of the PMOS transistor 2312 of the first gain circuit 231, the source of the P-type output transistor 271 is connected to the power supply voltage (VDD), the gate of the N-type output transistor 272 is connected to the drain of the NMOS transistor 2322 of the second gain circuit 232, and the source of the N-type output transistor 272 is connected to the ground voltage (VSS).

[0062] The feedforward capacitor circuit 19 of the present embodiment includes a first capacitor 291 and a second capacitor 292, wherein one end of the first capacitor 291 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17, and the other end of the first capacitor 291 is connected to the node VP1 of the first gain circuit 231 via a first component 295; one end of the second capacitor 292 is connected to the drain connection point of the P-type output transistor 271 and the N-type output transistor 272 in the output stage circuit 17, and the other end of the second capacitor 292 is connected to the node VN1 of the second gain circuit 232 via a second component 296. The first component 295 and the second component 296 are impedances in the circuit, which can be wiring, resistors, diodes or metal oxide semiconductors (MOS), etc.

[0063] By means of the first capacitor 291 and the second capacitor 292, when the waveform of the output voltage signal Vout rises instantaneously, the gain stage circuit 13 can be driven to quickly turn on the P-type output transistor 271 of the output stage circuit 17 to charge the output voltage signal Vout, and when the waveform of the output voltage signal Vout drops instantaneously, the gain stage circuit 13 can be driven to quickly turn on the N-type output transistor 272 of the output stage circuit 17 to discharge the output voltage signal Vout. In detail, when the waveform of the output voltage Vout rises instantaneously, the high voltage is coupled to the node VP1 via the first capacitor 291 and the first component 295, and is coupled to the node VN1 via the second capacitor 292 and the second component 296, so that the voltage of the node VP1 rises due to voltage coupling, and the voltage of the node VN1 rises due to voltage coupling, causing the PMOS transistor 2312 of the first gain circuit 231 to be turned off, and the NMOS transistor 2322 of the second gain circuit 232 to be turned on, indirectly causing the voltage on the gate connection PP of the P-type output transistor 271 to drop, and the voltage on the gate connection NN of the N-type output transistor 272 to drop, so as to quickly turn on the P-type output transistor 271 of the output stage circuit 17 to charge the output voltage signal Vout, thereby accelerating the rising time of the output voltage signal Vout. On the contrary, when the waveform of the output voltage signal Vout drops instantaneously, since the low voltage is coupled to the node VP1 via the first capacitor 291 and the first component 295, and is coupled to the node VN1 via the second capacitor 292 and the second component 296, the voltage of the node VP1 drops due to voltage coupling, and the voltage of the node VN1 drops due to voltage coupling, causing the PMOS transistor 2312 of the first gain circuit 231 to be turned on, and the NMOS transistor 2322 of the second gain circuit 232 to be turned off, indirectly causing the voltage on the gate connection PP of the P-type output transistor 271 to rise, and the voltage on the gate connection NN of the N-type output transistor 272 to rise, so as to quickly turn on the N-type output transistor 272 of the output stage circuit 17 to discharge the output voltage signal Vout, thereby accelerating the time for the output voltage signal Vout to fall.

[0064] To prove the excellent effect of the present invention, Hspice simulation software is used to compare the instantaneous response speed with and without the feedforward capacitor. Figure 4 As shown, under the condition that the input voltage signal difference of the operational amplifier is 0.2V~4.8V, a load 43 (RL=20K, CL=200pF) of a fifth-order resistor (R) and a capacitor (C) is added to the output of the operational amplifier 41 to measure the instantaneous response speed of the output from 0.2V to 4.8V. The measurement point MP is the front end of the fifth-order RC that is the percentage (10%~90%, 1%~99%) of the output waveform voltage.

[0065] When the analog operational amplifier 41 is based on Figure 2 When the operational amplifier circuit of the first embodiment is used, the percentage of the measured output voltage is 10% to 90% and 1% to 99%, and the obtained results are shown in Table 1 and Table 2:

[0066] Table 1

[0067]

[0068] Table 2

[0069]

[0070]

[0071] It can be seen from Table 1 and Table 2 that the first embodiment of the present invention can accelerate the transient response speed by 167 to 331 ns when the percentage of the measured output voltage is 10% to 90%, and can accelerate the transient response speed by 95 to 258 ns when the percentage of the measured output voltage is 1% to 99%.

[0072] When the analog operational amplifier 41 is based on Figure 3 When the operational amplifier circuit of the second embodiment is used, the percentage of the measured output voltage is 10% to 90% and 1% to 99%, and the obtained results are shown in Table 3 and Table 4:

[0073] Table 3

[0074]

[0075] Table 4

[0076]

[0077] It can be seen from Table 3 and Table 4 that the second embodiment of the present invention can accelerate the transient response speed by 227-266ns when the percentage of the measured output voltage is 10%-90%, and can accelerate the transient response speed by 222-269ns when the percentage of the measured output voltage is 1%-99%.

[0078] In addition, since the present invention utilizes the coupling phenomenon of the feedforward capacitor to speed up the transient time of the operational amplifier, it has a better effect when the waveform of the input voltage signal is a steep waveform. If the waveform of the input voltage signal is a rounded waveform, then Figure 5As shown, an auxiliary operational amplifier 52 can be added to the input end of the operational amplifier 51 implemented by the operational amplifier circuit of the present invention (that is, the input end of the input stage circuit 11). The auxiliary operational amplifier 52 can calibrate the waveform of the input voltage signal to change the rounded waveform into a steep waveform, thereby exerting the excellent effect of the present invention. For example, if the waveform 53 of the input voltage signal is RC charging and discharging, it can be equivalent to a rounded waveform with two steep line segments. After the waveform calibration of the auxiliary operational amplifier 52, the two steep line segments can be corrected into a corrected waveform 55 with one steep line segment, thereby greatly increasing the coupling amount of the operational amplifier 51 of the feedforward capacitor of the present invention, thereby accelerating the instantaneous response speed of the waveform 57 of the output voltage signal of the operational amplifier 51.

[0079] The above embodiments are merely examples for the convenience of description. The scope of rights claimed by the present invention should be based on the claims, but not limited to the above embodiments.

Claims

1. An operational amplifier circuit, characterized in that: Include: An input stage circuit receives an input voltage signal; a gain stage circuit coupled to the input stage circuit, the gain stage circuit comprising a first gain circuit, a floating AB class control circuit and a second gain circuit coupled together in sequence; an output stage circuit, coupled to the gain stage circuit, providing an output voltage signal, wherein the output stage circuit comprises a P-type output transistor and an N-type output transistor, and the drains of the P-type output transistor and the N-type output transistor are connected together; a compensation circuit coupled to the input stage circuit and the output stage circuit; and A feedforward capacitor circuit is coupled to the output stage circuit and the gain stage circuit, wherein the feedforward capacitor circuit includes a first capacitor and a second capacitor, one end of the first capacitor is connected to the drain connection point of the P-type output transistor and the N-type output transistor, the other end of the first capacitor is connected to a first node of the first gain circuit via a first component, one end of the second capacitor is connected to the drain connection point of the P-type output transistor and the N-type output transistor, and the other end of the second capacitor is connected to a second node of the second gain circuit via a second component, so as to drive the gain stage circuit to quickly turn on the P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal rises instantaneously, and to drive the gain stage circuit to quickly turn on the N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage signal drops instantaneously.

2. The operational amplifier circuit according to claim 1, wherein: The first gain circuit is composed of two PMOS transistors, and the gates of the two PMOS transistors are both connected to the first node. The second gain circuit is composed of two NMOS transistors, and the gates of the two NMOS transistors are both connected to the second node.

3. The operational amplifier circuit according to claim 2, wherein: The input stage circuit includes a first current mirror, a P-type differential input circuit and a first active load coupled together in sequence, and a second active load, an N-type differential input circuit and a second current mirror coupled together in sequence, wherein the second active load is composed of four PMOS transistors, and the gates of the four PMOS transistors are all connected to a third node, and the first active load is composed of four NMOS transistors, and the gates of the four NMOS transistors are all connected to a fourth node.

4. The operational amplifier circuit according to claim 3, wherein: The compensation circuit includes a first compensation capacitor and a second compensation capacitor. The first compensation capacitor is coupled between the second active load and the drain connection point of the P-type output transistor and the N-type output transistor. The second compensation capacitor is coupled between the first active load and the drain connection point of the P-type output transistor and the N-type output transistor.

5. The operational amplifier circuit according to claim 3, wherein: The feed-forward capacitor circuit further includes a third capacitor and a fourth capacitor, which are used to drive the input stage circuit to quickly turn on the P-type output transistor of the output stage circuit to charge the output voltage signal when the waveform of the output voltage signal rises instantaneously, and to drive the input stage circuit to quickly turn on the N-type output transistor of the output stage circuit to discharge the output voltage signal when the waveform of the output voltage drops instantaneously.

6. The operational amplifier circuit according to claim 5, wherein: One end of the third capacitor is connected to the drain connection point of the P-type output transistor and the N-type output transistor, and the other end of the third capacitor is connected to the third node via a third component. One end of the fourth capacitor is connected to the drain connection point of the P-type output transistor and the N-type output transistor, and the other end of the fourth capacitor is connected to the fourth node via a fourth component.

7. The operational amplifier circuit according to claim 3, wherein: The gate of the P-type output transistor is connected to the drain of a PMOS transistor of the first gain circuit and the drain of a PMOS transistor of the second active load, and the gate of the N-type output transistor is connected to the drain of an NMOS transistor of the second gain circuit and the drain of an NMOS transistor of the first active load.

8. The operational amplifier circuit according to claim 6, wherein: The first component, the second component, the third component and the fourth component include wiring, resistors, diodes or metal oxide semiconductors (MOS).

9. The operational amplifier circuit according to claim 2, wherein: The input stage circuit includes a first current mirror, a rail-to-rail differential input circuit and a second current mirror coupled together in sequence.

10. The operational amplifier circuit according to claim 9, wherein: The compensation circuit includes a first compensation capacitor and a second compensation capacitor. The first compensation capacitor is coupled between the rail-to-rail differential input circuit and the first gain circuit, and the drain connection point of the P-type output transistor and the N-type output transistor. The second compensation capacitor is coupled between the rail-to-rail differential input circuit and the second gain circuit, and the drain connection point of the P-type output transistor and the N-type output transistor.

11. The operational amplifier circuit according to claim 9, wherein: The gate of the P-type output transistor is connected to the drain of a PMOS transistor of the first gain circuit, and the gate of the N-type output transistor is connected to the drain of an NMOS transistor of the second gain circuit.

12. The operational amplifier circuit according to claim 9, wherein: The first component and the second component include wiring, resistors, diodes or metal oxide semiconductors (MOS).

13. The operational amplifier circuit according to claim 1, wherein: It also includes an auxiliary operational amplifier, which is arranged at the input end of the input stage circuit.

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