Calibrating an interpolating divider using a virtual phase-locked loop

Abstract

The present invention discloses a clock generator including an interpolation divider, which includes a phase interpolator and a multi-mode divider. The interpolation divider is configured to generate an output clock signal based on a clock signal, a control code and a phase interpolator calibration signal. The clock generator includes a calibration circuit, which is configured to generate a phase interpolator calibration signal based on a clock signal, an output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop, which is configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate a phase interpolator calibration signal based on the digital phase error signal.

Description

Technical Field

[0001] The present invention relates to generating clock signals for electronic devices, and more particularly, to generating clock signals using interpolative dividers. Background Art

[0002] A typical clock generator utilizes a phase-locked loop provided with a reference signal from a source such as a crystal oscillator to generate an output clock signal having a frequency consistent with a target application. A technique for generating a clock signal having a frequency that is not reasonably related to the frequency of a reference clock signal uses an interpolation divider to divide the high-frequency clock signal by a fraction. The interpolation divider includes an integer divider, a phase interpolator, and a digital control circuit. The gain error of the phase interpolator can cause a mismatch between the size of the least-significant bit of the integer divider and the full-scale range of the phase interpolator. Therefore, a technique for calibrating a phase interpolator and an integer divider is desired to reduce the gain error interpolation of the phase interpolator. Summary of the invention

[0003] In at least one embodiment of the present invention, the clock generator includes an interpolation divider, which includes a phase interpolator and a multi-mode divider. The interpolation divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit, which is configured to generate a phase interpolator calibration signal based on the clock signal, the output clock signal, and the phase interpolator code. The calibration circuit includes a phase-locked loop, which is configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate a phase interpolator calibration signal based on the digital phase error signal.

[0004] In at least one embodiment of the present invention, a method includes generating an output clock signal using an interpolation divider in response to a clock signal, a control code, and a phase interpolator calibration signal. The method includes generating a phase interpolator calibration signal based on the clock signal, the output clock signal, and the phase interpolator code. Generating the phase interpolator calibration signal includes generating a digital phase error signal based on a reference timestamp signal and generating a timestamp signal based on the clock signal and the output clock signal. Generating the phase interpolator calibration signal includes adjusting the phase interpolator calibration signal based on the digital phase error signal.

[0005] In at least one embodiment of the invention, a method includes generating an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The method includes generating a digital error signal based on a downsampled version of the output clock signal and an estimated version of the downsampled version of the output clock signal. The method includes using a minimum mean square filter to generate a phase interpolator calibration signal based on the digital error signal and the phase interpolator control code. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0007] Figure 1 A functional block diagram of an exemplary clock product is shown.

[0008] Figure 2 A functional block diagram of an exemplary clock generator is shown.

[0009] Figure 3 A functional block diagram of an exemplary interpolating divider is shown.

[0010] Figure 4 A functional block diagram of an exemplary clock generator consistent with at least one embodiment of the present invention is shown, the exemplary clock generator including an interpolating divider and a calibration circuit including a virtual phase-locked loop.

[0011] Figure 5 A functional block diagram of a portion of an exemplary clock generator including an interpolating divider and a calibration circuit is shown consistent with at least one embodiment of the present invention.

[0012] Figure 6 A detailed functional block diagram of a portion of an exemplary clock generator including an interpolating divider and a calibration circuit consistent with at least one embodiment of the present invention is shown.

[0013] Figure 7 Exemplary waveforms for calibrating a circuit consistent with at least one embodiment of the present invention are shown.

[0014] Figure 8 A functional block diagram of a portion of an exemplary clock generator including multiple output interpolation dividers and a shared calibration circuit is shown consistent with at least one embodiment of the present invention.

[0015] Fig. 9 A functional block diagram of a portion of an exemplary clock generator including multiple output interpolation dividers and a shared calibration circuit is shown consistent with at least one embodiment of the present invention.

[0016] The use of the same reference symbols in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0017] Reference Figure 1 , an embodiment of the clock product 100 includes a controller 102 and a clock generator 104, which monitors at least one received clock signal (e.g., CLKIN (P: 1)) using a clock signal REFCLK (e.g., a clock signal generated using a crystal oscillator including an external crystal 101 coupled to an XA / XB input terminal) and provides at least one output clock signal CLKOUT (N: 1) and at least one clock quality signal, where P and N are integers greater than zero. In an embodiment of the clock product 100, the clock signal REFCLK is generated based on a stable source such as a crystal oscillator, a microelectromechanical structure (MEMS) oscillator, or other suitable low-jitter source. The controller 102 provides configuration information to the clock generator 104 using an interface signal CTL. The clock generator 104 provides clock quality information (e.g., LOS XA_XB or CLK_STATUS) to the controller 102, and the controller 102 outputs one or more alarm signals (e.g., CLK_FAULT) based on the clock quality information.

[0018] Reference Figure 2 , the clock generator 204 includes a phase-locked loop 110, which is used to generate an input clock signal CLKVCO based on a clock signal REFCLK. The phase-locked loop 110 includes a phase / frequency detector 112, which generates a phase difference signal based on the clock signal REFCLK and a feedback signal provided by a feedback divider 118. The phase / frequency detector 112 provides the phase difference signal to a voltage-controlled oscillator 116 via a loop filter 114. The voltage-controlled oscillator 116 can be implemented as a ring oscillator, an LC oscillator, or other suitable oscillator structure. The input clock signal CLKVCO has a frequency based on the clock signal REFCLK and the frequency of FBDIV1.

[0019] In an embodiment of the clock generator 204, the phase-locked loop 110 provides the clock signal CLKVCO to the output interpolation divider 166, which is configured as a digitally controlled oscillator. The output interpolation divider 166 generates the output clock signal CLKOUT based on the input clock signal CLKVCO and the control signal (e.g., the filtered phase difference signal OL_OUT). The external phase-locked loop 130 generates the filtered phase difference signal OL_OUT, which is a control code, and the output interpolation divider 166 uses it as a fractional divider ratio N. The external phase-locked loop 130 uses the phase detector 136, the loop filter 138, and the feedback divider 140 to lock to the input clock signal CLKIN to generate a filtered phase difference signal OL_OUT that is updated at a frequency based on the input clock signal CLKIN and FBDIV2.

[0020] Figure 3 An exemplary embodiment of the output interpolation divider 166 is shown. The digital control circuit 302 generates a digital control signal for the analog circuit 304 of the output interpolation divider 166 based on the filtered phase difference signal OL_OUT, which may be non-integer. The analog circuit 304 includes a multi-mode divider 306 and a phase interpolator 308. The digital control circuit 302 generates a sequence of corresponding control codes DIVCODE and PICODE that control the multi-mode divider 306 and the phase interpolator 308, respectively. In one embodiment, the digital control circuit 302 includes a first order deltasignal modulator that generates an integer stream that approximates the filtered phase difference signal OL_OUT. Therefore, the digital control circuit 302 provides the integer portion of the filtered phase difference signal OL_OUT to the multi-mode divider 306 and provides the digital quantization error as the control code PICODE to the phase interpolator 308. In one embodiment, the multi-mode divider 306 is an integer divider that inverts the integer of the corresponding edge of the input clock signal CLKVCO before generating the corresponding output edge of the divided clock signal FDIVCLK, as indicated by the digital control code DIVCODE. The phase interpolator 308 interpolates between the divided clock signal FDIVCLK and one or more delayed versions of the divided clock signal FDIVCLK (e.g., one or more equally divided phases of the divided clock signal FDIVCLK, equally divided by the entire period of the input clock CLKVCO) based on the control code PICODE corresponding to the phase error using techniques well known in the art.

[0021] In at least one embodiment, the phase interpolator 308 delays the divided clock signal FDIVCLK by selecting a phase from 256 equally spaced divided clock signals according to the value of the control code PICODE. For example, the control code PICODE may have F bits (e.g., F=8), which corresponds to P=2 F (e.g., P=256) different PICODEs i (e.g., 0≤i≤P-1), which corresponds to P different delay values. P-1 ) introduces a maximum delay, which corresponds to a target maximum delay of almost one period of the input clock signal CLKVCO (e.g., a delay of 255 / 256×the period of the input clock signal CLKVCO). The target delay increment (i.e., the delay difference between consecutive PICODEs, e.g., the control code PICODE i With control code PICODE i+1 The delay difference between <PICODE i <PICODE p-1 ) is one period of the input clock signal CLKVCO divided by P. An exemplary interpolation divider is further described in U.S. Patent No. 7,417,510, entitled “Direct Digital Interpolation Synthesis,” filed on October 17, 2006, which names Yunteng Huang as the inventor, the entire contents of which are incorporated herein by reference.

[0022] In at least one embodiment of the phase interpolator 308, the target performance is achieved by converting the phase interpolator code into analog phase interpolator control signals using a current digital-to-analog converter. In at least one embodiment, a first-order noise shaping dynamic element matching encoding technique is used to convert the control code PICODE, which may be periodic, into a plurality of digital control signals provided to the analog circuit 304. The analog circuit 304 includes a digital-to-analog converter that converts those control signals into separate analog control signals and provides the analog control signals to the current sources in the phase interpolator 308.

[0023] In one embodiment, the phase interpolator 308 generates a plurality of equally spaced phases of the divided clock signal FDIVCLK and interpolates appropriate phases of these phases to generate the output clock signal CLKOUT. Such techniques are well known in the art. Other interpolator implementations may be used based on factors such as required accuracy, power factor, design complexity, available chip area, and the number of bits used to represent digital quantization errors.

[0024] If the actual delay generated by the PICODE-to-delay conversion does not correspond to the target delay of the PICODE-to-delay conversion, the performance of the clock generator may be degraded (e.g., the output clock signal CLKOUT has phase noise and spurs). Figure 4 The clock generator 500 implements a calibration technique that reduces or eliminates the effect of a mismatch between the size of the least significant bit of the multi-mode divider and the range of the phase interpolator to reduce phase noise and spurs in the output clock signal CLKOUT. The calibration technique digitizes the time corresponding to the edge of the downsampled output clock signal CLKOUT to generate a digital time code (e.g., a time stamp) TSTMP.

[0025] In at least one embodiment, the time-to-digital converter 318 generates a digital time code that represents the edge times of a reference clock signal derived from the same source (e.g., generated by the fractional divider 310 based on the input clock signal CLKVCO), although other embodiments use different reference clock signals to generate the digital time code. The time-to-digital converter 318 provides the timestamp signal to the virtual phase-locked loop 312 in the calibration circuit 370. The calibration circuit 370 includes a virtual phase-locked loop 312 (i.e., a digital phase-locked loop) that generates a reference signal and uses the reference signal to generate a phase error signal. The calibration circuit 370 includes a minimum mean square loop 320, which is an adaptive loop that uses the phase error signal to generate the calibration control code PIGAIN.

[0026] Reference Figure 5, the virtual phase-locked loop 312 estimates the digital time signal TSTMP_EST, which is a feedback reference signal without spurious. The virtual phase-locked loop 312 uses the feedback reference signal to generate a digital phase error signal ERROR. The virtual phase-locked loop 312 provides the digital phase error signal ERROR to the minimum mean square loop 320. The minimum mean square loop 320 associates the digital phase error signal ERROR with the control code PICODE. The minimum mean square loop 320 adapts (ie, adjusts) the calibration control code PIGAIN until the error is zero. In at least one embodiment, the analog output interpolation divider 340 includes a phase interpolator that adjusts the gain of the phase interpolator according to the calibration control code PIGAIN. In at least one embodiment of the clock generator 500, the digital-to-analog converter generates a calibration current according to the calibration control code PIGAIN, and can be combined with the current generated by the phase interpolator based on the control code PICODE. In at least one embodiment, the output interpolation divider 166 adjusts the control code provided to the phase interpolator until the gain error is zero. Any suitable gain adjustment technique can be used. In at least one embodiment of the clock generator 500, the frequency of the input clock signal CLKVCO is much greater (i.e., at least one order of magnitude greater) than the frequency of the output clock signal CLKOUT. For example, the frequency of the input clock signal CLKVCO is 13 GHz, the frequency of the output clock signal CLKOUT is 100 MHz, the resolution of the control code PICODE is 300 femtoseconds, and the calibration control code PIGAIN corresponds to a delay in femtoseconds.

[0027] Reference Figure 4-6 In at least one embodiment, the virtual phase-locked loop 312 includes a digital phase detector that receives a digital time code and provides a digital time error code. The virtual phase-locked loop 312 is a type II digital phase-locked loop including separate proportional and integral paths. The virtual phase-locked loop 312 operates at a clock rate of the downsampled output clock signal CLKOUT (e.g., at a clock rate of 6 MHz or other rates less than 100 MHz). The virtual phase-locked loop 312 is updated when a new value of the digital time code TSTMP is available. The z-domain representation of the exemplary virtual phase-locked loop 312 includes a digital phase detector 702 (e.g., a digital summing circuit).

[0028] In at least one embodiment, the virtual phase-locked loop 312 has a data path size of 32 bits, of which 8 bits are integer bits and 24 bits are fractional bits. The binary point is aligned with the binary point of the time-to-digital converter 318. Hatched summing circuits (e.g., circuit 710) are non-saturating summing circuits that facilitate processing less than all bits of the digital time code TSTMP. The virtual phase-locked loop 312 uses only 19 of the 44 bits received from the time-to-digital converter 318 and ignores additional integer bits (e.g., most-significant bits). The digital values ​​received by the virtual phase-locked loop 312 wrap around. The calculations of the virtual phase-locked loop 312 generate additional data path fractional bits (e.g., least significant bits). Portions of the digital time code received by the digital phase detector 702 and provided by the virtual phase-locked loop 312 wrap around (i.e., repeat or flip) over time. Reference Figure 4 , Figure 6 and Figure 7 When a wrap event is not aligned (e.g., the flip of the digital time code TSTMP and the flip of the estimated digital time code TSTMP_EST are not aligned), the virtual phase-locked loop 312 generates a large error signal (e.g., a pulse in the digital phase error signal PRE_VPLL_ERROR). In at least one embodiment, the wrap detection and correction circuit 720 compensates for the wrap error in the digital phase error signal PRE_VPLL_EST and generates a corrected digital phase error signal NXT_VPLL_ERROR, which is stored in the status register VPLL_ERROR_D1[n]. For example, the wrap detection and correction circuit 720 compares the digital phase error signal PRE_VPLL_ERROR with a previous value of the digital phase error signal PRE_VPLL_ERROR. If the current value substantially exceeds the previous value (e.g., exceeds a predetermined amount), the wrap detection and correction circuit 720 compensates the value of the digital phase error signal PRE_VPLL_ERROR and provides the compensated value as the digital phase error signal NXT_VPLL_ERROR. Otherwise, the wrap detection and correction circuit 720 provides the digital phase error signal PRE_VPLL_ERROR as the digital phase error signal NXT_VPLL_ERROR.

[0029] The virtual phase-locked loop 312 includes a proportional loop filter with a gain K P (stored in the corresponding register K P [n]) and a digital loop filter 704 having a gain of K I (stored in the corresponding register K I[n]) and the z-domain representation:

[0030]

[0031] The output of the digital loop filter 704 drives a digitally controlled oscillator 708, which has a gain K V (stored in the corresponding register K V [n]), and has a z-domain representation:

[0032]

[0033] Integrator 714 has a z-domain representation:

[0034]

[0035] And according to the edge of the downsampled version of the output clock signal CLKOUT (e.g., the output of the divider 316), a free-running period estimate is used to program to generate the expected time code with the same period as the digital time code TSTMP. In at least one embodiment, the free-running period estimate is:

[0036]

[0037] Where N is the division ratio of the interpolation divider, such as the filtered phase difference signal OL_OUT provided to the output interpolation divider 166. In at least one embodiment of the virtual phase-locked loop 312, the register FRPE[n] stores the predetermined value to reduce the computational requirements. The target period of the digital time code TSTMP is known because the frequency configuration of the output interpolation divider 166 is known. Instead of using this frequency configuration information, a free-running period estimate can be generated by taking the difference between the first two values ​​of the digital time code TSTMP.

[0038] Circuit 710 generates a predicted next time code, an estimated digital time code TSTMP_EST, in response to capturing the value of the free-running oscillator signal using the output of the digitally controlled oscillator 708. Virtual phase-locked loop 312 provides the phase error signal ERROR to the least mean square loop 320. The least mean square loop 320 multiplies the control code PICODE by the phase error signal ERROR and accumulates the obtained product. The extractor 314 downsamples the accumulated, obtained product (e.g., multiplied by 128) and provides the extracted signal as the calibration control code PIGAIN. In at least one embodiment of the virtual phase-locked loop 312, the wraparound frequency of the intermediate signal within the virtual phase-locked loop 312 increases as the number of integer bits used decreases.

[0039] Circuit 710 combines the output of the digitally controlled oscillator 708 with the ideal period estimate to generate a timestamp estimate TSTMP_EST (i.e., an estimated digital clock signal) and feeds it back to the digital phase detector 702. In at least one embodiment of the virtual phase-locked loop 312, when the control circuit first enables the virtual phase-locked loop 312, the control circuit also initializes the integrator 714 with the first value of the digital time code TSTMP to generate an approximate phase alignment. The virtual phase-locked loop 312 is given a time lock. The control circuit then enables the minimum mean square loop 320 within the amount of time required to converge to the correct value. The control circuit configures the minimum mean square loop 320 with a high gain to adapt quickly, but reduces the gain during calibration to reduce noise. The virtual phase-locked loop 312 then corrects rounding errors in the free-running period estimate calculation, or tracks changes in the frequency configuration of the output interpolation divider 166. In some embodiments, the gain in the virtual phase-locked loop 312 is stored in a register ( Figure 6 ), and is programmable to achieve flexible bandwidth and zero position. The type II topology of the virtual phase-locked loop 312 makes the average value of the error signal VPLL_ERROR_D1[n] zero. Therefore, the minimum mean square loop 320 does not introduce adaptive bias. The control circuit configures the minimum mean square loop 320 with minimum gain to average the quantization error in the input time code TSTMP over the entire range of the phase interpolator.

[0040] Calibration can be performed in foreground or background mode. The control circuit selects the downsampling rate and the bandwidth of the virtual phase-locked loop to correctly perform the calibration cycle in the foreground operation mode. In an embodiment of the digital control circuit 302 using a first-order delta-sigma (ΔΣ, integral-differential) modulator to control the multi-mode divider 306, the control code PICODE received by the phase interpolator 308 is a sawtooth wave, which may appear due to aliasing. Therefore, any gain error will also appear as a corresponding sawtooth wave based on the digital time code TSTMP. In order to perform proper calibration, the bandwidth of the virtual phase-locked loop 312 is less than the fundamental frequency of the sawtooth wave to ensure that the virtual phase-locked loop 312 does not track the gain error. The fundamental frequency of the error can be controlled by setting the fractional part x of the interpolation divider and the downsampling rate M. The downsampling rate M is set to control the output frequency of the divider 316 within the functional range of the time digital converter 318. The output frequency of the divider 316 also sets the reference rate of the virtual phase-locked loop 312 and the update rate of the minimum mean square loop 320, thereby determining the time required for calibration. Set x = N / 2 B / M, where N is an odd number close to 2 B-1, and B is the number of bits of resolution of the phase interpolator 308 (e.g., B=8), the fundamental frequency of the sawtooth wave is set to be relatively high. Therefore, the bandwidth of the virtual phase-locked loop 312 is set to be high for fast establishment and to ensure that the minimum mean square loop 320 receives a value within the range of the control code PICODE.

[0041] In at least one embodiment of the clock product, the digital time code TSTMP has a sufficiently slow data rate to allow the calibration circuit 370 to serially process data for multiple output interpolation dividers that each store state variables. In at least one embodiment of the clock generator 500, the divider 316 and the time-to-digital converter 318 are circuits dedicated to foreground calibration of the output interpolation dividers. However, in other embodiments of the clock generator 500, the divider 316 and the time-to-digital converter 318 are reused or time-multiplexed between calibration and other system functions. Figure 4 , 8 In at least one embodiment of the clock generator, the frequency divider 416 and the time-to-digital converter 418 may not be available for foreground calibration based on the frequency plan. Therefore, the frequency divider 416 and the time-to-digital converter 418 are included and shared by the interpolation dividers 404, 406, 408, 410, and 412, which are calibrated sequentially or in a cyclic manner to achieve calibration as a background process. The controller executes firmware that determines the division ratio (e.g., N) in use. A , N B , N C , N D or N E ) Set control code M CAL , and generates a control signal CTL, so that the selection circuit 414 provides the selected output clock signal CLKOUT n and distributes the associated state variables to the divider 416 , the time-to-digital converter 418 , and the calibration circuit 430 .

[0042] After initialization and during normal operation, the virtual phase-locked loop and the least mean square loop of the calibration circuit 430 operate in a background mode according to the target frequency schedule. Background calibration can be initiated periodically at a rate sufficient to track changes in operating conditions and temperature. The fractional portion x of the interpolation split ratio is observed and M CAL One of two prime divide ratios is programmed to set the input frequency of the signal provided to the time-to-digital converter 418 to be close to the target frequency. The first prime divide ratio is checked to ensure that x×M CALis sufficiently far from an integer (determined by the bandwidth of the virtual phase locked loop 312). If not, a second prime division ratio is checked. The prime division ratio is selected so that if neither product is sufficiently far from an integer, then x is close enough to an integer that the virtual phase locked loop will track it and prevent good calibration. For example, for two output interpolation dividers, the control circuitry or firmware executed on the controller sets M based on the interpolation divider ratio used. CAL . It uses one of two possible prime numbers M1 and M2. For example, if N = k / M1, then degeneracy is possible. If the effective split ratios of M1 and M2 are both close to integers, then N itself is close to integer and calibration is skipped. Note that if N is an integer, no calibration is required.

[0043] Reference Figure 4 In at least one embodiment of the clock generator 500, the virtual phase-locked loop 312 is used to implement other types of calibration or other signal processing goals. For example, the calibration can be extended to calibrate the nonlinearity of the phase interpolator in the analog circuit 304. In at least one embodiment, the calibration circuit 370 is coupled between the time-to-digital converter 318 and the digital-to-time converter (e.g., an interpolation divider in the feedback loop of the phase-locked loop) to reduce or eliminate jitter.

[0044] Although circuits and physical structures are generally assumed as prerequisites when describing embodiments of the present invention, it is well known that in modern semiconductor design and manufacturing, physical structures and circuits can be embodied in a computer-readable description form, suitable for subsequent design, simulation, testing or manufacturing stages. The structures and functions represented as discrete components in the exemplary configuration can be implemented as combined structures or components. It is expected that various embodiments of the present invention include circuits, circuit systems, related methods, and tangible computer-readable media (e.g., VHSIC hardware description language (VHDL), Verilog, GDSII data, electronic design exchange format (EDIF) and / or Gerber files) having such circuits, systems and methods encoded thereon, all as described herein and as defined in the appended claims. In addition, computer-readable media can store instructions and data that can be used to implement the present invention. Instructions / data can be related to hardware, software, firmware, or a combination thereof.

[0045] The description of the present invention set forth herein is illustrative and is not intended to limit the scope of the present invention as described in the appended claims. For example, although the present invention has been described in an embodiment using a least mean square loop, it will be appreciated by those skilled in the art that the teachings herein can be used with other adaptive loops. Unless otherwise clearly stated in the context, the terms "first", "second", "third", etc. used in the claims are used to distinguish different items in the claims, and do not otherwise represent or imply any time sequence, position or quality. The embodiments disclosed herein may be modified and amended based on the description set forth herein without departing from the scope of the present invention as set forth in the appended claims.

Claims

1. A clock generator, comprising: an interpolating divider including a phase interpolator and a multi-mode divider, the interpolating divider being configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal; as well as a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code, wherein the calibration circuit comprises: a phase locked loop configured to generate a digital phase error signal based on a reference timestamp signal and to generate a timestamp signal based on the clock signal and the output clock signal; and An adaptive loop is configured to generate the phase interpolator calibration signal based on the digital phase error signal.

2. The clock generator according to claim 1, further comprising: an integer frequency divider configured to generate a divided output clock signal in response to the output clock signal and an integer code; as well as A time-to-digital converter is configured to generate the time stamp signal, the time stamp signal including a digital code corresponding to an edge of a clock signal based on a frequency division of the clock signal.

3. The clock generator according to claim 1 or 2, wherein: The phase-locked loop includes two integrators and is configured to make the digital phase error signal have a zero mean.

4. The clock generator according to claim 1 or 2, wherein: The phase locked loop includes an integrator programmed with a free running period estimate to generate a reference timestamp signal having the same period as the timestamp signal.

5. The clock generator according to claim 1, wherein: The reference timestamp signal is a spurious attenuated version of the timestamp signal.

6. The clock generator according to claim 1 or 2, wherein: The phase-locked loop comprises: A wrap detection and correction circuit is configured to compensate for rollover errors caused by the phase locked loop and the adaptive loop using less than all bits of the timestamp signal.

7. The clock generator according to claim 1, further comprising: a first frequency divider configured to generate an integer-divided output clock signal; a second frequency divider configured to provide an integer-divided clock signal; as well as A time-to-digital converter is configured to generate the time stamp signal based on the integer-divided output clock signal and the integer-divided clock signal.

8. The clock generator according to claim 1, wherein: The difference between the reference timestamp signal and the timestamp signal is the digital phase error.

9. The clock generator according to claim 1, wherein: The adaptive loop includes a least mean square filter.

10. The clock generator according to claim 1, 2, 5, 7, 8 or 9, wherein: The phase-locked loop comprises: a digital circuit configured to calculate a difference between the timestamp signal and the reference timestamp signal to generate the digital phase error signal; a first integrator configured to generate an integrated phase error signal based on the digital phase error signal; a proportional circuit path configured to generate a proportional phase error signal based on the digital phase error signal; a second digital circuit configured to calculate a sum of the integrated phase error signal and the proportional phase error signal; a second integrator responsive to the sum; a free-running period estimator circuit configured to generate a desired timestamp signal; and A third digital circuit is configured to generate the reference time stamp signal based on a sum of the expected time stamp signal and an output of the second integrator.

11. The clock generator according to claim 1, 2, 5, 8 or 9, further comprising: a selection circuit configured to selectively output an active output clock signal generated by one of the plurality of output interpolation dividers; a shared integer divider configured to generate a divided active clock signal in response to the active output clock signal and a corresponding integer code; and a shared time-to-digital converter configured to generate a corresponding time stamp signal based on edges of the divided active clock signal, Wherein, the calibration circuit is also configured to generate an active phase interpolator calibration signal based on the clock signal, the active output clock signal and the corresponding phase interpolator code, and the active phase interpolator calibration signal is used to periodically update the phase interpolator calibration signal.

12. A method comprising: generating an output clock signal using an interpolating divider in response to the clock signal, the control code, and the phase interpolator calibration signal; as well as Based on the clock signal, the output clock signal and a phase interpolator code, generating the phase interpolator calibration signal, wherein generating the phase interpolator calibration signal comprises: generating a digital phase error signal based on a reference timestamp signal and generating a timestamp signal based on a clock signal and said output clock signal; as well as The phase interpolator calibration signal is adjusted based on the digital phase error signal.

13. The method according to claim 12, further comprising: generating a divided output clock signal in response to the output clock signal and an integer code; as well as The time stamp signal is generated, the time stamp signal including a digital code corresponding to an edge of the divided output clock signal based on the clock signal.

14. The method according to claim 12 or 13, further comprising: generating a divider control code and a phase interpolator control code based on the control code; as well as A phase interpolator circuit is controlled based on a combination of the phase interpolator calibration signal and the phase interpolator control code.

15. The method according to claim 12 or 13, wherein: The digital phase error signal has a zero mean.

16. The method according to claim 12 or 13, further comprising: The reference time stamp signal is generated with the same period as the time stamp signal.

17. The method according to claim 12 or 13, further comprising: Generate an integer-divided output clock signal; Generate a clock signal with integer division frequency; as well as The time stamp signal is generated based on the integer-divided output clock signal and the integer-divided clock signal.

18. The method according to claim 12 or 13, further comprising: selectively providing an active output clock signal generated by one of a plurality of output interpolating dividers; generating a divided active clock signal in response to the active output clock signal and a corresponding integer code; generating a corresponding time stamp signal based on the edge of the divided active clock signal; and An active phase interpolator calibration signal is periodically updated based on the clock signal, the active output clock signal, and a corresponding phase interpolator code.

19. The method according to claim 18, wherein: The selectively providing is a cyclic selection of active output clock signals from a plurality of output interpolating dividers.

20. A method comprising: generating an output clock signal based on the clock signal, the control code, and the phase interpolator calibration signal; generating a digital error signal based on a downsampled version of the output clock signal and an estimated version of the downsampled version of the output clock signal; as well as The phase interpolator calibration signal is generated based on the digital error signal and a phase interpolator control code using a least mean square filter.

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