A visible light communication receiving circuit

Abstract

The present invention discloses a visible light communication receiving circuit, including a photoelectric receiver, a pulse neuron circuit, a decoder, a buffer and a comparator, wherein the photoelectric receiver, the pulse neuron circuit, the decoder, the buffer and the comparator are connected in sequence; the photoelectric receiver is a circuit for converting an input light signal into a current signal; the input of the pulse neuron circuit is a current signal, and the output is a series of voltage pulse signals containing neural coding information; the decoder is a circuit for converting a voltage pulse signal into a digital signal; the buffer is used to temporarily store multiple output data of the decoder, and the multiple output data are sequentially input into the comparator; the comparator is used to output a digital signal by comparing two adjacent output data. The circuit of the present invention significantly improves the anti-interference ability of the visible light communication receiving circuit and simplifies the signal processing circuit. Compared with the traditional signal processing circuit, the pulse neuron circuit has a simple structure and low cost.

Description

Technical Field

[0001] The present invention relates to the field of visible light communication, and in particular to a visible light communication receiving circuit. Background Art

[0002] Visible light communication is sensitive to various types of noise interference, and anti-interference has always been an important issue in visible light communication. The main electronic anti-interference methods currently used in visible light communication receivers include: electronic filtering, anti-interference coding, high-sensitivity receivers, advanced amplification circuits, etc.; achieving good results often requires more complex circuits. Summary of the invention

[0003] The purpose of the present invention is to provide a visible light communication receiving circuit to overcome the problem that a complex circuit needs to be designed in order to achieve a good effect in the existing receiving circuit.

[0004] In order to achieve the above tasks, the present invention adopts the following technical solutions:

[0005] A visible light communication receiving circuit comprises a photoelectric receiver, a pulse neuron circuit, a decoder, a buffer and a comparator, wherein the photoelectric receiver, the pulse neuron circuit, the decoder, the buffer and the comparator are connected in sequence.

[0006] Furthermore, the photoelectric receiver is a circuit for converting an input optical signal into a current signal.

[0007] Furthermore, the pulse neuron circuit is a circuit that imitates the electronic properties of biological neuron cells, and its input is a current signal, and its output is a series of voltage pulse signals containing neural coding information.

[0008] Furthermore, the decoder is a circuit that converts a voltage pulse signal into a digital signal.

[0009] Furthermore, the buffer is used to temporarily store multiple output data of the decoder, and input the multiple output data into the comparator in sequence; the comparator is used to output a digital signal by comparing two adjacent output data.

[0010] Furthermore, the comparison principle of the comparator is: for two adjacent output data S provided by the buffer x and S x+1 , if S x Greater than or equal to S x+1 , then output 0; if S x Less than S x+1 , then output 1; by comparing adjacent output signals in sequence, a digital signal composed of 0 / 1 is output.

[0011] Furthermore, the working process of the visible light communication receiving circuit includes:

[0012] The neural coding information is carried by the flashing frequency of the input light signal. First, the photoelectric receiver receives the input light signal and converts it into a current signal. The input of the pulse neuron circuit is the current signal output by the photoelectric receiver, and the output is a series of voltage pulse signals. The neural coding information is also converted and loaded into the voltage pulse signal.

[0013] Then, the voltage pulse signal will be decoded by the decoder; when the peak value of a voltage pulse signal reaches the decoder, the decoder will send an enable signal to the buffer and comparator at the same time, and the enable signal will automatically return to zero after being maintained for several clock cycles; while sending the enable signal, the 8-bit binary number obtained by the current conversion is saved to the buffer, and then automatically reset to start the next conversion;

[0014] As the voltage pulse signal is input, the 8-bit binary number in the decoder will gradually increase until the pulse peak of the next voltage pulse signal reaches the decoder; then the information carried between two adjacent pulse peaks will be input into the buffer by the decoder in sequence;

[0015] The buffer contains multiple 8-bit binary data stacks, which can temporarily store the output data of multiple decoders; when the buffer receives the enable signal of the decoder, it will push the data that entered the buffer earliest to the comparator, release the storage space, and then receive the data sent by the decoder; through this buffer, the data sent by the decoder will be input into the comparator in sequence;

[0016] The comparator temporarily stores and compares the binary data input from two adjacent buffers, and outputs 0 or 1 according to the comparison result; when the comparator receives the enable signal from the decoder, it clears the earlier received data of the two data. After clearing, the comparator only has one data S x At the same time, the comparator will receive the latest data S output by the buffer x+1 , compared with S x and S x+1 , if S x Greater than or equal to S x+1 , then output 0; if S x Less than S x+1 , then output 1.

[0017] Compared with the prior art, the present invention has the following technical features:

[0018] 1. The circuit provided by the present invention significantly improves the anti-interference ability of the visible light communication receiving circuit; experiments show that under the condition of a signal-to-noise ratio of -20dB, the signal can still be accurately identified.

[0019] 2. The present invention simplifies the signal processing circuit. Compared with the traditional signal processing circuit, the present invention directly performs digital signal processing, has a simple circuit structure and low cost.

[0020] 3. The present invention integrates the signal processing circuit and the analog-to-digital conversion circuit. The pulse neuron circuit itself has the analog-to-digital conversion function. The present invention integrates the signal processing and the analog-to-digital conversion into one circuit, further simplifying the circuit and reducing the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the circuit structure of the present invention. DETAILED DESCRIPTION

[0022] Biological neurons naturally have good anti-interference capabilities, and pulse neuron circuits that mimic the electrical properties of neurons also have this ability. Some studies have begun to use pulse neuron circuits to protect against electromagnetic interference, but currently, there is still a blank in using such circuits for visible light communication.

[0023] The present invention proposes a visible light communication receiving circuit with a pulse neuron circuit, which has strong anti-interference ability, a simple structure and low cost.

[0024] See also Figure 1 A visible light communication receiving circuit of the present invention includes a photoelectric receiver, a pulse neuron circuit, a decoder, a buffer and a comparator, wherein the photoelectric receiver, the pulse neuron circuit, the decoder, the buffer and the comparator are connected in sequence.

[0025] In the circuit structure provided by the present invention:

[0026] The photoelectric receiver is a circuit for converting an input optical signal into a current signal; the pulse neuron circuit is a circuit that imitates the electronic properties of biological neuron cells, whose input is a current signal and output is a series of voltage pulse signals containing neural coding information; the decoder is a circuit that converts a voltage pulse signal into a digital signal; the buffer is used to temporarily store multiple output data of the decoder, and input the multiple output data into the comparator in sequence; the comparator is used to output a digital signal by comparing two adjacent output data, thereby realizing the conversion from optical signal to digital signal; wherein, the comparison principle of the comparator is:

[0027] For the two adjacent output data S provided by the buffer x and S x+1 , if S x Greater than or equal to S x+1 , then output 0; if S x Less than S x+1, then output 1; by comparing adjacent output signals in sequence, a digital signal composed of 0 / 1 is output.

[0028] Based on the above circuit, the working process of the present invention is as follows:

[0029] The neural coding information is carried by the flashing frequency of the input light signal; first, the photoelectric receiver receives the input light signal and converts it into a current signal; the input of the pulse neuron circuit is the current signal output by the photoelectric receiver, and the output is a series of voltage pulse signals; the neural coding information is also converted at the same time and loaded into the voltage pulse signal.

[0030] Then, the voltage pulse signal will be decoded by the decoder; when the pulse peak of a voltage pulse signal reaches the decoder, the decoder will send an enable signal to the buffer and comparator at the same time, and the enable signal will automatically return to zero after being maintained for several clock cycles; while sending the enable signal, the 8-bit binary number obtained by the current conversion is saved to the buffer, and then automatically reset to start the next conversion.

[0031] As the voltage pulse signal is input, the 8-bit binary number in the decoder will gradually increase until the pulse peak of the next voltage pulse signal reaches the decoder; therefore, the information carried between two adjacent pulse peaks will be input into the buffer in sequence by the decoder.

[0032] The buffer contains multiple 8-bit binary data stacks, which can temporarily store the output data of multiple decoders; when the buffer receives the enable signal from the decoder, it will push the data that enters the buffer earliest to the comparator, release the storage space, and then receive the data sent by the decoder; through this buffer, the data sent by the decoder will be input into the comparator in sequence.

[0033] The comparator temporarily stores and compares the binary data input from two adjacent buffers, and outputs 0 or 1 according to the comparison result; when the comparator receives the enable signal from the decoder, it clears the earlier received data of the two data. After clearing, the comparator only has one data S x At the same time, the comparator will receive the latest data S output by the buffer. x+1 Compare S x and S x+1 , if S x Greater than or equal to S x+1 , then output 0; if S x Less than S x+1 , then output 1.

[0034] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A visible light communication receiving circuit, characterized in that: It includes a photoelectric receiver, a pulse neuron circuit, a decoder, a buffer and a comparator, wherein the photoelectric receiver, the pulse neuron circuit, the decoder, the buffer and the comparator are connected in sequence; The working process of the visible light communication receiving circuit includes: The neural coding information is carried by the flashing frequency of the input light signal. First, the photoelectric receiver receives the input light signal and converts it into a current signal. The input of the pulse neuron circuit is the current signal output by the photoelectric receiver, and the output is a series of voltage pulse signals. The neural coding information is also converted and loaded into the voltage pulse signal. Then, the voltage pulse signal will be decoded by the decoder; when the peak value of a voltage pulse signal reaches the decoder, the decoder will send an enable signal to the buffer and comparator at the same time, and the enable signal will automatically return to zero after being maintained for several clock cycles; while sending the enable signal, the 8-bit binary number obtained by the current conversion is saved to the buffer, and then automatically reset to start the next conversion; As the voltage pulse signal is input, the 8-bit binary number in the decoder will gradually increase until the pulse peak of the next voltage pulse signal reaches the decoder; then the information carried between two adjacent pulse peaks will be input into the buffer by the decoder in sequence; The buffer contains multiple 8-bit binary data stacks, which can temporarily store the output data of multiple decoders; when the buffer receives the enable signal of the decoder, it will push the data that entered the buffer earliest to the comparator, release the storage space, and then receive the data sent by the decoder; through this buffer, the data sent by the decoder will be input into the comparator in sequence; The comparator temporarily stores and compares the binary data input from two adjacent buffers, and outputs 0 or 1 according to the comparison result; when the comparator receives the enable signal from the decoder, it will clear the earlier received data of the two data. After clearing, the comparator will only have one data Sx left; at the same time, the comparator will receive the latest data Sx+1 output from the buffer, compare Sx and Sx+1, and if Sx is greater than or equal to Sx+1, it will output 0; if Sx is less than Sx+1, it will output 1.

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