Apparatus and method for comparing an input current with a set of current thresholds

Abstract

A current comparator includes: a first comparator configured to generate a first output signal based on a comparison of a first current with at least a second current; a second comparator configured to generate a second output signal based on a comparison of the first current with at least a third current; and a circuit configured to: direct the first current to the first comparator to perform a comparison of the first current with at least the second current when a blocking first current is applied to the second comparator; or direct the first current to the second comparator to perform a comparison of the first current with at least the third current when a blocking first current is applied to the first comparator.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Non - Provisional Patent Application No. 16 / 251,997, filed on January 18, 2019, and U.S. Provisional Patent Application No. 62 / 717,285, filed on August 10, 2018, the entire contents of which are incorporated herein by reference as if set forth in full below for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure generally relate to current comparators, and more particularly, to an apparatus and method for comparing an input current with a set of current thresholds. Background Art

[0004] A current comparator can be used to generate an output signal based on a comparison of an input current with a set of current thresholds. For example, if the input current is lower than all of the current thresholds in the set of current thresholds, the current comparator generates an output signal having a particular value. If the input current is higher than all of the current thresholds in the set of current thresholds, the current comparator generates an output signal having another particular value. In a similar manner, if the input current is lower than some of the current thresholds in the set of current thresholds but higher than other current thresholds in the set of current thresholds, the current comparator generates an output signal having yet another particular value. The output signal of the current comparator can be used to control one or more other components.

[0005] As with many devices, designers are concerned with the accuracy of the comparison performed by the current comparator. Additionally, component count and power consumption of the current comparator are another consideration for designers. Summary of the Invention

[0006] A simplified summary of one or more embodiments is presented below to provide a basic understanding of such embodiments. This summary is not an exhaustive overview of all contemplated embodiments, and is neither intended to identify key or critical elements of all embodiments nor to delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description presented later.

[0007] One aspect of the present disclosure relates to an apparatus, comprising: a first comparator having a first input for receiving an input signal, a second input for receiving a reference signal, and an output; and a set of one or more switches having an input coupled to the output of the first comparator, wherein the set of one or more switches operates in response to an output signal from the first comparator to select a threshold current from a set of one or more threshold currents for comparison with the input signal.

[0008] Another aspect of the present disclosure relates to an apparatus, comprising: a first comparator having a first input for receiving an input signal, a second input for receiving a reference signal, and an output; a current source providing a first threshold current; a first current sink providing a second threshold current; a second current sink providing a third threshold current; and a set of one or more switches coupled between the current source and the first and second current sinks, the set of one or more switches having an input coupled to the output of the first comparator.

[0009] Another aspect of the present disclosure relates to an apparatus, the apparatus comprising: a current source, a first switching device, a second switching device, and a first current sink, wherein the current source, the first switching device, the second switching device, and the first current sink are serially coupled between a first voltage rail and a second voltage rail. The apparatus further comprises: a first comparator including a first input and a second input, the first input being coupled to a node between the current source and the first switching device, and the second input receiving a reference signal; a second comparator including a first input and a second input, the first input being coupled to a node between the second switching device and the first current sink, and the second input receiving a reference signal; and a third comparator including a first input, a second input, and an output, the first input receiving an input signal and being coupled to a node between the first switching device and the second switching device, the second input receiving a reference signal, and the output being coupled to control inputs of the first switching device and the second switching device.

[0010] Another aspect of the present disclosure relates to an apparatus, comprising: a first comparator configured to generate a first output signal based on a comparison of a first current with at least a second current; a second comparator configured to generate a second output signal based on a comparison of the first current with at least a third current; and circuitry configured to direct the first current to the first comparator to perform a comparison of the first current with at least the second current when a blocking first current is applied to the second comparator, or to direct the first current to the second comparator to perform a comparison of the first current with at least the third current when the blocking first current is applied to the first comparator.

[0011] Another aspect of the present disclosure relates to a method, comprising: generating a first output signal based on a comparison of a first current with at least a second current; generating a second output signal based on a comparison of the first current with at least a third current; and enabling a comparison of the first current with at least the second current when a comparison of the first current with at least the third current is disabled; or enabling a comparison of the first current with at least the third current when a comparison of the first current with at least the second current is disabled.

[0012] Another aspect of the present disclosure relates to an apparatus including: components for generating a first output signal based on a comparison of a first current with at least a second current; components for generating a second output signal based on a comparison of the first current with at least a third current; and components for enabling the components for comparing the first current with at least the second current when disabling the components for comparing the first current with at least the third current; or for enabling the components for comparing the first current with at least the third current when disabling the components for comparing the first current with at least the second current.

[0013] To achieve the foregoing aspects and related purposes, one or more embodiments include the features described in detail below and particularly pointed out in the claims. The following description and the drawings set forth in detail certain illustrative aspects of one or more embodiments. However, these aspects merely indicate several of the various ways in which the principles of the various embodiments may be employed, and the description of the embodiments is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram illustrating an exemplary current comparator in accordance with one aspect of the present disclosure.

[0015] Figure 2 A schematic diagram illustrating another exemplary current comparator in accordance with another aspect of the present disclosure.

[0016] Figures 3A to 3B Illustrating a current comparator based on different comparison results in accordance with another aspect of the present disclosure Figure 2 schematic diagram of an exemplary equivalent circuit.

[0017] Figure 4A A block diagram illustrating an exemplary voltage control circuit in accordance with another aspect of the present disclosure.

[0018] Figure 4B A schematic diagram illustrating another exemplary current comparator in accordance with another aspect of the present disclosure.

[0019] Figure 4C A table illustrating mapping of a current comparator output to a decoder output to a DC-to-DC converter output voltage in accordance with another aspect of the present disclosure.

[0020] Figure 4D Another table illustrating mapping of a decoder output to a DC-to-DC converter output voltage in accordance with another aspect of the present disclosure.

[0021] Figure 4E A graph illustrating various signals associated with the operation of a voltage control circuit over time in accordance with another aspect of the present disclosure.

[0022] Figure 4F FIG. illustrates a state diagram of various signals associated with the operation of a voltage control circuit according to another aspect of the present disclosure.

[0023] Figure 5 FIG. illustrates a flowchart of an exemplary method of comparing an input current with a set of current thresholds according to another aspect of the present disclosure. DETAILED DESCRIPTION

[0024] The following detailed description presented in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. To provide a thorough understanding of the various concepts, the detailed description includes specific details. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0025] Figure 1 FIG. illustrates a schematic diagram of an exemplary current comparator 100 according to one aspect of the present disclosure. The current comparator 100 receives an input current signal I sig and compares the input current signal I sig with a set of current thresholds I TH1 -I TH3 and generates a set of output currents D3 - D1 based on the comparison.

[0026] As an example, if the input current signal I sig is lower than all of the current thresholds in the set of current thresholds I TH1 -I TH3 , the output signals D3 - D1 may have a value of 000. If the input current signal I sig is higher than the current threshold I TH1 but lower than the current threshold I TH2 -I TH3 , the output signals D3 - D1 may have a value of 001. If the input current signal I sig is higher than the current threshold I TH1 -I TH2 but lower than the current threshold I TH3 , the output signals D3 - D1 may have a value of 011. And, if the input current signal I sig is higher than all of the sets in the set of current thresholds I TH1 -I TH3 , the output signals D3 - D1 may have a value of 111.

[0027] Specifically, the current comparator 100 includes a first current path between a high voltage rail Vdd and a low voltage rail Vss (e.g., ground). The first current path includes a first current source I coupled in series with a first transistor M1 01 , and the first transistor M1 may be configured as an n-channel metal oxide semiconductor field effect transistor (NMOSFET). A current source (such as the first current source I 01 and other current sources described herein) provides a substantially constant current and may include a transistor (such as a p-channel metal oxide semiconductor field effect transistor (PMOSFET)) having a control terminal (e.g., a gate) that is biased with a substantially constant voltage. The drain and gate of the first transistor M1 are electrically coupled together to form a current mirror with other current paths described herein. An input current signal I sig is applied to a node between the first current source I 01 and the first transistor M1.

[0028] The current comparator 100 further includes a second current path between the high voltage rail Vdd and the low voltage rail Vss. The second current path includes a second current source I coupled in series with a second transistor M2 02 , and the second transistor M2 may also be configured as an NMOSFET. The gate of the transistor M2 is electrically coupled to the gate and drain of the transistor M1 to form a current mirror relationship between the first current path and the second current path.

[0029] Similarly, the current comparator 100 further includes a third current path between the high voltage rail Vdd and the low voltage rail Vss. The third current path includes a third current source I coupled in series with a third transistor M3 03 , and the third transistor M3 may also be configured as an NMOSFET. The gate of the transistor M3 is electrically coupled to the gate and drain of the transistor M1 to form a current mirror relationship between the first current path and the third current path.

[0030] In a similar manner, the current comparator 100 further includes a fourth current path between the high voltage rail Vdd and the low voltage rail Vss. The fourth current path includes a fourth current source I coupled in series with a fourth transistor M4 04 , and the fourth transistor M4 may also be configured as an NMOSFET. The gate of the transistor M4 is electrically coupled to the gate and drain of the transistor M1 to form a current mirror relationship between the first current path and the fourth current path.

[0031] The current comparator 100 further includes a set of threshold current sinks I TH1 -I TH3 . A current sink (such as the current sink ITH1 -I TH3 and other current sinks described herein) sink substantially constant currents and may include a transistor (such as, an NMOSFET) having a control terminal (e.g., a gate) that is biased with a substantially constant voltage. The first threshold current sink I of the set TH1 is coupled between a node between a second current source I in a second current path 02 and a second transistor M2 and a low voltage rail Vss. The second threshold current sink I of the set TH2 is coupled between a node between a third current source I in a third current path 03 and a third transistor M3 and a low voltage rail Vss. And, the third threshold current sink I of the set TH3 is coupled between a node between a fourth current source I in a fourth current path 04 and a fourth transistor M4 and a low voltage rail Vss. In this example, the third threshold current sink I TH3 sinks a higher current than the second threshold current sink I TH2 , and the second threshold current sink I TH2 sinks a higher current than the first threshold current sink I TH1 (e.g., I TH3 > I TH2 > I TH1 ).

[0032] The current comparator 100 additionally includes a set of comparators CMP1 - CMP3. The first comparator CMP1 includes a positive input terminal coupled to a node between a second current source I in a second current path 02 and a second transistor M2. The second comparator CMP2 includes a positive input terminal coupled to a node between a third current source I in a third current path 03 and a third transistor M3. The third comparator CMP3 includes a positive input terminal coupled to a node between a fourth current source I in a fourth current path 04 and a fourth transistor M4. The set of comparators CMP1 - CMP3 each include a negative input terminal configured to receive a threshold voltage that may be set to Vdd / 2. The set of comparators CMP1 - CMP3 includes outputs configured to generate bits of output signals D1 - D3, respectively.

[0033] The current source I of the first current path 01 , the current source I of the second current path 02 , the current source I of the third current path 03 , and the current source I of the fourth current path 04configured to generate substantially the same current. Similarly, the transistor M1 of the first current path, the transistor M2 of the second current path, the transistor M3 of the third current path, and the transistor M4 of the fourth current path are configured to have substantially the same dimensions (e.g., substantially the same channel width W and channel length L). As a result, and due to the current mirror relationship between the first current path and the second current path, the third current path, and the fourth current path, the second current path, the third current path, and the fourth current path are configured to respectively generate a copy current I sig substantially the same as the input current signal I sig1 , I sig2 and I sig3 .

[0034] The positive terminal of the comparator has a very high impedance; thus, substantially all of the copy current flows into the threshold current sink I TH1 -I TH3 . If the copy current is lower than the corresponding threshold current, the voltage at the corresponding positive terminal of the corresponding comparator is substantially Vss (the voltage at the low voltage rail). Conversely, if the copy current is higher than the corresponding threshold current, the voltage at the corresponding positive terminal of the corresponding comparator is substantially Vdd (the voltage at the high voltage rail). As described above, the current sink is configured such that the current threshold I TH3 is greater than the current threshold I TH2 , and in turn such that the threshold current I TH2 is greater than the threshold current I TH1 .

[0035] The reason why the voltage at the positive terminal of the corresponding comparator is Vss when the copy current is lower than the corresponding threshold current and Vdd when the copy current is higher than the corresponding threshold current is as follows: If the copy current is higher than the corresponding threshold current (e.g., I sig1 -I TH1 > 0), then the excess current flows through an equivalent resistance, which is the internal resistance of the corresponding current source / sink (I 02 , M2 and I TH1 ) connected in parallel. Since the equivalent resistance of the current source / sink is relatively high, the small amount of excess current flowing through these devices causes the voltage at the positive terminal of the corresponding comparator (e.g., CMP1) to rise substantially to the rail voltage Vdd. On the other hand, if the copy current is lower than the corresponding threshold current (e.g., I sig1 -I TH1 < 0), then no excess current flows through the current source / sink (I 02 , M2 and I TH1)'s internal resistance. Therefore, the voltage at the positive terminal of the corresponding comparator (e.g., CMP1) is substantially Vss.

[0036] Therefore, if the input current signal I sig is lower than all the current thresholds I TH1 -I TH3 , then the voltage at the corresponding positive terminals of the comparators CMP1 - CMP3 is substantially Vss, and this voltage is less than the threshold voltage Vdd / 2 applied to the negative terminals of the comparators. Therefore, the output signals D3 - D1 generated by the comparators CMP1 - CMP3 are 000.

[0037] If the input current signal I sig is higher than the first current threshold I TH1 , but lower than the current thresholds I TH2 and I TH3 , then the voltage at the positive terminal of the comparator CMP1 is substantially Vdd, and the voltages at the positive terminals of the comparators CMP2 and CMP3 are substantially Vss. Therefore, the output D1 of the comparator CMP1 is logic one (1) and the outputs D2 - D3 of the comparators CMP2 - CMP3 are logic zero (00). Therefore, the output signal D3 - D1 has a value of 001.

[0038] If the input current signal I sig is higher than the first current threshold I TH1 and the second current threshold I TH2 , but lower than the third current threshold I TH3 , then the voltages at the positive terminals of the comparators CMP1 - CMP2 are substantially Vdd, and the voltage at the positive terminal of the comparator CMP3 is substantially Vss. Therefore, the outputs D1 - D2 of the comparators CMP1 - CMP2 are 11, and the output D3 of the comparator CMP3 is 0. Therefore, the output signal has a value of 011.

[0039] Similarly, if the input current signal I sig is higher than all the current thresholds I TH1 -I TH3 , then the voltages at the positive terminals of the comparators CMP1 - CMP3 are substantially Vdd, and all these voltages are higher than the threshold voltage Vdd / 2 applied to the negative terminals of the comparators. Therefore, the comparators CMP3 - CMP1 generate an output signal D3 - D1 with a value of 111.

[0040] The current comparator 100 has several drawbacks. First, due to process variations, the current sources I 01 to I 04Do not generate substantially the same current, and there is a mismatch between transistors M1 to M4. As a result, the replicated currents I sig1 to I sig3 generated by the second current path, the third current path, and the fourth current path may not be substantially the same as the input current signal I sig . Because there may be errors when generating the replicated currents I sig1 to I sig3 , the comparison performed by comparators CMP1 - CMP3 may also be incorrect. Therefore, the output signals D3 - D1 may not be as accurate as desired.

[0041] Secondly, the current paths for generating the replicated currents I sig1 to I sig3 require a large number of components (e.g., current sources I 02 -I 04 and transistors M2 - M4). This significantly increases the component count of current comparator 100; thus, the integrated circuit footprint for implementing current comparator 100 may be undesirably large. Additionally, due to the large number of components, current comparator 100 consumes a large amount of power. Therefore, it is necessary to improve the accuracy, reduce the number of components, and reduce the power consumption of the current comparator.

[0042] Figure 2 FIG. illustrates a schematic diagram of another exemplary current comparator 200 according to another aspect of the present disclosure. In summary, current comparator 200 performs substantially the same operations as current comparator 100 (e.g., comparing an input current signal I sig with three current thresholds I TH1 -I TH3 and generating output signals based on the comparison). However, compared to using three current paths in current comparator 100, current comparator 200 uses only a single current path; thus, current comparator 200 is less likely to generate output signal errors due to possible replicated current mismatches in current comparator 100. Additionally, because there is only a single current path in current comparator 200, current comparator 200 requires fewer components and consumes less power.

[0043] Specifically, current comparator 200 includes a threshold current source I TH3 series - coupled with a first transistor M1 (e.g., NMOSFET), a second transistor M2 (e.g., p-channel MOSFET or PMOSFET), and a threshold current sink I TH1 between a high voltage rail Vdd and a low voltage rail Vss. Current comparator 200 further includes another threshold current sink I TH2 , and this threshold current sink I TH2is coupled between an input node (between the first transistor M1 and the second transistor M2) and the low voltage rail Vss. Similar to the current comparator 100, the threshold current sink I TH3 sinks a current greater than the threshold current sink I TH2 sinks, and the current source I TH1 sinks a current less than the threshold current sink I TH2 and I TH3 's current sinking (e.g., I TH3 > I TH2 > I TH1 ). The input current signal I sig is applied to the input node between the first transistor M1 and the second transistor M2. Although the input current I Figure 2 is shown flowing into the current comparator 200 in sig , it should be understood that the input current I sig can flow into and / or out of the current comparator 200.

[0044] The current comparator 200 further includes a set of comparators CMP1 - CMP3. Each of the comparators CMP1 - CMP3 includes a negative input terminal configured to receive a threshold voltage that can be set to Vdd / 2. The positive terminal of the comparator CMP1 is coupled to the node between the threshold current source I TH1 and the first transistor M1. The positive terminal of the comparator CMP2 is coupled to the input node between the first transistor M and the second transistor M2. The positive terminal of the comparator CMP3 is coupled to the node between the second transistor M2 and the threshold current sink I TH3 . The comparators CMP3 - CMP1 are configured to generate bits of the output signals D3 - D1, respectively.

[0045] Additionally, the current comparator 200 includes an inverter I having an input coupled to the output of the second comparator CMP2. The inverter I includes an output coupled to the gates of the first transistor M1 and the second transistor M2.

[0046] In operation, if the current signal I sig is below the second threshold current I TH2, the voltage at the positive input terminal of the second comparator CMP2 is substantially Vss, which is lower than the threshold voltage Vdd / 2 applied to the negative input terminal of the second comparator CMP2. Therefore, the output D2 of the second comparator CMP2 is "0" or a low logic voltage (e.g., substantially Vss). The inverter I inverts the "0" and generates a "1" or a high logic voltage (e.g., substantially Vdd). The high logic voltage generated by the inverter I and applied to the gates of the transistors M1 and M2 causes the transistor M1 to turn on and the transistor M2 to turn off.

[0047] Figure 3A The figure shows when the input current signal I sig is lower than the second current threshold I TH2 , a schematic diagram of an exemplary equivalent circuit of the current comparator 200. When the transistor M2 is turned off, the transistor M2, the threshold current sink I TH3 and the third comparator CMP3 are effectively disabled; and thus these devices can be removed from the equivalent circuit. Additionally, since the transistor M1 is turned on, it can be represented in the equivalent circuit as a short circuit that directly couples the threshold current source I TH1 to the threshold current sink I TH2 . Since the states of the outputs of the comparator CMP2 and the inverter I are known, these devices can also be removed from the equivalent circuit.

[0048] Therefore, the equivalent circuit includes a threshold current source I TH2 coupled in series with the threshold current sink I TH1 between the high voltage rail Vdd and the low voltage rail Vss. The input signal I sig is applied to the input node between the threshold current source I TH1 and the threshold current sink I TH2 . The positive input terminal of the first comparator CMP1 is coupled to the input node. The negative input terminal of the first comparator CMP1 receives the threshold voltage Vdd / 2.

[0049] Therefore, if the following relationship is applied, the first comparator CMP1 generates D1 as a logic one (1):

[0050] I sig + I TH1 > I TH2 or I sig > I TH2 – I TH1

[0051] Otherwise, the first comparator CMP1 generates D1 as a logic zero (0). Therefore, when the input signal I sig is lower than the second current threshold I TH2When the output signal states D2 and D3 are logic zero (0), and the state of output signal D1 depends on the input current signal I sig is greater than the difference between the current threshold I TH2 and I TH1 .

[0052] If the current signal I sig is higher than the second threshold current I TH2 , then the voltage at the positive input terminal of the second comparator CMP2 is substantially Vdd, which is higher than the threshold voltage Vdd / 2 applied to the negative input terminal of the second comparator CMP2. Accordingly, the output D2 of the second comparator CMP2 is "1" or a high logic voltage (e.g., substantially Vdd). The inverter I inverts the "1" and generates a "0" or a low logic voltage (e.g., substantially Vss). The low logic voltage generated by the inverter I and applied to the gates of the transistors M1 and M2 causes the transistor M1 to turn off and the transistor M2 to turn on.

[0053] Figure 3B FIG. shows a schematic diagram of an exemplary equivalent circuit of the current comparator 200 when the input current signal I sig is higher than the second current threshold I TH2 . When the transistor M1 is turned off, the transistor M1, the threshold current source I TH1 and the first comparator CMP1 are effectively disabled; accordingly, these devices can be removed from the equivalent circuit. Additionally, since the transistor M2 is turned on, it can be represented in the equivalent circuit as a short circuit that directly couples the input node to the threshold current sink I TH3 . Since the states of the outputs of the comparator CMP2 and the inverter I are known, these devices can also be removed from the equivalent circuit.

[0054] Accordingly, the equivalent short circuit includes the threshold current sinks I TH2 and I TH3 coupled in parallel between the input node and the low voltage rail Vss. The input signal I sig is applied to the input node. The positive input terminal of the third comparator CMP3 is coupled to the input node. The negative input terminal of the third comparator CMP3 receives the threshold voltage Vdd / 2.

[0055] Accordingly, if the following relationship holds, the third comparator CMP3 generates D3 as a logic one (1):

[0056] I sig >I TH2 +I TH3

[0057] Otherwise, the third comparator CMP3 generates D3 as a logic zero (0). Thus, when the input signal I sig is higher than the second current threshold I TH2 , the states D1 and D2 of the output signal are logic ones (1), and the state D3 of the output signal depends on whether the input current signal I sig is greater than the sum of the current thresholds I TH2 and I TH3 .

[0058] Referring again to Figure 2 , the current comparator 200 redirects the input current I TH2 to the appropriate comparator CMP1 or CMP3 based on a comparison of the input current with the current threshold I sig . For example, if it is determined that the input current I sig is lower than the second threshold current I TH2 , then the second comparator CMP2 directs the input current to the first comparator CMP1 via the inverter I and the first transistor M1 and the second transistor M2 for comparison (when a blocking input current is applied to the third comparator CMP3) of the input current with the difference between the threshold currents I TH2 and I TH1 . Similarly, if it is determined that the input current I sig is higher than the second threshold current I TH2 , then the second comparator CMP2 directs the input current I sig to the third comparator CMP3 via the inverter I and the first transistor M1 and the second transistor M2 for comparison (when a blocking input current is applied to the first comparator CMP1) of the input current with the sum of the threshold currents I TH2 and I TH3 .

[0059] It can be seen that the current comparator 200 has a single current path that can be reconfigured based on the result of a comparison of the input current I sig with the second threshold current I TH2 . Since there is no need to duplicate the input current, this results in a more accurate comparison, as discussed, the input current is error-prone, and the input current I sig is directly used to perform the required comparison. In addition, since there is only a single current path, the current comparator 200 includes fewer components compared to the current comparator 100. Thus, the current comparator 200 requires less integrated circuit footprint to implement and consumes less power than the current comparator 100.

[0060] Although in the above example, the input current is compared with three (3) thresholds, it should be understood that a current comparator implementing the above concept can be adapted to compare the input current with more than three (3) thresholds.

[0061] FIG. 4 illustrates a block diagram of an exemplary voltage control circuit 400 in accordance with another aspect of the present disclosure. In this example, the voltage control circuit 400 is configured to control or regulate the power supply voltage for a power amplifier (PA). However, it should be understood that the voltage control circuit 400 can be configured to control or regulate any voltage at a particular node.

[0062] The current comparator 200 discussed above can be used in many applications, one of which is to control the power supply voltage Vs for a power amplifier (PA). More specifically, the current comparator 200 can be used to control the power supply voltage Vs for the PA such that the power supply voltage Vs substantially tracks the envelope of the input signal or output signal of the PA, or to vary the power supply voltage Vs in any desired manner.

[0063] In particular, the voltage control circuit 400 includes: a power amplifier (PA) 410 (which can generally be any load); a controller 420; a linear amplifier 430 including an output capacitor C and a feedback network having a feedback resistor R fb coupled in parallel; a current comparator 440; a decoder 450; a DC-to-DC converter 460 including an inductor L; and an antenna 470. In this example, the current comparator 440 can be configured to be similar to the current comparator 200 but with some modifications as described below. fb

[0064] An input voltage signal V in is applied to the input of the PA 410. The PA 410 is configured to amplify the input voltage signal V in in to generate an output voltage signal V out . The output voltage signal V out is applied to the antenna 470 to generate a wireless signal. The PA 410 is coupled between a high voltage rail and a low voltage rail Vss, and the high voltage rail receives a variable power supply voltage Vs. The remaining components of the voltage control circuit 400 generate and control the power supply voltage Vs such that the power supply voltage Vs can substantially track the envelope of the input voltage signal V in or the envelope of the output voltage signal V out (e.g., if the gain of the PA is substantially constant), or vary in any desired manner. This variation of the power supply voltage Vs can be performed in a manner that improves the power efficiency operation of the PA 410.

[0065] To generate the supply voltage Vs for PA 410, for example, a directional coupler is used to sample the input voltage signal V in and provide the sample V is to the controller 420. The controller 420 determines the envelope of the input voltage signal V is by processing the sampled signal V in . The power controller 420 generates a control voltage V in / G based on the envelope of the input voltage signal V tgt , and applies the control voltage V tgt / G to the positive input terminal of the linear amplifier 430, where V tgt is the target supply voltage for the supply voltage Vs and G is the gain of the linear amplifier 430. As further discussed herein, the controller 420 also generates a threshold control signal th_set and sends the threshold control signal th_set to the current comparator 440 to set its current threshold. The linear amplifier 430 generates or absorbs a current I tgt / G based on a comparison of the feedback voltage at the negative input of the linear amplifier 430 with the control voltage V amp to maintain the supply voltage Vs of the PA 410 for tracking the envelope of the input voltage signal V in .

[0066] The sample I amp of the current I amp_scaled is applied to the input of the current comparator 440. The sampled current I amp can be generated from the current I amp_scaled via a current mirror, where the ratio of the sampled current I amp_scaled to the current I amp is less than one (1) to reduce the power consumption for the voltage control circuit 400. The current comparator 440 compares the sampled current I amp_scaled with a low current threshold I TH_N and a high current threshold I TH_P , and generates an output signal including bits cmp_h, cmp_m, and cmp_l. The low current threshold I TH_N and the high current threshold I TH_P are programmable and are set by the threshold control signal th_set generated by the controller 420. The decoder 450 decodes the bits cmp_h, cmp_m, cmp_l from the output of the current comparator 440 and generates a control signal etdrv<1:0> for the DC-DC converter 460. As further discussed in detail below, the DC-DC converter 460 can be configured as a buck converter or a switched-mode power supply (SMPS), and generates most of the power for the PA 410, generating a voltage VSW based on the control signal etdrv<1:0>.

[0067] Figure 4B A schematic diagram illustrating a current comparator 440 according to another aspect of the present disclosure. The current comparator 440 is similar to the current comparator 200, except that the threshold current sink I TH2 is set to zero (0) current; or in fact, the threshold current sink I TH2 does not exist in the current comparator 440. In the case where the intermediate threshold current I TH2 is set to zero (0), the current comparator 440 compares the sampled amplifier current I amp_scaled with the positive threshold current I TH_P and the negative threshold current I TH_N .

[0068] In particular, the current comparator 440 includes a threshold current source I TH_N , a first transistor M1 (e.g., an NMOSFET), a second transistor M2 (e.g., a PMOSFET), and a threshold current sink I TH_P , all of which are serially coupled between the high voltage rail Vdd and the low voltage rail Vss. The current comparator 440 further includes a set of comparators CMP1-CMP3, each comparator including a negative input terminal configured to receive a threshold voltage that is set to Vdd / 2.

[0069] The first comparator CMP1 includes a positive input terminal that is coupled to the node between the threshold current source I TH_N and the first transistor M1. The second comparator CMP2 includes a positive input terminal that is coupled to the input node between the first transistor M1 and the second transistor M2, to which the sampled amplifier current I amp_scaled is applied. The third comparator CMP3 includes a positive input terminal that is coupled to the node between the second transistor M2 and the threshold current sink I TH_P . The first comparator CMP1, the second comparator CMP2, and the third comparator CMP3 respectively generate bits cmp_l, cmp_m, and cmp_h of the output signal of the current comparator 440.

[0070] The current comparator 440 further includes an inverter I, which includes an input and an output, the input being coupled to the output of the second comparator CMP2, and the output being coupled to the gates of the transistor M1 and the transistor M2.

[0071] In operation, if the sampled amplifier current I amp_scaledis negative (flowing out of the current comparator 440), the second comparator CMP2 generates cmp_m as a logical zero (0) (e.g., substantially Vss), and the logical zero is applied to the input of the inverter I. The inverter I inverts the logical zero (0) to generate a logical one (1) (e.g., substantially Vdd), and the logical one is applied to the gates of transistors M1 and M2. As a result, transistor M1 turns on and transistor M2 turns off. Therefore, the comparison performed by the first comparator CMP1 is the sampled amplifier current I amp_scaled is more negative than the current threshold I TH_N If the sampled amplifier current I amp_scaled is more negative than the current threshold I TH_N the first comparator CMP1 generates cmp_l as a logical zero (0). If the sampled amplifier current I amp_scaled is less negative than the current threshold I TH_N the first comparator CMP1 generates cmp_l as a logical one (1).

[0072] If the sampled amplifier current I amp_scaled is positive (flowing into the current comparator 440), the second comparator CMP2 generates cmp_m as a logical one (1) (e.g., substantially Vdd), and the logical one is applied to the input of the inverter I. The inverter I inverts the logical one (1) to generate a logical zero (0) (e.g., substantially Vss), and the logical zero is applied to the gates of transistors M1 and M2. As a result, transistor M1 turns off and transistor M2 turns on. Therefore, the comparison performed by the third comparator CMP3 is the sampled amplifier current I amp_scaled is more positive than the current threshold I TH_P If the sampled amplifier current I amp_scaled is less than the current threshold I TH_P , the third comparator CMP3 generates cmp_h as a logical zero (0). If the sampled amplifier current I amp_scaled is greater than the current threshold ITH_P, the third comparator CMP3 generates cmp_h as a logical one (1).

[0073] Figure 4C illustrates a table for mapping the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 to the output signals (etdrv<1> and etdrv<0>) of the decoder 450 to the output voltage VSW of the DC-DC converter 460 according to another aspect of the present disclosure.

[0074] As indicated, when the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 are 000, it means that the amplifier 430 is absorbing more than the absorption threshold (corresponding to I TH_N) current, the decoder 450 generates its output signal (etdrv<1:0>) as 00 to command the DC-DC converter 460 to generate its output voltage VSW at zero (0) volts. This occurs when the supply voltage Vs is significantly higher than the target supply voltage V tgt This occurs when the linear amplifier 430 is drawing more current than the draw current threshold and the voltage VSW is zero (0) volts, such that the current supplied by the DC-DC converter 460 to the PA 410 is decreasing, and these two actions work together to reduce the supply voltage Vs.

[0075] When the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 change state from 000 to 001, meaning that the amplifier 430 is drawing current but not exceeding the draw threshold and the draw current is decreasing, the decoder 450 maintains its output signal (etdrv<1:0>) as 00 to continue to command the DC-DC converter 460 to generate its output voltage VSW at zero (0) volts. Again, this occurs when the supply voltage Vs is higher than the target supply voltage V tgt and both the amplifier 430 and the DC-DC converter 460 work together to further reduce the supply voltage Vs.

[0076] When the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 change state from 001 to 011, meaning that the amplifier 430 has stopped drawing current and is supplying current, the decoder 450 generates its output signal (etdrv<1:0>) as 01 to command the DC-DC converter 460 to generate the output voltage VSW at a voltage substantially equal to the battery voltage VBAT. This occurs when the supply voltage Vs is less than the target supply voltage V tgt The voltage VSW is brought to VBAT such that the current supplied by the DC-DC converter 460 to the PA 410 does not decrease rapidly (it may increase or may not increase). This will reduce the rate at which the amplifier 430 has to supply current. The two actions work together to reduce the error in the supply voltage Vs relative to the target supply voltage V tgt

[0077] When the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 change state from 011 to 111, meaning that the amplifier 430 is supplying more current than the supply threshold, the decoder 450 generates its output signal (etdrv<1:0>) as 11 to command the DC-DC converter 460 to generate its output voltage VSW at an auxiliary voltage VAUX higher than the battery voltage VBAT. When the supply voltage VS is significantly lower than the target supply voltage V tgt ​And this occurs when the linear amplifier 430 is providing a current that exceeds the supply current threshold and the voltage VSW is VAUX, such that the current supplied by the DC-DC converter 460 to the PA 410 is increasing, and the two actions work together to increase the supply voltage Vs.

[0078] When the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 change state from 111 to 011, it means that the amplifier 430 is providing current but not exceeding the supply threshold, and the supply current is decreasing. The decoder 450 holds its output signal (etdrv<1:0>) at 11 to instruct the DC-DC converter 460 to hold its output voltage VSW at VAUX. When the supply voltage Vs is lower than the target supply voltage V tgt But is increasing, and this occurs when the linear amplifier 430 is providing current and the voltage VSW is VAUX, such that the current supplied by the DC-DC converter 460 to the PA 410 is increasing, and the two actions work together to increase the supply voltage Vs.

[0079] When the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 change state from 011 to 001, it means that the amplifier 430 has stopped providing current and is absorbing current. The decoder 450 generates its output signal (etdrv<1:0>) as 01 to instruct the DC-DC converter to generate its output voltage VSW at VBAT. This occurs when the supply voltage Vs is greater than the target supply voltage V tgt At that time. The voltage VSW is brought to VBAT such that the current supplied by the DC-DC converter 460 to the PA 410 does not increase rapidly (it can decrease or may not decrease). This will reduce the rate at which the amplifier 430 has to absorb current. The two actions work together to reduce the error in the supply voltage Vs with respect to the target supply voltage V tgt In the supply voltage Vs.

[0080] When the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 change state from 001 to 000, it means that the amplifier 430 is absorbing a current that exceeds the absorption threshold. The decoder 450 generates its output signal (etdrv<1:0>) as 00 to instruct the DC-DC converter 460 to generate its output voltage VSW at 0V. This process continues to repeat.

[0081] Figure 4DIllustrated is another table that maps the output etdrv<1:0> of decoder 450 to the output voltage VSW of DC-DC converter 460 according to another aspect of the present disclosure. This table only summarizes the above description of mapping the output of decoder 450 to the output voltage VSW of DC-DC converter 460. That is, when decoder 450 generates etdrv<1:0> as 00, this instructs DC-DC converter 460 to generate its output voltage VSW at 0V. When decoder 450 generates etdrv<1:0> as 01, this instructs DC-DC converter 460 to generate its output voltage VSW at VBAT. When decoder 450 generates etdrv<1:0> as 11, this instructs DC-DC converter 460 to generate its output voltage VSW at VAUX.

[0082] Figure 4E Illustrated is a graph of the various signals versus time associated with the operation of voltage control circuit 400 according to another aspect of the present disclosure. The top portion of the graph illustrates the sampled amplifier current I TH P versus the positive current threshold I TH N and the negative current threshold I amp_scaled As discussed above, when the sampled amplifier current I amp_scaled is greater than 0 or positive, amplifier 430 is supplying current I amp to the high voltage rail of PA 410. When the sampled amplifier current I amp_scaled is less than 0 or negative, amplifier 430 is drawing current I amp from the high voltage rail of PA 410.

[0083] The second portion from the top of the graph illustrates the states of the output signals (cmp_h, cmp_m, cmp_l) of current comparator 440. As discussed, when the output signal of current comparator 440 is 000, amplifier 430 is drawing current in excess of the draw threshold (I TH_N ). This is indicated in the first and seventh columns of the graph. When the output signal of current comparator 440 is 001, amplifier 430 is drawing current not in excess of the draw threshold (I TH_N ). This is indicated in the second and sixth columns of the graph. When the output signal of current comparator 440 is 011, amplifier 430 is supplying current not in excess of the supply threshold (I TH_P ). This is indicated in the third and fifth columns of the graph. And, when the output signal of current comparator 440 is 111, amplifier 430 is supplying current in excess of the supply threshold (I TH_P ). This is indicated in the fourth column of the graph.

[0084] The bottom portion of the graph illustrates the output signal etdrv<1:0> of decoder 450 and the corresponding output voltage VSW of DC-DC converter 460. As discussed, as indicated in the first and seventh columns of the graph, when amplifier 430 is drawing current in excess of the draw threshold (I TH_N ), the output signal etdrv<1:0> of decoder 450 is 00 to command DC-DC converter 460 to generate its output voltage VSW at 0V. Additionally, as indicated in the second column of the graph, when amplifier 430 is drawing current not in excess of the draw threshold (I TH_N ) and the drawn current is decreasing, the output signal etdrv<1:0> of decoder 450 is also 00 to indicate that DC-DC converter 460 maintain its output voltage VSW at 0V.

[0085] As indicated in the third column of the graph, when amplifier 430 is supplying current not in excess of the supply threshold (I TH_P ) and the supply current is increasing, the output signal etdrv<1:0> of decoder 450 is 01 to command DC-DC converter 460 to maintain its output voltage VSW at VBAT. As indicated in the fourth column of the graph, when amplifier 430 is supplying current in excess of the supply threshold (I TH_P ), the output signal etdrv<1:0> of decoder 450 is 11 to command DC-DC converter 460 to generate its output voltage VSW at VAUX. As indicated in the fifth column of the graph, when amplifier 430 is supplying current not in excess of the supply threshold (I TH_P ) and the supply current is decreasing, the output signal etdrv<1:0> of decoder 450 is 11 to command DC-DC converter 460 to maintain its output voltage VSW at VAUX. As indicated in the sixth column of the graph, when amplifier 430 is drawing current not in excess of the draw threshold (I TH_N ) and the drawn current is increasing, the output signal etdrv<1:0> of decoder 450 is 01 to indicate that DC-DC converter 460 generate its output voltage VSW at VBAT.

[0086] Figure 4FThe state diagram of various signals associated with the voltage control circuit 400 according to another aspect of the present disclosure is illustrated. The state diagram also summarizes the operations discussed above. Each state (represented by an ellipse) includes three vertically stacked parameters. The top parameter is the output signal (cmp_h, cmp_m, cmp_l) of the current comparator 440. The middle parameter is the output signal etdrv<1:0> of the decoder 450. And, the bottom parameter is the output voltage VSW of the DC-DC converter 460.

[0087] The first (leftmost ellipse) state relates to the period of time when the amplifier 430 is absorbing a current exceeding the absorption threshold (I TH_N ). In this state, the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 are 000, the output signal etdrv<1:0> of the decoder 450 is 00, and the output voltage VSW of the DC-DC converter 460 is 0V. From this state, the voltage control circuit 400 enters the state (upper left ellipse) where the amplifier 430 is absorbing a current not exceeding the absorption threshold (I TH_N ) and the absorption current is decreasing. In this state, the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 are 001, the output signal etdrv<1:0> of the decoder 450 remains 00, and the output voltage VSW of the DC-DC converter 460 remains 0V.

[0088] Starting from this state, the voltage control circuit 400 enters the state (upper right ellipse) where the amplifier 430 is providing a current not exceeding the supply threshold (I TH_P ) and the supply current is increasing. In this state, the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 are 011, the output signal etdrv<1:0> of the decoder 450 is 01, and the output voltage VSW of the DC-DC converter 460 is now VBAT. Starting from this state, the voltage control circuit 400 enters the state (rightmost ellipse) where the amplifier 430 is providing a current exceeding the supply threshold (I TH_P ). In this state, the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 are 111, the output signal etdrv<1:0> of the decoder 450 is 11, and the output voltage VSW of the DC-DC converter 460 is now VAUX.

[0089] Starting from this state, the voltage control circuit 400 enters the state where the amplifier 430 is providing a current not exceeding the supply threshold (I TH_P) and the state where the supply current is decreasing (lower right ellipse). In this state, the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 are 011, the output signal etdrv<1:0> of the decoder 450 is still 11, and the output voltage VSW of the DC - to - DC converter 460 is still VAUX. Starting from this state, the voltage control circuit 400 enters the state where the amplifier 430 is absorbing a current not exceeding the absorption threshold (I TH_N ) and the state where the absorption current is decreasing (lower left ellipse). In this state, the output signals (cmp_h, cmp_m, cmp_l) of the current comparator 440 are 001, the output signal etdrv<1:0> of the decoder 450 is 01, and the output voltage VSW of the DC - to - DC converter 460 is now VBAT. Starting from this state, the voltage control circuit 400 enters the first (left - most ellipse) state and repeats the process.

[0090] By changing the control voltage V in based on the input voltage signal V tgt / G, the controller 420 can change the power supply voltage Vs for the PA 410 to track the envelope of the input voltage signal V in or the output voltage signal V out , or change the power supply voltage Vs in any desired manner.

[0091] The controller 420 can program the positive current threshold I TH_P and the negative current threshold I TH_N via the threshold control signal th_set. The controller 420 can set the positive current threshold I TH_P and the negative current threshold I TH_N to be far apart, such that the current generated by the DC - to - DC converter 460 slopes slowly, reducing the noise in the power supply voltage Vs at the cost of power efficiency. Conversely, the controller 420 can set the positive current threshold I TH_P and the negative current threshold I TH_N to be relatively close to each other, such that the current generated by the DC - to - DC converter 460 slopes faster, improving power efficiency while increasing the noise in the power supply voltage Vs. Therefore, the threshold control signal th_set can be set to achieve a desired trade - off between power efficiency and noise in the power supply voltage Vs.

[0092] Figure 5 Illustrates a flowchart of an exemplary method 500 for comparing an input current (e.g., a first current) with a set of current thresholds (e.g., a second current and a third current) according to another aspect of the present disclosure.

[0093] Method 500 includes generating a first output signal based on a comparison of a first current with at least a second current (block 510). Examples of apparatus for generating a first output signal based on a comparison of a first current with at least a second current include comparator CMP1 of current comparator 200 or 440.

[0094] Method 500 further includes generating a second output signal based on a comparison of the first current with at least a third current (block 520). Examples of apparatus for generating a second output signal based on a comparison of the first current with at least a third current include comparator CMP3 of current comparator 200 or 440.

[0095] Method 500 further includes enabling the comparison of the first current with at least the second current when the comparison of the first current with at least the third current is disabled (block 530). Examples of apparatus for enabling the comparison of the first current with at least the second current when the apparatus for comparing the first current with at least the third current is disabled include comparator CMP2, inverter I, and transistor M1 configured to be turned on and transistor M2 configured to be turned off.

[0096] Alternatively, method 500 includes enabling the comparison of the first current with at least the third current when the comparison of the first current with at least the second current is disabled (block 540). Examples of apparatus for enabling the comparison of the first current with at least the third current when the apparatus for comparing the first current with at least the second current is disabled include comparator CMP2, inverter I, and transistor M1 configured to be turned off and transistor M2 configured to be turned on.

[0097] The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device, comprising: A first comparator having a first input for receiving an input signal, a second input for receiving a reference signal, and an output; A set of one or more switches having an input coupled to the output of the first comparator, wherein the set of one or more switches operates in response to a first output signal from the first comparator to select a threshold current from a set of one or more threshold currents; And A second comparator for generating a second output signal, the second comparator having a first input for receiving a signal based on a comparison of the input signal with the selected threshold current, and a second input for receiving the reference signal, the selected threshold current corresponding to the first output signal being in a first state.

2. The device according to claim 1, further comprising a third comparator for generating a third output signal based on a comparison of the input signal with the selected threshold current, the selected threshold current corresponding to the first output signal being in a second state.

3. The device according to claim 1, wherein the set of one or more switches includes n-channel metal-oxide-semiconductor field-effect transistors (NMOS), wherein the set of one or more switches includes p-channel metal-oxide-semiconductor field-effect transistors (PMOS), or wherein the set of one or more switches includes NMOS and PMOS.

4. The device according to claim 3, further comprising: A current source for generating one of the threshold currents in the set of one or more threshold currents; And A first current sink for sinking another of the threshold currents in the set of one or more threshold currents; Wherein the current source, the NMOS, the PMOS, and the first current sink are serially coupled between a high voltage rail and a low voltage rail, wherein the first input of the first comparator is coupled to a node between the NMOS and the PMOS, and wherein the gates of the NMOS and the PMOS are coupled to the output of the first comparator.

5. The device according to claim 4, further comprising a second current sink for sinking another of the threshold currents in the set of one or more threshold currents, wherein the second current sink is coupled between the first input of the first comparator and the low voltage rail.

6. The device according to claim 1, further comprising a current source for generating one of the threshold currents in the set of one or more threshold currents.

7. The device according to claim 1, further comprising a current sink for sinking one of the threshold currents in the set of one or more threshold currents.

8. The device according to claim 1, wherein the input signal includes an input current.

9. The device according to claim 1, further comprising a current device for generating three threshold currents in the set for comparison with the input signal.

10. A device, comprising: A first comparator having a first input for receiving an input signal, a second input for receiving a reference signal, and an output; A current source for providing a first threshold current; A first current sink for providing a second threshold current; A second current sink for providing a third threshold current; A set of one or more switches coupled between the current source and the first current sink and the second current sink, the set of one or more switches having an input coupled to the output of the first comparator; And A second comparator having a first input for receiving a signal based on a comparison of the input signal with a difference between the second threshold current and the first threshold current, and a second input for receiving the reference signal.

11. The apparatus according to claim 10, wherein the set of one or more switches includes an n-channel metal-oxide-semiconductor field-effect transistor (NMOS) and a p-channel metal-oxide-semiconductor field-effect transistor (PMOS).

12. The apparatus according to claim 11, wherein the current source, the NMOS, the PMOS, and the first current sink are coupled in series between a high voltage rail and a low voltage rail, wherein the first input of the first comparator is coupled to a node between the NMOS and the PMOS, and the gates of the NMOS and PMOS are coupled to the output of the first comparator.

13. The apparatus according to claim 12, wherein the second current sink is coupled between the first input of the first comparator and the low voltage rail.

14. The apparatus according to claim 10, further comprising a second comparator for comparing the input signal with a difference between the second threshold current and the first threshold current.

15. An apparatus comprising: A first comparator having a first input for receiving an input signal, a second input for receiving a reference signal, and an output; A current source for providing a first threshold current; A first current sink for providing a second threshold current; A second current sink for providing a third threshold current; A set of one or more switches coupled between the current source and the first current sink and the second current sink, the set of one or more switches having an input coupled to the output of the first comparator; And A second comparator having a first input for receiving a signal based on a comparison of the input signal with a sum of the first threshold current and the second threshold current, and a second input for receiving the reference signal.

16. An apparatus comprising: A current source; A first switching device; A second switching device; A first current sink, wherein the current source, the first switching device, the second switching device, and the first current sink are coupled in series between a first voltage rail and a second voltage rail; A first comparator including a first input coupled to a node between the current source and the first switching device, and a second input for receiving a reference signal; A second comparator, comprising: a first input coupled to a node between the second switching device and the first current sink, and a second input for receiving the reference signal; and A third comparator, comprising: a first input for receiving an input signal and coupled to a node between the first switching device and the second switching device, a second input for receiving the reference signal, and an output coupled to control inputs of the first switching device and the second switching device.

17. The apparatus according to claim 16, further comprising a second current sink coupled between the first input of the third comparator and the second voltage rail.

18. The apparatus according to claim 16, wherein the first switching device and the second switching device each comprise a field effect transistor (FET).

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