Image sensor and method for manufacturing the same

Abstract

The disclosed embodiments are related to an image sensor and a manufacturing method thereof. An image sensor includes a storage device, wherein the storage device includes a storage element, a first dielectric layer, and a light shielding element. The storage element includes a storage node and a storage transistor gate, wherein the storage transistor gate is located above the storage node. The first dielectric layer is located above a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the storage element, wherein in a vertical projection along the stacking direction of the storage element and the light shielding element on a plane, the light shielding element overlaps at least a portion of the perimeter of the storage transistor gate, and the stacking direction is perpendicular to the plane.

Description

Technical Field

[0001] The disclosed embodiments relate to an image sensor and a manufacturing method thereof. Background Art

[0002] In order to capture fast-moving objects, it is preferred to use an image sensor with a global shutter. A global shutter is often implemented by placing a memory element in each pixel of the image sensor array in addition to a photodiode and readout circuitry. The memory element is configured to temporarily store photogenerated charge, thereby enabling each row of the image sensor array to be exposed at the same time. Summary of the invention

[0003] The disclosed embodiment provides an image sensor including a storage device, wherein the storage device includes a storage element, a first dielectric layer and a light shielding element. The storage element includes a storage node and a storage transistor gate, wherein the storage transistor gate is located above the storage node. The first dielectric layer is located above a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the storage element, wherein in a vertical projection on a plane along the stacking direction of the storage element and the light shielding element, the light shielding element overlaps at least a portion of the perimeter of the storage transistor gate, and the stacking direction is normal to (or perpendicular to) the plane.

[0004] The disclosed embodiment provides an image sensor including a photosensitive device, a storage device adjacent to the photosensitive device, and a driving circuit adjacent to the storage device. The storage device includes a substrate, a PN junction, a gate dielectric layer, a gate electrode, a first dielectric layer, a shielding layer, and a second dielectric layer. The PN junction is located in the substrate. The gate dielectric layer is located on the substrate and above the PN junction. The gate electrode is located above the gate dielectric layer. The first dielectric layer has a first portion located on the gate electrode and a second portion located on the substrate, wherein the first portion is connected to the second portion. The shielding layer is located above the gate electrode and is electrically isolated from the gate electrode. The second dielectric layer is located above the shielding layer and the gate electrode, wherein in a vertical projection on the substrate along the stacking direction of the substrate and the gate electrode, the shielding layer at least overlaps with the edge of the gate electrode.

[0005] The disclosed embodiment provides a method for manufacturing an image sensor, which includes the following steps: providing a substrate; forming a storage node in the substrate; forming a storage transistor gate on the substrate and above the storage node; forming a first dielectric material on the storage transistor gate and the substrate; forming a semiconductor material on the first dielectric material; patterning the semiconductor material to form a shielding layer having a first contact hole to expose a portion of the first dielectric material located on top of the storage transistor gate; patterning the first dielectric material exposed by the first contact hole to form a first dielectric layer having a second contact hole to expose the storage transistor gate; forming a first silicide layer on the storage transistor gate exposed by the first contact hole formed in the shielding layer and the second contact hole formed in the first dielectric layer; and forming a second silicide layer on the shielding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram illustrating an image sensor according to some embodiments of the present disclosure.

[0008] Figure 2 is a schematic top view of an image sensor according to some embodiments of the present disclosure.

[0009] Figures 3 to 12 are schematic cross-sectional views of various stages in a method of manufacturing a storage device and a transistor of an image sensor according to some embodiments of the present disclosure.

[0010] Fig.13 is a schematic cross-sectional view of a storage device of a pixel unit of an image sensor according to some embodiments of the present disclosure.

[0011] Fig.14A and Fig. 14B is a schematic cross-sectional view of a storage device of an image sensor of a semiconductor structure according to some embodiments of the present disclosure.

[0012] Fig.15A and Fig. 15B is a schematic cross-sectional view of a storage device of an image sensor of a semiconductor structure according to some embodiments of the present disclosure.

[0013] Fig.16A and Fig. 16B is a schematic cross-sectional view of a storage device of an image sensor of a semiconductor structure according to some embodiments of the present disclosure.

[0014] Fig.17 is a flow chart illustrating a method of manufacturing an image sensor according to some embodiments of the present disclosure.

[0015] Fig.18 is a flow chart illustrating a method of manufacturing an image sensor according to some embodiments of the present disclosure.

[0016] [Explanation of Symbols]

[0017] 10: Image Sensor

[0018] 100: Substrate

[0019] 100t, 108t, 130t, 160t, 170t, 214t, 208t, S120M: top surface

[0020] 102a, 102b: first doping region

[0021] 104a, 104b: second doping region

[0022] 106, 206: Gate dielectric layer

[0023] 108, 208: Gate electrode

[0024] 110, 210: Spacers

[0025] 112, 212: Gate structure

[0026] 114: Storage node

[0027] 120, 160, 160': Dielectric layer

[0028] 120M: Dielectric material

[0029] 130A, 130B, 130C, 130D: semiconductor layer

[0030] 130b: Bottom surface

[0031] 130M: Semiconductor Materials

[0032] 132: Center

[0033] 134: Peripheral part

[0034] 140: Silicide layer

[0035] 140a: first silicide layer

[0036] 140b: second silicide layer

[0037] 150: Etch stop layer

[0038] 162: Part 1

[0039] 164: Part 2

[0040] 170: Conductive contact

[0041] 180: Inner connection structure

[0042] 182: Interconnect dielectric layer

[0043] 184: Internal conductive pattern

[0044] 214: Source / drain region

[0045] A-A', B-B': line

[0046] DC: driving circuit

[0047] FD: Floating Diffusion

[0048] LSE: Light Shielding Element

[0049] ME: Storage Element

[0050] O1, O2, O3, O4, OP, OP1, OP2: Open

[0051] OD1, OD2: Active area

[0052] PD: Photosensitive device

[0053] Pixout: Image Data

[0054] PR1, PR2: Photoresist layer

[0055] PU: Pixel Unit

[0056] R1, R2: Area

[0057] RS: Row select transistor

[0058] RST: Reset transistor

[0059] S301, S302, S303, S304, S305, S306, S307, S308, S309, S401, S402, S403, S404, S405, S406, S407, S408, S409, S410, S411: Steps

[0060] SD, SD2, SD3, SD4: storage devices

[0061] SF: Source follower transistor

[0062] SG: Storage gate electrode

[0063] SHG: Shutter Gate Transistor

[0064] T130: Thickness

[0065] TE: Transistor element

[0066] TG1: First transfer gate transistor

[0067] TG2: Second transfer gate transistor

[0068] X, Y, Z: direction

[0069] V aa 、V pix :Voltage

[0070] V cc : Reference voltage

[0071] W110, W130, W210: Sidewall DETAILED DESCRIPTION

[0072] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. It is contemplated that there are other components, values, operations, materials, arrangements, etc. For example, the following description in which a first feature is formed "on" or "on" a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0073] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0074] In addition, for ease of description, terms such as “first,” “second,” “third,” etc. may be used herein to describe similar or different elements or features shown in the figures, and may be used interchangeably depending on the order of presence or the context of description.

[0075] Figure 1 is a schematic diagram showing an image sensor included in a semiconductor structure according to some embodiments of the present disclosure. Figure 1 In some embodiments, the image sensor 10 includes a shutter gate transistor SHG, a photosensitive device PD, a first transfer gate transistor TG1, a storage device SD, and a driving circuit DC. The image sensor 10 may be referred to as a complementary metal-oxide-semiconductor (CMOS) image sensor. For example, the image sensor 10 includes a global shutter. It should be noted that Figure 1 The illustrated elements may constitute one pixel unit of the image sensor 10. In other words, for simplicity, only one pixel unit is shown as a representative. It should be understood that the image sensor 10 may include a pixel array composed of a plurality of pixel units.

[0076] In some embodiments, the photosensitive device PD is formed by a PN junction formed by the first doping region 102a and the second doping region 104a. In some embodiments, the first doping region 102a is doped with an n-type dopant, and the second doping region 104a is doped with a p-type dopant. However, this is not a limitation in the present disclosure. Depending on the conductivity type of the substrate used to construct the semiconductor structure, the dopants in the first doping region 102a and the second doping region 104a are interchangeable. When incident light is irradiated, the photosensitive device PD is capable of accumulating image charge in response to the incident light. For example, the photosensitive device PD includes a photodiode. It should be noted that the photodiode is only used as an exemplary illustration of the photosensitive device PD, and the present disclosure is not limited thereto. Other suitable photosensitive devices may be used as long as such devices are capable of accumulating image charge when incident light is irradiated. For example, the photosensitive device PD may include a storage device having charge storage.

[0077] In some embodiments, the shutter gate transistor SHG is coupled to the photosensitive device PD. For example, the source or drain of the shutter gate transistor SHG is coupled to a voltage V aa, to selectively deplete the image charge accumulated in the photosensitive device PD. In some embodiments, the first transfer gate transistor TG1 is located between the photosensitive device PD and the storage device SD. In some embodiments, the first transfer gate transistor TG1 can control the transfer of the image charge accumulated in the photosensitive device PD to the storage device SD. For example, during operation of the image sensor 10, the first transfer gate transistor TG1 can receive a transfer signal and perform the transfer of the image charge accumulated in the photosensitive device PD to the storage device SD based on the transfer signal.

[0078] In some embodiments, the storage device SD is coupled to the first transfer gate transistor TG1 and the photosensitive device PD to receive the image charges accumulated in the photosensitive device PD and store the received image charges in a depletion region. Figure 1 As shown, the storage device SD may be adjacent to the photosensitive device PD. In some embodiments, the storage device SD includes a first doping region 102b, a second doping region 104b, and a storage gate electrode SG. In some embodiments, the image charge is stored in the first doping region 102b, the second doping region 104b, and a substrate (e.g., Figure 3 The first doping region 102b of the storage device SD and the first doping region 102a of the photosensitive device PD can be formed simultaneously in the same step. Similarly, the second doping region 104b of the storage device SD and the second doping region 104a of the photosensitive device PD can also be formed simultaneously in the same step. However, the present disclosure is not limited thereto. In some alternative embodiments, the first doping regions 102a, 102b and the second doping regions 104a, 104b can be formed separately in different steps. Figure 2 , Figures 3 to 12 ,and Fig.13 The structure of the storage device SD is discussed in more detail.

[0079] In some embodiments, the driving circuit DC is disposed adjacent to the storage device SD. The driving circuit DC includes a second transfer gate transistor TG2, a floating diffusion FD, a reset transistor RST, a source follower transistor SF, and a row select transistor RS. In some embodiments, the second transfer gate transistor TG2 is coupled to the output of the storage device SD. Similar to the first transfer gate transistor TG1, the second transfer gate transistor TG2 also provides a function of selectively transferring the image charge accumulated in the storage device SD to the floating diffusion FD. In some embodiments, the second transfer gate transistor TG2 and the storage gate electrode SG can be actuated together to transfer the image charge stored in the storage device SD to the floating diffusion FD. For example, a bias voltage can be applied to the storage gate electrode SG and the gate of the second transfer gate transistor TG2 to generate an electric field, thereby forming a channel for charge movement. In some embodiments, due to the generated electric field, charges stored in the first doping region 102 b, the second doping region 104 b, and the substrate below the second doping region 104 b are pulled out from the first doping region 102 b and the second doping region 104 b and enter the channel of the second transfer gate transistor TG2 adjacent to the storage device SD. These charges can then travel through the channel of the second transfer gate transistor TG2 to reach the floating diffusion region FD. In some embodiments, the drain of the second transfer gate transistor TG2 can serve as the drain of the storage device SD.

[0080] In some embodiments, the floating diffusion region FD is referred to as a readout node. The floating diffusion region FD is, for example, a lightly doped n-type region at least partially formed in a p-well. In some embodiments, the floating diffusion region FD can be used as a capacitor for storing image charges.

[0081] like Figure 1 As shown, in some embodiments, the reset transistor RST is coupled to the floating diffusion region FD and the voltage V pix , to selectively reset the image charge in the floating diffusion region FD. For example, the reset transistor RST can discharge or charge the floating diffusion region FD to a preset voltage in response to the reset signal. In some embodiments, the source follower transistor SF is coupled to the floating diffusion region FD and the voltage V aaFor example, the source follower transistor SF can provide a high impedance output. The source follower transistor SF can be an amplifier transistor that amplifies the signal of the floating diffusion region FD for a readout operation. In some embodiments, the row select transistor RS is coupled to the source follower transistor SF. In some embodiments, the other end of the row select transistor RS is coupled to a readout column line (not shown) to selectively output the image data Pixout.

[0082] Since the driving circuit DC performs a readout function, in some embodiments, the driving circuit DC is referred to as a readout circuit. Figure 1 The diagram of image sensor 10 shown is only an example, and the present disclosure is not limited thereto. In some alternative embodiments, image sensor 10 may have a different circuit design. For example, first transfer gate transistor TG1 may be omitted. In some alternative embodiments, the layout of components in driver circuit DC may be changed according to circuit requirements. For example, driver circuit DC may be configured to have a plurality of transistors. Figure 1 , the driving circuit DC is illustrated as a four transistor (4T) circuit system. However, in some alternative embodiments, the driving circuit DC may be a three transistor (3T) circuit system, a five transistor (5T) circuit system, or any other suitable circuit system.

[0083] However, the present disclosure is not limited thereto. In some embodiments, the first transfer gate transistor TG1 is incorporated into the photosensitive device PD, and the second transfer gate transistor TG2 is incorporated into the storage device SD, so that the driving circuit DC is a three-transistor (3T) circuit system including a reset transistor RST, a source follower transistor SF, and a row select transistor RS.

[0084] The operation of the image sensor 10 will be briefly described below. In order to prevent the signal to be received from being mixed with the previously received signal, a reset procedure is first performed. During the reset procedure, a reference voltage V is applied to the reset transistor RST. cc To turn on the reset transistor RST, and the voltage V pix becomes the reference voltage V cc In some embodiments, the reference voltage V cc It can be 3.3V. Then, through the reset transistor RST and the voltage V pix Pull the potential of the floating diffusion region FD to the reference voltage V cc At the same time, the storage gate electrode SG and the second transfer gate transistor TG2 are turned on, so that the high reference voltage V ccThe charge previously stored in the storage device SD can be exhausted, thereby resetting the storage device SD. In some embodiments, the photosensitive device PD is exhausted together with the storage device SD. For example, the voltage V aa Set as reference voltage V cc , and the shutter gate transistor SHG can be turned on to deplete the charge previously accumulated in the photosensitive device PD. It should be noted that during this stage, the first transfer gate transistor TG1 is turned off. After ensuring that the storage device SD is reset and the photosensitive device PD is depleted, the shutter gate transistor SHG, the first transfer gate transistor TG1, and the second transfer gate transistor TG2 are turned off. When incident light is irradiated, image charges are trapped in the photosensitive device PD. In order to access the image charges accumulated in the photosensitive device PD, the first transfer gate transistor TG1 and the storage gate electrode SG are turned on so that the image charges accumulated in the photosensitive device PD are transferred to the storage device SD. In order to access the image charges stored in the storage device SD, the storage gate electrode SG and the second transfer gate transistor TG2 are turned on to transfer the image charges from the depletion region of the storage device SD to the floating diffusion region FD. Subsequently, the source follower transistor SF is turned on to amplify the signal of the floating diffusion region FD for a readout operation, and the row selection transistor RS is turned on to selectively output the image data Pixout.

[0085] Figure 2 is a schematic top view of a portion of a pixel unit included in an image sensor of a semiconductor structure according to some embodiments of the present disclosure, wherein for the purpose of illustration, the Figure 1 The arrangement of certain features in a pixel unit PU of the image sensor 10 shown in FIG. Figure 2 , the photosensitive device PD, the storage device SD, and the driving circuit DC are shown in FIG. In some embodiments, the storage device SD and the driving circuit DC are arranged adjacent to each other along a direction Y to facilitate electrical coupling between the storage device SD and the driving circuit DC, and the storage device SD and the driving circuit DC are arranged adjacent to the photosensitive device PD along a direction X to facilitate electrical coupling between the storage device SD and the photosensitive device PD, wherein the direction X is different from the direction Y. The direction X may be perpendicular to the direction Y. However, the present disclosure is not limited thereto. Other suitable arrangements may be used as long as the above electrical coupling is achieved with acceptable image charge loss during image charge transfer.

[0086] Figures 3 to 12 is a schematic cross-sectional view of various stages in a method of manufacturing a storage device and a transistor of a pixel unit included in an image sensor according to some embodiments of the present disclosure, wherein Figures 3 to 12 is along Figure 2The depicted schematic cross-sectional view of the storage device SD and the transistor (eg, transistor RST, SF, or RS) is taken along line AA′. Fig.13 is a schematic cross-sectional view of a storage device of a pixel unit included in an image sensor according to some embodiments of the present disclosure, wherein Fig.13 It is along Figure 2 A schematic cross-sectional view of the storage device SD taken along line BB' is shown. Fig.17 is a flow chart illustrating a method for manufacturing an image sensor included in a semiconductor structure according to some embodiments of the present disclosure.

[0087] refer to Figure 3 In some embodiments, a substrate 100 is provided. Figure 3 As shown, for example, the substrate 100 is divided into several regions, such as region R1 (eg, Figure 2 The position of the storage element ME and the light shielding element LSE in the storage device SD), the region R2 (for example, Figure 2 The position of the transistor element TE in the transistor RST, SF or RS of the driving circuit DC) and other areas ( Figure 3 (not shown) (e.g., Figure 2 The position of the photosensitive element such as the photosensitive device PD or the first transfer gate transistor TG1 or the second transfer gate transistor TG2 ( Figure 2 In addition, for example, the substrate 100 also includes a plurality of isolation regions (not shown), which are formed to isolate a plurality of different devices, such as storage devices (e.g., storage devices SD) and transistors (e.g., transistors RST, SF, RS, TG1, or TG2). The isolation regions may utilize isolation techniques such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI) to electrically isolate the various regions. If the isolation region is made of STI, the STI region may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. In some instances, the filled trench has a multilayer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

[0088] In some embodiments, substrate 100 is a semiconductor substrate. For example, substrate 100 may be made of: a suitable elemental semiconductor, such as crystalline silicon, diamond, or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. For example, substrate 100 may be a semiconductor on an insulator, such as silicon on insulator (SOI) or silicon on sapphire.

[0089] In some embodiments, substrate 100 is a p-type substrate. However, the present disclosure is not limited thereto. In some alternative embodiments, an n-type substrate is suitable as substrate 100. For example, substrate 100 also includes other features, such as various doped regions, buried layers, and / or epitaxial layers. Substrate 100 may include various doped regions (e.g., p-type wells or n-type wells) according to design requirements. In some embodiments, the doped regions are doped with p-type dopants (e.g., boron or BF2) and / or n-type dopants (e.g., phosphorus or arsenic). In addition, the doped regions may be formed directly on substrate 100 with a P-well structure, an N-well structure, a dual-well structure, or a raised structure.

[0090] like Figure 3 As shown and based on Fig.17 In step S301, a first doped region 102b and a second doped region 104b are formed in the substrate 100 within the region R1 to form a memory node 114. The first doped region 102b may be formed by doping the substrate 100 with a first type of dopant, and the second doped region 104b may be formed by doping the substrate 100 above the first doped region 102b with a second type of dopant. In some embodiments, the first type of dopant is different from the second type of dopant. For example, when the substrate 100 is a p-type substrate, the first doped region 102b may be doped with an n-type dopant (e.g., phosphorus or arsenic), and the second doped region 104b may be doped with a p-type dopant (e.g., boron or BF2) to form a PN junction between the first doped region 102b and the second doped region 104b. Similarly, when the substrate 100 is an n-type substrate, the first doping region 102b may be doped with a p-type dopant, and the second doping region 104b may be doped with an n-type dopant to form a PN junction between the first doping region 102b and the second doping region 104b. In some embodiments, the dopant may be doped into the first doping region 102b and the second doping region 104b by an ion implantation process.

[0091] As described above, the first doping region 102a and the second doping region 104a of the photosensitive device PD may be formed in a manner similar to the first doping region 102b and the second doping region 104b. Therefore, although not shown, it should be understood that the photosensitive device PD is located within the substrate 100.

[0092] continue Figure 3 And according to Fig.17 In step S302, in some embodiments, a gate structure 112 and a gate structure 212 are formed on the substrate 100 in the region R1 (for example, on the storage node 114) and the region R2, respectively, the gate structure 112 having a pair of spacers 110 disposed at two opposite sides thereof, and the gate structure 212 having a pair of spacers 210 disposed at two opposite sides thereof. In some embodiments, the gate structure 112 includes a gate dielectric layer 106 and a gate electrode 108 stacked on the gate dielectric layer 106 along a direction Z, and the spacers 110 are located at two opposite sides of the gate structure 112 along a direction X. In some embodiments, the direction X (and the direction Y) are different from the direction Z. For example, the direction Z is perpendicular to the direction X and / or the direction Y. Similarly, in some embodiments, the gate structure 212 includes a gate dielectric layer 206 and a gate electrode 208 stacked on the gate dielectric layer 206 along the direction Z, and the spacers 210 are located at two opposite sides of the gate structure 212 along the direction X.

[0093] In some embodiments, the gate structure 112 in the region R1 is similar to or identical to the gate structure 212 in the region R2. In some other embodiments, the elements in the gate structure 112 are different from the elements in the gate structure 212. In some embodiments, the spacer 110 in the region R1 is similar to or identical to the spacer 210 in the region R2. In some other embodiments, the spacer 110 is different from the spacer 210. It should be noted that the details described below regarding the elements of the spacer 110 and the gate structure 112 can also be applied to the elements of the spacer 210 and the gate structure 212, and thus the description of the spacer 210 and the description of the elements in the gate structure 212 are omitted. In other words, for example, the gate structures 112 and 212 are formed by the same steps, and the spacers 110 and 210 are formed by the same steps. However, the present disclosure is not limited thereto; as another option, the gate structures 112 and 212 can be formed in different steps, and the spacers 110 and 210 can be formed in different steps.

[0094] In some embodiments, the gate dielectric layer 106 and the gate electrode 108 are located on the substrate 100 in a sequence from bottom to top (e.g., in the direction Z). The gate dielectric layer 106 includes silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or a combination thereof. It should be noted that a high-k dielectric material is generally a dielectric material having a dielectric constant greater than 4. The high-k dielectric material includes a metal oxide. Examples of metal oxides for high-k dielectric materials include oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and / or combinations thereof. In some embodiments, the gate dielectric layer 106 is a high-k dielectric layer having a thickness ranging from about 10 angstroms to 30 angstroms measured along the direction Z. In some embodiments, the gate electrode 108 is made of polysilicon. The gate electrode 108 may be made of undoped polysilicon or doped polysilicon. For example, the gate electrode 108 is referred to as a polysilicon gate.

[0095] The gate dielectric layer 106 and the gate electrode 108 may be formed by forming a blanket layer (not shown) of dielectric material on the substrate 100; forming a blanket layer (not shown) of polysilicon material on the blanket layer of dielectric material; patterning the blanket layer of polysilicon material to form the gate electrode 108; and patterning the blanket layer of dielectric material to form the gate dielectric layer 106. In one embodiment, the blanket layer of dielectric material is formed using a suitable process, but not limited to, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), flowable chemical vapor deposition (FCVD), thermal oxidation, UV-ozone oxidation, or a combination thereof. In one embodiment, the blanket layer of polysilicon material is formed by ALD, CVD, or PVD, but not limited to these processes. The patterning process may include photolithography and etching processes, wherein the etching process may be, but is not limited to, dry etching, wet etching, or a combination thereof.

[0096] In some embodiments, after forming the gate structure 112 (including the gate dielectric layer 106 and the gate electrode 108), a spacer 110 is formed at two opposite sides of the gate structure 112 (e.g., the sidewalls of the gate dielectric layer 106 and the sidewalls of the gate electrode 108). The spacer 110 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluoride-doped silicate glass (FSG), a low-k dielectric material, or a combination thereof. It should be noted that a low-k dielectric material is generally a dielectric material having a dielectric constant lower than 3.9. The spacer 110 may have a multilayer structure including one or more liner layers. The liner layer includes a dielectric material, such as silicon oxide, silicon nitride, and / or other suitable materials. The formation of the spacer 110 may be achieved by depositing a suitable dielectric material and anisotropically etching away the dielectric material.

[0097] At this point, the gate structure 112, the spacer 110, and the storage node 114 formed in the region R1 together constitute a storage element ME (of the storage device SD), wherein the storage node 114 is located in the substrate 100, and the gate structure 112 and the spacer 110 are located on (the top surface 100t of) the substrate 100. For example, the storage node 114 overlaps with the gate structure 112, and the spacer 110 surrounds the gate structure 112. In some embodiments, in a vertical projection along the direction Z on the XY plane, the perimeter of the storage node 114 is surrounded by the inner edge of the spacer 110. For example, the perimeter of the storage node 114 is away from the inner edge of the spacer 110 in the vertical projection on the XY plane along the direction Z. However, the present disclosure is not limited thereto; and as another option, the perimeter of the storage node 114 may be substantially aligned with the edge of the spacer 110 in the vertical projection on the XY plane along the direction Z. In some embodiments, the storage element ME is part of a storage device SD, wherein the storage node 114 is referred to as a storage node and the gate electrode 108 is referred to as a storage gate electrode. Figure 1 ) can act as a charge source of the storage device SD, which can provide image charges to the storage node 114 of the storage element ME in the storage device SD.

[0098] like Figure 3As shown, in some embodiments, after forming the spacers 110, 210, source / drain regions 214 are formed at two opposite sides of the gate structure 212 in the region R2 in the substrate 100 to form a transistor element TE of a transistor (e.g., transistor RST, SF, or RS). For example, the source / drain regions 214 are formed at the sidewalls of the gate dielectric layer 206 and the sidewalls of the gate electrode 208. In some embodiments, the pair of source / drain regions 214 can be formed by a doping process, an epitaxial growth process, or a combination thereof. In some embodiments, the source / drain regions 214 are formed by doping the substrate 100 with a p-type dopant or an n-type dopant. In some embodiments, the dopant is doped into the source / drain regions 214 by ion implantation. Alternatively, in some embodiments, a portion of the substrate 100 is removed by etching or other suitable processes, and the dopant is formed in the hollow region by epitaxial growth. In some embodiments, the epitaxial layer includes SiGe, SiC or other suitable materials. In some embodiments, the doping process and the epitaxial growth process can be performed in-situ to form the source / drain regions 214 .

[0099] At this point, the gate structure 212, the spacer 210, and the source / drain region 214 formed in the region R2 together constitute a transistor element TE (of the transistor RST, SF, or RS), wherein the source / drain region 214 is located in the substrate 100, the gate structure 212 and the spacer 210 are located on (the top surface 100t of) the substrate 100, and a channel (not labeled) is located between the source / drain region 214 in the substrate 100 and underlying the gate structure 212 and the spacer 210. For example, the source / drain region 214 surrounds the spacer 210, and the spacer 210 surrounds the gate structure 212. In some embodiments, in a vertical projection on the XY plane along the direction Z, the gate structure 212 is surrounded by the source / drain region 214 and the spacer 210, wherein the perimeter of the gate structure 212 is away from the edge of the source / drain region 214, and the perimeter of the gate structure 212 is substantially aligned with the edge of the spacer 210. In one embodiment, the spacer 210 overlaps at least a portion of the source / drain region 214 in a vertical projection on the XY plane along the direction Z, wherein the edge of the source / drain region 214 is away from the edge of the spacer 210. For example, Figure 3As shown, the spacer 210 partially covers the surface 214t of the source / drain region 214. However, the present disclosure is not limited to this; and as another option, the source / drain region 214 is adjacent to the spacer 210 in a vertical projection on the XY plane along the direction Z, wherein the edge of the source / drain region 214 is substantially aligned with the edge of the spacer 210. The transistor element TE may be referred to as a metal-oxide-semiconductor (MOS) device. In one embodiment, if the dopant in the source / drain region 214 is a p-type dopant, the transistor element TE is a PMOS device. In an alternative embodiment, if the dopant in the source / drain region 214 is an n-type dopant, the transistor element TE is an NMOS device. In some embodiments, the transistor element TE is used as a transistor located in Figure 1 A portion of the transistors of the logic transistors (eg, reset transistor RST, source follower transistor SF, and row select transistor RS) in the driver circuit DC is shown.

[0100] In some embodiments, the type of dopant in the source / drain region 214 is the same as the type of dopant in the first doping region 102 b. However, the present disclosure is not limited thereto. In some alternative embodiments, the type of dopant in the source / drain region 214 is the same as the type of dopant in the second doping region 104 b.

[0101] refer to Figure 4 And according to Fig.17In step S303, in some embodiments, a dielectric material 120M and a semiconductor material 130M covering the memory element ME and the transistor element TE are formed on the substrate 100. In some embodiments, the dielectric material 120M and the semiconductor material 130M are individually located on the substrate 100 in a blanket layer in a sequence from bottom to top (for example, in the direction Z). The dielectric material 120M includes silicon oxide formed by deposition or other suitable methods. The deposition may include CVD (for example, high-density plasma CVD (HDPCVD) or sub-atmospheric CVD (SACVD)) or molecular layer deposition (MLD). As another option, the material of the dielectric material 120M may include silicon nitride, silicon oxynitride, a high dielectric constant dielectric material, etc.; the present disclosure is not limited thereto. In some embodiments, the dielectric material 120M is conformally formed on the memory element ME, the transistor element TE, and the substrate 100 exposed from the memory element ME and the transistor element TE, wherein the top surface 108t of the gate electrode 108, the sidewall W110 of the spacer 110, the top surface 208t of the gate electrode 208, the sidewall W210 of the spacer 210, the top surface 214t of the source / drain region 214, and the top surface 100t of the substrate 100 exposed therefrom are covered by the dielectric material 120M. In one embodiment, the thickness of the dielectric material 120M is approximately in the range of 250 angstroms to 350 angstroms when measured along the direction Z.

[0102] In some embodiments, the semiconductor material 130M is made of polysilicon or polycrystalline germanium. The semiconductor material 130M may be made of undoped polysilicon or doped polysilicon or undoped polycrystalline germanium or doped polycrystalline germanium. For example, the semiconductor material 130M is a polysilicon layer formed by deposition (e.g., CVD) or other suitable methods. In some embodiments, the semiconductor material 130M is conformally formed on the dielectric material 120M, wherein the thickness T130 of the semiconductor material 130M is approximately in the range of 200 angstroms to 500 angstroms when measured along the direction Z (e.g., the shortest distance from the bottom surface 130b of the semiconductor material 130M to the top surface 130t of the semiconductor material 130M).

[0103] refer to Figure 5 And according to Fig.17 In step S304, in some embodiments, the semiconductor material 130M is patterned to form a semiconductor layer 130A on the memory element ME (eg, on the gate structure 112 and the spacer 110). Figure 5As shown, at least a portion of the semiconductor layer 130A overlies and overlaps the edge of the spacer 110 and the gate structure 112 along the direction Z, wherein the location of the opening (or "recess" or "trench") OP1 corresponds to the location of the gate structure 112. In some embodiments, the opening OP1 formed in the semiconductor layer 130A exposes a portion of the dielectric material 120M located above the gate structure 112. For example, the top surface S120M of the dielectric material 120M located in the region R1 is partially exposed by the semiconductor layer 130A. In some embodiments, as Figure 5 As shown, the region R2 does not have the semiconductor layer 130A. For example, the top surface S120M of the dielectric material 120M located in the region R2 is completely exposed by the semiconductor layer 130A.

[0104] In some embodiments, the patterning process may include a photolithography process and an etching process. The formation of the semiconductor layer 130A may include: forming a photoresist layer PR1, the photoresist layer PR1 covers a portion of the semiconductor material 130M in the region R1 (for example, located above the storage element ME) but does not cover the semiconductor material 130M in the region R2, and removing the semiconductor material 130M not covered by the photoresist layer PR1 (in the two regions R1 and R2) by etching; and thereby forming a semiconductor layer 130A having an opening OP1 above the storage element ME. In some embodiments, the material of the photoresist layer PR1, for example, includes a positive resist material or a negative resist material suitable for a patterning process, and the patterning process is, for example, a masked photolithography process or a maskless photolithography process (for example, electron-beam (e-beam) writing or ion-beam (ion-beam) writing). In some embodiments, after the semiconductor layer 130A is formed, the photoresist layer PR1 is removed. In one embodiment, the photoresist layer PR1 is removed by an acceptable ashing process and / or a photoresist stripping process (e.g., using oxygen plasma, etc.). The present disclosure is not limited thereto. In some embodiments, the semiconductor layer 130A provides a function of shielding a previously formed element (e.g., a memory element ME) from incident light, wherein the semiconductor layer 130A is referred to as a shielding layer of a light shielding element LSE of the memory element ME. In some embodiments, the light shielding element LSE is electrically isolated from the memory element ME.

[0105] refer to Figure 6In some embodiments, the dielectric material 120M is patterned to form a dielectric layer 120 over the gate structure 112 and the spacer 110, wherein the dielectric layer 120 has an opening (or referred to as a "recess" or "groove") OP2 exposing a portion of the gate structure 112 (e.g., the top surface 108t of the gate electrode 108). In some embodiments, on the XY plane, the positioning position of the opening OP2 falls within the positioning position of the opening OP1, and the positioning position of the semiconductor layer 130A falls within the positioning position of the dielectric layer 120. For example, the gate electrode 108 is partially exposed by the opening OP2 formed in the dielectric layer 120, and the dielectric layer 120 and the gate electrode 108 partially exposed by the dielectric layer 120 are exposed by the opening OP1 formed in the semiconductor layer 130A. In some embodiments, the opening OP1 is spatially connected to the opening OP2. For example, the opening OP1 and the opening OP2 are collectively referred to as the opening OP. Figure 6 As shown, in some embodiments, in region R1, the substrate 100 and the memory element ME are partially exposed by the dielectric layer 120, and the dielectric layer 120 is partially exposed by the semiconductor layer 130A. In some embodiments, the transistor element TE does not have the dielectric layer 120. For example, the transistor element TE and the substrate 100 exposed by the transistor element TE are completely exposed by the dielectric layer 120 and the semiconductor layer 130A.

[0106] The formation of the dielectric layer 120 may include: forming a photoresist layer PR2, the photoresist layer PR2 covers a portion of the dielectric material 120M in the region R1 (with the semiconductor layer 130A overlying thereon) but does not cover the dielectric material 120M in the region R2, and removing the dielectric material 120M (in the regions R1 and R2) not covered by the photoresist layer PR2 by etching; and thereby forming the dielectric layer 120 having the opening OP2 above the memory element ME. The material of the photoresist layer PR2 may be similar or identical to the material of the photoresist layer PR1, and therefore the description of the material of the photoresist layer PR2 is omitted. During the etching process, the sidewall W130 and the top surface 130t of the semiconductor layer 130A are covered by the photoresist layer PR2 to avoid any undesirable removal of the semiconductor layer 130A. In some embodiments, after the dielectric layer 120 is formed, the photoresist layer PR2 is removed.

[0107] refer to Figure 7 And according to Fig.17In step S305, in some embodiments, a silicide layer 140 is formed to cover the exposed surface of the semiconductor layer 130A (e.g., the top surface 130t and the sidewall W130), the exposed surface of the gate electrode 108 (e.g., the top surface 108t), the exposed surface of the gate electrode 208 (e.g., the top surface 208t), and the exposed surface of the source / drain region 214 (e.g., the top surface 214t). In some embodiments, the silicide layer 140 is conformally formed to correspond to the contours of the semiconductor layer 130A, the gate electrodes 108, 208, and the source / drain region 214. In some embodiments, since the resistance between the silicide layer 140 and the later-formed element (e.g., the metal contact) is low, the silicide layer 140 provides a better conductivity between the previously formed element (e.g., the semiconductor layer 130A, the exposed gate electrodes 108, 208, and the exposed source / drain region 214) and the later-formed element. The material of the silicide layer 140 includes, for example, cobalt silicide, nickel silicide, titanium silicide, or tungsten silicide. The silicide layer 140 may be formed of a silicide material and may be formed by deposition, for example, PVD, CVD, and ALD. However, the present disclosure is not limited thereto.

[0108] In some embodiments, Figure 7 As shown, the silicide layer 140 surrounds the semiconductor layer 130A, wherein the semiconductor layer 130A and the silicide layer 140 surrounding the semiconductor layer 130A are collectively referred to as the light shielding element LSE of the storage element ME in the storage device SD. The light shielding element LSE may overlap with the perimeter of the storage element ME in a vertical projection on the XY plane along the direction Z. In some embodiments, due to the light shielding element LSE of the storage device SD, when the photosensitive device PD (such as Figure 1 When the image charge is provided to the storage node 114 of the storage element ME in the storage device SD by the light shielding element LSE (e.g., including the semiconductor layer 130A and the silicide layer 140), the storage element ME is shielded from the incident light. In this way, the semiconductor layer 130A is not electrically connected to other conductive components in the storage device SD. For example, the light shielding element LSE (e.g., the semiconductor layer 130A) can be grounded.

[0109] In some embodiments, the dielectric layer 120 is located between the light shielding element LSE (e.g., the semiconductor layer 130A and the silicide layer 140) and the storage element ME (e.g., the gate structure 112 and the spacer 110) and between the semiconductor layer 130A and the substrate 100. It should be noted that sufficient isolation between the gate electrode 108 and the semiconductor layer 130A is crucial to ensure the reliability of the storage device SD. For example, when the minimum distance between the gate electrode 108 and the semiconductor layer 130A is small enough, the breakdown voltage (Vbd) of the storage device SD will be sharply reduced, resulting in a phenomenon of Vbd tailing during reliability testing. In other words, when there is no sufficient isolation between the gate electrode 108 and the semiconductor layer 130A, the device life of the storage device SD will be shortened. Due to the dielectric layer 120 (having the above-mentioned specific thickness range) between the gate electrode 108 (of the storage element ME) and the semiconductor layer 130A (of the light shielding element LSE), sufficient isolation between the gate electrode 108 and the semiconductor layer 130A can be provided, thereby ensuring a longer life of the storage device SD.

[0110] Alternatively, the silicide layer 140 may be formed by the following steps: forming a metal conductive material (not shown) to contact the exposed semiconductor layer 130A, the exposed gate electrodes 108, 208, and the exposed source / drain regions 214; performing a heat treatment on the metal conductive material so that a portion of the metal conductive layer covering (contacting) the exposed semiconductor layer 130A, the exposed gate electrodes 108, 208, and the exposed source / drain regions 214 reacts with the exposed semiconductor layer 130A, the exposed gate electrodes 108, 208, and the exposed source / drain regions 214 to form a metal silicide layer (e.g., the silicide layer 140); and removing the remaining unreacted metal conductive layer. The heat treatment may include, for example, argon (Ar) rapid thermal annealing, hydrogen (H2) furnace thermal annealing, etc.

[0111] refer to Figure 8 In some embodiments, Figure 7 An etch stop layer 150 is formed on the structure shown. Specifically, the etch stop layer 150 is formed to overlie the storage device SD (including the memory element ME) and the transistor element TE. Figure 8As shown. The etch stop layer 150 may be referred to as a contact etch stop layer (CESL). The etch stop layer 150 comprises, for example, silicon nitride, carbon-doped silicon nitride, or a combination thereof. In some embodiments, the etch stop layer 150 is deposited, for example, by using processes such as CVD, HDPCVD, SACVD, MLD, or other suitable methods. In some embodiments, before forming the etch stop layer 150, a buffer layer (not shown) is further formed on the substrate 100. In an embodiment, the buffer layer is an oxide, such as silicon oxide; however, the present disclosure is not limited thereto, and other compositions may be utilized. In some embodiments, the buffer layer is deposited by processes such as CVD, HDPCVD, SACVD, MLD, or other suitable methods.

[0112] refer to Fig. 9 And according to Fig.17 In step S306, in some embodiments, a dielectric layer 160 is formed on the etch stop layer 150 covering the storage device SD (including the storage element ME) and the transistor element TE. In some embodiments, the dielectric layer 160 is formed in a conformal manner. In some embodiments, the dielectric layer 160 is referred to as an interlayer dielectric layer (ILD). The dielectric layer 160 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbide oxynitride, spin-on glass (SOG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), FSG, carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In some alternative embodiments, the dielectric layer 160 may include a low dielectric constant dielectric material. Examples of low dielectric constant dielectric materials include black diamond (BLACK DIAMOND) (Applied Materials of Santa Clara, Calif.), xerogel, aerogel, amorphous fluorinated carbon, parylene, bis-benzocyclobutene (BCB), Flare, (Dow Chemical, Midland, Mich.), hydrogen silsesquioxane (HSQ) or fluorinated silicon oxide (SiOF) and / or combinations thereof. It should be understood that dielectric layer 160 may include one or more dielectric materials. In some embodiments, dielectric layer 160 is formed to a suitable thickness by FCVD, CVD, HDPCVD, SACVD, spin coating, sputtering or other suitable methods.

[0113] In some embodiments, the dielectric layer 160 is planarized to obtain a top surface 160t with high coplanarity, thereby facilitating subsequent process steps. The planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, an etching process, or other suitable processes or combinations thereof.

[0114] refer to Fig.10 And according to Fig.17 In step S307, in some embodiments, the dielectric layer 160 and the etch stop layer 150 are patterned to form a plurality of openings (or referred to as "recesses" or "grooves"), such as openings O1 to O4. In some embodiments, the openings O1, O2, O3, and O4 penetrate the dielectric layer 160 and the etch stop layer 150, wherein the openings O1, O2, O3, and O4 respectively expose the silicide layer 140 overlying at least one of the gate electrode 108, the semiconductor layer 130A, the gate electrode 208, and the source / drain region 214 for future electrical connection. In some embodiments, the patterning process may include a photolithography process and an etching process.

[0115] refer to Fig.11 And according to Fig.17 In step S308, in some embodiments, a plurality of conductive contacts 170 are formed to fill the openings O1 to O4. In some embodiments, the conductive contacts 170 may be formed in the following manner. First, a conductive material (not shown) is deposited on the dielectric layer 160, and the conductive material is filled into the openings O1 to O4. Subsequently, the portion of the conductive material outside the openings O1 to O4 is removed to obtain the conductive contacts 170. In some embodiments, the conductive material may be removed by a CMP process, an etching process, or other suitable process. Fig.11As shown, for example, the top surface 170t of the conductive contact 170 is substantially flush and substantially coplanar with the top surface 160t of the dielectric layer 160. The conductive contact 170 may be referred to as a metal contact of the storage element ME and the light shielding element LSE of the storage device SD and the transistor element TE. For example, in the region R1, the conductive contact 170 formed in the opening O1 is electrically coupled to the gate structure 112 of the storage element ME through the silicide layer 140, and the conductive contact 170 formed in the opening O2 is electrically coupled to the semiconductor layer 130A through the silicide layer 140. Similarly, for example, in the region R2, the conductive contact 170 formed in the opening O3 is electrically coupled to the gate structure 212 of the transistor element TE through the silicide layer 140, and the conductive contact 170 formed in the opening O4 is electrically coupled to at least one of the source / drain regions 214 through the silicide layer 140.

[0116] refer to Fig.12 And according to Fig.17 In step S309, in some embodiments, an interconnect structure 180 is formed over the dielectric layer 160 and the conductive contact 170. During this stage, the storage device SD and the transistor (e.g., transistor RST, SF, or RS) are substantially completed. Similarly, the formation of the first transfer gate transistor TG1 between the photosensitive device PD and the storage device SD and the second transfer gate transistor TG2 between the storage device SD and the driving circuit DC can be formed in a manner similar to or the same as the formation of the transistors in the region R2 (e.g., transistor RST, SF, or RS), and therefore the formation of the first transfer gate transistor TG1 and the second transfer gate transistor TG2 is omitted for simplicity.

[0117] The interconnect structure 180 includes an interconnect dielectric layer 182 and a plurality of interconnect conductive patterns 184 at least partially embedded in the interconnect dielectric layer 182. In some embodiments, the material of the interconnect dielectric layer 182 includes polyimide, epoxy resin, acrylic resin, phenolic resin, BCB, polybenzoxazole (PBO) or any other suitable polymer dielectric material. The interconnect dielectric layer 182 can be formed, for example, by suitable manufacturing techniques such as spin coating, CVD, PECVD, etc. The interconnect conductive pattern 184 can be formed in the following manner. First, the interconnect dielectric layer 182 is patterned to form a plurality of openings (or referred to as "recesses" or "grooves") by photolithography and etching processes. Thereafter, the interconnect conductive pattern 184 is formed on the interconnect dielectric layer 182, and the interconnect conductive pattern 184 is formed to extend into the opening of the interconnect dielectric layer 182. The interconnect conductive pattern 184 can be formed, for example, by electroplating, deposition and / or photolithography and etching. In some embodiments, the material of the interconnect conductive pattern 184 includes aluminum, titanium, copper, nickel, tungsten and / or alloys thereof.

[0118] In some embodiments, Fig.12 As shown, the conductive contact 170 formed in the opening O1 contacts both the silicide layer 140 located on the gate electrode 108 and the internally connected conductive pattern 184 to provide an electrical connection between the gate electrode 108 and the internally connected conductive pattern 184, and the conductive contact 170 formed in the opening O2 contacts both the silicide layer 140 located on the semiconductor layer 130A and the internally connected conductive pattern 184 to provide an electrical connection between the semiconductor layer 130A and the internally connected conductive pattern 184. Similarly, for example, the conductive contact 170 formed in the opening O3 contacts both the silicide layer 140 located on the gate electrode 208 and the internally connected conductive pattern 184 to provide an electrical connection between the gate electrode 208 and the internally connected conductive pattern 184, and the conductive contact 170 formed in the opening O4 contacts both the silicide layer 140 located on at least one of the source / drain regions 214 and the internally connected conductive pattern 184 to provide an electrical connection between the at least one of the source / drain regions 214 and the internally connected conductive pattern 184.

[0119] although Fig.12 One layer of the interconnect structure 180 is shown, but the present disclosure is not limited thereto. In some alternative embodiments, the interconnect structure 180 may be a multi-layer structure. For example, the interconnect structure 180 may include a plurality of interconnect dielectric layers 182 sequentially stacked on each other and a plurality of interconnect conductive patterns 184 sandwiched between / embedded in the interconnect dielectric layers 182.

[0120] Fig.13 It is along Figure 2 Schematic cross-sectional view of region R1 (for storage device SD) along line BB' in FIG. Figure 2 , the light shielding element LSE is located in the region R1 (for the storage device SD) and is not located in other regions such as the region R2 (for the driving circuit DC). For example, in some embodiments, from a top view (e.g., XY plane), the semiconductor layer 130A surrounds the conductive contact 170 in the region R1, while the semiconductor layer 130A does not surround the conductive contact 170 in the region R2.

[0121] Also refer to Figure 2 , Fig.12 and Fig.13For example, from a top view, the semiconductor layer 130A substantially covers the gate electrode 108 and the active area OD1 of the storage device SD, and exposes the gate electrode 208 and the active area OD2 of the transistor (e.g., the transistor RST, SF, or RS in the driving circuit DC). In some embodiments, the active area OD1 may be a region that performs a storage function of the storage device SD, and the active area OD2 may be a region that performs a logic processing function of the driving circuit DC. For example, the active area OD1 of the storage device SD may include at least a storage element ME having a first doping region 102b, a second doping region 104b, and a gate electrode 108, and the active area OD2 of the transistor (e.g., the transistor RST, SF, or RS in the driving circuit DC) may include at least a transistor element TE having a source / drain region 214 and a gate electrode 208. As described above, since the storage device SD is used to store image charges received from the photosensitive device PD, the active area OD1 of the storage device SD is preferably not irradiated by incident light to avoid damaging the stored image charges. By using a light shielding element LSE (e.g., semiconductor layer 130A) covering the active area OD1 of the storage device SD, the active area OD1 of the storage device SD can be shielded from incident light. In this way, damage to the image charge stored in the storage device SD can be fully prevented, thereby providing accurate image data for readout. Since the semiconductor layer 130A provides the function of shielding the active area OD1 of the storage device SD from incident light, in some embodiments, the semiconductor layer 130A can be electrically grounded through the conductive contact 170 and the silicide layer 140 formed in the opening O2.

[0122] In some embodiments, Figure 2 , Fig.12 and Fig.13 As shown, for the light shielding element LSE, the semiconductor layer 130A includes a central portion 132 and a peripheral portion 134 surrounding the central portion 132, wherein the thickness T130 of the semiconductor layer 130A is constant. In some embodiments, from a top view (e.g., XY plane), the positioning position of the peripheral portion 134 is offset relative to the positioning position of the gate structure 112. On the XY plane in the direction Z, the projection of the central portion 132 may partially overlap with the projection of the gate structure 112. For example, the central portion 132 includes a plate structure having an opening OP1, wherein the opening OP1 overlaps with a portion of the gate structure 112, the plate structure extends on the substrate 100 and above the gate structure 112 in a conformal manner (corresponding to the geometric shape of the storage element ME), and the peripheral portion 134 extends on the substrate 100 and beside the gate structure 112. However, the present disclosure is not limited thereto.

[0123] In an alternative embodiment, in the light shielding element LSE, the semiconductor layer 130A may be replaced by the semiconductor layer 130B, see Fig.14A and Fig. 14B The storage device SD2 shown in FIG. is similar to the storage device SD2 shown in FIG. Fig.12 and Fig.13 , Fig.14A It is along Figure 2 Schematic cross-sectional view of region R1 (for storage device SD2) along line AA' in FIG. Fig. 14B It is along Figure 2 Schematic cross-sectional view of region R1 (for storage device SD2) along line BB' in FIG. Elements similar or substantially the same as previously described elements will use the same reference numerals, and certain details or descriptions of the same elements may not be repeated here. In some embodiments, Fig.12 and Fig.13 Compared to the semiconductor layer 130A shown in FIG. 1 , the semiconductor layer 130B does not include the peripheral portion 134. Fig.14A and Fig. 14B As shown, the semiconductor layer 130B includes only a central portion 132 , wherein a thickness T130 of the semiconductor layer 130B is constant.

[0124] In other alternative embodiments, in the light shielding element LSE, the semiconductor layer 130A may be replaced by a semiconductor layer 130C, see Fig.15A and Fig. 15B The storage device SD3 shown in FIG. is similar to the storage device SD3 shown in FIG. Fig.12 and Fig.13 , Fig.15A It is along Figure 2 Schematic cross-sectional view of region R1 (for storage device SD3) along line AA' in FIG. Fig. 15B It is along Figure 2 1 is a schematic cross-sectional view of region R1 (for storage device SD3) along line BB' in FIG. Elements similar to or substantially identical to previously described elements will use the same reference numerals, and certain details or descriptions of the same elements may not be repeated here. In some embodiments, compared to semiconductor layer 130A, the difference is that the thickness T130 of semiconductor layer 130C is non-constant. For example, Fig.15A and Fig. 15B As shown, the top surface 130t of the semiconductor layer 130C is substantially parallel to the top surface 100t of the substrate 100, wherein the thickness T130 of the semiconductor layer 130C increases along a direction from the central portion 132 toward the peripheral portion 134 (e.g., a radial direction from the edge of the opening OP1 toward the outer periphery of the peripheral portion 134).

[0125] In some alternative embodiments, in the light shielding element LSE, the semiconductor layer 130A may be replaced by a semiconductor layer 130D, see Fig.16A and Fig. 16B The storage device SD4 shown in FIG. Fig.12 and Fig.13 , Fig.16A It is along Figure 2 Schematic cross-sectional view of region R1 (for storage device SD4) along line AA' in FIG. Fig. 16B It is along Figure 2 Schematic cross-sectional view of region R1 (for storage device SD4) along line BB' in FIG. Elements similar to or substantially identical to previously described elements will use the same reference numerals, and certain details or descriptions of the same elements may not be repeated here. In some embodiments, storage device SD4 uses a dielectric layer 160' to replace dielectric layer 160, wherein dielectric layer 160' includes a first portion 162 and a second portion 164 stacked on first portion 162 along direction Z.

[0126] like Fig.16A and Fig. 16B As shown, a storage node 114 (including a first doped region 102 b and a second doped region 104 b) is located in a substrate 100, a gate structure 112 and a spacer 110 are located on the substrate 100 and on the storage node 114 to form a storage element ME, a dielectric layer 120 is located on the storage element ME and partially exposes a portion of the gate electrode 108, a silicide layer 140 a is located on the portion of the gate electrode 108 exposed by an opening OP2 of the dielectric layer 120, a first portion 162 of a dielectric layer 160 ′ is located on the storage element ME, a light shielding element LSE (including a semiconductor layer 130D and a silicide layer 140 b disposed thereon) is located on the first portion 162, a second portion 164 of the dielectric layer 160 ′ is located on the light shielding element LSE, a conductive contact 170 is located in the dielectric layer 160 ′ to be electrically coupled to the storage element ME and the light shielding element LSE, and an interconnect structure 180 is located on the dielectric layer 160 ′ and electrically connected to the conductive contact 170. For example, one of the conductive contacts 170 is located in the opening O1 penetrating the first portion 162 and the second portion 164 of the dielectric layer 160' to be electrically coupled to the storage element ME by contacting the silicide layer 140a. For another example, one of the conductive contacts 170 is located in the opening O2 penetrating the second portion 164 of the dielectric layer 160' to be electrically coupled to the light shielding element LSE by contacting the silicide layer 140b. The silicide layer 140b may be in contact with the top surface 130t of the semiconductor layer 130D. The silicide layer 140b may further be in contact with the sidewall W130 of the semiconductor layer 130D.

[0127] In some embodiments, Fig.16A and Fig. 16B In the embodiment of the present invention, the dielectric layer 120, the etch stop layer 150, and the first portion 162 of the dielectric layer 160' are located between the semiconductor layer 130D and the gate electrode 108, which can undoubtedly provide sufficient isolation between the light shielding element LSE (e.g., the semiconductor layer 130D) and the storage element ME (e.g., the gate electrode 108), thereby ensuring a longer life of the storage device SD4. In some embodiments, in the light shielding element LSE, the semiconductor layer 130D includes a central portion 132 and a peripheral portion 134 surrounding the central portion 132, wherein the thickness T130 of the semiconductor layer 130D is constant. In some embodiments, from a top view (e.g., an XY plane), the positioning position of the peripheral portion 134 is offset relative to the positioning position of the gate structure 112. In a vertical projection on the XY plane along the direction Z, the central portion 132 may partially overlap with the gate structure 112. For example, the central portion 132 includes a plate structure having an opening (not labeled), wherein the opening overlaps the opening O1 and a portion of the gate structure 112, the plate structure extends on the substrate 100 and over the gate structure 112 in a non-conformal manner (corresponding to the geometry of the memory element ME), and the peripheral portion 134 extends on the substrate 100 and beside the gate structure 112. However, the present disclosure is not limited thereto. In other words, the plate structure of the semiconductor layer 130D is flat and planar.

[0128] The formation and materials of the first silicide layer 140a and the second silicide layer 140b are Figure 7 The formation and material of the silicide layer 140 described in the foregoing are similar or substantially the same, and the formation and material of the first portion 162 and the second portion 164 of the dielectric layer 160' are similar or substantially the same. Fig. 9 The formation and materials of the dielectric layer 160 described in are similar or substantially the same and thus are not repeated here for the sake of brevity.

[0129] In one embodiment, the storage device SD4 can be Fig.18 It should be understood that Fig.18 Other processing may occur before, during, and after the illustrated actions of the method to complete the formation of the storage device SD4. Fig.18 The method at least includes steps S401 to S411. For example, Fig.18The method shown begins with step S401, which forms a storage node in a substrate; step S402, which forms a gate structure above the storage node; step S403, which forms a first silicide layer above the gate structure; step S404, which forms a first portion of an interlayer dielectric (ILD) layer; step S405, which forms a semiconductor material above the first portion of the ILD layer; step S406, which patterns the semiconductor material to form a semiconductor layer above the gate structure; step S407, which forms a second silicide layer above the semiconductor layer; step S408, which forms a second portion of the ILD layer; step S409, which forms a plurality of openings in the first portion and / or the second portion of the ILD layer to expose the first silicide layer located above the gate structure and the second silicide layer located above the semiconductor layer; step S410, which forms a plurality of metal contacts in the openings to be electrically coupled to the semiconductor layer and the gate structure; and step S411, which forms an interconnect on the ILD layer, the interconnect being electrically coupled to the metal contacts.

[0130] According to some embodiments, an image sensor includes a storage device, wherein the storage device includes a storage element, a first dielectric layer, and a light shielding element. The storage element includes a storage node and a storage transistor gate, wherein the storage transistor gate is located above the storage node. The first dielectric layer is located above a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the storage element, wherein in a vertical projection on a plane along the stacking direction of the storage element and the light shielding element, the light shielding element overlaps at least a portion of the perimeter of the storage transistor gate, and the stacking direction is normal to (or perpendicular to) the plane.

[0131] In some embodiments, in the image sensor, the storage node includes a PN junction. In some embodiments, in the image sensor, the storage element further includes: a first metal silicide layer located above the storage transistor gate exposed by the first dielectric layer and electrically coupled to the storage transistor gate exposed by the first dielectric layer, wherein the storage transistor gate includes: a gate electrode, a portion of the gate electrode is exposed by a first recess formed in the first dielectric layer; and a gate dielectric layer located between the storage node and the gate electrode, wherein the first metal silicide layer is in contact with the portion of the gate electrode exposed by the first recess formed in the first dielectric layer. In some embodiments, in the image sensor, the light shielding element further includes: a second metal silicide layer located above the semiconductor layer and in contact with the semiconductor layer. In some embodiments, in the image sensor, the storage device further comprises a substrate, the storage node is located in the substrate, and the storage transistor gate is located on the substrate, wherein the first dielectric layer comprises: a first dielectric portion extending above the storage transistor gate; and a second dielectric portion extending above the substrate and beside the storage transistor gate, and the first dielectric portion and the second dielectric portion are connected to each other, and wherein the light shielding element comprises: a first shielding portion located on the first dielectric portion. In some embodiments, in the image sensor, wherein the storage device further comprises: a second dielectric layer located between the light shielding element and the storage element, and located between the first dielectric layer and the light shielding element. In some embodiments, in the image sensor, the light shielding element further comprises: a second shielding portion located above the second dielectric portion, and the first dielectric portion and the second dielectric portion are connected to each other. In some embodiments, in the image sensor, the thickness of the light shielding element is non-constant. In some embodiments, in the image sensor, the storage device further comprises: a second dielectric layer located between the light shielding element and the storage element, and located between the first dielectric layer and the light shielding element. In some embodiments, in the image sensor, the light shielding element is configured to be electrically grounded.

[0132] According to some embodiments, an image sensor includes a photosensitive device, a storage device adjacent to the photosensitive device, and a driving circuit adjacent to the storage device. The storage device includes a substrate, a PN junction, a gate dielectric layer, a gate electrode, a first dielectric layer, a shielding layer, and a second dielectric layer. The PN junction is located in the substrate. The gate dielectric layer is located on the substrate and above the PN junction. The gate electrode is located on the gate dielectric layer. The first dielectric layer has a first portion located on the gate electrode and a second portion located on the substrate, wherein the first portion is connected to the second portion. The shielding layer is located on the gate electrode and is electrically isolated from the gate electrode. The second dielectric layer is located on the shielding layer and the gate electrode, wherein in a vertical projection on the substrate along the stacking direction of the substrate and the gate electrode, the shielding layer at least overlaps with the edge of the gate electrode.

[0133] In some embodiments, in the image sensor, the storage device further comprises: a first metal contact located in the second dielectric layer and electrically grounding the shielding layer; a second metal contact located in the second dielectric layer and electrically coupled to the gate electrode, the second metal contact penetrating the second dielectric layer and passing through a first recess formed in the shielding layer and a second recess formed in the first dielectric layer; and an internal connection located on the second dielectric layer and electrically coupled to the first metal contact and the second metal contact. In some embodiments, in the image sensor, in the vertical projection on the substrate along the stacking direction, the first recess formed in the shielding layer and the second recess formed in the first dielectric layer overlap with the gate electrode. In some embodiments, in the image sensor, in the vertical projection on the substrate along the stacking direction, the perimeter of the first recess formed in the shielding layer is offset relative to the perimeter of the second recess formed in the first dielectric layer. In some embodiments, in the image sensor, the shielding layer includes: a first plate structure having a first shielding part and a second shielding part, a recess formed in the first shielding part, the second shielding part connected to the first shielding part and surrounding the first shielding part, wherein the first shielding part extends on the first part of the first dielectric layer, the recess is located on the top of the gate electrode, and the second shielding part extends on the second part of the first dielectric layer; or a second plate structure having a third shielding part, a recess formed in the third shielding part, wherein the third shielding part extends on the first part of the first dielectric layer, and the recess is located on the top of the gate electrode.

[0134] According to some embodiments, a method for manufacturing an image sensor includes the following steps: providing a substrate; forming a storage node in the substrate; forming a storage transistor gate on the substrate and above the storage node; forming a first dielectric material over the storage transistor gate and the substrate; forming a semiconductor material over the first dielectric material; patterning the semiconductor material to form a shielding layer having a first contact hole to expose a portion of the first dielectric material located on top of the storage transistor gate; patterning the first dielectric material exposed by the first contact hole to form a first dielectric layer having a second contact hole to expose the storage transistor gate; forming a first silicide layer on the storage transistor gate exposed by the first contact hole formed in the shielding layer and the second contact hole formed in the first dielectric layer; and forming a second silicide layer on the shielding layer.

[0135] In some embodiments, in the method of manufacturing an image sensor, the first silicide layer and the second silicide layer are formed in the same step. In some embodiments, the method of manufacturing an image sensor further comprises: globally depositing an etch stop layer on the first silicide layer and the second silicide layer; depositing a second dielectric layer on the etch stop layer; forming a first conductive contact in a first opening penetrating the etch stop layer and the second dielectric layer to electrically couple to the storage transistor gate through the first silicide layer; forming a second conductive contact in a second opening penetrating the etch stop layer and the second dielectric layer to electrically couple to the shielding layer through the second silicide layer; and forming an internal connection electrically coupled to the first conductive contact and the second conductive contact. In some embodiments, in the method of manufacturing an image sensor, forming the storage node in the substrate further comprises forming a photosensitive node in the substrate away from the storage node. In some embodiments, in the method of manufacturing an image sensor, forming the storage transistor gate on the substrate and above the storage node further comprises: forming a transistor gate on the substrate and between the storage node and the photosensitive node and away from the storage transistor gate.

[0136] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor, comprising: Storage devices, including: Storage elements, including: Storage nodes; and a storage transistor gate located on the storage node; a first dielectric layer overlying a portion of the storage transistor gate; and A light shielding element, located on the first dielectric layer and comprising: a semiconductor layer electrically isolated from the memory element, wherein the light shielding element overlaps at least a portion of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element; and a second metal silicide layer, located on the semiconductor layer and in contact with the semiconductor layer; The stacking direction is perpendicular to the plane. 2 . The image sensor according to claim 1 , wherein the storage node comprises a PN junction.

3. The image sensor according to claim 1, wherein the storage element further comprises: a first metal silicide layer located on the storage transistor gate exposed by the first dielectric layer and electrically coupled to the storage transistor gate exposed by the first dielectric layer, The storage transistor gate comprises: a gate electrode, a portion of which is exposed by a first recess formed in the first dielectric layer; and a gate dielectric layer located between the storage node and the gate electrode, The first metal silicide layer is in contact with the portion of the gate electrode exposed by the first recess formed in the first dielectric layer. The image sensor according to claim 1 , wherein the second metal silicide layer covers the semiconductor layer.

5. The image sensor according to claim 1, wherein the storage device further comprises a substrate, the storage node is located in the substrate, and the storage transistor gate is located on the substrate, The first dielectric layer comprises: a first dielectric portion extending over the storage transistor gate; as well as a second dielectric portion extending above the substrate and beside the storage transistor gate, wherein the first dielectric portion and the second dielectric portion are connected to each other, and wherein the light shielding element comprises: The first shielding part is located on the first dielectric part.

6. The image sensor according to claim 5, wherein the storage device further comprises: The second dielectric layer is located between the light shielding element and the storage element, and between the first dielectric layer and the light shielding element.

7. The image sensor according to claim 5, wherein the light shielding element further comprises: The second shielding part is located on the second dielectric part, and the first shielding part and the second shielding part are connected to each other. The image sensor according to claim 7 , wherein a thickness of the light shielding member is non-constant.

9. The image sensor according to claim 7, wherein the storage device further comprises: The second dielectric layer is located between the light shielding element and the storage element, and between the first dielectric layer and the light shielding element. 10 . The image sensor according to claim 1 , wherein the light shielding member is configured to be electrically grounded.

11. An image sensor, comprising: Photosensitive device; A storage device, adjacent to the photosensitive device and comprising: substrate; A PN junction is located in the substrate; A gate dielectric layer, located on the substrate and above the PN junction; A gate electrode, located on the gate dielectric layer; a first dielectric layer having a first portion located on the gate electrode and a second portion located on the substrate, the first portion being connected to the second portion; a shielding layer located on the gate electrode and electrically isolated from the gate electrode, wherein the shielding layer comprises a semiconductor layer located on the first dielectric layer and a metal silicide layer covering the semiconductor layer; and a second dielectric layer located on the shielding layer and the gate electrode, wherein in a vertical projection on the substrate along the stacking direction of the substrate and the gate electrode, the shielding layer at least overlaps with an edge of the gate electrode; and The driving circuit is adjacent to the storage device.

12. The image sensor according to claim 11, wherein the storage device further comprises: a first metal contact disposed in the second dielectric layer and electrically grounding the shielding layer; a second metal contact located in the second dielectric layer and electrically coupled to the gate electrode, the second metal contact penetrating the second dielectric layer and passing through a first recess formed in the shielding layer and a second recess formed in the first dielectric layer; as well as The inner connection is located on the second dielectric layer and is electrically coupled to the first metal contact and the second metal contact. 13 . The image sensor according to claim 12 , wherein in the vertical projection along the stacking direction on the substrate, the first recess formed in the shielding layer and the second recess formed in the first dielectric layer overlap the gate electrode. 14 . The image sensor of claim 13 , wherein in the vertical projection along the stacking direction on the substrate, a perimeter of the first recess formed in the shielding layer is offset relative to a perimeter of the second recess formed in the first dielectric layer.

15. The image sensor according to claim 11, wherein the shielding layer comprises: a first plate structure having a first shielding portion and a second shielding portion, the first shielding portion having a recess formed therein, the second shielding portion being connected to and surrounding the first shielding portion, wherein the first shielding portion extends over the first portion of the first dielectric layer, the recess being located on top of the gate electrode, and the second shielding portion extending over the second portion of the first dielectric layer; or A second plate structure has a third shielding portion with a recess formed therein, wherein the third shielding portion extends over the first portion of the first dielectric layer and the recess is located on top of the gate electrode.

16. A method for manufacturing an image sensor, comprising: providing a substrate; forming a storage node in the substrate; forming a storage transistor gate on the substrate and above the storage node; forming a first dielectric material over the storage transistor gate and the substrate; forming a semiconductor material over the first dielectric material; patterning the semiconductor material to form a shielding layer having a first contact hole to expose a portion of the first dielectric material located on top of the storage transistor gate; patterning the first dielectric material exposed by the first contact hole to form a first dielectric layer having a second contact hole, thereby exposing the storage transistor gate; forming a first silicide layer on the storage transistor gate exposed by the first contact hole formed in the shielding layer and the second contact hole formed in the first dielectric layer; as well as A second silicide layer is formed on the shielding layer. 17 . The method according to claim 16 , wherein the first silicide layer and the second silicide layer are formed in a same step.

18. The method according to claim 16, further comprising: globally depositing an etch stop layer over the first silicide layer and the second silicide layer; depositing a second dielectric layer over the etch stop layer; forming a first conductive contact in a first opening penetrating the etch stop layer and the second dielectric layer to be electrically coupled to the storage transistor gate through the first silicide layer; forming a second conductive contact in a second opening through the etch stop layer and the second dielectric layer to electrically couple to the shielding layer through the second silicide layer; as well as An internal connection is formed that is electrically coupled to the first conductive contact and the second conductive contact.

19. The method of claim 16, wherein forming the storage node in the substrate further comprises forming a photosensitive node in the substrate away from the storage node.

20. The method of claim 19, wherein forming the storage transistor gate on the substrate and above the storage node further comprises: A transistor gate is formed on the substrate and between the storage node and the photosensitive node and away from the storage transistor gate.

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