Cellular structure of shield gate trench MOSFET and manufacturing method thereof

Abstract

The invention discloses a cellular structure of a shield gate trench MOSFET and a manufacturing method thereof, the cellular structure of the shield gate trench MOSFET comprises a substrate, a drift region and an interlayer dielectric layer, the drift region is provided with a deep trench, and the deep trench is internally provided with a shield gate, an intermediate oxide layer and a control gate; a body region and a source region are formed at the upper part of the drift region through injection, the interlayer dielectric is provided with a source electrode contact hole which penetrates through the source region and extends into the body region, and highly doped contact regions are formed on the side wall and the bottom of the source electrode contact hole through injection; and a charge balance region is formed below the source electrode contact hole through high-energy ion implantation. According to the invention, by arranging the charge balance region, the lateral depletion of the shield gate to the adjacent drift region can be enhanced when the shield gate trench MOSFET device is in a reverse bias state, the specific on-resistance of the device is reduced, the depletion of the drift region of the epitaxial layer is accelerated, and the reliability and radiation resistance of the device are improved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit applications, and in particular relates to a cell structure of a shielded gate trench MOSFET and a manufacturing method thereof. Background Art

[0002] Trench MOSFET improves performance by building the gate in the deep trench inside the structure on the basis of traditional DMOS. The structure of the trench gate in the trench MOSFET passes through the P-type body region to the bottom of the P-type body region, forming a channel between the source region and the drain region, effectively reducing the JFET region in the traditional DMOS. Therefore, the total on-resistance of the trench MOSFET is significantly reduced. In addition, the reduction of the total on-resistance is not only due to the elimination of the series resistance of the JFET region, but also the vertical structure of the gate can make the cell density larger, so the channel resistance, accumulation region resistance, and drift region resistance are all reduced. On the basis of the trench MOSFET, predecessors proposed the shielded gate-trench MOSFET. The emergence of the shielded gate trench MOSFET structure significantly improves the characteristics of the previous trench MOSFET with large input capacitance and high switching loss. In addition, due to the existence of the shielded gate, the influence of the gate voltage on the drain is greatly reduced. When the reverse voltage is applied to the drain, a stronger electric field can be formed, further reducing the on-resistance. Although the shielded gate trench MOSFET can effectively reduce the on-resistance of DMOS and there is also a certain lateral electric field, due to the presence of the trench sidewall oxide layer, its voltage-resistant layer still belongs to the conventional "resistance-type" voltage-resistant layer. As the reverse breakdown voltage continues to increase, its on-resistance will gradually increase, and it cannot get rid of the "silicon limit" relationship between the on-resistance and voltage resistance of traditional power devices. Although it can be optimized by adjusting the structure and injection conditions, this contradiction always exists. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a cell structure of a shielded gate trench MOSFET and a manufacturing method thereof.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A cell structure of a shielded gate trench MOSFET, comprising a substrate, a drift region arranged on the substrate and an interlayer dielectric layer arranged on the drift region, wherein a drain metal is arranged at the lower end of the substrate, a deep trench is arranged on the drift region, and a sidewall oxide layer is arranged on the groove wall of the deep trench; a shielding gate is arranged at the lower part of the deep trench, a control gate is arranged at the upper part of the deep trench, and the shielding gate and the control gate are isolated by an intermediate oxide layer; an active region is formed by implantation at the upper part of the drift region, and a body region is formed by implantation below the source region A source metal is arranged at a position above the source region on the interlayer dielectric layer corresponding to a position above the source region, a source contact hole is arranged below the source metal, penetrating the interlayer dielectric and the source region and extending into the body region, and the source contact hole is filled with a metal plug; the sidewalls and the bottom of the source contact hole are both formed with a highly doped contact region by injection; a charge balance region is formed below the source contact hole by high-energy ion injection, and the charge balance region is used to enhance the lateral depletion of the shield gate to the adjacent drift region when the shield gate trench MOSFET device is in a reverse bias state.

[0006] Furthermore, the drift region includes a first epitaxial layer grown on a substrate and a second epitaxial layer grown on the first epitaxial layer, and the deep trench penetrates the second epitaxial layer and extends into the first epitaxial layer.

[0007] Furthermore, the substrate is a heavily doped substrate of a first doping type, and the first epitaxial layer and the second epitaxial layer are both heavily doped with the first doping type; the shield gate and the control gate are of a second doping type; the body region is lightly doped with the second doping type; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on a side of the source region adjacent to a deep trench, and the second heavily doped region is located on a side of the first heavily doped region away from the deep trench; the first heavily doped region is heavily doped with the first doping type, and the second heavily doped region is heavily doped with the second doping type; the charge balance region is of the second doping type, and the highly doped contact region is heavily doped with the second doping type.

[0008] Furthermore, the resistivity of the substrate is 0.001Ω.cm to 0.003Ω.cm, the material of the metal plug is tungsten, and the material of the source metal is aluminum copper.

[0009] Further, the first doping type is N-type doping, and the second doping type is P-type doping; or

[0010] The first doping type is P-type doping, and the second doping type is N-type doping.

[0011] Furthermore, the width of the charge balance region is 0.13 μm to 0.17 μm, the depth is 2.2 μm to 2.8 μm, and the carrier concentration is 3.7 e 16 cm-3 ~4.3e 16 cm -3 .

[0012] A method for manufacturing a cell structure of a shielded gate trench MOSFET comprises the following steps:

[0013] S100, forming a drift region on a substrate, and forming a deep trench on the drift region;

[0014] S200, sequentially forming a shield gate, an intermediate oxide layer and a control gate in the deep trench;

[0015] S300, sequentially forming a body region and a source region on the upper portion of the drift region by implantation;

[0016] S400, forming an interlayer dielectric layer by chemical vapor deposition, and performing through-hole etching above the source region to form a source contact hole that penetrates the interlayer dielectric and the source region and extends into the body region;

[0017] S500, performing high-energy ion implantation through the source contact hole and below the source contact hole to form a charge balance region, and forming a highly doped contact region on the sidewall and bottom of the source contact hole by implantation;

[0018] S600, filling a metal plug in the source contact hole, and forming a source metal connected to the metal plug on the interlayer dielectric layer; and forming a drain metal on the back side of the substrate.

[0019] Furthermore, the substrate is a heavily doped substrate of a first doping type, and the drift region is heavily doped with the first doping type; the shield gate and the control gate are of a second doping type; the body region is lightly doped with the second doping type; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on a side of the source region adjacent to a deep trench, and the second heavily doped region is located on a side of the first heavily doped region away from the deep trench; the first heavily doped region is heavily doped with the first doping type, and the second heavily doped region is heavily doped with the second doping type; the charge balance region is of the second doping type, and the highly doped contact region is heavily doped with the second doping type.

[0020] Furthermore, the step S100 includes the following sub-steps:

[0021] S101, taking a substrate having a first epitaxial layer;

[0022] S102, thinning the first epitaxial layer and then growing a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer form a drift region;

[0023] S103, sequentially growing a first oxide layer, a nitride layer, and a second oxide layer on the second epitaxial layer;

[0024] S104, defining a deep trench formation region; and sequentially removing the first oxide layer, the nitride layer, and the second oxide layer in the deep trench formation region by photolithography to expose the surface of the second epitaxial layer in the deep trench region;

[0025] S105 , etching downward the exposed portion of the second epitaxial layer and extending it into the first epitaxial layer to form a deep trench.

[0026] Furthermore, the step S200 includes the following sub-steps:

[0027] S201, etching and removing the second oxide layer, retaining the first oxide layer and the nitride layer; linearly oxidizing the groove wall of the deep groove, and depositing a third oxide layer;

[0028] S202, growing polysilicon once by using an epitaxial growth process until the deep trench is filled and the outer surface of the deep trench is covered;

[0029] S203, removing the primary polysilicon in the area outside the deep trench by chemical mechanical polishing, and etching back the primary polysilicon in the deep trench, so that the remaining primary polysilicon after etching is located at the bottom of the deep trench to form a shielding gate;

[0030] S204, depositing silicon oxide to form a fourth oxide layer until the deep trench is filled;

[0031] S205, etching back the fourth oxide layer in the deep trench to form a shallow trench; the remaining fourth oxide layer below the shallow trench forms an intermediate oxide layer;

[0032] S206, etching and removing the third oxide layer on the side wall of the shallow trench, and removing the nitride layer and the first oxide layer on the drift region;

[0033] S207, forming a thin oxide layer on the sidewalls of the shallow trench and the surface of the drift region by thermal oxidation;

[0034] S208, growing secondary polysilicon by epitaxial growth process until the shallow trench is filled and the outer surface of the shallow trench is covered;

[0035] S209, removing the secondary polysilicon in the area outside the shallow trench by chemical mechanical polishing, and etching back the secondary polysilicon in the shallow trench to make it lower than the silicon surface, thereby forming a control gate;

[0036] S210 , performing thermal annealing on the control gate and forming a surface oxide layer.

[0037] In the present invention, based on the production and manufacturing principle of the existing shielded gate trench MOSFET device, the second doping type impurities are injected into the drift region of the first doping type through high energy injection to form a super junction VDMOS structure, thereby improving the performance of the VDMOS. In this structure, by utilizing the charge balance effect, the lateral depletion of the drift region of the shielded gate trench MOSFET device when reverse biased is increased, so that the existing structure can use a higher concentration of doping while ensuring that the breakdown voltage remains unchanged, thereby reducing the on-resistance; without changing the concentration and thickness of the drift region in the existing shielded gate trench MOSFET device, a higher breakdown voltage is obtained; and the reliability and radiation resistance of the shielded gate trench MOSFET device are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0039] Figure 1 It is a structural schematic diagram of an embodiment of a cell structure of a shielded gate trench MOSFET of the present invention.

[0040] Figure 2 It is a flow chart of an embodiment of a method for manufacturing a cell structure of a shielded gate trench MOSFET according to the present invention.

[0041] Figure 3 Schematic diagram of the structure after deep trenches are formed.

[0042] Figure 4 Schematic diagram of the structure after depositing the third oxide layer.

[0043] Figure 5 This is a schematic diagram of the structure after growing polysilicon once.

[0044] Figure 6 This is a schematic diagram of the structure after the polysilicon is etched back.

[0045] Figure 7 A schematic diagram of the structure after etching back the fourth oxide layer and removing the third oxide layer, the nitride layer and the first oxide layer.

[0046] Figure 8 Schematic diagram of the structure after forming a thin oxide layer.

[0047] Fig. 9 Schematic diagram of the structure after secondary polysilicon growth.

[0048] Fig.10 Schematic diagram of the structure after the body region is formed.

[0049] Fig.11 It is a schematic diagram of the structure after forming the source contact hole.

[0050] Fig.12 Schematic diagram of the structure after the charge balance region and the highly doped contact region are formed.

[0051] The accompanying drawings in the specification are as follows:

[0052] Substrate-100; drift region-200; first epitaxial layer-210; second epitaxial layer-220; deep trench-230; sidewall oxide layer-231; shield gate-232; intermediate oxide layer-233; control gate-234; surface oxide layer-235; shallow trench-236; body region-240; source region-250; first heavily doped region-251; second heavily doped region-252;

[0053] First oxide layer-310; nitride layer-320; second oxide layer-330; third oxide layer-340; primary polysilicon-350; thin oxide layer-360; secondary polysilicon-370; interlayer dielectric layer-400; source contact hole-500; highly doped contact region-501; metal plug-510; charge balance region-520; drain metal-600; source metal-700. DETAILED DESCRIPTION

[0054] The following describes the implementation methods of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other without conflict.

[0055] See also Figure 1 , Figure 1 The schematic diagram of the structure of the cell structure of the shielded gate 232 trench MOSFET of the present invention is a schematic diagram of the structure of the cell structure of the shielded gate 232 trench MOSFET of the present invention. The cell structure of the shielded gate 232 trench MOSFET of the present embodiment includes a substrate 100, a drift region 200 disposed on the substrate 100, and an interlayer dielectric layer 400 disposed on the drift region 200. The substrate 100 is a heavily doped substrate 100 of the first doping type, the resistivity of the substrate 100 is 0.001Ω.cm to 0.003Ω.cm, and a drain metal 600 is disposed at the lower end of the substrate 100, thereby forming the drain of the shielded gate 232 trench MOSFET device.

[0056] A deep trench 230 is provided on the drift region 200, and a sidewall oxide layer 231 is provided on the groove wall of the deep trench 230; a shield gate 232 is provided at the lower part of the deep trench 230, and a control gate 234 is provided at the upper part of the deep trench 230, and the shield gate 232 and the control gate 234 are isolated by an intermediate oxide layer 233. In this embodiment, the drift region 200 includes a first epitaxial layer 210 grown on the substrate 100 and a second epitaxial layer 220 grown on the first epitaxial layer 210, and the deep trench 230 penetrates the second epitaxial layer 220 and extends into the first epitaxial layer 210. The shield gate 232 is formed by etching back the polysilicon filled in the deep trench 230, and the shield gate 232 structure is located at the bottom of the deep trench 230. After the shield gate 232 is formed, an oxide layer is formed on the top thereof and etched back to form an intermediate isolation oxide layer, and the thickness of the intermediate isolation oxide layer is about 200nm. The control gate 234 is formed by etching back after filling polysilicon again on the upper part of the deep trench 230. The width of the control gate 234 is greater than the width of the shield gate 232, so that the impurity concentration in the subsequent channel region (i.e., the region where the deep trench 230 is located) is not affected by the shield gate 232. The depth of the control gate 234 can be varied, and is usually adjusted according to the depth of the deep trench 230.

[0057] The first epitaxial layer 210 and the second epitaxial layer 220 are both heavily doped with the first doping type, and the thickness and resistivity of the first epitaxial layer 210 and the second epitaxial layer 220 are selected according to the designed breakdown voltage of the shield gate 232 trench MOSFET device. For example, for a SGTMOS device with a breakdown voltage of about 100V, the thickness of the first epitaxial layer 210 can be 5.5μm, and the resistivity can be 0.18Ω.cm, and the thickness of the second epitaxial layer 220 can be 3.0μm, and the resistivity can be 0.36Ω.cm. For a shield gate 232 trench MOSFET device with a higher designed breakdown voltage, the thickness of its epitaxial layer is usually thicker.

[0058] The depth of the deep trench 230 is usually determined by the breakdown voltage of the designed device. The higher the breakdown voltage requirement, the deeper the depth of the deep trench 230. For a shielded gate 232 trench MOSFET with a breakdown voltage of about 100V, the depth of the deep trench 230 can be 6.1μm, the width can be designed to be 1μm, and the pitch width can be selected to be 2.5μm. The thickness of the oxide layer 231 at the bottom and sidewall of the deep trench 230 can be selected to be 550nm.

[0059] The upper part of the drift region 200 is implanted to form an active region 250. The carrier concentration of the source region 250 is generally 1e 19 cm -3The source region 250 may include a first heavily doped region 251 and a second heavily doped region 252, wherein the first heavily doped region 251 is located on a side of the source region 250 adjacent to the deep trench 230, and the second heavily doped region 252 is located on a side of the first heavily doped region 251 away from the deep trench 230. The first heavily doped region 251 is heavily doped with the first doping type, and the second heavily doped region 252 is heavily doped with the second doping type. A body region 240 is formed below the source region 250 by implantation, and the body region 240 is lightly doped with the second doping type. The impurity concentration of the body region 240 is generally between 1e 17 cm -3 The main purpose is to meet the device threshold voltage and ensure that the device does not experience source-drain punchthrough.

[0060] A source metal 700 is provided at a position above the interlayer dielectric layer 400 corresponding to the source region 250, and the material of the source metal 700 may be aluminum copper. A second heavily doped region 252 is provided below the source metal 700, penetrating the interlayer dielectric and the source region 250, and extending into the source contact hole 500 of the body region 240. The source contact hole 500 is filled with a metal plug 510, so that the source region 250 is connected to the source metal 700 through the metal plug 510, forming the source of the shield gate 232 trench MOSFET device. The source contact hole 500 is filled with a metal plug 510 structure to reduce the area of ​​the device, and the material of the metal plug 510 is generally tungsten metal, that is, the metal plug 510 is generally a tungsten plug.

[0061] In addition, after the source contact hole 500 is formed, a highly doped contact region 501 is formed by implantation on the sidewall and bottom of the source contact hole 500. The highly doped contact region 501 is heavily doped with the second doping type to form an ohmic contact. A charge balance region 520 is formed below the source contact hole 500 by high-energy ion implantation. The charge balance region 520 is used to enhance the lateral depletion of the shield gate 232 to the adjacent drift region 200 when the shield gate 232 trench MOSFET device is in a reverse bias state. The charge balance region 520 is of the second doping type, and the width of the charge balance region 520 is 0.13μm to 0.17μm, preferably 0.15μm; the depth of the charge balance region 520 is 2.2μm to 2.8μm, preferably 2.5μm; the carrier concentration is 3.7e 16 cm -3 ~4.3e 16 cm -3 , preferably 4e 16 cm -3 , so that the carrier concentration is roughly consistent with that in the surrounding drift region, ensuring lateral depletion.

[0062] In this embodiment, the shield gate 232 trench MOSFET device is an N-type device, that is, the first doping type is N-type doping, and the second doping type is P-type doping. At this time, the doping impurities of the substrate 100 can be arsenic, and the doping impurities of the first epitaxial layer 210 and the second epitaxial layer 220 can be phosphorus. Of course, the shield gate 232 trench MOSFET device can also be a P-type device, at this time, the first doping type is P-type doping, and the second doping type is N-type doping.

[0063] In this embodiment, by injecting ions below the source contact hole 500, the original "resistance type" voltage-resistant layer is changed into a "junction type" voltage-resistant layer, which can reduce the resistance of the JFET area; accelerate EPI depletion, ensure that the electric field strength at the edge of the trench is small, and improve the reliability of the shielding gate 232 trench MOSFET device; optimize the radiation resistance of the shielding gate 232 trench MOSFET device.

[0064] In this embodiment, based on the production and manufacturing principle of the existing shielded gate 232 trench MOSFET device, the second doping type impurities are injected into the drift region 200 of the first doping type through high energy injection to form a super junction VDMOS structure, thereby improving the performance of the VDMOS. In this structure, by utilizing the charge balance effect, the lateral depletion of the drift region 200 of the shielded gate 232 trench MOSFET device is increased when the reverse bias is applied, so that the existing structure can use a higher concentration of doping while ensuring that the breakdown voltage remains unchanged, thereby reducing the on-resistance. Similarly, without changing the concentration and thickness of the drift region 200 in the existing shielded gate 232 trench MOSFET device, the structure also has a higher breakdown voltage. This embodiment reduces the specific on-resistance of the shielded gate 232 trench MOSFET device, accelerates the depletion of the epitaxial layer drift region 200, ensures that the trench edge electric field strength is small, and improves the reliability of the shielded gate 232 trench MOSFET device; in addition, the radiation resistance of the shielded gate 232 trench MOSFET device can also be effectively improved.

[0065] See also Figure 2 , Figure 2 This is a flow chart of an embodiment of a method for manufacturing a cell structure of a shield gate 232 trench MOSFET of the present invention. This embodiment is described by taking an N-type shield gate 232 trench MOSFET as an example. Of course, a P-type shield gate 232 trench MOSFET can also be manufactured using the method of this embodiment, and only the doping type of each part needs to be changed. The cell structure manufacturing method of the shield gate 232 trench MOSFET includes the following steps:

[0066] S100, please refer to Figure 3 , a drift region 200 is formed on the substrate 100, and a deep trench 230 is formed on the drift region 200. Figure 3 In the figure, the grooves at both ends are the grooves of the terminal region, and the three grooves in the middle are the deep grooves 230 of the cell structure, that is, Figure 3 3 cell structures are shown in FIG. This step may include the following sub-steps:

[0067] S101, obtain a substrate 100 having a first epitaxial layer 210. The substrate 100 is an N+ substrate 100, the doping impurities of which may be arsenic, the resistivity of which is generally 0.001 Ω.cm to 0.003 Ω.cm, and the first epitaxial layer 210 is N+ doped.

[0068] S102, thinning the first epitaxial layer 210, and etching the first epitaxial layer 210 to a suitable thickness according to the designed breakdown voltage of the shield gate 232 trench MOSFET device. Then grow the second epitaxial layer 220, the second epitaxial layer 220 is N+ doped, and the first epitaxial layer 210 and the second epitaxial layer 220 form a drift region 200. The thickness and resistivity of the second epitaxial layer 220 are also selected according to the designed breakdown voltage of the shield gate 232 trench MOSFET device.

[0069] S103 , sequentially growing a first oxide layer 310 , a nitride layer 320 , and a second oxide layer 330 on the second epitaxial layer 220 ; the first oxide layer 310 , the nitride layer 320 , and the second oxide layer 330 form a hard mask layer, and the hard mask layer is generally about 450 nm.

[0070] S104, using photoresist to define the formation area of ​​the deep trench 230; and removing the first oxide layer 310, the nitride layer 320 and the second oxide layer 330 in the formation area of ​​the deep trench 230 in sequence by photolithography to expose the silicon surface of the second epitaxial layer 220 in the deep trench 230 area.

[0071] S105 , etching the exposed portion of the second epitaxial layer 220 downwards and extending the exposed portion into the first epitaxial layer 210 to form a deep trench 230 .

[0072] S200, forming a shield gate 232, an intermediate oxide layer 233 and a control gate 234 in the deep trench 230 in sequence. This step may include the following sub-steps:

[0073] S201, please refer to Figure 4 , the second oxide layer 330 is removed by etching, and the first oxide layer 310 and the nitride layer 320 are retained; then, the groove wall of the deep trench 230 is linearly oxidized, and a third oxide layer 340 is deposited.

[0074] S202, please refer to Figure 5, an epitaxial growth process is used to grow a P-type doped primary polysilicon 350 until the deep trench 230 is filled and the outer surface of the deep trench 230 is covered.

[0075] S203, please refer to Figure 6 , chemical mechanical grinding is performed on the epitaxially grown primary polysilicon 350 until the primary polysilicon 350 on the surface (i.e., the secondary polysilicon 370 outside the deep trench 230) is completely ground away. Afterwards, the primary polysilicon 350 in the deep trench 230 is etched back, and the remaining primary polysilicon 350 after etching is located at the bottom of the deep trench 230, forming a shielding gate 232. Figure 6 It can be seen that the primary polysilicon 350 in the trench of the terminal region is only etched back to be flush with the silicon surface, which is different from the etched back position of the primary polysilicon 350 in the deep trench 230 of the cellular structure.

[0076] S204 , depositing silicon oxide to form a fourth oxide layer until the deep trench 230 is fully filled.

[0077] S205, please refer to Figure 7 , the fourth oxide layer in the deep trench 230 is etched back to form a shallow trench 236; the remaining fourth oxide layer below the shallow trench 236 forms an intermediate oxide layer. The thickness of the intermediate isolation oxide layer is about 200 nm.

[0078] S206, please continue reading Figure 7 , the third oxide layer 340 on the side wall of the shallow trench 236 is etched away, so that the width of the control gate 234 formed subsequently is greater than the width of the shield gate 232; and the nitride layer 320 and the first oxide layer 310 on the drift region 200 are removed.

[0079] S207, please refer to Figure 8 A thin oxide layer 360 is formed on the sidewalls of the shallow trench 236 and the surface of the drift region 200 by thermal oxidation.

[0080] S208, please refer to Fig. 9 , an epitaxial growth process is used to grow P-type doped secondary polysilicon 370 until the shallow trench 236 is filled and the outer surface of the shallow trench 236 is covered.

[0081] S209, please refer to Fig.10 The epitaxially grown secondary polysilicon 370 is subjected to chemical mechanical polishing until the secondary polysilicon 370 on the surface (i.e., the secondary polysilicon 370 outside the shallow trench 236) is completely polished away. Afterwards, the secondary polysilicon 370 in the shallow trench 236 is etched back to be about 100 nm below the silicon surface, thereby forming a control gate 234.

[0082] S210, please continue reading Fig.10, thermal annealing is performed on the control gate 234, and a surface oxide layer 235 is formed.

[0083] S300, please continue to read Fig.10 , a body region 240 and a source region 250 are sequentially formed by implantation on the upper part of the drift region 200. Specifically, a photoresist is first used to define the area of ​​the body region 240 on the drift region 200, and then ion implantation is performed in the body region 240, and then a well is pushed to form the body region 240. Please refer to Fig.11 Then, a source region 250 is formed by implantation on the upper portion of the body region 240. The body region 240 is P-doped, and the source region 250 includes an N+ doped region.

[0084] S400, please continue to read Fig.11 An interlayer dielectric layer 400 is formed by chemical vapor deposition, and through-hole etching is performed above the source region 250 to form a source contact hole 500 that penetrates the interlayer dielectric and the source region 250 and extends into the body region 240 .

[0085] S500, please refer to Fig.12 , high-energy ion implantation is performed below the source contact hole 500 to form a charge balance region 520, and a highly doped contact region 501 is formed by implantation on the sidewalls and bottom of the source contact hole 500. The charge balance region 520 is P-type doped and is used to enhance the lateral depletion of the shield gate 232 to the adjacent drift region 200 when the shield gate 232 trench MOSFET device is in a reverse bias state. The width of the charge balance region 520 is 0.13μm to 0.17μm, preferably 0.15μm; the depth of the charge balance region 520 is 2.2μm to 2.8μm, preferably 2.5μm; the carrier concentration is 3.7e 16 cm -3 ~4.3e 16 cm -3 , preferably 4e 16 cm -3 , so as to be roughly consistent with the carrier concentration of the surrounding drift region to ensure lateral depletion. The highly doped contact region 501 is P+ doped to form an ohmic contact.

[0086] S600, please continue to read Figure 1 , filling a metal plug 510 in the source contact hole 500, and forming a source metal 700 connected to the metal plug 510 on the interlayer dielectric layer 400; and after thinning the substrate 100, forming a drain metal 600 on the back side of the substrate 100; these are all conventional process steps and will not be described in detail here.

[0087] The cell structure manufacturing method of the shielded gate 232 trench MOSFET of this embodiment only adds the process of injecting to form the charge balance region 520 on the basis of the original device cell structure manufacturing process, so the manufacturing difficulty does not increase. This embodiment forms the charge balance region 520 by adding ion implantation on the basis of the original shielded gate 232 trench MOSFET design process, thereby enhancing the lateral depletion of carriers, reducing the specific on-resistance of the shielded gate 232 trench MOSFET device, accelerating the depletion of the epitaxial layer drift region 200, ensuring that the electric field strength at the trench edge is small, and improving the reliability of the shielded gate 232 trench MOSFET device; in addition, the radiation resistance of the shielded gate 232 trench MOSFET device can be effectively improved; thus, the device performance of the shielded gate 232 trench MOSFET can be effectively improved without adding additional photolithography layers and cumbersome processes.

[0088] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A cell structure of a shielded gate trench MOSFET, characterized in that: The invention comprises a substrate, a drift region arranged on the substrate and an interlayer dielectric layer arranged on the drift region, wherein a drain metal is arranged at the lower end of the substrate, a deep trench is arranged on the drift region, and a sidewall oxide layer is arranged on the trench wall of the deep trench; a shielding gate is arranged at the lower part of the deep trench, a control gate is arranged at the upper part of the deep trench, and the shielding gate and the control gate are isolated by an intermediate oxide layer; an active region is formed by injection at the upper part of the drift region, a body region is formed by injection below the source region, a source metal is arranged at a position corresponding to the upper part of the source region on the interlayer dielectric layer, a source contact hole penetrating the interlayer dielectric and the source region and extending into the body region is arranged below the source metal, and a metal plug is filled in the source contact hole; a highly doped contact region is formed on the sidewall and the bottom of the source contact hole by injection; a charge balance region is formed by high-energy ion injection below the source contact hole, and the charge balance region is used to enhance the lateral depletion of the shielding gate to the adjacent drift region when the shielding gate trench MOSFET device is in a reverse bias state.

2. The cell structure of the shielded gate trench MOSFET according to claim 1, wherein: The drift region includes a first epitaxial layer grown on a substrate and a second epitaxial layer grown on the first epitaxial layer. The deep trench penetrates the second epitaxial layer and extends into the first epitaxial layer.

3. The cell structure of the shielded gate trench MOSFET according to claim 2, characterized in that: The substrate is a heavily doped substrate of a first doping type, and the first epitaxial layer and the second epitaxial layer are both heavily doped with the first doping type; the shield gate and the control gate are of a second doping type; the body region is lightly doped with the second doping type; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on a side of the source region adjacent to a deep trench, and the second heavily doped region is located on a side of the first heavily doped region away from the deep trench; the first heavily doped region is heavily doped with the first doping type, and the second heavily doped region is heavily doped with the second doping type; the charge balance region is of the second doping type, and the highly doped contact region is heavily doped with the second doping type.

4. The cell structure of the shielded gate trench MOSFET according to claim 3, characterized in that: The resistivity of the substrate is 0.001Ω.cm-0.003Ω.cm, the material of the metal plug is tungsten, and the material of the source metal is aluminum copper.

5. The cell structure of the shielded gate trench MOSFET according to claim 1, wherein: The first doping type is N-type doping, and the second doping type is P-type doping; or The first doping type is P-type doping, and the second doping type is N-type doping.

6. The cell structure of the shielded gate trench MOSFET according to any one of claims 1 to 5, characterized in that: The charge balance region has a width of 0.13 μm to 0.17 μm, a depth of 2.2 μm to 2.8 μm, and a carrier concentration of 3.7 e 16 cm -3 ~4.3e 16 cm -3 .

7. A method for manufacturing a cell structure of a shielded gate trench MOSFET, characterized in that: The following steps are involved: S100, forming a drift region on a substrate, and forming a deep trench on the drift region; S200, sequentially forming a shield gate, an intermediate oxide layer and a control gate in the deep trench; S300, sequentially forming a body region and a source region on the upper portion of the drift region by implantation; S400, forming an interlayer dielectric layer by chemical vapor deposition, and performing through-hole etching above the source region to form a source contact hole that penetrates the interlayer dielectric and the source region and extends into the body region; S500, performing high-energy ion implantation through the source contact hole and below the source contact hole to form a charge balance region, and forming a highly doped contact region on the sidewall and bottom of the source contact hole by implantation; S600, filling a metal plug in the source contact hole, and forming a source metal connected to the metal plug on the interlayer dielectric layer; A drain metal is formed on the back side of the substrate.

8. The method for manufacturing a cell structure of a shielded gate trench MOSFET according to claim 7, wherein: The substrate is a heavily doped substrate of a first doping type, and the drift region is heavily doped with the first doping type; the shield gate and the control gate are of a second doping type; the body region is lightly doped with the second doping type; the source region includes a first heavily doped region and a second heavily doped region, the first heavily doped region is located on a side of the source region adjacent to a deep trench, and the second heavily doped region is located on a side of the first heavily doped region away from the deep trench; the first heavily doped region is heavily doped with the first doping type, and the second heavily doped region is heavily doped with the second doping type; the charge balance region is of the second doping type, and the highly doped contact region is heavily doped with the second doping type.

9. The method for manufacturing a cell structure of a shielded gate trench MOSFET according to claim 7, wherein: The step S100 includes the following sub-steps: S101, taking a substrate having a first epitaxial layer; S102, thinning the first epitaxial layer and then growing a second epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer form a drift region; S103, sequentially growing a first oxide layer, a nitride layer, and a second oxide layer on the second epitaxial layer; S104, defining a formation area of ​​a deep trench; and sequentially removing the first oxide layer, the nitride layer, and the second oxide layer in the deep trench formation region by photolithography to expose the surface of the second epitaxial layer in the deep trench region; S105 , etching downward the exposed portion of the second epitaxial layer and extending it into the first epitaxial layer to form a deep trench.

10. The method for manufacturing a cell structure of a shielded gate trench MOSFET according to claim 7, wherein: The step S200 includes the following sub-steps: S201, etching and removing the second oxide layer, retaining the first oxide layer and the nitride layer; linearly oxidizing the groove wall of the deep groove, and depositing a third oxide layer; S202, growing polysilicon once by using an epitaxial growth process until the deep trench is filled and the outer surface of the deep trench is covered; S203, removing the primary polysilicon in the area outside the deep trench by chemical mechanical polishing, and etching back the primary polysilicon in the deep trench, so that the remaining primary polysilicon after etching is located at the bottom of the deep trench to form a shielding gate; S204, depositing silicon oxide to form a fourth oxide layer until the deep trench is filled; S205, etching back the fourth oxide layer in the deep trench to form a shallow trench; the remaining fourth oxide layer below the shallow trench forms an intermediate oxide layer; S206, etching and removing the third oxide layer on the side wall of the shallow trench, and removing the nitride layer and the first oxide layer on the drift region; S207, forming a thin oxide layer on the sidewalls of the shallow trench and the surface of the drift region by thermal oxidation; S208, growing secondary polysilicon by epitaxial growth process until the shallow trench is filled and the outer surface of the shallow trench is covered; S209, removing the secondary polysilicon in the area outside the shallow trench by chemical mechanical polishing, and etching back the secondary polysilicon in the shallow trench to make it lower than the silicon surface, thereby forming a control gate; S210 , performing thermal annealing on the control gate and forming a surface oxide layer.

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