Integrated circuit package, wafer assembly, and method of producing the wafer assembly

Abstract

The present application relates to an integrated circuit package, wafer assembly, and method of producing the wafer assembly. An integrated circuit (IC) package includes a first die and a second die, wherein at least one of the first die or the second die includes an optical window having an optical transmission wavelength range between 0.1 micrometers and 1.0 millimeters; and a mediator die between the first die and the second die, wherein the mediator die is coupled to the first die at a first surface of the mediator to form a first bonding interface, wherein the mediator is coupled to the second die at a second surface of the mediator die to form a second bonding interface, wherein the second surface is opposite the first surface, wherein the first bonding interface and the second bonding interface form a sealed cavity of the IC package, the sealed cavity is at least partially formed by the optical window, and wherein the mediator die includes electrical routing.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to integrated circuit (IC) packages and more particularly to a windowed wafer assembly with an interposer. BACKGROUND

[0002] An interposer is a structure that is coupled to wafers. In particular, an interposer can be positioned between wafers to provide mechanical support and / or act as a brace between wafers. Thus, an interposer provides structural rigidity and mechanical support. SUMMARY

[0003] In a described example of an integrated circuit (IC) package, the IC package includes: a first die and a second die, wherein at least one of the first die or the second die includes an optical window having a light transmission wavelength range between 0.1 microns and 1.0 millimeters; and an interposer die between the first die and the second die, wherein the interposer die is coupled to the first die at a first surface of the interposer to form a first bonding interface, wherein the interposer is coupled to the second die at a second surface of the interposer die to form a second bonding interface, wherein the second surface is opposite the first surface, wherein the first bonding interface and the second bonding interface form a sealed cavity of the IC package, the sealed cavity is at least partially formed by the optical window, and wherein the interposer die includes electrical routing.

[0004] In a described example of a method of producing an optical wafer assembly, the method includes: coupling a first wafer to a first surface of an interposer to form a first bonding interface; coupling a second wafer to a second surface of the interposer to form a second bonding interface, the second surface on an opposite side from the first surface, wherein at least one of the first die or the second die includes an optical window having a light transmission wavelength range between 0.1 microns and 1.0 millimeters, wherein the first bonding interface and the second bonding interface are sealed to form a sealed cavity, the sealed cavity is at least partially formed by the optical window, and wherein the interposer includes electrical routing.

[0005] In one described example of a wafer assembly, the wafer assembly includes: a first wafer; a second wafer, wherein at least one of the first wafer or the second wafer includes an optical wafer having an optical transmission wavelength range between 0.1 microns and 1.0 millimeters; and an interposer coupled to the first wafer and the second wafer at respective first and second surfaces of the interposer, wherein the second surface is opposite the first surface, and wherein the interposer includes electrical routing. The example wafer assembly also includes: a first bonding interface between the first wafer and the interposer; and a second bonding interface between the second wafer and the interposer, wherein the first and second bonding interfaces form a sealed cavity, the sealed cavity at least partially formed by the optical wafer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1A is a top view of an example optical wafer assembly in accordance with the teachings of this disclosure.

[0007] Figure 1B is a detailed view of a portion of the example optical wafer assembly of Figure 1A

[0008] Figure 2 is a cross-sectional view of an example windowed integrated circuit (IC) package in accordance with the teachings of this disclosure, shown along line A-A of Figure 1B

[0009] Figure 3 is a cross-sectional view of an example wafer for producing the windowed IC package of Figure 2

[0010] Figure 4 is a cross-sectional view of an example interposer for producing the IC package of Figure 2

[0011] Figure 5 is a cross-sectional view of an alternative windowed example IC package in accordance with the teachings of this disclosure.

[0012] Figure 6 is a cross-sectional view of an example wafer assembly for producing a plurality of the windowed IC packages of Figure 5

[0013] Figure 7 is a cross-sectional view of a portion of the example wafer assembly of Figure 6

[0014] Figure 8 is a flowchart representative of an example method for producing the examples described herein. DETAILED DESCRIPTION ​​​​​​

[0015] The drawings are not to scale. Instead, the dimensions of the layers or regions can be exaggerated in the drawings for clarity. Generally, the same reference numbers will be used throughout the drawing and accompanying written description to refer to the same or like parts. As used in this patent, the statement that any part (e.g., layer or region) is on another part (e.g., positioned on, located on, disposed on, or formed on another part) means that the referenced part is in contact with the other part, or that the referenced part is above the other part with one or more intervening parts located therebetween. The statement that any part is in contact with another part means that the referenced parts are in direct physical contact with each other without any intervening part.

[0016] As used herein, the term "over" is used in reference to the bulk region of a base semiconductor substrate (e.g., a semiconductor wafer) on which integrated circuits are formed. Specifically, as used herein, a first component of an integrated circuit is "over" a second component when the first component is farther from the bulk region of the semiconductor substrate than the second component. Likewise, as used herein, a first component is "under" another component when the first component is closer to the bulk region of the semiconductor substrate than the other component. As noted above, one component can be over or under another component without intervening components therebetween or while in direct contact with each other.

[0017] Wafer assemblies with interposer layers are described. The interposer layers are implemented as mechanical supports and / or couplings between two wafers (e.g., fabricated wafers). In particular, an interposer layer is placed between two wafers to operably couple the two wafers together, thereby defining a wafer assembly. Subsequently, the wafer assembly can be singulated and / or diced into discrete IC packages (e.g., discrete dies). In some known examples, to provide electrical coupling to the dies, the dies are subdivided from the wafer assembly and attached to a substrate. In turn, a wire bonding process is used to electrically couple the dies to bond pads of the substrate using wire bonds. Further, in some known examples, the wire bonds are encapsulated to prevent mechanical damage. However, these processes can be time consuming and expensive.

[0018] Example implementations described herein have electrically active interposers with integrated electrical routing. These interposers are to be bonded to at least one optical window wafer, thereby reducing (e.g., eliminating) the need for coupling, wire bonding, and encapsulating dies, thereby saving associated time and cost. Example implementations described herein have active interposers (e.g., interposers) with electrical routing disposed within. The interposer is coupled to a first wafer (e.g., wafer chip) at a first side of the interposer via a first bonding interface and to a second wafer (e.g., optical window) at a second side of the interposer opposite the first side via a second bonding interface. The first and second bonding interfaces, together with the interposer, form a sealed cavity (e.g., a hermetic sealed cavity, a substantially gas-impermeable seal, etc.) and the electrical routing within the interposer is electrically coupled to at least one of the first or second wafers. In other words, the interposer enables additional area / volume for electrical routing, and increases functionality while providing mechanical support. Thus, example implementations described herein enable wafer-level chip-scale packaging and multi-die stacking.

[0019] In some examples, the active interposer includes electrical devices (e.g., fabricated electrical devices, diodes, transistors, etc.) disposed and / or embedded within. For example, the electrical devices can be coupled to the aforementioned electrical routing of the interposer. In some examples, the interposer is at least partially composed of silicon (e.g., single-crystalline form or polycrystalline form, silicon semiconductor with at least one oxidized surface, etc.). In other examples, the interposer is at least partially composed of ceramic (e.g., co-fired ceramic material or body, low-temperature co-fired ceramic, etc.).

[0020] As used herein, the term "interposer" refers to a structure coupled to at least one wafer and / or disposed between wafers. As used herein, the term "wafer assembly" refers to an assembly including at least one wafer and an interposer. As used herein, the term "die" refers to a portion of a wafer and / or a layer of a wafer that has been cut and / or singulated from a wafer. In other words, the term "die" can also refer to a layer or a portion of a wafer singulated from a wafer assembly. As used herein, the term "optical window" refers to a layer, an opening in a surface, and / or a body that is at least translucent and allows light to travel through.

[0021] Figure 1A is a top view of an example optical wafer assembly (e.g., wafer stack, bonded wafer stack, bonded assembly, etc.) 100 in accordance with the teachings of this disclosure. In particular, the optical wafer assembly 100 is shown with an interposer 101 extending laterally as a lattice structure (in Figure 1Aboth the first wafer 102 and the second wafer 103 are stacked in a direction into the page of FIG. 1. In particular, the first wafer 102 and the second wafer 103 have an outer shape that forms a perimeter 104 that is shown as transparent for clarity. Further, the interposer 101 includes pads (e.g., electrical contact pads, land grid array (LGA) pads, ball grid array (BGA) pads, etc.) 108 and a dicing perimeter line (e.g., a dicing line, a dicing boundary, a score edge, etc.) 110. Further, the optical wafer assembly 100 includes a die portion 112 that is a portion or section of the optical wafer assembly 100 that is to be separated into individual dies.

[0022] In Figure 1A In the illustrated example of FIG. 1, the interposer 101 is coupled and / or bonded to both the first wafer 102 and the second wafer 103. In particular, the interposer 101 is mounted to the first wafer 102 on a first side or surface of the interposer 101 and to the second wafer 103 on a second side or surface of the interposer 101. In other words, in this example, the interposer 101 forms a mechanical support and / or brace between the first wafer 102 and the second wafer 103. According to examples described herein, the interposer 101 also includes a buried conductor layer disposed within a substrate of the interposer 101 and / or electrical wiring within (e.g., routed through) the buried conductor layer and / or vias of the interposer 101. The aforementioned electrical wiring can be used to provide a current path between one or more of the first wafer 102 and the second wafer 103. Thus, the electrical wiring couples electrical components of at least one of the first wafer 102 or the second wafer 103 together. In some examples, the electrical wiring electrically couples the first wafer 102 and the second wafer 103 to each other (e.g., provides electrical wiring between the first wafer 102 and the second wafer 103 disposed on opposite sides or surfaces of the interposer 101).

[0023] In some examples, the interposer 101 includes active electrical components (e.g., fabricated electrical components). In particular, the active electrical components can be embedded (e.g., embedded via a fabrication process, etc.) within the interposer 101 to drive a reset voltage, sense a package environment, and / or any other desired functionality. In some examples, the interposer 101 is at least partially composed of ceramic (e.g., a ceramic substrate). Additionally or alternatively, the interposer 101 is at least partially composed of silicon.

[0024] Although the interposer 101 is depicted as extending generally across the perimeter 104, in this example it generally exhibits a circular (e.g., circle, ellipse, etc.) overall shape, the interposer 101 and / or the first wafer 102 and the second wafer 103 can be implemented in any suitable shape (e.g., rectangle, triangle, pentagon, hexagon, octagon, polygon, ellipse, etc.). In some examples, the interposer 101 extends only across a portion of the first wafer 102 and the second wafer 103 and / or the perimeter 104. In some examples, the perimeter 104 is formed by a ring (e.g., a gold ring for electroplating contacts) approximately 2-4 mm (e.g., 3 mm) wide. In some such examples, the ring is used for metal plating contacts with board bonding pads and sealing rings.

[0025] refer to Figure 1B ,exhibit Figure 1A Detailed view of the optical wafer assembly 100. (See attached image.) Figure 1B As can be seen, the interposer 101 is shown to have a plurality of individual die portions 118 with the aforementioned gasket 108. In this example, the perimeter (e.g., perimeter gasket, sealing ring) 120 of the interposer 101 is used to form a seal (e.g., a hermetically sealed seal, a hermetically sealed region, a hermetically sealed bladder region, etc.) for the corresponding die portions 118. As described above... Figure 1A As mentioned, the instance perimeter 110 forms a cutting edge and / or area, allowing the die portion 118 to be separated from the optical wafer assembly 100 (e.g., during the simplification process of the optical wafer assembly 100).

[0026] Figure 2 It is along Figure 1BA cross-sectional view of an example windowed integrated circuit (IC) package (e.g., singulated portion, die portion, singulated portion, etc.) 200 in accordance with the teachings of this disclosure is shown taken along line A-A. In particular, the IC package 200 is representative of, for example, a die assembly singulated (e.g., diced, cleaved, subdivided, etc.) from the optical wafer assembly 100 of FIG. 1. The illustrated example IC package 200 includes a interposer die (e.g., interposer segment, diced interposer) 202 subdivided from the interposer 101 and a first die (e.g., diced wafer) 204 subdivided from the first wafer 102, which in this example is implemented as an optical window (e.g., optically transparent layer / material). The example interposer die 202 includes wiring (e.g., buried wiring, embedded wiring, fabricated wiring, etc.) 206 disposed within a body (e.g., substrate body material, etc.) 208. In this example, the interposer 101 and thus the interposer die 202 is at least partially composed of ceramic (e.g., ceramic material, ceramic substrate, co-fired ceramic, etc.). Further, the interposer die 202 includes pads (e.g., interconnect pads, land grid array pads, etc.) 210 mounted thereto and pads 212, all of which are electrically coupled to vias (e.g., blind vias, buried vias, etc.) 214 associated with the wiring 206. In this example, pads 216 of a second die (e.g., diced wafer) 220 and a bonding layer (e.g., intermediate layer) 218 are operably coupled to the pads 212.

[0027] To provide mechanical support and / or rigidity between the first die 204 and the second die 220, the illustrated example interposer die 202 is coupled and / or bonded to the first die 204 at a first bonding interface at a first side 222 of the interposer die 202 and likewise, to the second die 220 at a second bonding interface at a second side 224 of the interposer die 202. In this example, the second side 224 is on an opposite side of the interposer die 202 from the first side 222. Thus, the interposer die 202 acts as a rigidifying support between the first die 204 and the second die 220. Thus, the example optical wafer assembly 100 is structurally reinforced. In some other examples, the first die 204 and the second die 220 are also mechanically coupled to one another.

[0028] To electrically couple the interposer die 202 and at least one of the first die 204 or the second die 220, the illustrated example interposer die 202 includes the wiring 206 extending therethrough (e.g., extending along multiple directions). In this particular example, the wiring 206 is electrically coupled to the pads 212 and thus to the pads 216 and the second die 220. In other words, the example interposer die 202 provides additional wiring access for the second die 220, thereby enabling, for example, the second die 220 to be relatively compact.

[0029] In the illustrated example, IC package 200 is an optically transmissive IC package (e.g., a digital light projector, a light measurement device, etc.). In particular, first die 204 is implemented, for example, as an optical window (e.g., a translucent window layer, an optically transmissive window, a translucent layer or portion, an optical quality window, etc.) having an optical transmission wavelength range between 0.1 microns and 1.0 millimeters, while second die 220 is implemented as an image processing complementary metal-oxide-semiconductor (CMOS) wafer. In some examples, the window can be at least partially composed of glass (e.g., borosilicate glass) and / or silicon. Additionally or alternatively, a majority of surface area (e.g., 90% or greater interface surface area) between interposer die 202 and first die 204 is bonded.

[0030] In some examples, wiring 206 includes a buried conductor, such as copper, for example. For example, a termination of wiring 206 can be formed by physical vapor deposition or electro-deposition of different materials such as gold, copper / nickel / gold, titanium / gold, and / or titanium / palladium / gold, etc. Additionally or alternatively, a termination material such as gold, platinum, or palladium can be implemented. In some examples, an internal termination material can be implemented as nickel / gold / indium, indium, tin, or any other suitable material having a relatively low melting point. In some examples, at least one of pads 210, 212, 216 is at least partially composed of gold. However, the example materials mentioned are merely examples, and any suitable material can be implemented instead.

[0031] In some examples, internal portion (e.g., internal volume) 230 is sealed (e.g., hermetically sealed, sealed to less than 10"6 helium leak rate). In some such examples, at least one of pads 212 is bonded to a corresponding pad 216 via bond layer 218 to at least partially form a seal perimeter and / or hermetic seal ring for internal portion 230. In other words, pads 214 and pads 216, along with bond layer 218, form a seal boundary that encloses a volume (e.g., an internal volume, an enclosed volume, etc.) within IC package 200. Furthermore, additional layers added near or below second die 220 (in view) can be used to further seal internal portion 230. Additionally or alternatively, pads 210, 212 and / or the hermetic seal ring that define the aforementioned seal perimeter are plated to a similar (e.g., same) height. For example, the aforementioned pads 210, 212 can be inside or outside of the hermetic seal ring. Figure 2

[0032] ​In some examples, at least one of the pads 210, 212, 216 is bonded by a plasma-activated fusion bond, a hydride-based electronic compound material (e.g., gold indium (AuIn)), a solid-liquid interdiffusion (SLID) bond, or the like. Additionally or alternatively, a solderable finish is implemented. In some examples, the pads 210 are plated LGA metal pads. In some examples, features and / or surfaces (e.g., external surfaces) of the IC package 200 are used as physical mechanical references (e.g., references). In some examples, a heat sink or other cooling component is bonded to the second die 220.

[0033] Figure 3 is for producing Figure 2 A cross-sectional view of an example wafer 103 of the windowed IC package 200 shown in FIG. 1 is shown. In particular, a die 220 of the IC package 200 is singulated from the wafer 103. In the depicted example, a cut region 304 is shown disposed between bulk regions 306, which subsequently form two dies 220 during singulation. In particular, cutting the cut region 304 separates the dies 220.

[0034] In some examples, the pads 216 are plated simultaneously with similar (e.g., identical) thicknesses. For example, the pads 216 can be positioned inside or outside of a hermetic seal ring. In this example, electrical routing associated with the wafer 103 does not extend through the aforementioned cut region 304. However, in other examples, electrical routing can extend through the cut region 304.

[0035] Figure 4 is for producing Figure 2 A cross-sectional view of an example interposer 101 of the IC package 200 shown in FIG. 1 is shown. In particular, the example interposer 101 is singulated and / or singulated to form Figure 2 a number of the interposer dies 202 shown in FIG. 1. In this example, the interposer 101 includes pads 402 and cut regions 404 disposed between non-separated ones of the interposer dies 202. Further, the example interposer dies 202 include routing 206 disposed and / or embedded therein. In the depicted example, the routing 206 is routed toward and electrically coupled to the pads 210, 212. While the routing 206 extends through the cut regions 404 in this example, in other examples the routing 206 can not extend through the cut regions 404. Additionally or alternatively, the routing 206 is electrically coupled to the pads 402, which form a metal bond to the wafer 102 (e.g., a metal and / or anode bond to an optical window surface of the wafer 102). In other examples, the pads 402 are not implemented and the interposer 101 is only mechanically coupled to the wafer 102.

[0036] In some examples, the cut zone 404 includes a scribe (e.g., a scribe pattern) 408 to facilitate singulation of the interposer 101 into discrete interposer dies 202. In some examples, the pads 212 and / or the pads 210 are masked during wafer plating (e.g., to form an LGA interface) for electrical coupling to the wafer 103.

[0037] Figure 5 is a cross-sectional view of an alternative example optical IC package 500 in accordance with the teachings of this disclosure. The illustrated example IC package 500 is formed from a first wafer 501, an interposer 502, and a second wafer 503. In the illustrated example, the IC package 500 includes an interposer die 506, which in this example at least partially consists of silicon. The interposer die 506 includes wiring 508, inner pads 510, and outer pads 512. Further, the example optical IC package 500 includes a first die 514, which in this example is implemented as a semi-transparent (e.g., transparent) layer or window. The example first die 514 is coupled to a first bonding interface of a first side 515 of the interposer die 506. Likewise, the example IC package 500 also includes a second die 520, which is coupled (e.g., indirectly coupled) to the interposer die 506 at a second bonding interface of a second side 521 of the interposer die 506. The example second die 520 is implemented as a digital micromirror device (DMD) chip. In this example, the second die 520 includes pads 522 coupled to the aforementioned pads 510 via an intermediate layer 524, which can consist of, for example, iridium.

[0038] In the illustrated example, a sealed volume (e.g., a hermetically sealed volume) 526 is formed by coupling the first die 514 and the second die 520 to the interposer die 506. In particular, the coupling of the pads 510, 522, and the intermediate layer 524 forms a bonding perimeter (e.g., a sealing boundary, a sealing frame, a sealing perimeter, etc.) between the second die 520 and the interposer die 506. Further, the sealing and bonding interface 528 between the first die 520 and the interposer die 506 also forms the sealed volume 526. In some examples, an electromechanical device, such as a microelectromechanical system (MEMS) device, is disposed within the sealed volume 526. In other examples, an electrical device 525 (e.g., a circuit board, a substrate, a die, etc.) is placed within the sealed volume 526. In some such examples, the electrical device 525 can be bonded to a surface within the sealed volume 526 and / or at least partially embedded within the first die 520. Additionally or alternatively, an electrical device 527 is formed and / or embedded within the interposer die 506.

[0039] In some examples, external pads (e.g., test interface points, external interface points, etc.) 530 are formed on pads 510 of the interposer die 506. For example, the external pads 530 can be used to test the electrical functionality of the second die 520. In other examples, the external pads 530 are implemented as electrical signals and / or communications (e.g., digital communications) during operation of the IC package 500. In some examples, the wiring 508 includes damascene (e.g., dual damascene copper) or buried metal line(s). Additionally or alternatively, a silicon dioxide / metal / via metal integration scheme is implemented. In some examples, the silicon wafer substrate has a dummy metal region to facilitate planarization. In some such examples, the dummy metal region is removed.

[0040] In some examples, a thermal isolator is added to the second die 520. In other examples, a thermal cooler (e.g., heat sink, thermal pad, etc.) is coupled to a side of the second die 520. In some examples, an outer surface of the first die 514 and / or an outer surface of the second die 520 form a mechanical datum and / or a reference reference for producing and / or assembling the IC package 500. Further, the above-described features can be implemented in this example or other examples, and vice versa. Figures 2-4 Any of the described features can be implemented in this example or other examples, and vice versa.

[0041] Figure 6 is for forming Figure 5 A cross-sectional view of an example wafer assembly 600 of a number of the example singulated IC packages 500 shown in FIG. 6A is shown. The wafer assembly 600 includes a first wafer 501, an interposer 502, and a second wafer 503. In particular, the IC package 500 is singulated and / or diced from the wafer assembly 600. As Figure 6 As can be seen in the illustrated example of FIG. 6B, a first dicing region 602 and a second dicing region 604 are shown.

[0042] To test the IC package 500 while the package 500 is still coupled (e.g., attached) to the example wafer assembly 600, the second dicing region 604 is cut (e.g., drilled) to expose the external pads 530. In some examples, the second dicing region 604 is wider (in the view of FIG. 6B) than the first dicing region 602 used to singulate the IC package 500. Figure 6 As can be seen in the illustrated example of FIG. 6B, a first dicing region 602 and a second dicing region 604 are shown.

[0043] To singulate the IC package 500 from the wafer assembly 600, the first dicing region 602 is cut (e.g., drilled) along the direction generally indicated by arrow 610, and the second dicing region 604 is cut along the direction generally indicated by arrow 612. In this example, the second dicing region 604 is cut first to enable wafer-level testing.

[0044] In some examples, the first dicing region 602 includes a scribe (e.g., a scribe cut) 618 to facilitate singulation of the IC package 500 from the wafer assembly 600. The scribe 618 can be circular in shape or include straight edges. Further, for example, the scribe 618 can be formed during a manufacturing process. In this example, the wiring 508 does not extend through the first dicing region 602. However, in other examples, the wiring can extend through the first dicing region 602.

[0045] Referring to Figure 7 , a portion of the wafer assembly 600 is depicted. In particular, Figure 6 , a precursor to the wafer assembly 600 is depicted. In Figure 7 , the depicted example, Figure 7 , the external pads 530 shown in Figure 5 and 6 have not yet been coupled to the pads 510. In the depicted example, the pads 510 are masked during indium plating, bonding, sawing. Thus, the LGA interface is formed on the pads 510.

[0046] Figure 8 is a flowchart representative of an example method 800 for producing the examples described herein. The example method 800 begins when a wafer (e.g., wafer 102, 103, 501, 503) is to be coupled with an interposer (e.g., interposer 101, interposer 502) to form a wafer assembly from which a plurality of IC packages are to be singulated.

[0047] At block 802, in some examples, electrical wiring is formed within the interposer. For example, the electrical wiring is embedded within the interposer as a buried trace and / or via, both of which can be formed during a manufacturing process. In some examples, the wiring extends within a cavity of the interposer. Additionally or alternatively, electronic components are fabricated within the interposer. In other examples, electrical components are assembled or placed into the interposer.

[0048] At block 804, a first wafer of the depicted example is coupled and / or bonded (e.g., via an inorganic bond, a high temperature fusion bond, etc.) to the interposer at a first side of the interposer. Any suitable process and / or coupling method can be used to bond the first wafer, including but not limited to mechanical bonding, adhesive bonding, chemical bonding, metallic bonding, anodic bonding, etc. In some examples, at least 90% of the interface between the interposer and the first wafer is bonded. In some examples, an organic bond (e.g., a low temperature fusion bond) is implemented.

[0049] At block 805, in some examples, an electrical device is placed into and / or formed within a cavity formed by the first wafer and the interposer. For example, a fabricated component, a die, and / or a printed circuit board can be placed and / or mounted within the cavity.

[0050] At block 806, a second wafer is coupled and / or bonded to the interposer at a second side of the interposer to form a wafer assembly. In this example, the second side is on an opposite side of the first side described above and in this example at least one of the first wafer or the second wafer includes an optical window. Further, bonding the first wafer and the second wafer to the interposer forms an adjacent sealed cavity that is at least partially formed by the optical window.

[0051] At block 808, in some examples, wiring of the interposer is coupled to at least one of the first wafer or the second wafer. This electrical wiring coupling can occur by virtue of assembling the first wafer or the second wafer to the interposer. In some examples, the interposer is electrically coupled to only one of the first wafer or the second wafer. Additionally or alternatively, the interposer is externally electrically coupled (e.g., via a wire bonding process, etc.) to an external device or component.

[0052] At block 810, at least one of the first wafer or the second wafer is diced. For example, a partial depth cut is performed to at least partially expose a test pad of an IC package of the wafer assembly.

[0053] At block 812, in some examples, the IC package is tested at the exposed test pad and / or test portion. For example, the test pad is exposed by the dicing such that a test probe can be brought into contact with the test pad. In other examples, the test pad is exposed without dicing (e.g., based on a geometry or shape of at least one of the first wafer or the second wafer).

[0054] At block 814, the IC package is separated from the wafer assembly. In other words, the IC package is singulated from the wafer assembly (e.g., during a dicing process).

[0055] At block 816, it is then determined whether to repeat the process. If the process is to be repeated (block 816), control of the process returns to block 802. Otherwise, the process ends.

[0056] In this description, the term "and / or," when used in the form "A, B, and / or C" means any combination or subset of A, B, C, for example: (a) A alone; (b) B alone; (c) C alone; (d) A with B; (e) A with C; (f) B with C; and (g) A, B, and C. Also, as used in this document, the phrase "at least one of A or B" (or "at least one of A and B") means any implementation that includes at least one of A, B, or both, for example: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0057] In accordance with the foregoing, example methods, apparatus, and articles of manufacture have been described that implement cost-effective and time-saving implementations of a dielectric layer with electrical routing. In accordance with examples described herein, electrical routing is disposed within the dielectric layer to reduce (e.g., eliminate) the need for expensive and time-consuming singulated post-wire bonding techniques. Moreover, examples described herein enable more compact and space-saving wafers by providing additional electrical routing area. Some examples described herein also implement relatively low-temperature operations, thereby saving energy and costs associated with high-temperature operations.

[0058] Within the scope of the claims, modifications in the described embodiments are possible, and other embodiments are possible.

Claims

1. An integrated circuit (IC) package, comprising: The first nude film; Second nude film; and An interposer layer is located between a first die and a second die. The interposer layer is coupled to the first die at a first surface via a first bonding interface and to the second die at a second surface via a second bonding interface. The second bonding interface includes a first pad, wherein a second pad is located on the second surface of the interposer layer. The interposer layer includes electrical wiring that electrically couples the first pad to the second pad, and the interposer layer provides rigid support for the first die and the second die. The first bonding interface and the second bonding interface form a sealed cavity between the first die and the second die.

2. The IC package according to claim 1, wherein the interposer layer includes an active electrical device.

3. The IC package of claim 1, wherein the second pad is a test pad adapted to be electrically coupled to a test probe.

4. The IC package of claim 1, wherein the first die comprises a complementary metal-oxide-semiconductor (CMOS) wafer and the second die comprises an optical window.

5. The IC package of claim 1, wherein the interposer is at least partially composed of silicon.

6. The IC package of claim 1, wherein the interposer is at least partially composed of a co-fired ceramic material.

7. The IC package according to claim 1, wherein the sealing cavity is hermetically sealed.

8. The IC package of claim 1, wherein the second pad is located outside the sealed cavity.

9. A method for producing an optical wafer assembly, the method comprising: The first wafer is coupled to the first surface of the interposer to form a first bonding interface; and A second wafer is coupled to a second surface of the interposer to form a second bonding interface, the second bonding interface including a first pad, wherein a second pad is on the second surface of the interposer, wherein the interposer includes electrical wiring that electrically couples the first pad to the second pad, and the interposer provides rigid support for the first wafer and the second wafer, wherein the first bonding interface and the second bonding interface form a sealed cavity between the first wafer and the second wafer.

10. The method of claim 9, wherein the second pad is a test pad, the method further comprising dicing at least one of the first wafer or the second wafer to expose the test pad.

11. The method of claim 10, wherein the first wafer is cut with a first slit, and wherein the second wafer is cut with a second slit wider than the first slit to expose the test pad.

12. The method of claim 9, further comprising defining or placing an active electrical device within the intermediary layer.

13. The method according to claim 9, wherein the sealing cavity is airtight.

14. An apparatus comprising: The first nude film; Second nude film; An interposer layer having a first surface and a second surface, the first surface being located on the first die and the second surface being located on the second die, wherein the interposer layer includes electrical wiring and provides rigid support for the first die and the second die; A first bonding interface is located between the first die and the intermediary layer; and A second bonding interface is located between the second die and the interposer, wherein the second bonding interface includes a first pad, a second pad on the second surface of the interposer, and electrical wiring electrically coupling the first pad to the second pad, wherein the first bonding interface and the second bonding interface form a sealed cavity between the first die and the second die.

15. The apparatus of claim 14, wherein the interposer layer comprises an active electrical component.

16. The apparatus of claim 14, wherein the first die is at least partially composed of borosilicate glass.

17. The apparatus of claim 14, wherein the intermediate layer is at least partially composed of co-fired ceramic.

18. The apparatus of claim 14, wherein the interposer layer includes serrated cuts to facilitate the separation of the integrated circuit (IC) package.

19. The apparatus of claim 14, wherein the second pad is located outside the sealing cavity.

Images