A semiconductor device unit and its manufacturing method and formed device

Abstract

The present invention provides a semiconductor device unit and a manufacturing method thereof and a formed device, characterized in that the unit comprises: a stacked layer formed by stacking two semiconductor material layers with doping characteristics, a gate control structure and an insulating passivation layer (31); the stacked layer is a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss has a positive bevel or right angle structure; the insulating passivation layer (31) is arranged on the side surface of the stacked layer, and cooperates with the positive bevel or right angle structure to form a cubic structure with the stacked layer; the gate control structure is arranged between the insulating passivation layer (31) and the stacked layer. The present invention can achieve a flat force-bearing surface, uniform force, and small force on the insulating gate, and can realize large-area interconnection.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device unit, a manufacturing method thereof, and a formed device. Background Art

[0002] Semiconductor devices made from semiconductor materials typically achieve specific functions through PN junctions containing P-type and N-type junctions, Schottky junctions containing metal-semiconductors, and gate control structures containing metal-oxide-semiconductors. These structures are often implemented through local doping or thin-film processing. Semiconductor devices use these structures to control the on and off of current, thereby achieving signal transmission. For high-power applications, semiconductor devices are often required to have the ability to block high voltages and conduct high currents at the same time. However, to achieve these functions, it is necessary to effectively reduce the on-resistance of the semiconductor material and effectively isolate the junction edge terminals. For example, the insulated gate bipolar transistor (IGBT) is a semiconductor device invented to meet the above functions.

[0003] More specifically, the current-carrying capacity of a semiconductor device is related to its size. Due to the inevitable distribution of defects in semiconductor crystal materials and the inevitable process defects that occur during device fabrication, the manufacturing yield decreases rapidly as the device area increases, even approaching zero. For example, a single IGBT chip is typically around 1 square centimeter in size, sufficient to handle currents of tens of amperes. For higher current handling capabilities, such as 1,000 amperes, using a 10-square-centimeter IGBT chip is impractical from a manufacturability and economic perspective. Existing technology typically achieves this by connecting multiple IGBT chips of the same specification in parallel. These chips are manufactured together on a wafer, tested, and screened, and then separated by dicing. These chips are then soldered to a common metal substrate, and the electrodes on the other side are connected to each other on another metal substrate using wire leads or pressing. Existing methods involve separating and then reassembling the chips, increasing manufacturing complexity and requiring high precision during reassembly. For example, the methods described in CN02822412.4 and CN02825276.4 require connecting qualified chips through a stepper lithography process, while unqualified chips are covered with an insulating layer. This poses the problem that the final electrodes formed depend on the distribution of qualified chips on each wafer, meaning that the electrodes on each wafer are different, which creates difficulties in subsequent use. Therefore, how to easily manufacture semiconductor devices capable of carrying high currents and device structure are important issues.

[0004] More specifically, semiconductor materials have a certain breakdown field strength, especially wide-bandgap materials such as silicon carbide (SiC), which have high breakdown field strength and high thermal conductivity. In order to be used in high-voltage applications, effective edge terminal isolation is required. More specifically, the electric field concentrated at the edge of the PN junction causes the device to break down prematurely at the junction edge, resulting in a decrease in the device's high-voltage blocking capability. Existing methods achieve edge terminal isolation by introducing additional charges at the edge of the PN junction to change the distribution of the electric field. For example, the junction terminal extension (JTE) achieves terminal isolation protection by introducing an extended area with the same doping at the junction edge. This requires precise calculations and multi-step micron-level semiconductor processing processes such as lithography, etching, implantation, and activation, and has relatively high requirements for design, process, and equipment. While the method described in PCT / SE98 / 00772 solves the edge terminal problem, it requires the chip to be individually segmented to ultimately achieve edge terminal isolation. The method described in PCT / US2008 / 072413 uses vertical deep trenches to achieve isolation, but this has the problem of poor tolerance for processing deviations. Insufficient verticality of the deep trenches will significantly affect the terminal isolation effect. The method described in US20140151841A1 can only achieve isolation of devices at both ends, and the chips must also be separated separately to ultimately achieve edge terminal isolation. Therefore, how to achieve high voltage blocking of semiconductor devices without separating the chips and simple and effective edge terminal isolation is an important issue.

[0005] For semiconductor devices controlled by insulated gates, they can be mainly divided into the following types according to the different gates: planar gate, in which the channel controlled by the insulated gate is located on the surface of the semiconductor; trench gate, in which the channel controlled by the insulated gate extends from the surface into the semiconductor and is perpendicular to the surface or at a certain angle. The semiconductor device can be turned on and off by controlling the insulated gate. The insulated gate is composed of a multi-layer composite of metal, insulator, semiconductor, etc. Compared with other parts of the semiconductor device, when the chip achieves electrical contact with the electrode by bearing mechanical pressure, the edge of the insulated gate has mechanical stress and becomes the weak point of the entire device. Figure 1 An exemplary insulated gate control device is given, which includes an insulated gate control structure and other components. The presence of a surface insulated gate limits the device's ability to form a large current channel through mechanical pressure contact between the upper and lower surface electrodes.

[0006] like Figure 2As shown, for the edge terminals of semiconductor devices, the width of the surface depletion region is increased mainly by locally doping to increase the curvature of the junction or removing a portion of the semiconductor to achieve the loss or compensation of space charge, thereby reducing the surface electric field. These structures are all located at the edge of the device, surrounding the entire current-conducting area and occupying a portion of the area, which plays a role in preventing the edge of the device from being affected by high electric fields. For large-area devices, if there is a defect at any point in the area surrounded by the edge terminal and it causes premature breakdown, the entire device will lose its function. As the current-carrying capacity requirements of semiconductor devices increase and the area of ​​the device increases, the probability of this situation occurring also increases significantly. Therefore, it is necessary to use certain methods to isolate these defective parts without affecting the continued functioning of other parts. Summary of the Invention

[0007] In order to solve the problem in the prior art that the insulating gate control edge needs to withstand stress and the entire device will become ineffective when a problem occurs in the unit, the present invention provides a semiconductor device unit and its manufacturing method and formed device. The present invention can reduce the stress that the insulating gate control edge needs to withstand and facilitates the isolation of the problem unit.

[0008] The technical solution provided by the present invention is:

[0009] A semiconductor device unit, characterized in that the unit comprises: a stacked layer formed by stacking two semiconductor material layers having doping characteristics, a gate control structure and an insulating passivation layer (31);

[0010] The stacked layer is a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss has a positive bevel or right angle structure;

[0011] The insulating passivation layer (31) is arranged on the side of the stacked layer, and cooperates with the positive oblique angle or right angle structure to form a cubic structure with the stacked layer;

[0012] The gate control structure is arranged between the insulating passivation layer (31) and the stacked layer.

[0013] Preferably, the stacked layer comprises: a collector region (10), a drift region (20), an emitter region (11) and a well region (21) arranged in sequence from bottom to top;

[0014] The collector region (10) and the well region (21) have a first doping characteristic;

[0015] The drift region (20) and the emitter region (11) have a second doping characteristic;

[0016] The first doping characteristic is N-type doping or P-type doping, and the corresponding second doping characteristic is P-type doping or N-type doping;

[0017] The side surface of the stacked layer is a positive bevel or right-angle structure, the upper side of which is smaller than or equal to the lower side, and passes through the well region (21), the emitter region (11) and the drift region (20) in sequence from top to bottom, and contacts or inserts into the collector region (10).

[0018] Preferably, there are two insulating passivation layers (31), which are respectively arranged in the positive bevel or right-angle structure on the side of the stacked layer, and the shape is adapted to the positive bevel or right-angle structure, and the depth of the first insulating passivation layer (31) is less than the depth of the second insulating passivation layer (31).

[0019] Preferably, the unit further comprises: a well contact electrode (42');

[0020] The gate control structure includes: an insulating gate (30) and a gate electrode (41);

[0021] The gate electrode (41) is arranged below the first insulating passivation layer (31), and the well contact electrode (42') is arranged below the second insulating passivation layer (31);

[0022] The gate electrode (41) is provided between the stacked layer, the gate electrode (41) and the first insulating passivation layer (31);

[0023] The gate electrode (41) is provided between the stacked layer and the well contact electrode (42') and the second insulating passivation layer (31).

[0024] Preferably, the unit further comprises: an emitter metal electrode (43) and a collector metal electrode (42);

[0025] The emitter metal electrode (43) is arranged above the stacked layer, and the collector metal electrode (42) is arranged below the stacked layer.

[0026] A semiconductor device comprising at least one unit;

[0027] On the same wafer, the units or the mirror-image units are fixedly connected to the upper and lower interconnected metals (3) and the metal base plate (4) in a repeated or intermittently repeated manner to form a semiconductor device.

[0028] A method for manufacturing a semiconductor device unit, comprising:

[0029] Layer structures formed of semiconductor materials having two doping characteristics are alternately stacked in sequence to form a stacked layer;

[0030] A positive bevel or right-angle structure is produced on the side of the stacked layer by etching and corroding, and the positive bevel or right-angle structure enters from the top to the bottom layer of the stacked layer;

[0031] Fabricating a gate control structure within the positive bevel or right-angle structure;

[0032] An insulating passivation layer (31) is fabricated and patterned on the gate control structure within the positive bevel or right angle structure on the side of the stack.

[0033] Preferably, the step of sequentially forming thin films of semiconductor materials having two doping characteristics and alternately stacking them to form a stacked layer comprises:

[0034] On the semiconductor material with the first doping characteristic of the collector region (10), a semiconductor thin film with the second doping characteristic is formed by epitaxy, deposition or other suitable methods to form a drift region (20);

[0035] On the drift region (20), a semiconductor thin film having a first doping characteristic is formed by epitaxy, deposition or other suitable methods to form an emission region (11);

[0036] On the emission region (11), a semiconductor film with second doping characteristics is made by epitaxy, deposition or other appropriate methods to form an emission well region (21).

[0037] Preferably, the manufacturing of the gate control structure in the positive bevel or right-angle structure includes:

[0038] A first insulating thin layer is formed on the collector region (10) including the drift region (20), the emitter region (11), the side of the well region (21) and the surface of the well region (21) to form an insulating gate (30) by oxidation, deposition or other suitable methods;

[0039] and forming and patterning a first conductive thin layer on the insulating gate (30) and below the first insulating passivation layer (31) to form a gate electrode (41);

[0040] Patterning the first insulating thin layer to form an insulating gate (30), and manufacturing and patterning a conductive layer under the second insulating passivation layer (31) to form a well contact electrode (42');

[0041] A third conductive thin layer is fabricated and patterned on the emitter well region (21) to form an emitter metal electrode (43).

[0042] Preferably, after manufacturing and patterning the insulating passivation layer (31) on the gate control structure within the positive bevel or right-angle structure on the side of the stacked layer, the method further includes: manufacturing and patterning a second conductive thin layer under the stacked layer to form a collector metal electrode (42).

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The present invention provides a semiconductor device unit and a manufacturing method thereof, characterized in that the unit comprises: a stacked layer formed by stacking two semiconductor material layers with doping characteristics, a gate control structure and an insulating passivation layer (31); the stacked layer is a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss has a positive bevel or right angle structure; the insulating passivation layer (31) is arranged on the side surface of the stacked layer, and cooperates with the positive bevel or right angle structure to form a cubic structure with the stacked layer; the gate control structure is arranged between the insulating passivation layer (31) and the stacked layer. The present invention can achieve a flat force-bearing surface, uniform force, and small force on the insulating gate, and can realize large-area interconnection.

[0045] The isolation of the chip edge terminals is achieved through non-through positive bevels, making it easy to isolate the chip edge terminals and avoiding the need for rearrangement of the chip after segmentation.

[0046] By isolating the defective chip parts through electrical contact, the morphology of the chip electrodes after interconnection is ensured to be unaffected by the distribution of defective chips on the wafer.

[0047] This is achieved by stacking semiconductor thin film layers with different doping levels. The preferred embodiment does not require selective doping and has low requirements for line width accuracy.

[0048] The insulation gate control is located between the upper and lower force-bearing surfaces. The upper and lower force-bearing electrode surfaces are flat, the material between the two electrodes is uniform, and the force balance is good;

[0049] Each functional unit is isolated from each other, and its functionality does not affect each other, so defective functional units can be selectively eliminated;

[0050] The functional unit can be expanded repeatedly indefinitely within the range allowed by the semiconductor substrate material used, there is no edge different from the functional area, and the outer contour is not restricted;

[0051] It is easy to realize specific functional circuits including diodes and switching tubes through interconnection or integration;

[0052] It is easy to expand in parallel again to form functional modules with greater flow capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A schematic diagram of an insulated gate control device in the prior art;

[0054] Figure 2 A schematic diagram of an edge terminal of a prior art device;

[0055] Figure 3 is a schematic diagram of a semiconductor device unit of the present invention;

[0056] Figure 4is a schematic diagram of a stack of doped semiconductor layers used to make a device unit of the present invention;

[0057] Figure 5 A schematic diagram of forming edge terminal isolation of the present invention;

[0058] Figure 6 Schematic diagram of the formation of the insulating gate dielectric of the present invention;

[0059] Figure 7 is a schematic diagram of forming a gate electrode of the present invention;

[0060] Figure 8 Schematic diagram of the formation of the base electrode of the present invention;

[0061] Figure 9 is a schematic diagram of the formation of a conductive electrode of the present invention;

[0062] Figure 10 Schematic diagram of the formation of insulating passivation of the present invention;

[0063] Figure 11 A schematic diagram of an embodiment of a large-area press-bonded device for interconnecting semiconductor devices according to the present invention;

[0064] Figure 12 A schematic diagram of an embodiment of a semiconductor device of the present invention that realizes series connection;

[0065] Figure 13 A schematic diagram of a method for manufacturing a semiconductor device unit according to the present invention;

[0066] Among them, 1 is a failed cell, 2 is mechanical pressure, 3 is interconnect metal, 4 is metal base, 10 is collector region, 20 is drift region, 11 is well region, 21 is emitter region, 30 is insulating gate, 31 is insulating passivation layer, 41 is gate electrode, 42 is collector metal electrode, 42' is well contact electrode, and 43 is emitter metal electrode. DETAILED DESCRIPTION

[0067] In order to better understand the present invention, the present invention is further described below with reference to the accompanying drawings and examples.

[0068] Example 1:

[0069] A semiconductor device comprising: at least one unit;

[0070] Each unit includes:

[0071] like Figure 3 As shown, the semiconductor substrate material as the support layer forms the collector region 10 and has a first doping characteristic;

[0072] The semiconductor layer with the second doping characteristic located on the collector region 10 forms a drift region 20;

[0073] The semiconductor layer with the first doping characteristic located above the drift region 20 forms a well region 11;

[0074] The semiconductor layer with the second doping characteristic located above the well region 11 forms an emitter region 21;

[0075] The insulating layer covering the sides of the collector region 10, the drift region 20, the well region 11, and the emitter region 21 forms an insulating gate 30, which can be silicon oxide or other insulating layers;

[0076] The conductive layer located above the insulating gate 30 forms a gate electrode 41, which may be doped polysilicon or other conductive layer;

[0077] The conductive thin layer located above the emitter region 21 forms an emitter metal electrode 43 and the conductive layer located below the collector region 10 forms a collector metal electrode 42;

[0078] The conductive layer located on the side of the collector region 10 and the drift region 20 , which is different from the side of the insulating gate 30 , forms a well contact electrode 42 ′;

[0079] An insulating passivation layer 31 located on the other side of the collector metal electrode 42; the insulating passivation layer may be a composite layer;

[0080] like Figure 11 and Figure 12 As shown, functional units 10 to 43 are composed of one or more functional units or units that are mirror-imaged and flipped left and right on a wafer, which are pressed by mechanical pressure 2 in a repeated or intermittent manner, and are connected to interconnect metal 3 and metal base plate 4 at the top and bottom to form a semiconductor device; or a part of the semiconductor device wafer is cut off to form a semiconductor device.

[0081] The unqualified cell 1 can be isolated by isolating the emitter metal electrode 43 at the top of the cell;

[0082] As shown in FIG13 , a method for manufacturing a semiconductor device unit includes:

[0083] like Figure 4 As shown, on the first semiconductor thin layer 10 having the first doping characteristic, a second semiconductor thin layer 20 having the second doping characteristic is formed by epitaxy, deposition or other appropriate methods;

[0084] On the second semiconductor thin layer 20, a third semiconductor thin layer 11 having a first doping characteristic is formed by epitaxy, deposition or other suitable methods;

[0085] On the third semiconductor thin layer 11, a fourth semiconductor thin layer 21 having a second doping characteristic is formed by epitaxy, deposition or other appropriate methods;

[0086] like Figure 5 As shown, by etching, corrosion or other suitable methods, a functional area with a positive bevel or vertical side surface is produced from the surface of the fourth semiconductor thin layer 21 to the first semiconductor thin layer 10 or to a portion of the first semiconductor thin layer 10, comprising the second semiconductor thin layer 20, the third semiconductor thin layer 11, and the fourth semiconductor thin layer 21;

[0087] like Figure 6 As shown, a first insulating thin layer 30 is formed on the first semiconductor thin layer 10 including the second semiconductor thin layer 20, the third semiconductor thin layer 11, the side of the fourth semiconductor thin layer 21 and the surface of the fourth semiconductor thin layer 21 by oxidation, deposition or other suitable methods;

[0088] like Figure 7 As shown, a first conductive thin layer 41 is formed on the first insulating thin layer 30, and the first conductive thin layer 41 is patterned;

[0089] like Figure 8 and Figure 9 As shown, the first insulating thin layer 30 is patterned, and a conductive layer 42' is formed on the first semiconductor thin layer 10, the second semiconductor thin layer 20 and the first insulating thin layer 30 and patterned;

[0090] like Figure 10 As shown, a third conductive thin layer 43 is formed on the fourth semiconductor thin layer 21 and patterned;

[0091] A second insulating thin layer 31 is formed on the first conductive thin layer 41, the first insulating thin layer 30, the third conductive thin layer 43 and the second conductive thin layer 42, and patterned;

[0092] A second conductive thin layer 42 is formed on the surface of the first semiconductor thin layer 10 on the other side of the surface of the third conductive thin layer 43 .

[0093] The first doping characteristic may be N-type doping or P-type doping, and the corresponding second doping characteristic may be P-type doping or N-type doping, which are different and correspond to each other.

[0094] The first semiconductor thin layer is a collector region after the cell is fabricated;

[0095] The second semiconductor thin layer serves as a drift region after the cell is fabricated;

[0096] The third semiconductor thin layer serves as a well region after the cell is fabricated;

[0097] The fourth semiconductor thin layer becomes the emitter region after the cell is fabricated;

[0098] The first insulating thin layer becomes an insulating gate after the cell is manufactured;

[0099] The second insulating thin layer is an insulating passivation layer after the cell is manufactured;

[0100] The first conductive thin layer serves as a gate electrode after the cell is fabricated;

[0101] The second conductive thin layer becomes the collector metal electrode after the cell is manufactured;

[0102] The conductive layer is a well contact electrode after the cell is fabricated;

[0103] The third conductive thin layer becomes the emitter metal electrode after the cell is manufactured;

[0104] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention are included in the scope of the claims of the present invention to be approved.

Claims

1. A semiconductor device unit, characterized in that: The unit comprises: a stacked layer formed by stacking two semiconductor material layers having doping characteristics, a gate control structure and an insulating passivation layer (31); The stacked layer is a boss structure, the upper bottom surface is smaller than the lower bottom surface, and the side surface of the boss has a positive bevel or right angle structure; The insulating passivation layer (31) is arranged on the side of the stacked layer, and cooperates with the positive oblique angle or right angle structure to form a cubic structure with the stacked layer; The gate control structure is arranged between the insulating passivation layer (31) and the stacked layer; The stacked layer comprises: a collector region (10), a drift region (20), a well region (11), and an emitter region (21) arranged in sequence from bottom to top; the unit further comprises: a well contact electrode (42'); The gate control structure comprises: an insulating gate (30) and a gate electrode (41); The gate electrode (41) is arranged below the first insulating passivation layer (31), and the well contact electrode (42') is arranged below the second insulating passivation layer (31); The insulating gate (30) is provided between the stacked layer and the gate electrode (41), and the insulating gate (30) is provided between the stacked layer and the first insulating passivation layer (31); The insulating gate (30) is provided between the stacked layer and the second insulating passivation layer (31); The upper surface of the well contact electrode (42') contacts the insulating gate (30); the side surface of the well contact electrode (42') contacts the side surface of the drift region (20); and the lower surface of the well contact electrode (42') contacts the upper surface of the collector region (10).

2. A semiconductor device unit according to claim 1, characterized in that: The collector region (10) and the well region (11) have a first doping characteristic; The drift region (20) and the emission region (21) have a second doping characteristic; The first doping characteristic is N-type doping or P-type doping, and the corresponding second doping characteristic is P-type doping or N-type doping; The side surface of the stacked layer is a positive bevel or right-angle structure, the upper side of which is smaller than or equal to the lower side, and passes through the emitter region (21), the well region (11) and the drift region (20) from top to bottom, and contacts or inserts into the collector region (10).

3. A semiconductor device unit according to claim 1, characterized in that: There are two insulating passivation layers (31), which are respectively arranged in the positive bevel or right-angle structure on the side of the stacked layer, and their shapes adapt to the positive bevel or right-angle structure, and the depth of the first insulating passivation layer (31) is less than the depth of the second insulating passivation layer (31).

4. A semiconductor device unit according to claim 1, characterized in that: The unit further comprises: an emitter metal electrode (43) and a collector metal electrode (42); The emitter metal electrode (43) is arranged above the stacked layer, and the collector metal electrode (42) is arranged below the stacked layer.

5. A semiconductor device, characterized in that: The device comprises at least one unit according to any one of claims 1 to 4; On the same wafer, the units or the mirror-image flipped units are fixedly connected in a repeated or intermittently repeated manner to respectively connect the interconnection metal (3) and the metal base plate (4) above and below to form a semiconductor device.

6. A method for manufacturing a semiconductor device unit, characterized in that: include: Layer structures formed of semiconductor materials having two doping characteristics are alternately stacked in sequence to form a stacked layer; A positive bevel or right-angle structure is produced on the side of the stacked layer by etching and corroding, and the positive bevel or right-angle structure enters from the top to the bottom layer of the stacked layer; Fabricating a gate control structure within the positive bevel or right-angle structure; Fabricating and patterning an insulating passivation layer (31) on the gate control structure within the positive bevel or right angle structure on the side of the stack; The manufacturing of the gate control structure in the positive bevel or right angle structure comprises: By oxidation or deposition, a first insulating thin layer is formed on the side of the collector region (10) including the drift region (20), the well region (11), and the emitter region (21) to form an insulating gate (30); and forming and patterning a first conductive thin layer on the insulating gate (30) and below the first insulating passivation layer (31) to form a gate electrode (41); Patterning the first insulating thin layer to form an insulating gate (30), and fabricating and patterning a conductive layer under the second insulating passivation layer (31) to form a well contact electrode (42'); Fabricating and patterning a third conductive thin layer on the emitter region (21) to form an emitter metal electrode (43); The upper surface of the well contact electrode (42') contacts the insulating gate (30); the side surface of the well contact electrode (42') contacts the side surface of the drift region (20); and the lower surface of the well contact electrode (42') contacts the upper surface of the collector region (10).

7. The method for manufacturing a semiconductor device unit according to claim 6, wherein: The step of sequentially forming thin films of semiconductor materials having two doping characteristics and alternately stacking them to form a stacked layer comprises: On the semiconductor material with the first doping characteristic of the collector region (10), a semiconductor thin film with the second doping characteristic is produced by epitaxy or deposition to form a drift region (20); On the drift region (20), a semiconductor thin film having a first doping characteristic is formed by epitaxy or deposition to form a well region (11); On the well region (11), a semiconductor film having a second doping characteristic is produced by epitaxy or deposition to form an emission region (21).

8. The method for manufacturing a semiconductor device unit according to claim 6, wherein: After manufacturing and patterning the insulating passivation layer (31) on the gate control structure within the positive bevel or right-angle structure on the side of the stacked layer, the method further includes: manufacturing and patterning a second conductive thin layer under the stacked layer to form a collector metal electrode (42).

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