Semiconductor Circuit and Electronic Device

Abstract

The semiconductor circuit of the present disclosure is provided with: a first circuit that generates an inverted voltage of the voltage at a first node and applies the inverted voltage to a second node; a second circuit that generates an inverted voltage of the voltage at the second node and applies the inverted voltage to the first node; a first storage element having a first terminal, a second terminal, and a third terminal, and storing information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to the direction of a first current flowing between the first terminal and the second terminal; a first transistor that couples the first node to the third terminal of the first storage element when in an on state; and a second transistor that is coupled to a first coupling node that is one of the first node and the second node and causes the first current to flow to the second terminal of the first storage element based on the voltage at the first coupling node.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor circuit capable of storing information and an electronic device including such a semiconductor circuit. Background Art

[0002] From an ecological perspective, it is desirable for an electronic device to have low power consumption. For example, in the case of a semiconductor circuit, a so-called power gating technique is generally used, in which power consumption is reduced by selectively stopping the power supply to some circuits. The circuits for which it is desired to stop the power supply in this way immediately return to the operating state where the power supply has not been stopped after the power supply restart. One method of achieving such a short-time return operation is to incorporate a non-volatile storage element in the circuit. For example, Patent Document 1 discloses a circuit in which an SRAM (static random access memory) as a volatile memory and a spin-injection magnetization-inversion type storage element are combined.

[0003] Citation List

[0004] Patent Document

[0005] Patent Document 1: International Publication No. WO 2009 / 028298 Summary of the Invention

[0006] Incidentally, in such a circuit including a storage element, high durability (reliability) is desired, and further improvement in durability is expected.

[0007] It is desirable to provide a semiconductor circuit and an electronic device that can enhance durability.

[0008] A semiconductor circuit according to an embodiment of the present disclosure includes: a first circuit, a second circuit, a first storage element, a first transistor, and a second transistor. The first circuit is configured to be able to generate an inverted voltage of a voltage at a first node and apply the inverted voltage to a second node. The second circuit is configured to be able to generate an inverted voltage of a voltage at the second node and apply the inverted voltage to the first node. The first storage element has a first terminal, a second terminal, and a third terminal, and is configured to be able to store information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to the direction of a first current flowing between the first terminal and the second terminal. The first transistor is configured to be able to couple the first node to the third terminal of the first storage element by being turned on. The second transistor can be coupled to a first coupling node, and is configured to be able to cause a first current to flow to the second terminal of the first storage element based on the voltage at the first coupling node, which is one of the first node and the second node.

[0009] An electronic circuit according to an embodiment of the present disclosure includes: the semiconductor circuit described above; and a battery that supplies a power supply voltage to the semiconductor circuit.

[0010] In the semiconductor circuit and the electronic device according to the embodiment of the present disclosure, the first circuit and the second circuit cause voltages that are inverted with respect to each other to appear at the first node and the second node. By turning on the first transistor, the first node is coupled to the third terminal of the first storage element. Based on the voltage at the first coupling node, which is one of the first node and the second node, the second transistor supplies a first current to the first terminal of the first storage element. In the first storage element, according to the direction of the first current flowing between the first terminal and the second terminal, the resistance state between the second terminal and the third terminal is set to a first resistance state or a second resistance state. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram showing a configuration example of a semiconductor circuit according to an embodiment of the present disclosure.

[0012] Figure 2 is a circuit diagram showing a configuration example of a storage cell according to the first embodiment.

[0013] Figure 3 is a circuit diagram showing a configuration example of a storage cell array including the Figure 2 storage cell shown in.

[0014] Figure 4 is a diagram for explaining an operation example of the storage element shown in Figure 2 .

[0015] Figure 5 is a table showing an operation example of the storage cell shown in Figure 2 .

[0016] Figure 6A is a circuit diagram showing an operation example of the storage cell shown in Figure 2 .

[0017] Figure 6B is a circuit diagram showing an operation example of the storage cell shown in Figure 2 .

[0018] Figure 6C is a circuit diagram showing an operation example of the storage cell shown in Figure 2 .

[0019] Figure 6D is a circuit diagram showing an operation example of the storage cell shown in Figure 2 .

[0020] Figure 6E is a circuit diagram showing an operation example of the storage cell shown in Figure 2Another circuit diagram of the operation example of the memory cell shown in

[0021] Figure 7 is a circuit diagram showing a configuration example of a memory cell according to a modification example of the first embodiment.

[0022] Figure 8 is a diagram showing Figure 7 an explanatory diagram of the operation example of the memory element shown in

[0023] Figure 9A is a diagram showing Figure 7 a circuit diagram of the operation example of the memory cell shown in

[0024] Figure 9B is a diagram showing Figure 7 another circuit diagram of the operation example of the memory cell shown in

[0025] Figure 9C is a diagram showing Figure 7 another circuit diagram of the operation example of the memory cell shown in

[0026] Figure 9D is a diagram showing Figure 7 another circuit diagram of the operation example of the memory cell shown in

[0027] Figure 9E is a diagram showing Figure 7 another circuit diagram of the operation example of the memory cell shown in

[0028] Figure 10 is a block diagram showing a configuration example of a semiconductor circuit according to a modification example.

[0029] Figure 11 is a block diagram showing a configuration example of a semiconductor circuit according to another modification example.

[0030] Figure 12 is a circuit diagram showing a configuration example of a memory cell according to another modification example of the first embodiment.

[0031] Figure 13 is a diagram showing Figure 12 a table of the operation example of the memory cell shown in

[0032] Figure 14A is a diagram showing Figure 12 a circuit diagram of the operation example of the memory cell shown in

[0033] Figure 14B is a diagram showing Figure 12 another circuit diagram of the operation example of the memory cell shown in

[0034] Figure 14C is a diagram showingFigure 12 Another circuit diagram of the operation example of the memory cell shown in

[0035] Figure 14D It shows Figure 12 Another circuit diagram of the operation example of the memory cell shown in

[0036] Figure 14E It shows Figure 12 Another circuit diagram of the operation example of the memory cell shown in

[0037] Figure 15 A circuit diagram showing a configuration example of a memory cell according to the second embodiment.

[0038] Figure 16 It shows including Figure 15 A circuit diagram of a configuration example of a memory cell array including the memory cell shown in

[0039] Figure 17A It shows Figure 15 A circuit diagram of the operation example of the memory cell shown in

[0040] Figure 17B It shows Figure 15 Another circuit diagram of the operation example of the memory cell shown in

[0041] Figure 18A It shows Figure 15 Another circuit diagram of the operation example of the memory cell shown in

[0042] Figure 18B It shows Figure 15 Another circuit diagram of the operation example of the memory cell shown in

[0043] Figure 18C It shows Figure 15 Another circuit diagram of the operation example of the memory cell shown in

[0044] Figure 19A It shows Figure 15 Another circuit diagram of the operation example of the memory cell shown in

[0045] Figure 19B It shows Figure 15 Another circuit diagram of the operation example of the memory cell shown in

[0046] Figure 19C It shows Figure 15 Another circuit diagram of the operation example of the memory cell shown in

[0047] Figure 20 A circuit diagram showing a configuration example of a memory cell according to a modified example of the second embodiment.

[0048] Figure 21A is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0049] Figure 21B is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0050] Figure 22A is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0051] Figure 22B is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0052] Figure 22C is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0053] Figure 23A is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0054] Figure 23B is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0055] Figure 23C is a circuit diagram showing an operation example of the memory cell shown in Figure 20 .

[0056] Figure 24 is a circuit diagram showing a configuration example of a memory cell according to a third embodiment.

[0057] Figure 25 is a circuit diagram showing a configuration example of a memory cell array including the memory cell shown in Figure 24 .

[0058] Figure 26 is a table showing an operation example of the memory cell shown in Figure 24 .

[0059] Figure 27A is a circuit diagram showing an operation example of the memory cell shown in Figure 24 .

[0060] Figure 27B is a circuit diagram showing an operation example of the memory cell shown in Figure 24 .

[0061] Figure 27Cis a circuit diagram showing Figure 24 another example of the operation of the memory cell shown in

[0062] Figure 27D is a circuit diagram showing Figure 24 another example of the operation of the memory cell shown in

[0063] Figure 27E is a circuit diagram showing Figure 24 another example of the operation of the memory cell shown in

[0064] Figure 28 is a circuit diagram showing a configuration example of a memory cell according to a modification example of the third embodiment.

[0065] Figure 29A is a circuit diagram showing Figure 28 the operation example of the memory cell shown in

[0066] Figure 29B is a circuit diagram showing Figure 28 another example of the operation of the memory cell shown in

[0067] Figure 29C is a circuit diagram showing Figure 28 another example of the operation of the memory cell shown in

[0068] Figure 29D is a circuit diagram showing Figure 28 another example of the operation of the memory cell shown in

[0069] Figure 29E is a circuit diagram showing Figure 28 another example of the operation of the memory cell shown in

[0070] Figure 30A is a circuit diagram showing a configuration example of a flip-flop circuit.

[0071] Figure 30B is a circuit diagram showing another configuration example of a flip-flop circuit.

[0072] Figure 30C is a circuit diagram showing another configuration example of a flip-flop circuit.

[0073] Figure 30D is a circuit diagram showing another configuration example of a flip-flop circuit.

[0074] Figure 31 is a circuit diagram showing a configuration example of a flip-flop circuit according to an embodiment of an application.

[0075] Figure 32 is a perspective view of the appearance configuration of a smartphone to which this embodiment is applied. Detailed Implementation Modes

[0076] In the following, some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the description is given in the following order.

[0077] 1. First Embodiment

[0078] 2. Second Embodiment

[0079] 3. Third Embodiment

[0080] 4. Application Examples and Applicable Examples

[0081] <1. First Embodiment>

[0082] [Configuration Example]

[0083] Figure 1 A configuration example of a semiconductor circuit (semiconductor circuit 1) according to an embodiment is shown. The semiconductor circuit 1 is configured to be able to store information. The semiconductor circuit 1 includes a controller 11, a power transistor 12, and a storage circuit 20.

[0084] The controller 11 is configured to control the operation of the storage circuit 20. Specifically, the controller 11 writes information into the storage circuit 20 based on a write command and write data supplied from the outside, and reads information from the storage circuit 20 based on a read command supplied from the outside. In addition, the controller 11 also has a function of controlling the power supply to the storage circuit 20 by supplying a power control signal SPG to the power transistor 12 to turn on and off the power transistor 12.

[0085] The power transistor 12 is a P-type MOS (Metal Oxide Semiconductor) transistor, and its gate is supplied with the power control signal SPG, its source is supplied with the power supply voltage VDD1, and its drain is coupled to the storage circuit 20.

[0086] With this configuration, in the semiconductor circuit 1, when the storage circuit 20 is in use, the power transistor 12 is turned on, and the storage circuit 20 is supplied with the power supply voltage VDD1 as the power supply voltage VDD. In addition, in the semiconductor circuit 1, when the storage circuit 20 is not in use, the power transistor 12 is turned off. In the semiconductor circuit 1, power consumption can be reduced by so-called power gating.

[0087] The storage circuit 20 is configured to store data. The storage circuit 20 includes a storage cell array 21 and drivers 22 and 23.

[0088] The storage cell array 21 includes a plurality of storage cells 30 arranged in a matrix.

[0089] Figure 2Shows a configuration example of the memory cells 30 in the memory cell array 21. Figure 3 Shows a configuration example of the memory cell array 21. Figure 3 In addition to the memory cell array 21, drivers 22 and 23 are also shown. The memory cell array 21 includes a plurality of word lines AWL, a plurality of control lines BWL, a plurality of bit lines BL, a plurality of bit lines BLB, a plurality of control lines CTRL, a plurality of restore control lines RESTOREL, and a plurality of reset control lines RESETL. The word lines AWL extend in the Figure 2 and Figure 3 horizontal direction in Figure 2 and Figure 3 . One end of each word line WL is coupled to the driver 22. The driver 22 applies a signal SAWL to the word line WL. The control lines BWL extend in the Figure 2 and Figure 3 horizontal direction in Figure 2 and Figure 3 . One end of each control line BWL is coupled to the driver 22. The driver 22 applies a signal SBWL to the control line BWL. The bit lines BL extend in the Figure 2 and Figure 3 vertical direction in Figure 2 and Figure 3 . One end of each bit line BL is coupled to the driver 23. The bit lines BLB extend in the Figure 2 and Figure 3 vertical direction in

[0090] . The driver 22 applies a signal SCTRL to the control line CTRL. The restore control lines RESTOREL extend in the

[0091] horizontal direction in

[0092] Figure 2 and Figure 3 . One end of each restore control line RESTOREL is coupled to the driver 22. The driver 22 applies a signal SRESTOREL to the restore control line RESTOREL. The reset control lines RESETL extend in the Figure 2 and Figure 3 horizontal direction in

[0090] . One end of each reset control line RESETL is coupled to the driver 22. The driver 22 applies a signal SRESETL to the reset control line RESETL.

[0090] The memory cell 30 includes an SRAM (static random access memory) circuit 40, transistors 31 to 38, and storage elements 91 and 92.

[0091] The SRAM circuit 40 is configured to store one-bit information through positive feedback. The SRAM circuit 40 includes transistors 41 to 46. Transistors 41 and 43 are P-type MOS transistors, and transistors 42, 44, 45, and 46 are N-type MOS transistors.

[0092] The gate of transistor 41 is coupled to node N1, the source is supplied with the power supply voltage VDD, and the drain is coupled to node N2. The gate of transistor 42 is coupled to node N1, the source is grounded, and the drain is coupled to node N2. Transistors 41 and 42 form an inverter IV1. The inverter IV1 is configured to invert the voltage VN1 at node N1 and output the inverted result to node N2. The gate of transistor 43 is coupled to node N2, the source is supplied with the power supply voltage VDD, and the drain is coupled to node N1. The gate of transistor 44 is coupled to node N2, the source is grounded, and the drain is coupled to node N1. Transistors 43 and 44 form an inverter IV2. The inverter IV2 is configured to invert the voltage VN2 at node N2 and output the inverted result to node N1. The gate of transistor 45 is coupled to the word line AWL, the source is coupled to the bit line BL, and the drain is coupled to node N1. The gate of transistor 46 is coupled to the word line AWL, the source is coupled to the bit line BLB, and the drain is coupled to node N2.

[0093] With this configuration, the input terminal of inverter IV1 and the output terminal of inverter IV2 are coupled to each other via node N1, and the input terminal of inverter IV2 and the output terminal of inverter IV1 are coupled to each other via node N2. This enables the SRAM circuit 40 to store one bit of information through positive feedback. Then, transistors 45 and 46 are turned on so that information is written into the SRAM circuit 40 via the bit lines BL and BLB, or information is read from the SRAM circuit 40.

[0094] Transistors 31 to 38 are N-type MOS transistors. The gate of transistor 31 is coupled to the restore control line RESTOREL, the drain is coupled to node N1, and the source is coupled to terminal T3 of the storage element 91. The gate of transistor 32 is coupled to node N1, the drain is coupled to the source of transistor 34, and the source is coupled to terminal T1 of the storage element 91 and the drain of transistor 33. The gate of transistor 33 is coupled to the reset control line RESETL, the drain is coupled to terminal T1 of the storage element 91 and the source of transistor 32, and the source is grounded. The gate of transistor 34 is coupled to the control line BWL, the drain is supplied with the power supply voltage VDD, and the source is coupled to the drain of transistor 32.

[0095] The gate of transistor 35 is coupled to the restore control line RESTOREL, the drain is coupled to node N2, and the source is coupled to terminal T3 of the storage element 92. The gate of transistor 36 is coupled to node N2, the drain is coupled to the source of transistor 38, and the source is coupled to terminal T1 of the storage element 92 and the drain of transistor 37. The gate of transistor 37 is coupled to the reset control line RESETL, the drain is coupled to terminal T1 of the storage element 92, the source of transistor 36, and the source is grounded. The gate of transistor 38 is coupled to the control line BWL, the drain is supplied with the power supply voltage VDD, and the source is coupled to the drain of transistor 36.

[0096] The storage elements 91 and 92 are non-volatile storage elements, and in this example, they are SOT type storage elements capable of storing information by changing the resistance state by using spin orbit torque (SOT: spin orbit torque).

[0097] The storage element 91 has a terminal T1, a terminal T2, a terminal T3, and a magnetoresistive element MR including a plurality of magnetic layers. Terminal T1 of the storage element 91 is coupled to the source of transistor 32 and the drain of transistor 33, terminal T2 is coupled to the control line CTRL, and terminal T3 is coupled to the source of transistor 31. The wiring between terminal T1 and terminal T2 is disposed adjacent to the magnetoresistive element MR. The storage element 91 is configured to store information by setting the state of the resistance value (resistance state) between terminal T2 and terminal T3 to a high resistance state RH or a low resistance state RL according to the direction of the current flowing between terminal T1 and terminal T2. The high resistance state RH is a state where the resistance value between terminal T2 and terminal T3 is high, and the low resistance state RL is a state where the resistance value between terminal T2 and terminal T3 is low. In the storage element 91, the current does not directly pass through the magnetoresistive element MR, but passes through the wiring adjacent to the magnetoresistive element MR, which makes it possible to set the state of the resistance value in the magnetoresistive element MR.

[0098] Figure 4 An operation example of the storage element 91 is schematically shown. In the storage element 91, the resistance state between terminal T2 and terminal T3 is set to the low resistance state RL by a predetermined current flowing from terminal T2 to terminal T1. In addition, in the storage element 91, the resistance state between terminal T2 and terminal T3 is set to the high resistance state RH by a predetermined current flowing from terminal T1 to terminal T2.

[0099] Similar to the storage element 91, the storage element 92 has a terminal T1, a terminal T2, a terminal T3, and a magnetoresistive element MR including a plurality of magnetic layers. Terminal T1 of the storage element 92 is coupled to the source of transistor 36 and the drain of transistor 37, terminal T2 is coupled to the control line CTRL, and terminal T3 is coupled to the source of transistor 35. Similar to the storage element 91 ( Figure 4) The storage element 92 is configured to store information by setting the state of the resistance value (resistance state) between the terminal T2 and the terminal T3 to a high resistance state RH or a low resistance state RL according to the direction of the current flowing between the terminal T1 and the terminal T2. Specifically, in the storage element 92, similar to the storage element 91, the resistance state between the terminal T2 and the terminal T3 is set to the low resistance state RL by a predetermined current flowing from the terminal T2 to the terminal T1, and the resistance state between the terminal T2 and the terminal T3 is set to the high resistance state RH by a predetermined current flowing from the terminal T1 to the terminal T2.

[0100] In this way, the memory cell 30 includes transistors 31 to 38 and storage elements 91 and 92 in addition to the SRAM circuit 40. Therefore, for example, in the case where the power supply transistor 12 is turned off to perform a standby operation, performing a storage operation immediately before the standby operation enables the storage elements 91 and 92, which are non-volatile memories, to store the information stored in the SRAM circuit 40, which is a volatile memory. Then, the semiconductor circuit 1 performs a recovery operation immediately after the standby operation, which enables the SRAM circuit 40 to store the information stored in the storage elements 91 and 92. This allows the semiconductor circuit 1 to return the state of each memory cell 30 to the state where the power supply has not stopped within a short time after restarting the power supply.

[0101] The driver 22 ( Figure 1 and Figure 3 ) is configured to apply the signal SAWL to the word line AWL, apply the signal SBWL to the control line BWL, apply the signal SCTRL to the control line CTRL, apply the signal SRESTORL to the restore control line RESTOREL, and apply the signal SRESETL to the reset control line RESETL based on the control signal supplied from the controller 11.

[0102] The driver 23 is configured to write information to the memory cell array 21 or read information from the memory cell array 21 via the bit lines BL and BLB. Specifically, the driver 23 writes information to the memory cell array 21 via the bit lines BL and BLB based on the control signal and data supplied from the controller 11. In addition, the driver 23 reads information from the memory cell array 21 via the bit lines BL and BLB based on the control signal supplied from the controller 11, and supplies the read information to the controller 11.

[0103] Here, the inverter IV1 corresponds to a specific example of the "first circuit" in the present disclosure. The inverter IV2 corresponds to a specific example of the "second circuit" in the present disclosure. The storage element 91 corresponds to a specific example of the "first storage element" in the present disclosure. The storage element 92 corresponds to a specific example of the "second storage element" in the present disclosure. The transistor 31 corresponds to a specific example of the "first transistor" in the present disclosure. The transistor 32 corresponds to a specific example of the "second transistor" in the present disclosure. The transistor 33 corresponds to a specific example of the "third transistor" in the present disclosure. The transistor 34 corresponds to a specific example of the "fourth transistor" in the present disclosure. The transistor 35 corresponds to a specific example of the "ninth transistor" in the present disclosure. The transistor 36 corresponds to a specific example of the "tenth transistor" in the present disclosure. The transistor 37 corresponds to a specific example of the "eleventh transistor" in the present disclosure. The transistor 38 corresponds to a specific example of the "twelfth transistor" in the present disclosure. The controller 11 and the driver 22 correspond to specific examples of the "controller" in the present disclosure.

[0104] [Operation and Working]

[0105] Next, a description of the operation and working of the semiconductor circuit 1 according to the present embodiment is given.

[0106] (Overview of Overall Operation)

[0107] First, a description of the overview of the overall operation of the semiconductor circuit 1 is given. The controller controls the operation of the storage circuit 20. Specifically, the controller 11 writes information into the storage circuit 20 based on a write command and write data supplied from the outside, and reads information from the storage circuit 20 based on a read command supplied from the outside. In addition, the controller 11 controls the power supply to the storage circuit 20 by supplying a power control signal SPG to the power transistor 12 to turn the power transistor 12 on and off. The power transistor 12 performs a conduction / turn-off operation based on the control signal supplied from the controller 11. Then, turning on the power transistor 12 causes the storage circuit 20 to be supplied with a power voltage VDD1 as the power voltage VDD. The driver 22 of the storage circuit 20 applies a signal SAWL to the word line AWL, a signal SBWL to the control line BWL, a signal SCTRL to the control line CTRL, a signal SRESTORL to the restore control line RESTOREL, and a signal SRESETL to the reset control line RESETL based on the control signal supplied from the controller 11. The driver 23 writes information into the storage cell array 21 via the bit lines BL and BLB based on the control signal and data supplied from the controller 11. In addition, the driver 23 reads information from the storage cell array 21 via the bit lines BL and BLB based on the control signal supplied from the controller 11, and supplies the read information to the controller 11.

[0108] (Details of the operation)

[0109] The semiconductor circuit 1 performs an initialization operation OP1 to reset the resistance states of the storage elements 91 and 92 to a predetermined resistance state (in this example, the low-resistance state RL). In the normal operation OP2, then the SRAM circuit 40, which is a volatile memory, stores information. For example, in the case where the power transistor 12 is turned off to perform the standby operation OP4, the semiconductor circuit 1 performs a storage operation OP3 immediately before the standby operation OP4, so that the storage elements 91 and 92, which are non-volatile memories, store the information stored in the SRAM circuit 40, which is a volatile memory. Then, the semiconductor circuit 1 performs a recovery operation OP5 immediately after the standby operation OP4 to cause the SRAM circuit 40 to store the information stored in the storage elements 91 and 92. This operation will be described in detail below.

[0110] Figure 5 An operation example of a specific storage cell 30 of interest in the semiconductor circuit 1 is shown. Figures 6A to 6E Each shows the operation state of the storage cell 30. Figure 6A Shows the state in the initialization operation OP1. Figure 6B Shows the state in the normal operation OP2. Figure 6C Shows the state in the storage operation OP3. Figure 6D Shows the state in the standby operation OP4. Figure 6E Shows the state in the recovery operation OP5. Figures 6A to 6E The inverters IV1 and IV2 are shown using symbols, and the transistors 31, 33, 34, 35, 37, and 38 are shown using switches corresponding to the operation states of the transistors.

[0111] (Initialization operation OP1)

[0112] The semiconductor circuit 1 first performs an initialization operation OP1 to reset the resistance states of the storage elements 91 and 92 to a predetermined resistance state (in this example, the low-resistance state RL). Specifically, for example, when the power supply of the system including the semiconductor circuit 1 is turned on, the semiconductor circuit 1 can perform the initialization operation OP1.

[0113] In the initialization operation OP1, as Figure 5 shown, the controller 11 first sets the voltage of the power control signal SPG to a low level. This turns on the power transistor 12 ( Figure 1 ) and the storage cell 30 is supplied with the power supply voltage VDD. In addition, the driver 22 sets the voltage of the signal SBWL to a low level and the voltage of the signal SRESTOREL to a low level. As Figure 6AAs shown, this turns off transistors 31, 34, 35, and 38. As a result, the SRAM circuit 40 is electrically separated from the storage elements 91 and 92. Additionally, as Figure 5 shown, the driver 22 sets the voltage of the signal SRESETL to a high level within a predetermined period. As Figure 6A shown, this turns on transistors 33 and 37. Additionally, as Figure 5 shown, the driver 22 sets the voltage of the signal SCTRL to a high level voltage VH (power supply voltage level) within a predetermined period. This causes the initialization current Iinit1 to flow sequentially through the control line CTRL, the storage element 91, and the transistor 33, and causes the initialization current Iinit2 to flow sequentially through the control line CTRL, the storage element 92, and the transistor 37, as Figure 6A shown. As a result, the resistance states of the storage elements 91 and 92 are set to the low-resistance state RL.

[0114] The resistance states of the storage elements 91 and 92 are reset and are thus set to the low-resistance state RL by the initialization operation OP1.

[0115] (Normal operation OP2)

[0116] After performing the initialization operation OP1, the semiconductor circuit 1 performs the normal operation OP2 to write information to the SRAM circuit 40, which is a volatile memory, or read information from the SRAM circuit 40.

[0117] In the normal operation OP2, the driver 22 sets the voltage of the signal SRESETL to a low level, as Figure 5 shown. As Figure 6B shown, this turns off transistors 33 and 37. Additionally, as Figure 5 shown, the driver 22 sets the voltage of the signal SCTRL to a low level voltage VL (ground level). It should be noted that this is not restrictive, and the driver 22 can set the control line CTRL to a floating state.

[0118] In this normal operation OP2, the semiconductor circuit 1 writes information into the SRAM circuit 40 of the memory cell 30 or reads information from the SRAM circuit 40. Specifically, in the case of writing information into the SRAM circuit 40, the driver 23 first applies signals having mutually inverted voltage levels corresponding to the information to be written to the bit lines BL and BLB. Then, the driver 22 sets the voltage of the signal SAWL to a high level, thereby turning on the transistors 35 and 46 of the SRAM circuit 40. This causes the information corresponding to the voltages of the bit lines BL and BLB to be written into the SRAM circuit 40. Additionally, in the case of reading information from the SRAM circuit 40, the driver 23 pre-charges each of the bit lines BL and BLB to a high-level voltage, for example, and thereafter the driver 22 sets the voltage of the signal SAWL to a high level, thereby turning on the transistors 45 and 46. This causes the voltage of one of the bit lines BL and BLB to change according to the information stored in the SRAM circuit 40. Then, the driver 23 detects the difference between the voltages of the bit lines BL and BLB, thereby reading the information stored in the SRAM circuit 40.

[0119] At this time, as Figure 6B shown, the transistors 31, 33, 34, 35, 37, and 38 are turned off. Therefore, current does not flow through the memory elements 91 and 92, which causes the resistance state of each of the memory elements 91 and 92 to be maintained at a predetermined resistance state (the low-resistance state RL in this example).

[0120] (Storage operation OP3)

[0121] Next, the storage operation OP3 is described. The semiconductor circuit 1 performs the storage operation OP3 before performing the standby operation OP4, thereby causing the memory elements 91 and 92 to store the information stored in the SRAM circuit 40.

[0122] In the storage operation OP3, as Figure 5 shown, the driver 22 sets the voltage of the signal SAWL to a low level. This turns off the transistors 45 and 46. In addition, the driver 22 sets the voltage of the signal SBWL to a high level within a predetermined period, as Figure 5 shown. As Figure 6C shown, this turns on each of the transistors 34 and 38, and the drains of the transistors 32 and 36 are supplied with the power supply voltage VDD. This causes a storage current Istore to flow through one of the memory elements 91 and 92.

[0123] In this example, the voltage VN1 at the node N1 is the high-level voltage VH, and the voltage VN2 at the node N2 is the low-level voltage VL. Therefore, in the memory cell 30, as Figure 6CAs shown, a high-level voltage VH is supplied to the gate of transistor 32, which causes a storage current Istore to flow sequentially through transistor 34, transistor 32, and storage element 91. As a result, the resistance state of storage element 91 is set to a high-resistance state RH. In memory cell 30, the resistance states of storage elements 91 and 92 are set in such a manner according to the information stored in SRAM circuit 40.

[0124] For example, the storage operation OP3 is performed on a row-by-row basis. For example, signal SBWL can be used to set the rows on which the storage operation OP3 is to be performed and the rows on which the storage operation OP3 is not to be performed. Specifically, driver 22 can set the voltage of signal SBWL to a high level for the rows on which the storage operation OP3 is to be performed within a predetermined time period and can maintain the voltage of signal SBWL at a low level for the rows on which the storage operation OP3 is not to be performed.

[0125] (Standby operation OP4)

[0126] Then, after the storage operation OP3, semiconductor circuit 1 turns off power transistor 12, thereby performing the standby operation OP4.

[0127] In the standby operation OP4, as Figure 5 shown, controller 11 sets the voltage of power control signal SPG to a high level. This turns off power transistor 12 ( Figure 1 ) and stops the power supply to memory cell 30. At this time, as Figure 6D shown, the resistance states of storage elements 91 and 92 are maintained.

[0128] (Recovery operation OP5)

[0129] Next, the recovery operation OP5 is described. In the case where the normal operation OP2 is performed after the standby operation OP4, semiconductor circuit 1 performs the recovery operation OP5 before performing the normal operation OP2, so that SRAM circuit 40 stores the information stored in storage elements 91 and 92.

[0130] In the recovery operation OP5, as Figure 5 shown, controller 11 sets the voltage of power control signal SPG to a low level. This turns on power transistor 12 ( Figure 1 ) and memory cell 30 is supplied with the power supply voltage VDD. Then, driver 22 sets the voltage of signal SRESTOREL to a high level only for a predetermined length of time immediately after power transistor 12 is turned on. As Figure 6E shown, this turns on each of transistors 31 and 35 during this time period. That is, during this time period, SRAM circuit 40 is electrically coupled to storage elements 91 and 92. Additionally, as Figure 5As shown, the driver 22 sets the voltage of the signal SCTRL to the low-level voltage VL (ground level). This causes the node N1 to be grounded via the storage element 91 and the node N2 to be grounded via the storage element 92. At this time, the resistance states of the storage elements 91 and 92 are different from each other; therefore, the voltage state in the SRAM circuit 40 is determined according to the resistance states of the storage elements 91 and 92.

[0131] In this example, as Figure 6E shown, the resistance state of the storage element 91 is set to the high-resistance state RH, and the resistance state of the storage element 92 is set to the low-resistance state RL. This causes the node N1 to be pulled down with a high resistance value and the node N2 to be pulled down with a low resistance value. Therefore, the voltage VN1 at the node N1 is set to the high-level voltage VH, and the voltage VN2 at the node N2 is set to the low-level voltage VL. Thus, in the memory cell 30, the SRAM circuit 40 stores information according to the information stored in the storage elements 91 and 92.

[0132] Note that, in this example, the voltage of the signal SRESTOREL is set to the high level only for a predetermined length of time immediately after the power supply transistor 12 is turned on, but this is not restrictive. Instead, for example, even before the power supply transistor 12 is turned on, the voltage of the signal SRESTOREL can be set to the high level in advance.

[0133] For example, all the memory cells 30 in the memory cell array 21 simultaneously perform the restore operation OP5. Note that this is not restrictive, and some of the memory cells 30 in the memory cell array 21 can perform the restore operation OP5 while other memory cells 30 do not perform the restore operation OP5. For example, in the case where the restore operation OP5 is performed row by row, the driver 22 can set the signal SRESTOREL to the high level only for the rows to perform the restore operation OP5 within a predetermined time period, and can maintain the signal SRESTOREL at the low level for the rows not to perform the restore operation OP5.

[0134] Thereafter, the semiconductor circuit 1 performs, for example, the initialization operation OP1, and then performs the normal operation OP2 ( Figure 6A ). In this way, the semiconductor circuit 1 sequentially repeats the initialization operation OP1, the normal operation OP2, the storage operation OP3, the standby operation OP4, and the restore operation OP5. Note that, in this example, the initialization operation OP1 is performed before the normal operation OP2, but this is not restrictive. The initialization operation OP1 can be performed at any time before the storage operation OP3.

[0135] In this manner, the semiconductor circuit 1 executes a storage operation OP3 immediately before a standby operation OP4, so that the storage elements 91 and 92 serving as non-volatile memories store the information stored in the SRAM circuit 40 serving as a volatile memory. Then, the semiconductor circuit 1 executes a restoration operation OP5 immediately after the standby operation OP4, so that the SRAM circuit 40 stores the information stored in the storage elements 91 and 92. This allows the semiconductor circuit 1 to return the state of each memory cell 30 to the state before the power supply was stopped in a short time after restarting the power supply.

[0136] In addition, in the semiconductor circuit 1, the SOT type storage elements 91 and 92 are used to configure the memory cell 30. Then, the storage elements 91 and 92 are configured to store information by setting the resistance state between the terminal T2 and the terminal T3 according to the direction of the current flowing between the terminal T1 and the terminal T2. This prevents current from flowing through the magnetoresistive element MR in the storage elements 91 and 92 when information is stored in the storage elements 91 and 92, which makes it possible to enhance the durability (reliability).

[0137] That is, for example, similar to the storage circuit described in Patent Document 1, in the case where a spin transfer torque (STT; spin transfer torque) magnetic tunnel junction (MJT; magnetic tunnel junction) element is used as a storage element, when storing information in the storage element, current is made to pass through the free layer, the tunnel insulating layer, and the pinned layer of the storage element. Therefore, passing current through the storage element in this way may cause the characteristics of the storage element to deteriorate over time and the durability to decrease. Meanwhile, in the semiconductor circuit 1 according to the present embodiment, the SOT type storage elements 91 and 92 are used to configure the memory cell 30. In addition, the storage elements 91 and 92 are configured to store information by setting the resistance state between the terminal T2 and the terminal T3 according to the direction of the current flowing between the terminal T1 and the terminal T2. In this way, in the storage elements 91 and 92, the current does not directly pass through the magnetoresistive element MR, but through the wiring adjacent to the magnetoresistive element MR, which makes it possible to set the state of the resistance value in the magnetoresistive element MR. Therefore, in the semiconductor circuit 1, when storing information in the storage elements 91 and 92, the current does not pass through the magnetoresistive element MR itself, which makes it possible to reduce the possibility of deterioration of the characteristics of the storage elements 91 and 92 over time. Therefore, this makes it possible to enhance the durability of the semiconductor circuit 1.

[0138] In addition, in the semiconductor circuit 1, the gate of the transistor 32 is coupled to the node N1, and the gate of the transistor 36 is coupled to the node N2. In Figure 6CIn the example, this enables the storage current Istore to pass through the storage element 91 via the transistor 32. That is, the storage current Istore can be prevented from flowing into the SRAM circuit 40 in the semiconductor circuit 1. This prevents the information stored in the SRAM circuit in the semiconductor circuit 1 from being lost due to the storage current flowing into the SRAM circuit as in the storage circuit of Patent Document 1, which enables the possibility of occurrence of so-called interference to be reduced.

[0139] [Effect]

[0140] As described above, in the present embodiment, the SOT type storage element is used to configure the storage cell, which enables the durability (reliability) to be enhanced.

[0141] In the present embodiment, the gate of the transistor 32 is coupled to the node N1, and the gate of the transistor 36 is coupled to the node N2, which enables the possibility of occurrence of interference to be reduced.

[0142] [Modification Example 1-1]

[0143] In the above-described embodiment, for example, as Figure 4 shown, a current is made to flow from the terminal T2 of the storage element 91 to the terminal T1, thereby setting the resistance state between the terminal T2 and the terminal T3 to the low resistance state RL, but this is not restrictive. The semiconductor circuit 1A according to this modification example is described in detail below. The semiconductor circuit 1A includes a storage circuit 20A. The storage circuit 20A includes a storage cell array 21A. The storage cell array 21A includes a plurality of storage cells 30A.

[0144] Figure 7 A configuration example of the storage cell 30A is shown. The storage cell 30A includes an SRAM circuit 40, transistors 31 to 38, and storage elements 91A and 92A. In this storage cell 30A, the gate of the transistor 32 is coupled to the node N2, and the gate of the transistor 36 is coupled to the node N1.

[0145] Figure 8 An operation example of the storage element 91A is schematically shown. In this storage element 91A, the resistance state between the terminal T2 and the terminal T3 is set to the high resistance state RH by a predetermined current flowing from the terminal T2 to the terminal T1. In addition, in the storage element 91A, the resistance state between the terminal T2 and the terminal T3 is set to the low resistance state RL by a predetermined current flowing from the terminal T1 to the terminal T2. The same applies to the storage element 92A.

[0146] Figures 9A to 9E Each shows the operation state of the storage cell 30A. Figure 9A The state in the initialization operation OP1 is shown. Figure 9BShows the state in the normal operation OP2. Figure 9C Shows the state in the storage operation OP3. Figure 9D Shows the state in the standby operation OP4. Figure 9E Shows the state in the recovery operation OP5.

[0147] In the initialization operation OP1, the controller 11 first sets the voltage of the power control signal SPG to a low level, as Figure 5 shown. This turns on the power transistor 12 ( Figure 1 ), and the storage unit 30A is supplied with the power supply voltage VDD. In addition, the driver 22 sets the voltage of the signal SBWL to a low level and sets the voltage of the signal SRESTOREL to a low level. As Figure 9A shown, this turns off the transistors 31, 34, 35, and 38. In addition, as Figure 5 shown, the driver 22 sets the voltage of the signal SRESETL to a high level within a predetermined period. As Figure 9A shown, this turns on the transistors 33 and 37. In addition, as Figure 5 shown, the driver 22 sets the voltage of the signal SCTRL to the high voltage VH (power supply voltage level) within a predetermined period. This causes the initialization current Iinit1 to flow sequentially through the control line CTRL, the storage element 91A, and the transistor 33, and causes the initialization current Iinit2 to flow sequentially through the control line CTRL, the storage element 92A, and the transistor 37, as Figure 9A shown. This sets the resistance states of the storage elements 91A and 92A to the high resistance state RH.

[0148] The operation in the normal operation OP2 is similar to the operation in the above-described embodiment ( Figure 6B ). At this time, as Figure 9B shown, the transistors 31, 33, 34, 35, 37, and 38 are turned off. Therefore, no current flows through the storage elements 91A and 92A, which causes the resistance state of each of the storage elements 91A and 92A to be maintained at a predetermined resistance state (in this example, the high resistance state RH).

[0149] In the storage operation OP3, the driver 22 sets the voltage of the signal SBWL to a high level within a predetermined period, as Figure 5 shown. As Figure 9C shown, this turns on each of the transistors 34 and 38, and the drains of the transistors 32 and 36 are supplied with the power supply voltage VDD. This causes the storage current Istore to flow through one of the storage elements 91A and 92A. In this example, the voltage VN1 of the node N1 is the high voltage VH, and the voltage VN2 of the node N2 is the low voltage VL. Therefore, in the storage unit 30A, asFigure 9C As shown, the gate of transistor 36 is supplied with a high-level voltage VH, which causes the storage current Istore to flow sequentially through transistor 38, transistor 36, and storage element 92A. As a result, the resistance state of storage element 92A is set to the low-resistance state RL.

[0150] The standby operation OP4 is similar to the operation in the above-described embodiment ( Figure 6D ). At this time, as Figure 9D shown, the resistance states of storage elements 91A and 92A are maintained.

[0151] In the recovery operation OP5, as Figure 5 shown, the controller 11 sets the voltage of the power control signal SPG to a low level. This turns on the power transistor 12 ( Figure 1 ), and the memory cell 30A is supplied with the power supply voltage VDD. Then, the driver 22 sets the voltage of the signal SRESTOREL to a high level only for a predetermined length of time immediately after turning on the power transistor 12. As Figure 9E shown, this turns on each of transistors 31 and 35 during this time period. Additionally, as Figure 5 shown, the driver 22 sets the voltage of the signal SCTRL to the low-level voltage VL (ground level). This causes node N1 to be grounded via storage element 91A, and causes node N2 to be grounded via storage element 92A. At this time, the resistance states of storage elements 91A and 92A are different from each other; thus, the voltage state in the SRAM circuit 40 is determined based on the resistance states of storage elements 91A and 92A. In this example, as Figure 9E shown, the resistance state of storage element 91A is set to the high-resistance state RH, and the resistance state of storage element 92A is set to the low-resistance state RL. This causes node N1 to be pulled down with a high resistance value, and causes node N2 to be pulled down with a low resistance value. Therefore, the voltage VN1 at node N1 is set to the high-level voltage VH, and the voltage VN2 at node N2 is set to the low-level voltage VL.

[0152] [Modification Example 1-2]

[0153] In the above-described embodiment, one power transistor 12 is provided, but this is not restrictive. Instead, for example, like Figure 10As in the semiconductor circuit 1B shown, a plurality of power transistors may be provided. The semiconductor circuit 1B includes a controller 11B, a plurality of power transistors 12A, 12B, ..., and a storage circuit 20B. The controller 11B supplies power control signals SPGA, SPGB, ... to the plurality of power transistors 12A, 12B, ... respectively to turn on and off the plurality of power transistors 12A, 12B, ..., thereby controlling the power supply to the storage circuit 20B. For example, each of the plurality of power transistors 12A, 12B, ... is provided in association with a corresponding one of the plurality of banks in the storage circuit 20B. This enables power supply control in units of the banks of the storage circuit 20B in the semiconductor circuit 1B.

[0154] [Modification Examples 1-3]

[0155] In the above embodiment, for example, P-type MOS transistors are used to configure the power transistors 12, but this is not restrictive. Instead, for example, as Figure 11 in the semiconductor circuit 1C shown, N-type MOS transistors may be used to configure the power transistors. The semiconductor circuit 1C includes a controller 11C, a power transistor 12C, and a storage circuit 20C. The controller 11C supplies a power control signal SPG to the power transistor 12C to turn on and off the power transistor 12C. The power transistor 12C is an N-type MOS transistor in this example, and its gate is supplied with the power control signal SPG, its drain is coupled to the storage circuit 20C, and its source is supplied with the ground voltage VSS1. With this configuration, in the semiconductor circuit 1C, when the storage circuit 20C is used, the power transistor 12C is turned on, and the storage circuit 20C is supplied with the ground voltage VSS1 as the ground voltage VSS. Also, in the semiconductor circuit 1C, when the storage circuit 20C is not used, the power transistor 12C is turned off.

[0156] The storage circuit 20C includes a storage cell array 21C and drivers 22C and 23. The storage cell array 21C includes a plurality of storage cells 30C.

[0157] Figure 12shows a configuration example of the memory cell 30C. The memory cell 30C includes an SRAM circuit 40, transistors 31C, 32 to 34, 35C and 36 to 38, and memory elements 91 and 92. The transistors 31C and 35C are P-type MOS transistors. The gate of the transistor 31C is coupled to the control line RESTOREL, the source is coupled to the node N1, and the drain is coupled to the terminal T3 of the memory element 91. The gate of the transistor 35C is coupled to the control line RESTOREL, the source is coupled to the node N2, and the drain is coupled to the terminal T3 of the memory element 92. The gate of the transistor 32 is coupled to the node N2, and the gate of the transistor 36 is coupled to the node N1. As Figure 4 shown, in the memory elements 91 and 92, the resistance state between the terminal T2 and the terminal T3 is set to the low resistance state RL by a predetermined current flowing from the terminal T2 to the terminal T1, and the resistance state between the terminal T2 and the terminal T3 is set to the high resistance state RH by a predetermined current flowing from the terminal T1 to the terminal T2.

[0158] The driver 22C is configured to apply the signal SAWL to the word line AWL, the signal SBWL to the control line BWL, the signal SCTRL to the control line CTRL, the signal SRESTORL to the restore control line RESTOREL, and the signal SRESETL to the reset control line RESETL based on the control signals supplied from the controller 11C.

[0159] Figure 13 shows an operation example of a specific memory cell 30C of interest in the semiconductor circuit 1C. Figures 14A to 14E Each shows the operation state of the memory cell 30C. Figure 14A shows the state in the initialization operation OP1. Figure 14B shows the state in the normal operation OP2. Figure 14C shows the state in the storage operation OP3. Figure 14D shows the state in the standby operation OP4. Figure 14E shows the state in the restore operation OP5.

[0160] In the initialization operation OP1, as Figure 13 shown, the controller 11C first sets the voltage of the power control signal SPG to a high level. This turns on the power transistor 12C ( Figure 11 ), and the memory cell 30C is supplied with the ground voltage VSS. In addition, the driver 22C sets the voltage of the signal SBWL to a low level and the voltage of the signal SRESTOREL to a high level. As Figure 14A shown, this turns off the transistors 31C, 34, 35C and 38. In addition, as Figure 13As shown, the driver 22C sets the voltage of the signal SRESETL to a high level within a predetermined period. As Figure 14A shown, this turns on the transistors 33 and 37. Additionally, as Figure 13 shown, the driver 22C sets the voltage of the signal SCTRL to a high level voltage VH (power supply voltage level) within a predetermined period. This causes the initialization current Iinit1 to flow sequentially through the control line CTRL, the storage element 91, and the transistor 33, and causes the initialization current Iinit2 to flow sequentially through the control line CTRL, the storage element 92, and the transistor 37, as Figure 14A shown. This sets the resistance states of the storage elements 91 and 92 to a low resistance state RL.

[0161] The operation in the normal operation OP2 is similar to the operation in the above-described embodiment ( Figure 6B ). At this time, as Figure 14B shown, the transistors 31C, 33, 34, 35C, 37, and 38 are turned off. Therefore, current does not flow through the storage elements 91 and 92, which causes the resistance state of each of the storage elements 91 and 92 to be maintained at a predetermined resistance state (in this example, the low resistance state RL).

[0162] In the storage operation OP3, as Figure 13 shown, the driver 22C sets the voltage of the signal SBWL to a high level within a predetermined period. As Figure 14C shown, this turns on each of the transistors 34 and 38, and the drains of the transistors 32 and 36 are supplied with the power supply voltage VDD. This causes the storage current Istore to flow through one of the storage elements 91 and 92. In this example, the voltage VN1 of the node N1 is the high level voltage VH, and the voltage VN2 of the node N2 is the low level voltage VL. Therefore, in the storage cell 30C, as Figure 14C shown, the gate of the transistor 36 is supplied with the high level voltage VH, which causes the storage current Istore to flow sequentially through the transistor 38, the transistor 36, and the storage element 92. As a result, the resistance state of the storage element 92A is set to the high resistance state RH.

[0163] In the standby operation OP4, as Figure 13 shown, the controller 11C sets the voltage of the power supply control signal SPG to a low level. This turns off the power supply transistor 12C ( Figure 11 ), and the supply of the ground voltage VSS to the storage cell 30C is stopped. At this time, as Figure 14D shown, the resistance states of the storage elements 91 and 92 are maintained.

[0164] In the recovery operation OP5, the controller 11C sets the voltage of the power supply control signal SPG to a high level, asFigure 13 as shown. This turns on the power transistor 12C ( Figure 11 ), and the storage cell 30C is supplied with the ground voltage VSS. Then, the driver 22C sets the voltage of the signal SRESTOREL to a low level only for a predetermined length of time immediately after turning on the power transistor 12C. As Figure 14E shown, this turns on each of the transistors 31C and 35C during this time period. Additionally, as Figure 13 shown, the driver 22C sets the voltage of the signal SCTRL to the high-level voltage VH (power supply voltage level) only for a predetermined length of time. This causes the node N1 to be coupled to the power supply via the storage element 91, and causes the node N2 to be coupled to the power supply via the storage element 92. At this time, the resistance states of the storage elements 91 and 92 are different from each other; thus, the voltage state in the SRAM circuit 40 is determined based on the resistance states of the storage elements 91 and 92. In this example, as Figure 14E shown, the resistance state of the storage element 91 is set to the low-resistance state RL, and the resistance state of the storage element 92 is set to the high-resistance state RH. This causes the node N1 to be pulled up with a low resistance value, and causes the node N2 to be pulled up with a high resistance value. Therefore, the voltage VN1 at the node N1 is set to the high-level voltage VH, and the voltage VN2 at the node N2 is set to the low-level voltage VL.

[0165] <2. Second Embodiment>

[0166] Next, a description of the semiconductor circuit 2 according to the second embodiment is given. In this embodiment, a storage cell is configured using one storage element. That is, in the above-described first embodiment, each storage cell includes two storage elements, while in this embodiment, each storage cell includes one storage element. It should be noted that components that are substantially the same as those of the semiconductor circuit 1 according to the above-described first embodiment are denoted by the same reference numerals, and their descriptions are appropriately omitted.

[0167] As Figure 1 shown, the semiconductor circuit 2 includes a storage circuit 50. The storage circuit 50 includes a storage cell array 51 and drivers 22 and 23. The storage cell array 51 includes a plurality of storage cells 60.

[0168] Figure 15 An example configuration of the storage cell 60 in the storage cell array 51 is shown. Figure 16 An example configuration of the storage cell array 51 is shown. The storage cell array 51 includes a plurality of word lines AWL, a plurality of control lines BWL, a plurality of bit lines BL, a plurality of bit lines BLB, a plurality of control lines CTRL, a plurality of restore control lines RESTOREL, and a plurality of reset control lines RESETL.

[0169] The memory cell 60 includes an SRAM circuit 70, transistors 31 to 34, and a memory element 91.

[0170] The SRAM circuit 70 includes transistors 71 to 74, 45, and 46. Transistors 71 to 74 respectively correspond to transistors 41 to 44 according to the above-described first embodiment ( Figure 2 ). Transistors 71 and 72 form an inverter IV3, and transistors 73 and 74 form an inverter IV4. The SRAM circuit 70 is configured to easily set the voltage at node N1 to a high level immediately after power is turned on.

[0171] Specifically, in this example, the gate length L73 of transistor 73 is equal to the gate length L71 of transistor 71, and the gate width W73 of transistor 73 is greater than the gate width W71 of transistor 71 (W73 > W71). In addition, the gate length L72 of transistor 72 is equal to the gate length L74 of transistor 74, and the gate width W72 of transistor 72 is greater than the gate width W74 of transistor 74 (W72 > W74). This makes it easy for inverter IV4 to output a high level and makes it easy for inverter IV3 to output a low level immediately after power is turned on.

[0172] In addition, in the SRAM circuit 70, as described later, in the restore operation OP5, when the resistance state of the memory element 91 is the high-resistance state RH, the current flowing from transistor 73 of inverter IV4 to node N1 is greater than the current flowing from node N1 via transistor 31 and the memory element 91 to the control line CTRL, and when the resistance state of the memory element 91 is the low-resistance state RL, the current flowing from transistor 73 of inverter IV4 to node N1 is less than the current flowing from node N1 via transistor 31 and the memory element 91 to the control line CTRL.

[0173] The gate of transistor 31 is coupled to the restore control line RESTOREL, the drain is coupled to node N1, and the source is coupled to terminal T3 of the memory element 91. The gate of transistor 32 is coupled to node N1, the drain is coupled to the source of transistor 34, and the source is coupled to terminal T1 of the memory element 91 and the drain of transistor 33. The gate of transistor 33 is coupled to the reset control line RESETL, the drain is coupled to terminal T1 of the memory element 91 and the source of transistor 32, and the source is grounded. The gate of transistor 34 is coupled to the control line BWL, the drain is supplied with the power supply voltage VDD, and the source is coupled to the drain of transistor 32.

[0174] Terminal T1 of the memory element 91 is coupled to the source of transistor 32 and the drain of transistor 33, terminal T2 is coupled to the control line CTRL, and terminal T3 is coupled to the source of transistor 31. In this memory element 91, asFigure 4 As shown, the resistance state between terminal T2 and terminal T3 is set to the low-resistance state RL by a predetermined current flowing from terminal T2 to terminal T1, and the resistance state between terminal T2 and terminal T3 is set to the high-resistance state RH by a predetermined current flowing from terminal T1 to terminal T2.

[0175] Here, the inverter IV3 corresponds to a specific example of the "first circuit" in the present disclosure. The inverter IV4 corresponds to a specific example of the "second circuit" in the present disclosure. The transistor 71 corresponds to a specific example of the "fifth transistor" in the present disclosure. The transistor 73 corresponds to a specific example of the "sixth transistor" in the present disclosure. The transistor 74 corresponds to a specific example of the "seventh transistor" in the present disclosure. The transistor 72 corresponds to a specific example of the "eighth transistor" in the present disclosure.

[0176] Figure 17A and Figure 17B 、 Figures 18A to 18C and Figures 19A to 19C each show the operation state of the storage unit 60. Figure 17A Shows the state in the initialization operation OP1. Figure 17B Shows the state in the normal operation OP2. Figures 18A to 18C Each shows the state when the voltage VN1 at the node N1 is the high-level voltage VH (VN1 = VH). Figure 18A Shows the state in the storage operation OP3. Figure 18B Shows the state in the standby operation OP4. Figure 18C Shows the state in the recovery operation OP5. Figures 19A to 19C Each shows the state when the voltage VN1 at the node N1 is the low-level voltage VL (VN1 = VL). Figure 19A Shows the state in the storage operation OP3. Figure 19B Shows the state in the standby operation OP4. Figure 19C Shows the state in the recovery operation OP5.

[0177] (Initialization operation OP1)

[0178] In the initialization operation OP1, the controller 11 first sets the voltage of the power control signal SPG to a low level, as Figure 5 shown. This turns on the power transistor 12 ( Figure 1 ), and the storage unit 60 is supplied with the power supply voltage VDD. In addition, the driver 22 sets the voltage of the signal SBWL to a low level and sets the voltage of the signal SRESTOREL to a low level. As Figure 17A shown, this turns off the transistors 31 and 34. As a result, the SRAM circuit 70 is electrically separated from the storage element 91. In addition, asFigure 5 As shown, the driver 22 sets the voltage of the signal SRESETL to a high level within a predetermined period. As Figure 17A shown, this turns on the transistor 33. Additionally, as Figure 5 shown, the driver 22 sets the voltage of the signal SCTRL to a high level voltage VH (power supply voltage level) within a predetermined period. As Figure 17A shown, this causes the initialization current Iinit to flow sequentially through the control line CTRL, the storage element 91, and the transistor 33. As a result, the resistance state of the storage element 91 is set to the low resistance state RL.

[0179] (Normal operation OP2)

[0180] In the normal operation OP2, the driver 22 sets the voltage of the signal SRESETL to a low level, as Figure 5 shown. As Figure 17B shown, this turns off the transistor 33. Additionally, as Figure 5 shown, the driver 22 sets the voltage of the signal SCTRL to a low level voltage (ground level). It should be noted that this is not restrictive, and the driver 22 can set the control line CTRL to a floating state.

[0181] In this normal operation OP2, the semiconductor circuit 2 writes information to the SRAM circuit 70 of the memory cell 60, or reads information from the SRAM circuit 70. At this time, as Figure 17B shown, the transistors 31, 33, and 34 are turned off. Therefore, no current flows through the storage element 91, which causes the resistance state of the storage element 91 to be maintained at a predetermined resistance state (in this example, the low resistance state RL).

[0182] (Storage operation OP3)

[0183] In the storage operation OP3, as Figure 5 shown, the driver 22 sets the voltage of the signal SAWL to a low level. This turns off the transistors 45 and 46. Additionally, the driver 22 sets the voltage of the signal SBWL to a high level within a predetermined period, as Figure 5 shown. This turns on the transistor 34, and the drain of the transistor 32 is supplied with the power supply voltage VDD, as Figure 18A and Figure 19A shown. Therefore, the resistance state of the storage element 91 is set according to the information stored in the SRAM circuit 70.

[0184] Specifically, for example, as Figure 18AAs shown, when the voltage VN1 at node N1 is the high-level voltage VH (VN1 = VH), the gate of transistor 32 is supplied with the high-level voltage VH, which causes the storage current Istore to flow sequentially through transistor 34, transistor 32, and storage element 91. As a result, the resistance state of storage element 91 is set to the high-resistance state RH.

[0185] In addition, for example, as Figure 19A shown, when the voltage VN1 at node N1 is the low-voltage level VL (VN1 = VL), the gate of transistor 32 is supplied with the low-level voltage VL; thus, current does not flow through storage element 91. As a result, the resistance state of storage element 91 is maintained at the low-resistance state RL.

[0186] (Standby operation OP4)

[0187] In standby operation OP4, as Figure 5 shown, the controller 11 sets the voltage of the power control signal SPG to the high level. This turns off the power transistor 12 ( Figure 1 ), and the power supply to the memory cell 60 is stopped. At this time, as Figure 18B and Figure 19B shown, the resistance state of storage element 91 is maintained.

[0188] (Recovery operation OP5)

[0189] In recovery operation OP5, as Figure 5 shown, the controller 11 sets the voltage of the power control signal SPG to the low level. This turns on the power transistor 12 ( Figure 1 ), and the memory cell 60 is supplied with the power supply voltage VDD. Then, the driver 22 sets the voltage of the signal SRESTOREL to the high level only for a predetermined length of time immediately after turning on the power transistor 12. This turns on transistor 31 during this time period, as Figure 18C and Figure 19C shown. In addition, as Figure 5 shown, the driver 22 sets the voltage of the signal SCTRL to the low-level voltage VL (ground level). This grounds node N1 via storage element 91. At this time, the voltage state in the SRAM circuit 70 is determined according to the resistance state of storage element 91.

[0190] Specifically, for example, as Figure 18CAs shown, when the resistance state of the storage element 91 is the high-resistance state RH, the node N1 is pulled down with a high resistance value. At this time, the current flowing from the transistor 73 of the inverter IV4 to the node N1 is greater than the current flowing from the node N1 to the control line CTRL via the transistor 31 and the storage element 91. Therefore, the voltage VN1 at the node N1 is set to the high-level voltage VH, and the voltage VN2 at the node N2 is set to the low-level voltage VL.

[0191] In addition, for example, as Figure 19C shown, when the resistance state of the storage element 91 is the low-resistance state RL, the node N1 is pulled down with a low resistance value. At this time, the current flowing from the transistor 73 of the inverter IV4 to the node N1 is less than the current flowing from the node N1 to the control line CTRL via the transistor 31 and the storage element 91. Therefore, the voltage VN1 at the node N1 is set to the low-level voltage VL, and the voltage VN2 at the node N2 is set to the high-level voltage VH.

[0192] In this way, in the semiconductor circuit 2, each memory cell 60 includes a storage element 91. Compared with the semiconductor circuit 1 according to the first embodiment, this makes it possible to reduce the number of elements in the semiconductor circuit 2, which makes it possible to reduce the area of the memory cell 60. Therefore, it is possible to reduce the area of the semiconductor circuit 2.

[0193] In addition, in the semiconductor circuit 2, the SRAM circuit 70 is configured to make the voltage VN1 at the node N1 easily set to the high-level voltage VH immediately after the power is turned on. Specifically, in the SRAM circuit 70, the gate width W73 of the transistor 73 in the inverter IV4 is greater than the gate width W71 of the transistor 71 in the inverter IV3 (W73 > W71), and the gate width W72 of the transistor 72 in the inverter IV3 is greater than the gate width W74 of the transistor 74 in the inverter IV4 (W72 > W74). In addition, in the SRAM circuit 70, when the resistance state of the storage element 91 is the high-resistance state RH ( Figure 18C ), the current flowing from the transistor 73 of the inverter IV4 to the node N1 is greater than the current flowing from the node N1 to the control line CTRL via the transistor 31 and the storage element 91, and when the resistance state of the storage element 91 is the low-resistance state RL ( Figure 19C ), the current flowing from the transistor 73 of the inverter IV4 to the node N1 is less than the current flowing from the node N1 to the control line CTRL via the transistor 31 and the storage element 91. This makes it possible to implement the recovery operation OP5 with one storage element 91 in the semiconductor circuit 3.

[0194] That is, in the semiconductor circuit 1 according to the first embodiment, for example, when the resistance state of the storage element 91 is the high-resistance state RH and the resistance state of the storage element 92 is the low-resistance state RL, in the recovery operation OP5, the node N2 is pulled down with a low resistance value, as Figure 6E shown. This causes the voltage VN2 at the node N2 to be set to the low-level voltage VL, and thus enables the voltage VN1 at the node N1 to be set to the high-level voltage VH. However, in the configuration where the transistors 35 to 38 and the storage element 92 are simply removed from the storage cell 30 in the semiconductor circuit 1, even if the recovery operation OP5 is intended to be performed, it is difficult to set the voltage VN1 at the node N1 to the high-level voltage VH.

[0195] Meanwhile, in the semiconductor circuit 2, the SRAM circuit 70 is configured to make it easy to set the voltage VN1 at the node N1 to the high-level voltage VH immediately after power-on. For example, as [[ shown, when the resistance state of the storage element 91 is the low-resistance state RL, this causes the voltage VN1 to be pulled down with a low resistance value, which causes the voltage VN1 to be set to the low-level voltage VL. Additionally, as ​ shown, when the resistance state of the storage element 91 is the high-resistance state RH, the node N1 is pulled down with a high resistance value, which causes the voltage VN1 to be set to the high-level voltage VH. That is, even when the node N1 is pulled down with a high resistance value, the voltage VN1 is not significantly affected but is set to the high-level voltage VH. This enables the recovery operation OP5 to be implemented with one storage element 91 in the semiconductor circuit 2.

[0196] As described above, in the present embodiment, each storage cell includes one storage element. This enables the area of the semiconductor circuit to be reduced.

[0197] In the present embodiment, the SRAM circuit is configured to make it easy to set the voltage at the node N1 to the high-level voltage immediately after power-on. This enables the recovery operation to be implemented with one storage element.

[0198] Other effects are similar to those of the above-described first embodiment.

[0199] [Modification Example 2-1]

[0200] In the above-described embodiment, the gate widths W of the transistors 71 to 74 in the inverters IV3 and IV4 are each set, but this is not restrictive. Instead, for example, the lengths L of the transistors 71 to 74 in the inverters IV3 and IV4 can be each set. Specifically, for example, the gate length L73 of the transistor 73 in the inverter IV4 can be less than the gate length L71 of the transistor 71 in the inverter IV3 (L73 < L71), and the gate length L72 of the transistor 72 in the inverter IV3 can be less than the gate length L74 of the transistor 74 in the inverter IV3 (L72 < L74). Even in such a case, the voltage VN1 at the node N1 can be easily set to the high-level voltage VH immediately after the power supply is turned on.

[0201] [Modification Example 2-2]

[0202] In the above-described embodiment, the gate width W73 of the transistor 73 in the inverter IV4 is greater than the gate width W71 of the transistor 71 in the inverter IV3 (W73 > W71), and the gate width W72 of the transistor 72 in the inverter IV3 is greater than the gate width W74 of the transistor 74 in the inverter IV4 (W72 > W74), but this is not restrictive. Instead, the gate widths W72 and W74 of the transistors 72 and 74 can be equal to each other, and the gate width W73 of the transistor 73 in the inverter IV4 can be greater than the gate width W71 of the transistor 71 in the inverter IV3 (W73 > W71). Additionally, for example, the gate widths W71 and W73 of the transistors 71 and 73 can be equal to each other, and the gate width W72 of the transistor 72 in the inverter IV3 can be greater than the gate width W74 of the transistor 74 in the inverter IV4 (W72 > W74). Even in such a case, the voltage VN1 at the node N1 can be easily set to the high-level voltage VH immediately after the power supply is turned on.

[0203] [Modification Example 2-3]

[0204] In the above-described embodiment, as ​ shown, current flows from the terminal T2 to the terminal T1 of the storage element 91, thereby setting the resistance state between the terminal T2 and the terminal T3 to the low-resistance state RL, but this is not restrictive. The semiconductor circuit 2A of this modification example will be described in detail below. The semiconductor circuit 2A includes a storage circuit 50A. The storage circuit 50A includes a storage cell array 51A. The storage cell array 51A includes a plurality of storage cells 60A.

[0205] ​Shows a configuration example of the storage unit 60A. The storage unit 60A includes an SRAM circuit 70, transistors 31 to 34, and a storage element 91A. In this storage unit 60A, the gate of the transistor 32 is coupled to the node N2. As ​ shown, in the storage element 91A, the resistance state between the terminal T2 and the terminal T3 is set to the high resistance state RH by a predetermined current flowing from the terminal T2 to the terminal T1, and the resistance state between the terminal T2 and the terminal T3 is set to the low resistance state RL by a predetermined current flowing from the terminal T1 to the terminal T2.

[0206] ​ and ​ 、 ​ and ​ each show the operation state of the storage unit 60A. ​ Shows the state in the initialization operation OP1. ​ Shows the state in the normal operation OP2. ​ Each shows the state when the voltage VN1 at the node N1 is the high-level voltage VH (VN1 = VH). ​ Shows the state in the storage operation OP3. ​ Shows the state in the standby operation OP4. ​ Shows the state in the recovery operation OP5. ​ Each shows the state when the voltage VN1 at the node N1 is the low-level voltage VL (VN1 = VL). ​ Shows the state in the storage operation OP3. ​ Shows the state in the standby operation OP4. ​ Shows the state in the recovery operation OP5.

[0207] In the initialization operation OP1, the controller 11 first sets the voltage of the power control signal SPG to the low level, as ​ shown. This turns on the power transistor 12 ( ​ ), and the storage unit 60A is supplied with the power supply voltage VDD. In addition, the driver 22 sets the voltage of the signal SBWL to the low level and sets the voltage of the signal SRESTOREL to the low level. As ​ shown, this turns off the transistors 31 and 34. As a result, the SRAM circuit 70 is electrically separated from the storage element 91A. In addition, as ​ shown, the driver 22 sets the voltage of the signal SRESETL to the high level within a predetermined period. As ​ shown, this turns on the transistor 33. In addition, as ​As shown, the driver 22 sets the voltage of the signal SCTRL to the high-level voltage VH (power supply voltage level) within a predetermined time period. As ​ shown, this causes the initialization current Iinit to flow sequentially through the control line CTRL, the storage element 91A, and the transistor 33. As a result, the resistance state of the storage element 91A is set to the high-resistance state RH.

[0208] The operation in the normal operation OP2 is similar to the operation in the above-described second embodiment ( ​ ). At this time, as ​ shown, the transistors 31, 33, and 34 are turned off. Therefore, no current flows through the storage element 91A, which causes the resistance state of the storage element 91A to be maintained at a predetermined resistance state (in this example, the high-resistance state).

[0209] In the storage operation OP3, the driver 22 sets the voltage of the signal SBWL to the high level within a predetermined time period, as ​ shown. This turns on the transistor 34, as ​ and ​ shown, and the drain of the transistor 32 is supplied with the power supply voltage VDD. Therefore, the resistance state of the storage element 91 is set according to the information stored in the SRAM circuit 70.

[0210] Specifically, for example, as ​ shown, when the voltage VN1 at the node N1 is the high-level voltage VH (VN1 = VH), the gate of the transistor 32 is supplied with the low-level voltage VL; therefore, no current flows through the storage element 91A. As a result, the resistance state of the storage element 91A is maintained at the high-resistance state RH.

[0211] In addition, for example, as Figure 23A shown, when the voltage VN1 at the node N1 is the low-level voltage VL (VN1 = VL), the gate of the transistor 32 is supplied with the high-level voltage VH, which causes the storage current Istore to flow sequentially through the transistor 34, the transistor 32, and the storage element 91A. As a result, the resistance state of the storage element 91A is set to the low-resistance state RL.

[0212] The standby operation OP4 is similar to the operation in the above-described second embodiment ( Figure 18B and Figure 19B ). At this time, as Figure 22B and Figure 23B shown, the resistance state of the storage element 91A is maintained.

[0213] In the recovery operation OP5, as Figure 5 shown, the controller 11 sets the voltage of the power control signal SPG to the low level. This turns on the power transistor 12 (Figure 1 ) is turned on, and the storage unit 60A is supplied with the power supply voltage VDD. Then, the driver 22 sets the voltage of the signal SRESTOREL to a high level only for a predetermined length of time immediately after the power transistor 12 is turned on. This turns on the transistor 31 during this time period, as shown in Figure 22C and Figure 23C . In addition, as shown in Figure 5 , the driver 22 sets the voltage of the signal SCTRL to the low level voltage VL (ground level). This causes the node N1 to be grounded via the storage element 91A. At this time, the voltage state in the SRAM circuit 70 is determined according to the resistance state of the storage element 91A.

[0214] Specifically, for example, as shown in Figure 22C , when the resistance state of the storage element 91A is the high resistance state RH, the node N1 is pulled down with a high resistance value. At this time, the current flowing from the transistor 73 of the inverter IV4 to the node N1 is greater than the current flowing from the node N1 to the control line CTRL via the transistor 31 and the storage element 91A. Therefore, the voltage VN1 at the node N1 is set to the high level voltage VH, and the voltage VN2 at the node N2 is set to the low level voltage VL.

[0215] In addition, for example, as shown in Figure 23C , when the resistance state of the storage element 91A is the low resistance state RL, the node N1 is pulled down with a low resistance value. At this time, in this example, the current flowing from the transistor 73 of the inverter IV4 to the node N1 is less than the current flowing from the node N1 to the control line CTRL via the transistor 31 and the storage element 91A. Therefore, the voltage VN1 at the node N1 is set to the low level voltage VL, and the voltage VN2 at the node N2 is set to the high level voltage VH.

[0216] [Modification Example 2 - 4]

[0217] Each modification example of the above - mentioned first embodiment can be applied to the semiconductor circuit 2 according to the above - mentioned embodiment.

[0218] <3. Third Embodiment>

[0219] Next, a description of the semiconductor circuit 3 according to the third embodiment is given. In this embodiment, the current path in the storage operation OP3 is configured to be different from the current path in the semiconductor circuit 1 according to the first embodiment. It should be noted that components that are substantially the same as those of the semiconductor circuit 1 according to the above - mentioned first embodiment are denoted by the same reference numerals, and their descriptions are appropriately omitted.

[0220] As shown in Figure 1As shown in the figure, the semiconductor circuit 3 includes a storage circuit 120. The storage circuit 120 includes a storage cell array 121 and drivers 122 and 23. The storage cell array 121 includes a plurality of storage cells 130.

[0221] Figure 24 A configuration example of the storage cell 130 in the storage cell array 121 is shown. Figure 25 A configuration example of the storage cell array 121 is shown. The storage cell array 121 includes a plurality of word lines AWL, a plurality of storage control lines STOREL, a plurality of bit lines BL, a plurality of bit lines BLB, a plurality of control lines CTRL, and a plurality of restore control lines RESTOREL. The storage control line STOREL extends in the Figure 24 and Figure 25 horizontal direction in the figure. One end of each storage control line STOREL is coupled to the driver 122. The driver 122 applies a signal SSTOREL to the storage control line STOREL.

[0222] The storage cell 130 includes an SRAM circuit 40, transistors 31, 35, 132, and 136, and storage elements 91 and 92.

[0223] The transistors 132 and 136 are N-type MOS transistors. The gate of the transistor 132 is coupled to the storage control line STOREL, the drain is coupled to the node N1, and the source is coupled to the terminal T1 of the storage element 91. The gate of the transistor 136 is coupled to the storage control line STOREL, the drain is coupled to the node N2, and the source is coupled to the terminal T1 of the storage element 92.

[0224] The terminal T1 of the storage element 91 is coupled to the source of the transistor 132, and the terminal T1 of the storage element 92 is coupled to the source of the transistor 136. In the storage elements 91 and 92, as Figure 4 shown in the figure, the resistance state between the terminal T2 and the terminal T3 is set to the low-resistance state RL by a predetermined current flowing from the terminal T2 to the terminal T1, and the resistance state between the terminal T2 and the terminal T3 is set to the high-resistance state RH by a predetermined current flowing from the terminal T1 to the terminal T2.

[0225] The driver 122 ( Figure 1 and Figure 25 ) is configured to apply a signal SAWL to the word line AWL, a signal SSTOREL to the storage control line STOREL, a signal SCTRL to the control line CTRL, and a signal SRESTORL to the restore control line RESTOREL based on the control signal supplied from the controller 11.

[0226] Here, the transistor 31 corresponds to a specific example of the "first transistor" in the present disclosure. The transistor 132 corresponds to a specific example of the "second transistor" in the present disclosure. The transistor 35 corresponds to a specific example of the "ninth transistor" in the present disclosure. The transistor 136 corresponds to a specific example of the "tenth transistor" in the present disclosure.

[0227] Figure 26 An operation example of a specific memory cell 130 of interest in the semiconductor circuit 3 is shown. Figures 27A to 27E Each shows an operation state of the memory cell 130. Figure 27A The state in the normal operation OP2 is shown. Figure 27B and Figure 27C Each shows the state in the storage operation OP3. Figure 27D The state in the standby operation OP4 is shown. Figure 27E The state in the recovery operation OP5 is shown.

[0228] (Normal operation OP2)

[0229] In the normal operation OP2, the driver 122 sets the voltage of the signal SSTOREL to a low level and sets the voltage of the signal SRESTOREL to a low level, as Figure 26 shown. As Figure 27A shown, this turns off the transistors 31, 35, 132, and 136. Additionally, as Figure 26 shown, the driver 122 sets the voltage of the signal SCTRL to a low voltage VL (ground level).

[0230] In this normal operation OP2, the semiconductor circuit 3 writes information to the SRAM circuit 40 of the memory cell 130 or reads information from the SRAM circuit 40. At this time, as Figure 27A shown, the transistors 31, 35, 132, and 136 are turned off. In this example, the resistance state of the storage element 91 is maintained at the low resistance state RL, and the resistance state of the storage element 92 is maintained at the high resistance state RH.

[0231] (Storage operation OP3)

[0232] In the storage operation OP3, the driver 122 sets the voltage of the signal SAWL to a low level, as Figure 26 shown. This turns off the transistors 45 and 46. Additionally, the driver 122 sets the voltage of the signal SSTOREL to a high level within a predetermined period, as Figure 26 shown. This turns on each of the transistors 132 and 136, as Figure 27B and Figure 27CAs shown. In the semiconductor circuit 3, the storage operation OP3 is separately executed in two operations OP31 and OP32.

[0233] First, in the operation OP31, the driver 122 sets the voltage of the signal SCTRL to the high-level voltage VH (power supply voltage level), as Figure 26 shown. This causes the storage current Istore1 to flow through one of the storage elements 91 and 92. In this example, the voltage VN1 at the node N1 is the high-level voltage VH, and the voltage VN2 at the node N2 is the low-level voltage VL. As Figure 27B shown, this causes the storage current Istore1 to sequentially flow through the storage element 92, the transistor 136, and the transistor 42 of the inverter IV1 in the storage cell 130. As a result, the resistance state of the storage element 92 is set to the low-resistance state RL.

[0234] Next, in the operation OP32, the driver 122 sets the voltage of the signal SCTRL to the low-level voltage VL (ground voltage level), as Figure 26 shown. This causes the storage current Istore2 to flow through the other of the storage elements 91 and 92. In this example, as Figure 27C shown, the storage current Istore2 sequentially flows through the transistor 43 of the inverter IV2, the transistor 132, and the storage element 91. As a result, the resistance state of the storage element 91 is set to the high-resistance state RH.

[0235] In this way, in the storage cell 130, the resistance state of each of the storage elements 91 and 92 is set according to the information stored in the SRAM circuit 40. It should be noted that in this example, the driver 122 sets the voltage of the signal SCTRL to the high-level voltage VH in the first operation OP31 and sets the voltage of the signal SCTRL to the low-level voltage VL in the next operation OP32, but this is not restrictive. Instead, for example, in the first operation OP31, the voltage of the signal SCTRL can be set to the low-level voltage VL, and in the next operation OP32, the voltage of the signal SCTRL can be set to the high-level voltage VH.

[0236] (Standby operation OP4)

[0237] In the standby operation OP4, as Figure 26 shown, the controller 11 sets the voltage of the power control signal SPG to the high level. This turns off the power transistor 12 ( Figure 1 ), and the power supply to the storage cell 130 is stopped. At this time, as Figure 27D shown, the resistance states of the storage elements 91 and 92 are maintained.

[0238] (Recovery operation OP5)

[0239] In the recovery operation OP5, as Figure 26 shown, the controller 11 sets the voltage of the power control signal SPG to a low level. This turns on the power transistor 12 ( Figure 1 ), and the storage unit 130 is supplied with the power supply voltage VDD. Then, the driver 122 sets the voltage of the signal SRESTOREL to a high level only for a predetermined length of time immediately after turning on the power transistor 12. As Figure 27E shown, this turns on each of the transistors 31 and 35 during this time period. Additionally, as Figure 26 shown, the driver 122 sets the voltage of the signal SCTRL to the low voltage VL (ground level). This causes the node N1 to be grounded via the storage element 91 and causes the node N2 to be grounded via the storage element 92. At this time, the resistance states of the storage elements 91 and 92 are different from each other; thus, the voltage in the SRAM circuit 40 is determined based on the resistance states of the storage elements 91 and 92.

[0240] In this example, as Figure 27E shown, the resistance state of the storage element 91 is the high resistance state RH, and the resistance state of the storage element 92 is the low resistance state RL. This causes the node N1 to be pulled down with a high resistance value and causes the node N2 to be pulled down with a low resistance value. Therefore, the voltage VN1 at the node N1 is set to the high voltage VH, and the voltage VN2 at the node N2 is set to the low voltage VL.

[0241] In this way, in the semiconductor circuit 3, the storage unit 130 is configured using the SRAM circuit 40, the storage elements 91 and 92, and the transistors 31, 35, 132, and 136, which allows for a reduction in the number of elements compared to the semiconductor circuit 1 according to the first embodiment. This allows for a reduction in the area of the storage unit 130, and thus the area of the semiconductor circuit 3 can be reduced.

[0242] Additionally, in the semiconductor circuit 3, the drain of the transistor 132 is coupled to the node N1, and the drain of the transistor 136 is coupled to the node N2. In the semiconductor circuit 3, then the storage operation OP3 is separately performed in two operations OP31 and OP32. This allows for setting the resistance state of each of the two storage elements 91 and 92 in this storage operation OP3. Therefore, this allows for omitting the initialization operation OP1 in the semiconductor circuit 3, which simplifies the operation.

[0243] As described above, in the present embodiment, the storage unit is configured using the SRAM circuit, the storage elements 91 and 92, and the transistors 31, 35, 132, and 136, which allows for a reduction in the area of the semiconductor circuit.

[0244] In this embodiment, the drain of transistor 132 is coupled to node N1, and the drain of transistor 136 is coupled to node N2, which enables simplified operation.

[0245] Other effects are similar to those of the first embodiment described above.

[0246] [Modification Example 3-1]

[0247] In the above embodiment, for example, as Figure 4 shown, current flows from terminal T2 to terminal T1 of storage element 91, thereby setting the resistance state between terminal T2 and terminal T3 to the low-resistance state RL, but this is not restrictive. The semiconductor circuit 3A according to this modification example is described in detail below. The semiconductor circuit 3A includes a storage circuit 120A. The storage circuit 120A includes a storage cell array 121A. The storage cell array 121A includes a plurality of storage cells 130A.

[0248] Figure 28 A configuration example of the storage cell 130A is shown. The storage cell 130A includes an SRAM circuit 40, transistors 31, 35, 132, and 136, and storage elements 91A and 92A. In this storage cell 130A, the drain of transistor 132 is coupled to node N2, and the gate of transistor 136 is coupled to node N1. As Figure 8 shown, in storage element 91A, the resistance state between terminal T2 and terminal T3 is set to the high-resistance state RH by a predetermined current flowing from terminal T2 to terminal T1, and the resistance state between terminal T2 and terminal T3 is set to the low-resistance state RL by a predetermined current flowing from terminal T1 to terminal T2. The same applies to storage element 92A.

[0249] Figures 29A to 29E Each shows an operating state of the storage cell 130A. Figure 29A The state in the normal operation OP2 is shown. Figure 29B and Figure 29C Each shows the state in the storage operation OP3. Figure 29D The state in the standby operation OP4 is shown. Figure 29E The state in the recovery operation OP5 is shown.

[0250] The operation in the normal operation OP2 is similar to the operation in the third embodiment above ( Figure 27A ). At this time, as Figure 29A shown, transistors 31, 35, 132, and 136 are turned off. In this example, the resistance state of storage element 91A is maintained at the low-resistance state RL, and the resistance state of storage element 92A is maintained at the high-resistance state RH.

[0251] In the storage operation OP3, the driver 122 sets the voltage of the signal SSTOREL to a high level within a predetermined period, as Figure 26 shown. This turns on each of the transistors 132 and 136, as Figure 29B and Figure 29C shown. In the semiconductor circuit 3A, the storage operation OP3 is separately executed in two operations OP31 and OP32.

[0252] First, in the operation OP31, the driver 122 sets the voltage of the signal SCTRL to a high level voltage VH (power supply voltage level), as Figure 26 shown. This causes a storage current Istore1 to flow through one of the storage elements 91A and 92A. In this example, the voltage VN1 at the node N1 is the high level voltage VH, and the voltage VN2 at the node N2 is the low level voltage VL. As Figure 29B shown, this causes the storage current Istore1 to sequentially flow through the storage element 91A, the transistor 132, and the transistor 42 of the inverter IV1 in the storage cell 130A. As a result, the resistance state of the storage element 91A is set to the high resistance state RH.

[0253] Next, in the operation OP32, the driver 122 sets the voltage of the signal SCTRL to a low level voltage VL (ground voltage level), as Figure 26 shown. This causes a storage current Istore2 to flow through the other of the storage elements 91A and 92A. In this example, as Figure 29C shown, the storage current Istore2 sequentially flows through the transistor 43 of the inverter IV2, the transistor 136, and the storage element 92A. As a result, the resistance state of the storage element 92A is set to the low resistance state RL.

[0254] The standby operation OP4 is similar to the operation in the above-described third embodiment ( Figure 27D ). At this time, as Figure 29D shown, the resistance states of the storage elements 91A and 92A are maintained.

[0255] In the recovery operation OP5, as Figure 26 shown, the controller 11 sets the voltage of the power control signal SPG to a low level. This turns on the power transistor 12 ( Figure 1 ), and the storage cell 130A is supplied with the power supply voltage VDD. Then, the driver 122 sets the voltage of the signal SRESTOREL to a high level only within a predetermined length of time immediately after turning on the power transistor 12. As Figure 29E shown, this turns on each of the transistors 31 and 35 within this period. Additionally, asFigure 26 As shown in Figure 26 , the driver 122 sets the voltage of the signal SCTRL to the low-level voltage VL (ground level). This causes the node N1 to be grounded via the storage element 91A and the node N2 to be grounded via the storage element 92A. At this time, the resistance states of the storage elements 91A and 92A are different from each other; therefore, the voltage in the SRAM circuit 40 is determined according to the resistance states of the storage elements 91A and 92A.

[0256] In this example, as Figure 29E shown in Figure 29E , the resistance state of the storage element 91A is the high-resistance state RH, and the resistance state of the storage element 92A is the low-resistance state RL. This causes the node N1 to be pulled down with a high resistance value and the node N2 to be pulled down with a low resistance value. Therefore, the voltage VN1 at the node N1 is set to the high-level voltage VH, and the voltage VN2 at the node N2 is set to the low-level voltage VL.

[0257] [Modification Example 3-2]

[0258] Each modification example of the above first embodiment can be applied to the semiconductor circuit 3 according to the above embodiment.

[0259] <4. Application Examples and Applicable Examples>

[0260] Next, descriptions of application examples of the technologies described in the above embodiments and modification examples and applicable examples of the technologies described in the above embodiments and modification examples in electronic devices are given.

[0261] (Application Example)

[0262] In the above embodiment, the present technology is applied to the SRAM circuit, but this is not restrictive. For example, the present technology can be applied to Figures 30A to 30D the flip-flop circuits 101 to 104 shown in Figures 30A to 30D . The flip-flop circuit 101 is a so-called master-slave D-type flip-flop circuit including a master latch circuit 101M and a slave latch circuit 101S. The same applies to the flip-flop circuits 102 to 104.

[0263] Figure 31 A configuration example of a flip-flop circuit 201 according to this application example is shown. The flip-flop circuit 201 is Figure 30AThe flip-flop circuit 101 shown in [figure reference], in which the technology according to the above-described embodiment is applied. The flip-flop circuit 201 includes a master latch circuit 101M and a slave latch circuit 201S. The technology according to the above-described first embodiment is applied to the slave latch circuit 201S. The slave latch circuit 201S includes inverters IV5 and IV6, a transmission gate TG, a switch 99, transistors 31 to 38, and storage elements 91 and 92. The input terminal of inverter IV5 is coupled to node N1 and the output terminal is coupled to node N2. The input terminal of inverter IV6 is coupled to node N2 and the output terminal is coupled to one end of the transmission gate TG and one end of the switch 99. One end of the transmission gate TG is coupled to the output terminal of inverter IV6 and one end of the switch 99, and the other end is coupled to node N1. One end of the switch 99 is coupled to the output terminal of inverter IV6 and one end of the transmission gate TG, and the other end is coupled to node N1. The switch 99 is turned off when performing the normal operation OP2, and is turned on when performing the initialization operation OP1, the storage operation OP3, and the recovery operation OP5.

[0264] It should be noted that, in this example, the technology according to the above-described embodiment is applied to the slave latch circuit, but this is not restrictive. Instead, for example, the technology according to the above-described embodiment can be applied to the master latch circuit.

[0265] (Applicable examples of electronic devices)

[0266] Figure 32 The appearance of a smart phone in which a semiconductor circuit according to any of the above embodiments or the like is applied is shown. The smart phone includes, for example, a main body 310, a display section 320, and a battery 330.

[0267] The semiconductor circuit according to any of the above embodiments or the like is applicable not only to such a smart phone but also to electronic devices in various fields, such as digital cameras, notebook personal computers, portable game machines, and video cameras. This technology is particularly effective when applied to portable electronic devices including a battery. This makes it possible to reduce power consumption in the electronic device.

[0268] Although the present technology has been described above with reference to some embodiments and modification examples and their specific application examples and applicable examples of electronic devices, the present technology is not limited to these embodiments or the like and can be modified in various ways.

[0269] For example, in the above application example, the present technology is applied to a D-type flip-flop circuit, but it is not limited thereto. For example, the present technology can be applied to other flip-flop circuits or can be applied to latch circuits.

[0270] Note that the effects described in this specification are illustrative rather than restrictive, and other effects may be provided.

[0271] Note that the present technology may have the following configurations. With the present technology according to the following configurations, durability can be enhanced.

[0272] (1) A semiconductor circuit, comprising:

[0273] A first circuit configured to generate an inverted voltage of a voltage at a first node and apply the inverted voltage to a second node;

[0274] A second circuit configured to generate an inverted voltage of the voltage at the second node and apply the inverted voltage to the first node;

[0275] A first storage element having a first terminal, a second terminal, and a third terminal, and configured to be able to store information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to a direction of a first current flowing between the first terminal and the second terminal;

[0276] A first transistor configured to be able to couple the first node to the third terminal of the first storage element by being turned on; and

[0277] A second transistor capable of being coupled to a first coupling node and configured to be able to cause the first current to flow to the second terminal of the first storage element based on a voltage at the first coupling node, the first coupling node being one of the first node and the second node.

[0278] (2) The semiconductor circuit according to (1), further comprising: a third transistor configured to be able to supply a first voltage to the first terminal of the first storage element by being turned on, wherein

[0279] The second transistor has a drain, a gate coupled to the first coupling node, and a source coupled to the first terminal of the first storage element.

[0280] (3) The semiconductor circuit according to (2), further comprising: a fourth transistor configured to be able to supply a second voltage different from the first voltage to the drain of the second transistor by being turned on.

[0281] (4) The semiconductor circuit according to (3), further comprising: a controller configured to be able to control operations of the first transistor, the third transistor, and the fourth transistor, wherein

[0282] The controller is configured to turn on the fourth transistor and turn off the first transistor and the third transistor within a first period, thereby setting the resistance state of the first storage element to a resistance state corresponding to the voltage at the first coupling node.

[0283] (5) The semiconductor circuit according to (4), wherein the controller is configured to be able to turn on the first transistor and turn off the third transistor and the fourth transistor within a second period after the first period, thereby setting the voltage at the first node to a voltage corresponding to the resistance state of the first storage element.

[0284] (6) The semiconductor circuit according to (5), further comprising: a power supply transistor that supplies power to the first circuit and the second circuit by being turned on, wherein

[0285] the controller is configured to be able to turn off the power supply transistor within a third period between the first period and the second period.

[0286] (7) The semiconductor circuit according to any one of (4) to (6), wherein the controller is configured to be able to turn on the third transistor and turn off the first transistor and the fourth transistor within a fourth period before the first period, thereby setting the resistance state of the first storage element to the first resistance state.

[0287] (8) The semiconductor circuit according to any one of (1) to (7), wherein the first circuit and the second circuit are configured to make the voltage at the first node easy to be set to a predetermined initial voltage after power is turned on.

[0288] (9) The semiconductor circuit according to (8), wherein

[0289] the first circuit includes a fifth transistor that couples a first power supply and the second node to each other by being turned on, the first power supply corresponding to the initial voltage, and

[0290] the second circuit includes a sixth transistor that couples the first power supply and the first node to each other by being turned on, the gate width of the sixth transistor being greater than the gate width of the fifth transistor.

[0291] (10) The semiconductor circuit according to (8) or (9), wherein

[0292] the second circuit includes a seventh transistor that couples a second power supply and the first node to each other by being turned on, the second power supply corresponding to a voltage different from the initial voltage, and

[0293] The first circuit includes an eighth transistor that couples the second power supply and the second node to each other when turned on, and the gate width of the eighth transistor is greater than the gate width of the seventh transistor.

[0294] (11) The semiconductor circuit according to any one of (8) to (10), wherein

[0295] The first circuit includes a fifth transistor that couples a first power supply, corresponding to the initial voltage, and the second node to each other when turned on, and

[0296] The second circuit includes a sixth transistor that couples the first power supply and the first node to each other when turned on, and the gate length of the sixth transistor is less than the gate length of the fifth transistor.

[0297] (12) The semiconductor circuit according to any one of (8) to (11), wherein

[0298] The second circuit includes a seventh transistor that couples a second power supply, corresponding to a voltage different from the initial voltage, and the first node to each other when turned on, and

[0299] The first circuit includes an eighth transistor that couples the second power supply and the second node to each other when turned on, and the gate length of the eighth transistor is less than the gate length of the seventh transistor.

[0300] (13) The semiconductor circuit according to any one of (8) to (12), wherein

[0301] The second circuit includes a sixth transistor that couples a first power supply, corresponding to the initial voltage, and the first node to each other when turned on, and

[0302] The current value of the current flowing from the first power supply to the first node when the sixth transistor is turned on is a current value between a first current value and a second current value. The first current value is the current flowing from the first node to the first storage element via the first transistor when the first transistor is turned on and the resistance state of the first storage element is the first resistance state. The second current value is the current flowing from the first node to the first storage element via the first transistor when the first transistor is turned on and the resistance state of the first storage element is the second resistance state.

[0303] (14) The semiconductor circuit according to (2) further includes:

[0304] A second storage element having a first terminal, a second terminal, and a third terminal, and configured to be able to store information by setting the resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to the direction of a second current flowing between the first terminal and the second terminal;

[0305] A ninth transistor configured to be able to couple the second node to the third terminal of the second storage element by being turned on;

[0306] A tenth transistor coupled to a second coupling node and configured to be able to cause the second current to flow to the second terminal of the second storage element based on the voltage at the second coupling node, the second coupling node being a node different from the first coupling node among the first node and the second node; and

[0307] An eleventh transistor configured to be able to supply the first voltage to the first terminal of the second storage element by being turned on, where

[0308] The tenth transistor has a drain, a gate coupled to the second coupling node, and a source coupled to the first terminal of the second storage element.

[0309] (15) The semiconductor circuit according to (14) further includes:

[0310] A fourth transistor configured to be able to supply a second voltage different from the first voltage to the drain of the second transistor by being turned on; and

[0311] A twelfth transistor configured to be able to supply the second voltage to the drain of the tenth transistor by being turned on.

[0312] (16) The semiconductor circuit according to (1) further includes:

[0313] A second storage element having a first terminal, a second terminal, and a third terminal, and configured to be able to store information by setting the resistance state between the second terminal and the third terminal to the first resistance state or the second resistance state according to the direction of a second current flowing between the first terminal and the second terminal;

[0314] A ninth transistor configured to be able to couple the second node to the third terminal of the second storage element by being turned on; and

[0315] A tenth transistor, capable of being coupled to a second coupling node, and configured to enable the second current to flow to a second terminal of the second storage element based on a voltage at the second coupling node, the second coupling node being a node different from the first coupling node among the first node and the second node, wherein

[0316] the second transistor has a drain coupled to the first coupling node, a gate, and a source coupled to a first terminal of the first storage element, and

[0317] the tenth transistor has a drain coupled to the second coupling node, a gate, and a source coupled to a first terminal of the second storage element.

[0318] (17) The semiconductor circuit according to (16), further comprising a controller configured to control operations of the first transistor, the second transistor, the ninth transistor, and the tenth transistor, and configured to apply a control voltage to a second terminal of the first storage element and a second terminal of the second storage element, wherein

[0319] the controller is configured to turn on the second transistor and the tenth transistor and turn off the first transistor and the ninth transistor during a first period, and set the control voltage to a third voltage and a fourth voltage in a time-division manner, so as to set a resistance state of the first storage element to a resistance state corresponding to a voltage at the first coupling node, and set a resistance state of the second storage element to a resistance state corresponding to a voltage at the second coupling node.

[0320] (18) The semiconductor circuit according to (17), wherein the controller is configured to turn on the first transistor and the ninth transistor and turn off the second transistor and the tenth transistor during a second period after the first period, so as to set a voltage at the first node to a voltage corresponding to a resistance state of the first storage element, and set a voltage at the second node to a voltage corresponding to a resistance state of the second storage element.

[0321] (19) The semiconductor circuit according to (1), wherein the first storage element is configured to store information by changing a resistance state by using spin orbit torque.

[0322] (20) The semiconductor circuit according to any one of (1) to (19), wherein the first circuit and the second circuit constitute a SRAM circuit.

[0323] (21) The semiconductor circuit according to any one of (1) to (19), wherein the first circuit and the second circuit constitute a latch circuit.

[0324] (22) The semiconductor circuit according to (21), wherein the latch circuit is a slave latch circuit in a flip-flop circuit having a master latch circuit and a slave latch circuit.

[0325] (23) An electronic device, comprising:

[0326] a semiconductor circuit; and

[0327] a battery that supplies a power supply voltage to the semiconductor circuit,

[0328] wherein the semiconductor circuit includes

[0329] a first circuit configured to be able to generate an inverted voltage of a voltage at a first node and apply the inverted voltage to a second node,

[0330] a second circuit configured to be able to generate an inverted voltage of the voltage at the second node and apply the inverted voltage to the first node,

[0331] a first storage element having a first terminal, a second terminal, and a third terminal, and configured to be able to store information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to a direction of a first current flowing between the first terminal and the second terminal,

[0332] a first transistor configured to be able to couple the first node to the third terminal of the first storage element by being turned on, and

[0333] a second transistor capable of being coupled to a first coupling node and configured to be able to cause the first current to flow to the second terminal of the first storage element based on a voltage at the first coupling node, the first coupling node being one of the first node and the second node.

[0334] This application claims the priority of Japanese Priority Patent Application JP2018-158366 filed with the Japan Patent Office on August 27, 2018, the entire contents of which are incorporated herein by reference.

[0335] Those skilled in the art should understand that various modifications, combinations, sub-combinations, and changes can be made depending on design requirements and other factors, as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A semiconductor circuit, comprising: a first circuit configured to generate an inverted voltage of a voltage at a first node and apply the inverted voltage to a second node; a second circuit configured to generate an inverted voltage of the voltage at the second node and apply the inverted voltage to the first node; a first storage element having a first terminal, a second terminal, and a third terminal, including a magnetoresistive element and configured to be able to store information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to a direction of a first current flowing between the first terminal and the second terminal. In the first storage element, the first current does not directly pass through the magnetoresistive element but through a wiring adjacent to the magnetoresistive element, which enables setting a state of a resistance value in the magnetoresistive element, and no current flows between the first terminal and the third terminal and between the second terminal and the third terminal, and the current does not pass through the magnetoresistive element itself; a first transistor configured to be able to couple the first node to the third terminal of the first storage element by being turned on; and a second transistor capable of being coupled to a first coupling node and configured to be able to cause the first current to flow to the second terminal of the first storage element based on a voltage at the first coupling node, the first coupling node being one of the first node and the second node.

2. The semiconductor circuit according to claim 1, further comprising: a third transistor configured to be able to supply a first voltage to the first terminal of the first storage element by being turned on, where the second transistor has a drain, a gate coupled to the first coupling node, and a source coupled to the first terminal of the first storage element.

3. The semiconductor circuit according to claim 2, further comprising: a fourth transistor configured to supply a second voltage different from the first voltage to the drain of the second transistor by being able to be turned on.

4. The semiconductor circuit according to claim 3, further comprising: a controller configured to be able to control operations of the first transistor, the third transistor, and the fourth transistor, where the controller is configured to turn on the fourth transistor and turn off the first transistor and the third transistor during a first period, thereby setting a resistance state of the first storage element to a resistance state corresponding to a voltage at the first coupling node.

5. The semiconductor circuit according to claim 4, wherein, the controller is configured to be able to turn on the first transistor and turn off the third transistor and the fourth transistor during a second period after the first period, thereby setting a voltage at the first node to a voltage corresponding to a resistance state of the first storage element.

6. The semiconductor circuit according to claim 5, further comprising: A power transistor that supplies power to the first circuit and the second circuit when turned on, wherein the controller is configured to be able to turn off the power transistor during a third period between the first period and the second period.

7. The semiconductor circuit according to claim 4, wherein, the controller is configured to be able to turn on the third transistor and turn off the first transistor and the fourth transistor during a fourth period before the first period, so as to set the resistance state of the first storage element to the first resistance state.

8. The semiconductor circuit according to claim 1, wherein, the first circuit and the second circuit are configured to make the voltage at the first node easy to be set to a predetermined initial voltage after power-on.

9. The semiconductor circuit according to claim 8, wherein the first circuit includes a fifth transistor that couples a first power supply and the second node to each other when turned on, the first power supply corresponding to the initial voltage, and the second circuit includes a sixth transistor that couples the first power supply and the first node to each other when turned on, the gate width of the sixth transistor being greater than the gate width of the fifth transistor.

10. The semiconductor circuit according to claim 8, wherein the second circuit includes a seventh transistor that couples a second power supply and the first node to each other when turned on, the second power supply corresponding to a voltage different from the initial voltage, and the first circuit includes an eighth transistor that couples the second power supply and the second node to each other when turned on, the gate width of the eighth transistor being greater than the gate width of the seventh transistor.

11. The semiconductor circuit according to claim 8, wherein the first circuit includes a fifth transistor that couples a first power supply and the second node to each other when turned on, the first power supply corresponding to the initial voltage, and the second circuit includes a sixth transistor that couples the first power supply and the first node to each other when turned on, the gate length of the sixth transistor being less than the gate length of the fifth transistor.

12. The semiconductor circuit according to claim 8, wherein the second circuit includes a seventh transistor that couples a second power supply and the first node to each other when turned on, the second power supply corresponding to a voltage different from the initial voltage, and the first circuit includes an eighth transistor that couples the second power supply and the second node to each other when turned on, the gate length of the eighth transistor being less than the gate length of the seventh transistor.

13. The semiconductor circuit according to claim 8, wherein the second circuit includes a sixth transistor that couples a first power supply and the first node to each other when turned on, the first power supply corresponding to the initial voltage, and When the sixth transistor is turned on, the current value of the current flowing from the first power supply to the first node is a current value between a first current value and a second current value. The first current value is the current flowing from the first node to the first storage element via the first transistor when the first transistor is turned on and the resistance state of the first storage element is the first resistance state. The second current value is the current flowing from the first node to the first storage element via the first transistor when the first transistor is turned on and the resistance state of the first storage element is the second resistance state.

14. The semiconductor circuit according to claim 2, further comprising: A second storage element having a first terminal, a second terminal, and a third terminal, and configured to be able to store information by setting the resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to the direction of a second current flowing between the first terminal and the second terminal; A ninth transistor configured to be able to couple the second node to the third terminal of the second storage element by being turned on; A tenth transistor coupled to a second coupling node and configured to be able to cause the second current to flow to the second terminal of the second storage element based on the voltage at the second coupling node. The second coupling node is a node different from the first coupling node among the first node and the second node; and An eleventh transistor configured to be able to supply the first voltage to the first terminal of the second storage element by being turned on, where the tenth transistor has a drain, a gate coupled to the second coupling node, and a source coupled to the first terminal of the second storage element.

15. The semiconductor circuit according to claim 14, further comprising: A fourth transistor configured to be able to supply a second voltage different from the first voltage to the drain of the second transistor by being turned on; and A twelfth transistor configured to be able to supply the second voltage to the drain of the tenth transistor by being turned on.

16. The semiconductor circuit according to claim 1, further comprising: A second storage element having a first terminal, a second terminal, and a third terminal, and configured to be able to store information by setting the resistance state between the second terminal and the third terminal to the first resistance state or the second resistance state according to the direction of a second current flowing between the first terminal and the second terminal; A ninth transistor configured to be able to couple the second node to the third terminal of the second storage element by being turned on; and A tenth transistor capable of being coupled to a second coupling node and configured to be able to cause the second current to flow to the second terminal of the second storage element based on the voltage at the second coupling node. The second coupling node is a node different from the first coupling node among the first node and the second node, where the second transistor has a drain, a gate coupled to the first coupling node, and a source coupled to the first terminal of the first storage element, and The tenth transistor has a drain coupled to the second coupling node, a gate, and a source coupled to the first terminal of the second storage element.

17. The semiconductor circuit according to claim 16, further comprising a controller configured to control the operations of the first transistor, the second transistor, the ninth transistor, and the tenth transistor, and configured to apply a control voltage to the second terminal of the first storage element and the second terminal of the second storage element, wherein the controller is configured to turn on the second transistor and the tenth transistor and turn off the first transistor and the ninth transistor during a first period, and set the control voltage to a third voltage and a fourth voltage in a time-division manner, so as to set the resistance state of the first storage element to a resistance state corresponding to the voltage at the first coupling node, and set the resistance state of the second storage element to a resistance state corresponding to the voltage at the second coupling node.

18. The semiconductor circuit according to claim 17, wherein, the controller is configured to turn on the first transistor and the ninth transistor and turn off the second transistor and the tenth transistor during a second period after the first period, so as to set the voltage at the first node to a voltage corresponding to the resistance state of the first storage element, and set the voltage at the second node to a voltage corresponding to the resistance state of the second storage element.

19. The semiconductor circuit according to claim 1, wherein, the first storage element is configured to store information by changing its resistance state using spin orbit torque.

20. The semiconductor circuit according to claim 1, wherein, the first circuit and the second circuit form a SRAM circuit.

21. The semiconductor circuit according to claim 1, wherein, the first circuit and the second circuit form a latch circuit.

22. The semiconductor circuit according to claim 21, wherein, the latch circuit is the slave latch circuit in a flip-flop circuit having a master latch circuit and a slave latch circuit.

23. An electronic device, comprising: a semiconductor circuit; and a battery for supplying a power supply voltage to the semiconductor circuit, the semiconductor circuit includes a first circuit configured to generate an inverted voltage of the voltage at a first node and apply the inverted voltage to a second node, a second circuit configured to generate an inverted voltage of the voltage at the second node and apply the inverted voltage to the first node, A first storage element having a first terminal, a second terminal, and a third terminal, including a magnetoresistive element and configured to be able to store information by setting a resistance state between the second terminal and the third terminal to a first resistance state or a second resistance state according to a direction of a first current flowing between the first terminal and the second terminal. In the first storage element, the first current does not directly pass through the magnetoresistive element but passes through a wiring adjacent to the magnetoresistive element, which enables setting a state of a resistance value in the magnetoresistive element, and no current flows between the first terminal and the third terminal and between the second terminal and the third terminal, and the current does not pass through the magnetoresistive element itself; A first transistor configured to be able to couple the first node to the third terminal of the first storage element by being turned on, and A second transistor capable of being coupled to a first coupling node and configured to be able to cause the first current to flow to the second terminal of the first storage element based on a voltage at the first coupling node, the first coupling node being one of the first node and the second node.

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