Method for manufacturing an integrated circuit device

Abstract

To fabricate an integrated circuit device, a feature layer is formed on a substrate in a first region for forming a plurality of chips and in a second region surrounding the first region. The feature layer has a step-difference portion in the second region. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on one another is formed. In the first region and the second region, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. The photoresist layer in the first region is exposed and developed by using the step-difference portion in the second region as an alignment mark to form a photoresist pattern.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0121726, filed with the Korean Intellectual Property Office on October 1, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a method of manufacturing an integrated circuit device, and more particularly, to a method of manufacturing an integrated circuit device capable of reducing process defects caused by rework in a lithography process of a manufacturing process of the integrated circuit device. Background Art

[0004] Recently, as the size reduction of integrated circuit devices has been rapidly progressing, the feature sizes of integrated circuit devices have been refined, and the line widths of each of the patterns forming the integrated circuit device have been gradually reduced. Accordingly, when forming patterns having various shapes, sizes, and densities for an integrated circuit device simultaneously, the process difficulty increases. Specifically, when performing a rework process for removing a photoresist pattern and forming a new photoresist pattern due to a defect in the photoresist pattern obtained after performing a lithography process for manufacturing an integrated circuit device, it is necessary to develop such a rework process in which the underlying structure, etch layer, or hard mask layer remaining on the substrate is not damaged by the rework atmosphere and the rework process can be stably performed. Summary of the Invention

[0005] The present inventive concept provides a method of manufacturing an integrated circuit device, which can improve the reliability of the integrated circuit device formed by stably performing a rework process, in which, although a rework process for removing a photoresist pattern and forming a new photoresist pattern is performed due to a defect in the photoresist pattern obtained after performing a lithography process for manufacturing an integrated circuit device, the underlying structure, etch layer, or hard mask remaining on the substrate is not damaged by the rework atmosphere.

[0006] According to an aspect of the inventive concept, a method of manufacturing an integrated circuit device is provided. In the method, a feature layer is formed on a substrate in a first region for forming a plurality of chips and a second region surrounding the first region, the feature layer having a flat upper surface in the first region and a stepped portion in the second region. In the first and second regions, a hard mask structure including a plurality of hard mask layers is formed on the feature layer. In the first and second regions, a protective layer is formed to cover the hard mask structure such that the hard mask structure is not exposed. In the first and second regions, a photoresist layer is formed on the protective layer. The photoresist layer in the first region is exposed and developed by using the stepped portion in the second region as an alignment mark to form a photoresist pattern. The protective layer and the hard mask structure are etched by using the photoresist pattern in the first region as an etch mask.

[0007] According to an aspect of the inventive concept, a method of manufacturing an integrated circuit device is provided. In the method, a first sub-structure covering the substrate in a cell array region and a second sub-structure covering the substrate in a scribe line region are formed on the substrate. A conductive layer covering the first and second sub-structures and having a stepped portion in the scribe line region is formed. A hard mask structure including a plurality of hard mask layers is formed on the conductive layer in the cell array region and the scribe line region. A protective layer covering the hard mask structure is formed such that the hard mask structure is not exposed in the cell array region and the scribe line region. A photoresist layer is formed on the protective layer in the cell array region and the scribe line region. The photoresist layer in the cell array region is exposed and developed by using the stepped portion in the scribe line region as an alignment mark to form a photoresist pattern. The protective layer and the hard mask structure are etched by using the photoresist pattern in the cell array region as an etch mask.

[0008] According to an aspect of the inventive concept, a method of manufacturing an integrated circuit device is provided. In the method, a first lower structure including a plurality of bit lines each including a metal layer is formed on a substrate in a cell array region, and a second lower structure is formed on the substrate in a scribe region, the second lower structure including trenches in its upper surface. A conductive layer is formed to cover the first lower structure and the second lower structure and having a step difference portion around the trenches in the scribe region. A hard mask structure including an amorphous silicon layer is formed on the conductive layer in the cell array region and the scribe region. A protective layer is formed to cover the hard mask structure such that the amorphous silicon layer is not exposed in the cell array region and the scribe region. A photoresist layer is formed on the protective layer in the cell array region. The photoresist layer in the cell array region is exposed and developed by using the step difference portion in the scribe region as an alignment mark to form a photoresist pattern. The photoresist pattern is inspected. When it is determined in the step of inspecting the photoresist pattern that the photoresist pattern is defective, the photoresist pattern is removed in an oxygen-containing atmosphere in a state where the protective layer covers the hard mask structure, and the steps of forming the photoresist layer and forming the photoresist pattern are performed again. By transcribing the shape of the photoresist pattern onto the conductive layer in the cell array region, a plurality of landing pads formed of a plurality of island patterns are formed of the conductive layer, the plurality of island patterns being spaced apart from each other and regularly arranged. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic plan view showing an exemplary configuration of an integrated circuit device that can be obtained by a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept;

[0011] Figure 2A is a view showing a plurality of island patterns that can be implemented in a plurality of chip regions of an integrated circuit device that can be obtained by a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. In Figure 2A wherein, (a) is a perspective view showing some parts of a plurality of chip regions, and (b) is a plan view showing a planar arrangement of the plurality of island patterns shown in (a);

[0012] Figure 2B is a plan view showing a configuration of a part of a scribe region of an integrated circuit device that can be obtained by a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept;

[0013] Figures 3A to 3H is a cross-sectional view showing a process of a method of sequentially manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept;

[0014] Figures 4A to 4C is a cross-sectional view of a process of a method of sequentially manufacturing an integrated circuit device according to other exemplary embodiments of the inventive concept;

[0015] Figure 5 is a block diagram showing another exemplary configuration of an integrated circuit device, which can be obtained by a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept;

[0016] Figure 6 shows Figure 5 a plan view of an exemplary layout configuration of an integrated circuit device of

[0017] Figure 7 shows Figure 6 a schematic plan layout of a main configuration of a cell array region of

[0018] Figure 8A and Figure 8B are cross-sectional views showing a cross-sectional configuration of a partial region of a cell array region included in an integrated circuit device, which can be obtained by a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept;

[0019] Figures 9A to 9E is a cross-sectional view of a process of a method of sequentially manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept; and

[0020] Figures 10A to 10J is a cross-sectional view of a process of forming a first lower structure and a conductive layer in a cell array region in a method of sequentially manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. Detailed Description

[0021] Hereinafter, various exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals always denote like elements.

[0022] Figure 1 is a schematic plan view of an integrated circuit device 100, which can be obtained by a method of manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept.

[0023] Referring to Figure 1 , the integrated circuit device 100 includes a substrate 110 having a plurality of chip regions CR and a scribe line region SLR surrounding the plurality of chip regions CR. On the substrate 110, the plurality of chip regions CR may be arranged in a matrix. The scribe line region SLR may include a dicing region for individuating the plurality of chip regions CR.

[0024] The plurality of chip regions CR can be high-density regions each having a high pattern density, and the scribing lane region SLR can be a low-density region having a low pattern density. Each of the plurality of chip regions CR can include a cell array region of a semiconductor memory device and a peripheral circuit region and a core region including circuits that can be electrically connected to a cell array included in the cell array region. In an exemplary embodiment, in the cell array region, a volatile memory cell array (such as a dynamic random access memory (DRAM)) or a non-volatile memory cell array (such as a flash memory) can be formed. In the cell array region, a plurality of patterns each having a small width can be spaced apart from each other, can be regularly arranged in the X direction or the Y direction perpendicular to the X direction, and can be repeatedly formed with a small pitch.

[0025] Referring to Figure 1 , the integrated circuit device 100 can be a semiconductor wafer 102. The semiconductor wafer 102 can include a substrate 110 having a plurality of chip regions CR and scribing lane regions SLR. Each of the plurality of chip regions CR can have a corresponding semiconductor device formed therein, which can form a corresponding semiconductor chip when separated from the semiconductor wafer 102. The plurality of semiconductor devices can be two-dimensionally arranged with respect to a top view of the semiconductor wafer 102. The integrated circuit device 100 can thus include the plurality of semiconductor devices. The plurality of semiconductor devices can include integrated circuits formed by an integrated circuit device manufacturing process. The plurality of semiconductor devices can be integrally formed together with the scribing lane regions SLR. The plurality of semiconductor devices of the integrated circuit device 100 can be semiconductor memory devices such as the integrated circuit device 200 described herein.

[0026] The scribing lane region SLR can be formed by a plurality of straight scribing lines extending in directions perpendicular to each other to form a grid (wherein the chip regions CR form the grid elements of the grid). Each of the chip regions CR can be surrounded by the scribing lane region SLR. The scribing lines of the scribing lane region SLR can indicate positions where the semiconductor wafer 102 can be cut (after semiconductor devices are formed in the chip regions CR) to separate the resulting semiconductor devices from each other (to form semiconductor chips corresponding to the semiconductor devices formed in the chip regions CR). In some examples, the scribing lane region SLR may not form circuits (such as no transistors) required to operate the resulting semiconductor devices formed in the chip regions CR. For example, metal patterns formed in the scribing lane region SLR can be electrically floating and / or not connected to the semiconductor devices formed in the chip regions CR.

[0027] Figure 2A is a diagram showing a plurality of island patterns PA that can be implemented in a chip region CR of an integrated circuit device 100 according to an example embodiment. In Figure 1 the integrated circuit device 100. Figure 2AIn (a), a perspective view shows some parts of the chip region CR, and in (b), a plan view shows the planar arrangement of the plurality of island patterns PA shown in (a).

[0028] Referring Figure 2A , in the integrated circuit device 100, in the chip region CR, it may include a lower structure 120 formed on a substrate 110 and a plurality of island patterns PA formed on the lower structure 120.

[0029] The substrate 110 may include a semiconductor element (such as silicon (Si) or germanium (Ge)) or a compound semiconductor (such as SiC, GaAs, InAs, or InP). The lower structure 120 may include an insulating layer, a conductive layer, or a combination of the above layers. For example, the lower structure 120 may include a structure including at least one conductive region. The conductive region may be formed of a doped structure, a doped semiconductor layer, a metal layer, or a combination of the above structures and layers. The lower structure 120 may include, for example, conductive regions of a wiring layer, a contact plug, and a transistor, and an insulating layer that insulates the wiring layer, the contact plug, and the transistor from each other.

[0030] The plurality of island patterns PA may be repeatedly arranged on the lower structure 120 in a horizontal direction (e.g., the X direction) at a first pitch P1 in the chip region CR. Each of the plurality of island patterns PA may have a cylindrical cross-section.

[0031] Each of the plurality of island patterns PA may include an insulating pattern, a conductive pattern, or a combination of the above patterns. In an exemplary embodiment, each of the plurality of island patterns PA may be formed of a doped semiconductor, a metal, a conductive metal nitride, or a combination of the above materials. Each of the plurality of island patterns PA may have a single-layer structure or a multi-layer structure.

[0032] In Figure 2A , the plurality of island patterns PA are shown spaced apart from each other and regularly arranged in the X direction or the Y direction to have a honeycomb structure in the plane. However, the inventive concept is not limited thereto. For example, the plurality of island patterns PA may be arranged in a matrix in the plane.

[0033] Figure 2B is a plan view showing the configuration of a part of the scribe line region SLR of the integrated circuit device 100 Figure 1 .

[0034] Referring Figure 2B , in the scribe line region SLR, a plurality of alignment marks AK may be formed. Each of the plurality of alignment marks AK may include a plurality of step difference portions ST indicating a plurality of recessed regions RR.

[0035] Figures 3A to 3His a cross-sectional view of a process of a method of sequentially manufacturing an integrated circuit device according to an exemplary embodiment of the inventive concept. Referring to Figures 3A to 3H , a method of forming the plurality of island patterns PA and alignment marks AK included in the integrated circuit device 100 shown in Figure 2A and Figure 2B will be described. In Figures 3A to 3H , cross-sections of regions taken along line X1-X1' of (b) in Figure 2A and line X2-X2' of Figure 2B are shown in process order.

[0036] Referring to Figure 3A , a lower structure 120 is formed on a substrate 110, and a feature layer 130 is formed on the lower structure 120.

[0037] In the chip region CR, the upper surface of the feature layer 130 may extend uniformly.

[0038] In the scribe region SLR, trenches 122 for forming the plurality of alignment marks AK (see Figure 2B ) may be formed in the upper surface of the lower structure 120. In the scribe region SLR, the feature layer 130 may conformally cover the upper surface of the lower structure 120 and the inner walls of the trenches 122. Accordingly, in the scribe region SLR, in the feature layer 130, as marked by the dashed line in Figure 3A , a stepped portion 130ST having a relatively large height SH may be located at the edge of the trench 122. The trenches 122 of the lower structure 120 and the stepped portion 130ST of the feature layer 130 formed thereon may form the alignment marks AK. The feature layer 130 may be formed of the same material as the constituent material of the plurality of island patterns PA (see Figure 2A ).

[0039] Referring to Figure 3B , a first hard mask layer 142 is formed on the feature layer 130 in the chip region CR and the scribe region SLR.

[0040] In an exemplary embodiment, the first hard mask layer 142 may include an amorphous carbon layer (ACL). To form the first hard mask layer 142, a chemical vapor deposition (CVD) process may be used. The first hard mask layer 142 may have a thickness of about 1,000 to about 2,000.

[0041] In the chip region CR, the first hard mask layer 142 may have a uniform thickness without a thickness deviation depending on the position. In the scribe lane region SLR, the thickness of the first hard mask layer 142 may not be uniform. Specifically, at the step difference portion 130ST of the feature layer 130 and its edge, the step coverage of the first hard mask layer 142 may deteriorate, such that at the step difference portion 130ST and its edge, the thickness of a part of the first hard mask layer 142 is much smaller than the thickness of other parts of the first hard mask layer 142.

[0042] Referring Figure 3C , in the chip region CR and the scribe lane region SLR, a second hard mask layer 144 is formed on the first hard mask layer 142.

[0043] In an exemplary embodiment, the second hard mask layer 144 may include an amorphous silicon layer. To form the second hard mask layer 144, a CVD process may be used. The second hard mask layer 144 may have a thickness of about 100 to about 800. The first hard mask layer 142 and the second hard mask layer 144 may form a hard mask structure 140.

[0044] In the chip region CR, the second hard mask layer 144 may have a uniform thickness without a thickness deviation depending on the position. In the scribe lane region SLR, the thickness of the second hard mask layer 144 may not be uniform. Specifically, at the step difference portion 130ST of the feature layer 130 and its edge, the step coverage of the portion of the second hard mask layer 144 covering the first hard mask layer 142 deteriorates, such that at the step difference portion 130ST and its edge, the thickness of the portion of the second hard mask layer 144 covering the first hard mask layer 142 may be much smaller than the thickness of other parts of the second hard mask layer 144.

[0045] Referring Figure 3D , in the chip region CR and the scribe lane region SLR, a protective layer 146 is formed on the hard mask structure 140.

[0046] The protective layer 146 may have a uniform thickness in the chip region CR and the scribe lane region SLR. In the scribe lane region SLR, on the step difference portion 130ST of the feature layer 130 and its edge, the thickness of the portion of the protective layer 146 covering the second hard mask layer 144 is not less than the thickness of other parts of the protective layer 146. The protective layer 146 covers the hard mask structure 140 such that the hard mask structure 140 is not exposed to the outside in the chip region CR and the scribe lane region SLR, and may maintain the minimum thickness required to protect the hard mask structure 140 in the chip region CR and the scribe lane region SLR.

[0047] The protective layer 146 can protect the feature layer 130 and the hard mask structure 140 from the peripheral atmosphere. In an exemplary embodiment, the protective layer 146 contacts the upper surface of the second hard mask layer 144 and can prevent the second hard mask layer 144 from being oxidized. The protective layer 146 can be formed of a material different from that of the second hard mask layer 144. In an exemplary embodiment, the protective layer 146 can include a silicon-containing layer containing oxygen atoms, nitrogen atoms, or a combination thereof. For example, the protective layer 146 can include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination of the above layers.

[0048] To form the protective layer 146, an atomic layer deposition (ALD) process can be used. The protective layer 146 can have a thickness of about 10 to about 500. In an exemplary embodiment, the thickness of the protective layer 146 can be less than the thickness of the second hard mask layer 144. For example, the second hard mask layer 144 can have a thickness of about 150 to about 250, and the protective layer 146 can have a thickness of about 20 to about 80. However, the thicknesses of the second hard mask layer 144 and the protective layer 146 are not limited thereto.

[0049] Referring to Figure 3E , on the protective layer 146, a resist underlayer 152 and a photoresist layer 154 are sequentially formed.

[0050] In an exemplary embodiment, the resist underlayer 152 can be formed of a polymer. For example, the resist underlayer 152 can be formed of polysiloxane. Polysiloxane is a polymer having a siloxane bond. Polysiloxane can include repeating units formed of monosiloxane, disiloxane, trisiloxane, and / or cyclotetrasiloxane.

[0051] The resist underlayer 152 can include at least one of a photoacid generator, a crosslinker, and an interfacial adhesion enhancer. The photoacid generator, which is a compound capable of generating an acid by light, can include, for example, an onium salt, which includes triphenylsulfonium trifluoromethanesulfonate, aromatic diazonium salts, sulfonium salts, triarylsulfonium salts, diarylsulfonium salts, monoarylsulfonium salts, iodonium salts, diaryliodonium salts, nitrobenzyl esters, disulfones, diazo-disulfones, sulfonates, trichloromethyltriazine, or N-hydroxysuccinimide. The crosslinker is used to crosslink the repeating units of the polysiloxane. The crosslinker can include, for example, melamine, urea, or polyols. The interfacial adhesion enhancer is used to improve the adhesion between the resist underlayer 152 and the photoresist layer 154 in order to prevent the pattern from collapsing or peeling off in subsequent processes for developing the photoresist layer 154. The interfacial adhesion enhancer can be formed of a polymer having monomer units including hydroxyl groups.

[0052] In other exemplary embodiments, the underlying resist layer 152 may be formed of a bottom anti-reflective coating (BARC). The BARC may be formed of an organic compound, an inorganic compound, or a combination of the above compounds. For example, the BARC may be formed of silicon nitride, silicon oxynitride, amorphous silicon, titanium (Ti), titanium dioxide, titanium nitride, chromium oxide, carbon (C), an organic anti-reflective coating (ARC) material, or a combination of the above materials. The ARC material may be formed of an acrylic resin having a light absorber and a hydroxyl group as a crosslinking reactant in the same molecule or a novolac resin having a light absorber and a hydroxyl group as a crosslinking reactant in the same molecule. However, the inventive concept is not limited thereto.

[0053] To form the underlying resist layer 152, spin coating, a CVD process, or an ALD process may be used. The underlying resist layer 152 may have a thickness of about 10 to about 400.

[0054] The photoresist layer 154 may be formed of a resist for extreme ultraviolet (EUV) (13.5 nm), a resist for KrF excimer laser (248 nm), a resist for ArF excimer laser (193 nm), or a resist for F2 excimer laser (157 nm). The photoresist layer 154 may have a thickness of about 100 to about 800.

[0055] Referring to Figure 3F , in the chip region CR, by exposing and developing the photoresist layer 154, a photoresist pattern 154P is formed on the photoresist layer 154. In the scribe lane region SLR, the photoresist layer 154 may not be exposed and developed. When exposing the photoresist layer 154, EUV (13.5 nm), KrF excimer laser (248 nm), ArF excimer laser, or F2 excimer laser (157 nm) may be used as a light source. In the chip region CR, the planar shape of the photoresist pattern 154P may be the same as the planar shape of a plurality of island patterns PA (see Figure 2A ) to be formed in the chip region CR. For example, the photoresist pattern 154P may be formed of a plurality of island patterns PA spaced apart from each other and regularly arranged.

[0056] Referring to Figure 3G , in Figure 3F the resulting material, by transcribing the shape of the photoresist pattern 154P to the feature layer 130, a feature pattern 130P is formed.

[0057] For example, in Figure 3FIn the resulting material, in the chip region CR, the underlying resist layer 152, the protective layer 146, and the hard mask structure 140 can be sequentially anisotropically etched by using the photoresist pattern 154P as an etching mask. As a result, by etching the hard mask structure 140, a hard mask structure pattern 140P can be obtained in the chip region CR. By anisotropically etching the feature layer 130 by using the hard mask structure pattern 140P in the chip region CR and the hard mask structure 140 in the scribe region SLR as etching masks, a feature pattern 130P can be formed in the chip region CR. The feature pattern 130P can form Figure 2A the plurality of island patterns PA shown in

[0058] During the etching process for forming the feature pattern 130P, at least some portions of the photoresist pattern 154P, the underlying resist layer 152, and the protective layer 146 provided on the hard mask structure 140 can be removed in the etching atmosphere. In Figure 3G shown, in the chip region CR, the first hard mask layer 142 and the second hard mask layer 144 forming the hard mask structure pattern 140P remain on the feature pattern 130P. However, the second hard mask layer 144 can be removed in the etching atmosphere, and only a portion of the first hard mask layer 142 can remain on the feature pattern 130P.

[0059] In an exemplary embodiment, after forming the feature pattern 130P, a portion of the lower structure 120 is etched by over-etching such that in the chip region CR, a recessed region (not shown) can be formed in a partial region of the upper surface of the lower structure 120 exposed through the feature pattern 130P. In other exemplary embodiments, in the chip region CR, the above-described recessed region may not be formed on the upper surface of the lower structure 120.

[0060] Referring to Figure 3H , by removing unnecessary materials remaining on the feature pattern 130P, the upper surface of the feature pattern 130P is exposed. To this end, an ashing process and a lift-off process can be used. In the scribe region SLR, the upper surface of the alignment mark AK formed in the feature layer 130 can be exposed again.

[0061] Figures 4A to 4C is a cross-sectional view of a process showing a method of sequentially manufacturing an integrated circuit device according to another exemplary embodiment of the inventive concept. Referring to Figures 4A to 4C , another method of forming the plurality of island patterns PA and the alignment mark AK included in the integrated circuit device 100 shown in Figure 2A and Figure 2B is described. In Figure 4A and Figure 4B , cross-sections taken along the line X1-X1' of (b) in Figure 2A and alongFigure 2B The cross-section corresponding to the region of the cross-section intercepted by the line X2-X2'.

[0062] Referring to Figure 4A and by the same method as described with reference to Figure 3A and Figure 3F a process of forming a photoresist pattern 154P on the substrate 110 is performed. Then, by inspecting the photoresist pattern 154P, the orientation state and defects of the photoresist pattern 154P can be inspected. As a result of inspecting the photoresist pattern 154P, when it is determined that the photoresist pattern 154P is defective, it is difficult to use the photoresist pattern 154P as an etching mask in a subsequent etching process, and it is necessary to perform a rework process to remove the photoresist pattern 154P and form a new photoresist pattern. For example, as a result of inspecting the photoresist pattern 154P, when a twisting phenomenon in which the photoresist pattern 154P is distorted, a striation phenomenon in which the surface of the photoresist pattern 154P is rough, a phenomenon in which the photoresist pattern 154P drops off, or a phenomenon in which the orientation state of the photoresist pattern 154P deviates beyond the tolerance occurs, it can be determined that the photoresist pattern 154P is defective.

[0063] For the rework process, the photoresist pattern 154P in the chip region CR and the photoresist layer 154 in the scribe lane region SLR can be exposed to a rework atmosphere 160.

[0064] In an exemplary embodiment, the rework atmosphere 160 may include an oxygen-containing atmosphere. For example, the photoresist pattern 154P in the chip region CR and the photoresist layer 154 in the scribe lane region SLR can be removed by a plasma ashing process in an oxygen-containing atmosphere. In another example, in order to remove the photoresist pattern 154P and the photoresist layer 154, by irradiating ultraviolet (UV) light in an oxygen-containing atmosphere, O3 and / or oxygen radicals are generated, and the photoresist pattern 154P and the photoresist layer 154 can be decomposed into CO2 and H2O by using O3 and oxygen radicals. In the case where the underlying resist layer 152 is formed of a polymer or an organic compound, when the photoresist pattern 154P in the chip region CR and the photoresist layer 154 in the scribe lane region SLR are removed, the underlying resist layer 152 can also be removed.

[0065] In other exemplary embodiments, the rework atmosphere 160 may be a wet atmosphere including a diluent composition. The diluent composition may include at least one compound selected from ethyl lactate, ethyl 3-ethoxypropionate, γ-butyrolactone, acetone, ester compounds, propylene glycol alkyl ether acetates, cyclohexanone, and methyl 2-hydroxyisobutyrate. However, the types of compounds that can be included in the diluent composition are not limited thereto.

[0066] Reference Figure 4B , after removing the photoresist pattern 154P in the chip region CR and the photoresist layer 154 in the scribe lane region SLR by the same method as described with reference to Figure 4A , the protective layer 146 can be exposed in the chip region CR and the scribe lane region SLR.

[0067] When performing the rework process described with reference to Figure 4A , the protective layer 146 can protect the hard mask structure 140 thereunder from the rework atmosphere 160.

[0068] For example, when the protective layer 146 is omitted, while removing the photoresist pattern 154P and the photoresist layer 154 by the same method as described with reference to Figure 4A , the hard mask structure 140 is exposed to the rework atmosphere 160. In this case, in the scribe lane region SLR, since the first hard mask layer 142 and the second hard mask layer 144 include vulnerable portions, the thickness of the vulnerable portions is much smaller than that of other portions due to the deteriorated step coverage around the step difference portion 130ST of the feature layer 130, and oxygen or a diluent composition included in the rework atmosphere 160 penetrates into the vulnerable portions. Therefore, around the step difference portion 130ST, the feature layer 130, the first hard mask layer 142, and / or the second hard mask layer 144 are partially removed or damaged. When the above results (i.e., removing or damaging the feature layer 130, the first hard mask layer 142, and / or the second hard mask layer 144) occur, the alignment mark AK in the scribe lane region SLR cannot perform the normal alignment mark function.

[0069] According to the inventive concept, since the second hard mask layer 144, which is the uppermost layer of the hard mask structure 140, is covered by the protective layer 146, especially at the edge of the step difference portion 130ST of the feature layer 130, since the protective layer 146 covers the second hard mask layer 144 and the second hard mask layer 144 is not exposed, when removing the photoresist pattern 154P and the photoresist layer 154 by the same method as described with reference to Figure 4A , in the scribe lane region SLR, damage or deformation to the feature layer 130 and the hard mask structure 140 can be prevented. Therefore, when performing a lithography process of forming a new photoresist pattern on the protective layer 146 in a subsequent process, precise control can be smoothly performed by using the alignment mark AK in the scribe lane region SLR.

[0070] Reference Figure 4C , in Figure 4B the chip region CR and the scribe lane region SLR of the obtained material by the same method as described with reference to Figure 3EAfter forming a resist underlayer 172 and a photoresist layer 174 that cover a protective layer 146 in a method similar to the described method, by using an alignment mark AK in a scribe lane region SLR to expose and develop the photoresist layer 174 in a chip region CR in a method similar to the described method, a photoresist pattern 174P is formed from the photoresist layer 174. Figure 3F After forming a photoresist pattern 174P, by a method similar to the described method, an inspection process, a rework process, and a process of forming a new photoresist pattern 174P for the photoresist pattern 174P can be performed at least once. Then, by performing the processes described with reference to

[0071] In an exemplary embodiment, after forming the photoresist pattern 154P, by a method similar to the described method, an inspection process, a rework process, and a process of forming a new photoresist pattern 174P for the photoresist pattern 154P can be performed at least once. Then, by performing the processes described with reference to Figures 4A to 4C In an exemplary embodiment, after forming the photoresist pattern 154P, by a method similar to the described method, an inspection process, a rework process, and a process of forming a new photoresist pattern 174P for the photoresist pattern 154P can be performed at least once. Then, by performing the processes described with reference to Figure 3G and Figure 3H In the chip region CR, a feature pattern 130P is formed on the lower structure 120, and in the scribe lane region SLR, the upper surface of the alignment mark AK of the feature layer 130 can be exposed again.

[0072] According to the method of manufacturing an integrated circuit device according to an exemplary embodiment of the present inventive concept described with reference to Figures 4A to 4C When performing a lithography process to pattern the feature layer 130 in the chip region CR, a protective layer 146 for protecting the hard mask structure 140 is formed on the hard mask structure 140, and a lithography process of forming a photoresist layer 154 on the protective layer 146 is performed. Therefore, after forming the photoresist layer 154, when performing a rework process of removing the photoresist layer 154 and forming the photoresist layer 174, in the edge of the step difference portion 130ST of the feature layer 130 in the scribe lane region SLR, although a partial region of the hard mask structure 140 includes a portion vulnerable to the rework atmosphere 160 due to poor step coverage of the hard mask structure 140, since the hard mask structure 140 is covered by the protective layer 146, the feature layer 130 and / or the hard mask structure 140 can be prevented from being damaged or deformed in the scribe lane region SLR while performing the rework process. Therefore, in a subsequent process, when performing a lithography process of forming a photoresist pattern 174P on the protective layer 146, precise control can be smoothly performed by using the alignment mark AK in the scribe lane region SLR.

[0073] Figure 5 FIG. is a block diagram showing an exemplary configuration of an integrated circuit device 200 according to an exemplary embodiment of the present inventive concept.

[0074] Referring to Figure 5 , the integrated circuit device 200 can be formed on Figure 1In the corresponding chip region CR of the integrated circuit device 100 shown. The chip region CR of the integrated circuit device 200 may include a first region 22 and a second region 24. The first region 22 may be a memory cell region of a dynamic random access memory (DRAM) device, and the second region 24 may be a peripheral circuit region of the DRAM device. In some embodiments, the semiconductor memory device formed in the chip region CR may be a DRAM device. In other embodiments, the semiconductor memory device formed in the chip region CR may be a static random access memory (SRAM), NAND flash memory, NOR flash memory, phase change random access memory (PRAM), ferroelectric random access memory (FRAM), resistive random access memory (RRAM), or magnetic random access memory (MRAM). The first region 22 may include a memory cell array 22A. The second region 24 may include a row decoder 52, a sense amplifier 54, a column decoder 56, a self-refresh control circuit 58, a command decoder 60, a mode register set (MRS) / extended mode register set (EMRS) circuit 62, an address buffer 64, and a data input / output circuit 66.

[0075] Figure 6 is a plan view showing an exemplary layout configuration of the integrated circuit device 200 Figure 5 .

[0076] Referring to Figure 6 , the chip region CR of the integrated circuit device 200 may be surrounded by a scribe line region SLR. The chip region CR of the integrated circuit device 200 may include a plurality of first regions 22, and each of the plurality of first regions 22 may be surrounded by a second region 24. The first region 22 may be a memory cell array region MCA of a DRAM device, and the second region 24 may be a peripheral circuit region and a core region in which the peripheral circuits of the DRAM device are formed.

[0077] In the first region 22, the memory cell array region MCA may include the memory cell array 22A described with reference to Figure 5 . The second region 24 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a bonding block CJT. In the sense amplifier block S / A, a plurality of bit line sense amplifiers may be arranged. The bonding block CJT may be arranged at a point where the sub-word line driver block SWD and the sense amplifier block S / A intersect each other. In the bonding block CJT, power drivers and ground drivers for driving the plurality of bit line sense amplifiers may be alternately arranged. In the second region 24, peripheral circuits such as an inverter chain or an input / output circuit may also be formed.

[0078] Figure 7 is a schematic plan layout showing the main components of the memory cell array region MCA of Figure 6 .

[0079] Reference Figure 7 , the unit array region MCA may include a plurality of active regions AC. Each of the plurality of active regions AC may be arranged to have a major axis in an inclined direction with respect to the X direction and the Y direction. A plurality of word lines WL may extend parallel to each other in the X direction through the plurality of active regions AC. On the plurality of word lines WL, a plurality of bit lines BL may extend parallel to each other in the Y direction. The plurality of bit lines BL may be connected to the plurality of active regions AC through a plurality of direct contacts DC. Among the plurality of bit lines BL, between two adjacent bit lines BL, a plurality of buried contacts BC may be formed. The plurality of buried contacts BC may be arranged side by side in the X direction and the Y direction. On the plurality of buried contacts BC, a plurality of conductive landing pads LP may be formed. The plurality of buried contacts BC and the plurality of conductive landing pads LP may connect a lower electrode (not shown) of a capacitor formed on the plurality of bit lines BL to the plurality of active regions AC. The plurality of conductive landing pads LP may be partially overlapped with the plurality of buried contacts BC.

[0080] Figure 8A and Figure 8B is a cross-sectional view showing a partial region of the unit array region MCA included in Figures 5 to 7 the integrated circuit device 200. Figure 8A shows a cross-sectional configuration of a partial region taken along line A-A' of Figure 7 , and Figure 8B shows a cross-sectional configuration of a partial region taken along line B-B' of Figure 7 .

[0081] Reference Figure 8A and Figure 8B , in the unit array region MCA of the integrated circuit device 200, a plurality of device isolation trenches T1 are formed in the substrate 210, and in the plurality of device isolation trenches T1, a plurality of device isolation layers 212 are formed. In the unit array region MCA, the plurality of active regions AC may be defined by the plurality of device isolation layers 212 in the substrate 210.

[0082] The substrate 210 may include silicon, for example, single crystal silicon, polycrystalline silicon, or amorphous silicon. In other embodiments, the substrate 210 may include at least one selected from germanium (Ge), SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 210 may include a conductive region, for example, a well doped with impurities or a structure doped with impurities. Each of the device isolation layers 212 may include an oxide layer, a nitride layer, or a combination of the above layers.

[0083] In the cell array region MCA, in the substrate 210, a plurality of word line trenches T2 extending in the first horizontal direction (X direction) are formed. In the plurality of word line trenches T2, a plurality of gate dielectric layers 216, a plurality of word lines 218, and a plurality of buried insulating layers 220 are formed. The plurality of word lines 218 may correspond to Figure 7 the plurality of word lines WL shown therein. On the upper surfaces of the plurality of buried insulating layers 220, a plurality of recessed spaces 220R may be formed. The plurality of gate dielectric layers 216 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, or a high-k dielectric layer having a dielectric constant higher than that of the silicon oxide layer. For example, the plurality of gate dielectric layers 216 may include HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2. The plurality of word lines 218 may be formed of Ti, TiN, tantalum (Ta), TaN, tungsten (W), WN, TiSiN, WSiN, or a combination of the above metals. The plurality of buried insulating layers 220 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination of the above layers.

[0084] In the cell array region MCA, a buffer layer 222 may be formed on the substrate 210. The buffer layer 222 may include a first insulating layer 222A and a second insulating layer 222B. Each of the first insulating layer 222A and the second insulating layer 222B may include an oxide layer, a nitride layer, or a combination of the above layers. In a plurality of direct contact holes DCH in the substrate 210, the plurality of direct contact members DC may be formed. The plurality of direct contact members DC may be connected to the plurality of active regions AC. The plurality of direct contact members DC may be formed of Si, Ge, W, WN, cobalt (Co), nickel (Ni), aluminum (Al), molybdenum (Mo), ruthenium (Ru), Ti, TiN, Ta, TaN, copper (Cu), or a combination of the above metals.

[0085] On the substrate 210 and the plurality of direct contacts DC, the plurality of bit lines BL may extend longitudinally in a second horizontal direction (Y direction). The plurality of bit lines BL may be respectively connected to the plurality of active regions AC through the plurality of direct contacts DC. Each of the plurality of bit lines BL may include a lower conductive pattern 230B, an intermediate conductive pattern 232B, and an upper conductive pattern 234B sequentially stacked on the substrate 210. In some examples, each of the plurality of bit lines BL may include a direct contact DC, an intermediate conductive pattern 232B, and an upper conductive pattern 234B sequentially stacked on the substrate 210. The lower conductive pattern 230B may be formed of doped polysilicon. In some examples, the lower conductive pattern 230B may be formed of the same material as the direct contact DC. Each of the intermediate conductive pattern 232B and the upper conductive pattern 234B may be formed of TiN, TiSiN, W, tungsten silicide, or a combination of the above metals. In an exemplary embodiment, the intermediate conductive pattern 232B may be formed of TiN, TiSiN, or a combination of the above metals, and the upper conductive pattern 234B may be formed of W. The plurality of bit lines BL may be respectively covered by a plurality of insulating cover lines CL. Each of the plurality of insulating cover lines CL may include a lower insulating cover pattern 236A, an insulating thin film pattern 244A, and an upper insulating cover pattern 250A. Each of the lower insulating cover pattern 236A, the insulating thin film pattern 244A, and the upper insulating cover pattern 250A may include a silicon nitride layer.

[0086] Sidewalls of the plurality of bit lines BL and the plurality of insulating cover lines CL may be covered by a plurality of insulating spacers 252. The plurality of insulating spacers 252 may extend longitudinally to be parallel to the plurality of bit lines BL in the Y direction. Each of the plurality of insulating spacers 252 may include an oxide layer, a nitride layer, an air spacer, or a combination of the above materials. In the present specification, the term "air" may represent air or a space including other gases that may be in a manufacturing process.

[0087] Among the plurality of bit lines BL, a plurality of conductive plugs 256 and a plurality of insulating baffles 254 may be arranged side by side in the Y direction. The plurality of conductive plugs 256 may longitudinally extend in the vertical direction (Z direction) from a recessed space RS formed in a substrate 210. The plurality of insulating baffles 254 may fill the plurality of recessed spaces 220R formed on the upper surface of a buried insulating layer 220, and may be arranged one by one among the plurality of conductive plugs 256. In the Y direction, two sidewalls of each of the plurality of conductive plugs 256 may be covered by the plurality of insulating baffles 254. The plurality of conductive plugs 256 arranged side by side in the Y direction may be insulated from each other by the plurality of insulating baffles 254. Each of the plurality of insulating baffles 254 may include a silicon nitride layer. The plurality of conductive plugs 256 may be formed Figure 7 as the plurality of buried contacts BC shown

[0088] On the plurality of conductive plugs 256, a plurality of metal silicide layers 258 and a conductive layer 260 may be sequentially formed. The conductive layer 260 may include a conductive barrier layer 262 and a main conductive layer 264. Each of the plurality of conductive landing pads LP may include the conductive layer 260. The plurality of metal silicide layers 258 and the plurality of conductive landing pads LP may be vertically stacked with the plurality of conductive plugs 256. Each of the plurality of metal silicide layers 258 may be formed of cobalt silicide, nickel silicide, or manganese silicide. The plurality of conductive landing pads LP may be respectively connected to the plurality of conductive plugs 256 through the plurality of metal silicide layers 258. The plurality of conductive landing pads LP may cover at least a part of the upper surface of an upper insulating cover pattern 250A to be vertically stacked with some parts of the plurality of bit lines BL. The conductive barrier layer 262 may be formed of Ti, TiN, or a combination of the above metals. The main conductive layer 264 may be formed of a metal, a metal nitride, conductive polysilicon, or a combination of the above materials. For example, the main conductive layer 264 may include W. In a plan view, the plurality of conductive landing pads LP may be in the form of the plurality of island patterns PA. The plurality of conductive landing pads LP may be electrically insulated from each other by the plurality of insulating layers 270 filling an insulating space 270S around the plurality of conductive landing pads LP. Each of the plurality of insulating layers 270 may include a silicon nitride layer, a silicon oxide layer, or a combination of the above layers.

[0089] Figures 9A to 9E is a cross-sectional view showing a method of manufacturing an integrated circuit device in sequence according to an exemplary embodiment of the inventive concept. In Figures 9A to 9E it, some components of a cell array region MCA included in a chip region CR and some components of a scribe line region SLR are sequentially shown.

[0090] Referring to Figure 9A, in the cell array region MCA, on the substrate 210, a first lower structure BS1 can be formed. The first lower structure BS1 includes the plurality of bit lines BL, the plurality of conductive plugs 256 inserted between the plurality of bit lines BL, the plurality of insulating cover lines CL formed on the plurality of bit lines BL, and the plurality of metal silicide layers 258 covering the upper surfaces of the plurality of conductive plugs 256. And in the scribe line region SLR, on the substrate 210, a second lower structure BS2 in which trenches 227 are formed can be formed. The second lower structure BS2 may include an insulating layer.

[0091] Then, a conductive layer 260 covering the first lower structure BS1 in the cell array region MCA and the second lower structure BS2 in the scribe line region SLR is formed.

[0092] Figures 10A to 10J is a cross-sectional view showing the process of sequentially forming Figure 9A the first lower structure BS1 and the conductive layer 260 covering the first lower structure BS1 in the cell array region MCA.

[0093] Referring to Figure 10A , in the cell array region MCA, in the substrate 210, the plurality of device isolation trenches T1 and the plurality of device isolation layers 212 are formed such that the plurality of active regions AC are defined in the substrate 210. Then, in the substrate 210, the plurality of word line trenches T2 as shown in Figure 8B can be formed. After cleaning the resulting material in which the plurality of word line trenches T2 are formed, in the plurality of word line trenches T2, the plurality of gate dielectric layers 216, the plurality of word lines 218, and the plurality of buried insulating layers 220 can be sequentially formed. In the plurality of active regions AC, by implanting impurity ions into both sides of each of the plurality of word lines 218, a plurality of source / drain regions can be formed on the plurality of active regions AC. In an exemplary embodiment, the plurality of source / drain regions can be formed before the plurality of word lines 218 are formed. Then, a buffer layer 222 is formed on the substrate 210.

[0094] Referring to Figure 10B , in the cell array region MCA, a lower conductive layer 230 is formed on the buffer layer 222.

[0095] Referring to Figure 10C, after forming the mask pattern M21 on the lower conductive layer 230, in the cell array region MCA, by etching the lower conductive layer 230 exposed through the opening M21O of the mask pattern M21, as well as a part of the substrate 210 and a part of the device isolation layer 212 exposed as a result of etching the lower conductive layer 230, the plurality of direct contact holes DCH exposing the plurality of active regions AC of the substrate 210 are formed. The mask pattern M21 may include an oxide layer, a nitride layer, or a combination of the above layers.

[0096] Referring to Figure 10D , from Figure 10C the resulting material, the mask pattern M21 is removed, and the plurality of direct contacts DC are formed in the plurality of direct contact holes DCH. In an exemplary process of forming the plurality of direct contacts DC, in the plurality of direct contact holes DCH and on the lower conductive layer 230, a conductive layer having a thickness sufficient to fill the plurality of direct contact holes DCH may be formed, and the conductive layer may be etched back so that the conductive layer remains only in the plurality of direct contact holes DCH. The conductive layer may be formed of Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination of the above metals.

[0097] Referring to Figure 10E , in the cell array region MCA, on the lower conductive layer 230 and the plurality of direct contacts DC, an intermediate conductive layer 232 and an upper conductive layer 234 are formed, and on the upper conductive layer 234, a lower insulating cover layer 236, an insulating thin film 244, and an upper insulating cover layer 250 are sequentially formed.

[0098] Each of the intermediate conductive layer 232 and the upper conductive layer 234 may be formed of TiN, TiSiN, W, tungsten silicide, or a combination of the above metals. Each of the lower insulating cover layer 236, the insulating thin film 244, and the upper insulating cover layer 250 may include a silicon nitride layer.

[0099] Referring to Figure 10F , in Figure 10E the resulting material, by patterning the upper insulating cover layer 250, the insulating thin film 244, and the lower insulating cover layer 236 in the cell array region MCA via a photolithography process, the plurality of insulating cover lines CL including a lower insulating cover pattern 236A, an insulating thin film pattern 244A, and an upper insulating cover pattern 250A sequentially stacked on the upper conductive layer 234 are formed.

[0100] Referring to Figure 10G , in Figure 10FIn the resulting material, the upper conductive layer 234, the intermediate conductive layer 232, and the lower conductive layer 230 are etched by using the lower insulating cover pattern 236A, the insulating film pattern 244A, and the upper insulating cover pattern 250A as etching masks to form the plurality of bit lines BL and to form the plurality of insulating spacers 252. The plurality of bit lines BL are formed by the lower conductive pattern 230B, the intermediate conductive pattern 232B, and the upper conductive pattern 234B. The plurality of insulating spacers 252 may fill the plurality of direct contact holes DCH around the plurality of direct contacts DC. After forming the plurality of insulating spacers 252, a line space LS may be left between the plurality of bit lines BL. By an etching process accompanying the formation of the plurality of bit lines BL and the plurality of insulating spacers 252, the height of the upper insulating cover pattern 250A may be reduced.

[0101] Referring to Figure 10H , in the cell array region MCA, by forming the plurality of insulating baffles 254 (see Figure 8B ) between each of the plurality of bit lines BL, one line space LS is divided into a plurality of contact spaces CS1. The plurality of insulating baffles 254 (see Figure 8B ) may be vertically stacked with the plurality of word lines 218 respectively. Due to the plurality of insulating baffles 254, one line space LS can be divided into the plurality of contact spaces CS1. Under the etching atmosphere accompanying the formation of the plurality of insulating baffles 254, the upper insulating cover pattern 250A and the insulating spacers 252 are exposed, so that the heights of the upper insulating cover pattern 250A and the insulating spacers 252 can be reduced. Then, by removing some portions of these structures exposed through the plurality of contact spaces CS1, a plurality of recessed spaces RS exposing the plurality of active regions AC are formed between the plurality of bit lines BL.

[0102] Referring to Figure 10I , in the cell array region MCA, a plurality of conductive plugs 256 are formed. The plurality of conductive plugs 256 fill the plurality of recessed spaces RS between the plurality of bit lines BL and a part of the plurality of contact spaces CS1 between the plurality of bit lines BL. Then, on the plurality of conductive plugs 256 exposed through the plurality of contact spaces CS1, the plurality of metal silicide layers 258 are formed.

[0103] Referring to Figure 10J , on Figure 10I the resulting material, a conductive layer 260 covering the exposed surface is formed.

[0104] Referring again to Figure 9A , in the cell array region MCA and the scribe line region SLR, the conductive layer 260 may be formed simultaneously.

[0105] The conductive layer 260 may include a conductive barrier layer 262 and a main conductive layer 264. The conductive barrier layer 262 may be formed of Ti, TiN, or a combination of the above metals. The main conductive layer 264 may be formed of a metal, a metal nitride, conductive polysilicon, or a combination of the above materials. For example, the main conductive layer 264 may include a tungsten layer.

[0106] In the scribe line region SLR, in the conductive layer 260, as marked by the dashed line in Figure 9A , a step difference portion 260ST may be provided. The trench 227 of the second lower structure BS2 and the step difference portion 260ST of the conductive layer 260 formed thereon may form an alignment mark AK2.

[0107] In the cell array region MCA, the conductive layer 260 may include an upper portion 260H1 of the conductive layer that covers the plurality of insulating cover lines CL and overlaps with the plurality of bit lines BL in the vertical direction (Z direction). In the scribe line region SLR, the conductive layer 260 forming the alignment mark AK2 may include: a high-level portion 260H2 that covers the upper surface of the second lower structure BS2; and a low-level portion 260L that covers the bottom surface of the trench 227 formed in the second lower structure BS2. The low-level portion 260L may extend in the horizontal direction along the X-Y plane at a level substantially the same as the upper conductive pattern 234B of the bit line BL in the cell array region MCA. The high-level portion 260H2 may extend in the horizontal direction at a level higher than the upper conductive pattern 234B of the bit line BL while covering the upper surface of the second lower structure BS2. The step difference portion 260ST of the conductive layer 260 may include a portion that extends in the vertical direction (Z direction) between the high-level portion 260H2 and the low-level portion 260L. In the conductive layer 260, the high-level portion 260H2 in the scribe line region SLR and the upper portion 260H1 of the conductive layer in the cell array region MCA may extend in the horizontal direction at substantially the same level. Here, the term "level" refers to the height in the vertical direction with respect to the upper surface of the substrate 210. Each of the upper conductive pattern 234B of the bit line BL and the conductive layer 260 may include a metal layer (e.g., a tungsten layer) formed of the same material.

[0108] After forming the conductive layer 260, the conductive layer 260 may only fill that part of the trench 227 formed in the second lower structure BS2 in the scribe line region SLR. Therefore, after forming the conductive layer 260, in the trench 227 remaining on the conductive layer 260, the step difference portion 260ST may be exposed.

[0109] Referring to Figure 9B , by referring to Figures 3B to 3EA method similar to the described method is to sequentially form a first hard mask layer 142, a second hard mask layer 144, a protective layer 146, an underlayer resist 152, and a photoresist layer 154 on the conductive layer 260 in the cell array region MCA and the scribe lane region SLR.

[0110] The first hard mask layer 142 may have a substantially constant thickness in the cell array region MCA, with little variation in thickness with different positions, and the thickness of the first hard mask layer 142 may not remain constant according to different positions in the scribe lane region SLR. Specifically, on the step difference portion 260ST of the conductive layer 260 and its edge, the step coverage of the first hard mask layer 142 deteriorates, such that around the step difference portion 260ST, the thickness of a part of the first hard mask layer 142 may be much smaller than the thickness of other parts of the first hard mask layer 142.

[0111] The second hard mask layer 144 may have a substantially constant thickness in the cell array region MCA, with little variation in thickness with different positions, and the thickness of the second hard mask layer 144 may not remain constant according to different positions in the scribe lane region SLR. Specifically, on the step difference portion 260ST of the conductive layer 260 and its edge, the step coverage of the second hard mask layer 144 covering the first hard mask layer 142 deteriorates, such that around the step difference portion 260ST, the thickness of a part of the second hard mask layer 144 may be much smaller than the thickness of other parts of the second hard mask layer 144.

[0112] The protective layer 146 may have a uniform thickness in the cell array region MCA and the scribe lane region SLR. In the protective layer 146, around the step difference portion 260ST of the conductive layer 260, the thickness of the part covering the second hard mask layer 144 is not smaller than the thickness of other parts of the protective layer 146. For example, the protective layer 146 may maintain at least a certain amount of thickness to protect the hard mask structure 140 while covering the hard mask structure 140, such that the hard mask structure 140 is not exposed to the outside in the cell array region MCA and the scribe lane region SLR. The exemplary configurations of the underlayer resist 152 and the photoresist layer 154 are the same as those described with reference to Figure 3E described.

[0113] With reference to Figure 9C and by the same method as described with reference to Figure 3F in the cell array region MCA, a photoresist pattern 154Q is formed from the photoresist layer 154 by exposing and developing the photoresist layer 154. In the scribe lane region SLR, the photoresist layer 154 may not be exposed and developed.

[0114] The planar shape of the photoresist pattern 154Q may be the same as Figure 8AThe planar shape of the plurality of conductive landing pads LP shown in the figure corresponds. The photoresist pattern 154Q may be formed of a plurality of island patterns PA spaced apart from each other and regularly arranged in the X direction.

[0115] In an exemplary embodiment, by inspecting the photoresist pattern 154Q, the orientation state and defects of the photoresist pattern 154Q can be inspected. As a result of inspecting the photoresist pattern 154Q, when it is determined that the photoresist pattern 154Q is defective, in a subsequent etching process, it is difficult to use the photoresist pattern 154Q as an etching mask, and it is necessary to perform a rework process to remove the photoresist pattern 154Q and form a new photoresist pattern. For example, as a result of inspecting the photoresist pattern 154Q, when a twisting phenomenon in which the photoresist pattern 154Q twists, a striation phenomenon in which the surface of the photoresist pattern 154Q is rough, a phenomenon in which the photoresist pattern 154Q drops, or a phenomenon in which the orientation state of the photoresist pattern 154Q deviates beyond the tolerance occurs, it can be determined that the photoresist pattern 154Q is defective.

[0116] For the rework process, the photoresist pattern 154Q in the chip region CR and the photoresist layer 154 in the scribe lane region SLR can be exposed to a rework atmosphere 160 (see Figure 4A ).

[0117] Referring to Figure 9D , in Figure 9C 's resulting material, by the same method as described with reference to Figure 3G , using the photoresist pattern 154Q in the cell array region MCA and the photoresist layer 154 in the scribe lane region SLR as an etching mask, by sequentially and anisotropically etching the under-resist layer 152, the protective layer 146, and the hard mask structure 140, and anisotropically etching the conductive layer 260 in the cell array region MCA, the plurality of conductive landing pads LP are formed in the cell array region MCA.

[0118] Then, by a method similar to the method described with reference to Figure 3H , by removing unnecessary material remaining on the plurality of conductive landing pads LP, the upper surfaces of the plurality of conductive landing pads LP are exposed, and in the scribe lane region SLR, the upper surface of the conductive layer 260 on which the alignment mark AK2 is formed can be exposed again.

[0119] As Figure 7As shown, in a plan view, the plurality of conductive landing pads LP may be in the form of the plurality of island patterns PA. The plurality of conductive landing pads LP may be vertically stacked on some portions of the plurality of bit lines BL on the plurality of insulating cover lines CL. While performing an etching process for forming the plurality of conductive landing pads LP in the cell array region MCA, in the cell array region MCA, an insulating space 270S exposing the plurality of insulating spacers 252 may be formed around the plurality of conductive landing pads LP.

[0120] Referring to Figure 9E , in Figure 9D the resulting material, an insulating layer 270 is formed to fill the insulating space 270S in the cell array region MCA and the trench 227 on the conductive layer 260 remaining in the scribe line region SLR.

[0121] In an exemplary embodiment, before filling the insulating space 270S with the insulating layer 270 in the cell array region MCA, air spacers may be formed in the plurality of insulating spacers 252 by deforming some portions of the plurality of insulating spacers 252 through the insulating space 270S. After forming the insulating layer 270, in the cell array region MCA, a lower electrode of a capacitor may be formed on a corresponding one of the plurality of conductive landing pads LP. In some examples, the integrated circuit device 200 may include a plurality of capacitor structures (not shown), and the plurality of capacitor structures are formed by sequentially forming a plurality of lower electrodes, a capacitor dielectric film, and an upper electrode on the plurality of landing pads LP in the cell array region MCA. The plurality of lower electrodes may be electrically connected to the plurality of landing pads LP respectively. The capacitor dielectric film may conformally cover the plurality of lower electrodes. The upper electrode may cover the capacitor dielectric film. The upper electrode may face the plurality of lower electrodes, and the capacitor dielectric film is located between the upper electrode and the plurality of lower electrodes. The capacitor dielectric film and the upper electrode may be integrally formed to cover the plurality of lower electrodes in the cell array region MCA.

[0122] By referring to Figures 9A to 9EAn exemplary method of manufacturing an integrated circuit device 200 is described. In order to simultaneously form the plurality of conductive landing pads LP arranged in the cell array region MCA and having a large pattern density and the alignment marks AK2 arranged in the scribe line region SLR, when performing a photolithography process, a protective layer 146 for protecting the hard mask structure 140 is formed on the hard mask structure 140, and a photoresist layer 154 is formed on the protective layer 146. Therefore, after the photoresist layer 154 is formed, in a rework process for removing the photoresist layer 154 again, although a partial region of the hard mask structure 140 includes a portion vulnerable to the rework atmosphere due to a deteriorated coverage rate of the hard mask structure 140 around the step difference portion 260ST of the conductive layer 260 in the scribe line region SLR, since the hard mask structure 140 can be covered and protected by the protective layer 146, while performing a rework process similar to the rework process described with reference to Figures 4A to 4C damage or deformation of the conductive layer 260 and the hard mask structure 140 can be prevented in the scribe line region SLR. Therefore, when performing a photolithography process for forming a new photoresist pattern on the protective layer 146 in a subsequent process, precise control can be smoothly performed by using the alignment marks AK2 in the scribe line region SLR. In addition, although the above rework process is performed multiple times, the hard mask structure 140 is protected by the protective layer 146. Therefore, when the rework process is performed multiple times, damage and deformation of the conductive layer 260 and the hard mask structure 140 can be prevented. Therefore, in the cell array region MCA, by precisely inspecting and correcting the orientation state and defects of the photoresist pattern 154P, the plurality of conductive landing pads LP each having a desired shape, size, and orientation state can be formed.

[0123] In addition, when forming the plurality of conductive landing pads LP having a large pattern density in the cell array region MCA, a raised pattern can be used. To this end, by using a mask structure including the hard mask structure 140 having a multilayer structure and the protective layer 146 for protecting the hard mask structure 140, the plurality of conductive landing pads LP having a large pattern density can be formed in the cell array region MCA by performing only one exposure process. For example, when using a double patterning process to form the plurality of conductive landing pads LP, due to problems caused by the double patterning process, the planar shape of the plurality of conductive landing pads LP may be non-uniform. However, according to the above-disclosed embodiments of the inventive concept, different from the method using a double patterning process, the plurality of conductive landing pads LP having a uniform planar shape can be obtained. Therefore, an undesired distribution deterioration or process defect can be prevented from occurring in the plurality of conductive landing pads LP, so as to improve the design freedom and maximize the process margin.

[0124] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A method of manufacturing an integrated circuit device, the method comprising the steps of: forming a feature layer on a substrate in a first region for forming a plurality of chips and a second region surrounding the first region, the feature layer having a flat upper surface in the first region and a stepped portion in the second region; forming a hard mask structure including a plurality of hard mask layers on the feature layer in the first region and the second region; forming a protective layer covering the hard mask structure such that the hard mask structure is not exposed in the first region and the second region; forming a photoresist layer on the protective layer in the first region and the second region; exposing and developing the photoresist layer in the first region by using the stepped portion in the second region as an alignment mark to form a photoresist pattern; etching the protective layer and the hard mask structure by using the photoresist pattern in the first region as an etching mask; and after etching the protective layer and the hard mask structure, etching the feature layer in the first region by using the pattern obtained by etching the protective layer and the hard mask structure as an etching mask to form a plurality of landing pads in the first region, the plurality of landing pads being located on buried contacts and partially vertically overlapping with the buried contacts, and vertically overlapping with bit lines, a lower surface of a portion of the landing pad vertically overlapping with the buried contact being lower than a lower surface of a portion of the landing pad vertically overlapping with the bit line.

2. The method according to claim 1, wherein, In the step of forming the hard mask structure, each of the plurality of hard mask layers includes a first portion having an uneven thickness on the stepped portion and an edge of the stepped portion, and wherein, in the step of forming the protective layer, the protective layer covers the hard mask structure such that the first portion is not exposed to the outside.

3. The method according to claim 1, wherein, The plurality of hard mask layers include an amorphous carbon layer and an amorphous silicon layer sequentially stacked on the feature layer, and wherein the step of forming the protective layer includes: forming a silicon-containing layer that contacts an upper surface of the amorphous silicon layer and includes oxygen atoms, nitrogen atoms, or a combination thereof.

4. The method according to claim 1, wherein, The step of forming the photoresist pattern includes: exposing the photoresist layer by using extreme ultraviolet light.

5. The method according to claim 1, wherein, The photoresist pattern includes a plurality of island patterns spaced apart from each other and regularly arranged in a first direction or a second direction perpendicular to the first direction.

6. The method according to claim 1, wherein The plurality of landing pads include a characteristic pattern of a plurality of island patterns spaced apart from each other and regularly arranged in the first direction.

7. The method according to claim 1, wherein The step of forming the hard mask structure is performed by a chemical vapor deposition process, and wherein the step of forming the protective layer is performed by an atomic layer deposition process.

8. The method according to claim 1, further comprising the step of: After forming the photoresist pattern and before etching the hard mask structure, inspect the photoresist pattern; and when it is determined that the photoresist pattern is defective in the step of inspecting the photoresist pattern, performing a rework process, wherein, performing the rework process includes the steps of: exposing the protective layer by removing the photoresist pattern in the first region and the second region; Form a new photoresist layer on the protective layer in the first region and the second region; and Form a new photoresist pattern by exposing and developing the new photoresist layer in the first region using the step difference portion in the second region as an alignment mark.

9. The method according to claim 8, wherein, The step of exposing the protective layer includes: Removing the photoresist pattern by ashing in an oxygen-containing atmosphere with the protective layer covering the hard mask structure.

10. The method according to claim 1, further comprising the steps of: Inspecting the photoresist pattern after forming the photoresist pattern and before etching the protective layer and the hard mask structure; and When it is determined that the photoresist pattern is defective in the step of inspecting the photoresist pattern, removing the photoresist pattern in an oxygen-containing atmosphere with the protective layer covering the hard mask structure, and re-executing the step of forming the photoresist layer and the step of forming the photoresist pattern.

11. A method of manufacturing an integrated circuit device, the method comprising the steps of: On a substrate, form a first lower structure covering the substrate in the cell array region and a second lower structure covering the substrate in the scribe region; Form a conductive layer covering the first lower structure and the second lower structure and having a step difference portion in the scribe region; Form a hard mask structure on the conductive layer in the cell array region and the scribe region, the hard mask structure including a plurality of hard mask layers; Form a protective layer covering the hard mask structure such that the hard mask structure is not exposed in the cell array region and the scribe region; Form a photoresist layer on the protective layer in the cell array region and the scribe region; Form a photoresist pattern by exposing and developing the photoresist layer in the cell array region using the step difference portion in the scribe region as an alignment mark; Etch the protective layer and the hard mask structure by using the photoresist pattern in the cell array region as an etch mask; and After etching the protective layer and the hard mask structure, etch the conductive layer in the cell array region by using the pattern obtained by etching the protective layer and the hard mask structure as an etch mask to form a plurality of landing pads in the cell array region, the plurality of landing pads being located on buried contacts and partially vertically overlapping with the buried contacts and vertically overlapping with bit lines, and a lower surface of a portion of the landing pad vertically overlapping with the buried contact being lower than a lower surface of a portion of the landing pad vertically overlapping with the bit line.

12. The method according to claim 11, wherein, The plurality of landing pads include a plurality of island patterns spaced apart from each other and regularly arranged in a first direction.

13. The method according to claim 11, wherein, The step of forming the photoresist pattern includes: exposing the photoresist layer using extreme ultraviolet light.

14. The method according to claim 11, wherein, The conductive layer includes a tungsten layer, wherein each of the plurality of hard mask layers includes an amorphous carbon layer and an amorphous silicon layer, a lower surface of the amorphous carbon layer contacts an upper surface of the tungsten layer, a lower surface of the amorphous silicon layer contacts an upper surface of the amorphous carbon layer, and Wherein, the protective layer includes a silicon-containing layer, a lower surface of the silicon-containing layer contacts an upper surface of the amorphous silicon layer, and the silicon-containing layer includes oxygen atoms, nitrogen atoms, or a combination thereof.

15. The method according to claim 11, wherein, The step of forming the hard mask structure is performed by a chemical vapor deposition process. Wherein, the step of forming the protective layer is performed by an atomic layer deposition process, and wherein, the protective layer includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination of the above layers.

16. The method according to claim 11, wherein, The step of forming the hard mask structure includes: forming a first hard mask layer formed of an amorphous carbon layer by using a chemical vapor deposition process, and forming a second hard mask layer including an amorphous silicon layer covering the amorphous carbon layer by using a chemical vapor deposition process. Wherein, the step of forming the protective layer includes: forming a silicon-containing layer including oxygen atoms, nitrogen atoms, or a combination thereof on the second hard mask layer by using an atomic layer deposition process, and wherein, a thickness of the protective layer is less than a thickness of the second hard mask layer.

17. The method according to claim 11, wherein, The first lower structure includes the bit line, the bit line includes a tungsten layer disposed at a first level on the substrate, and wherein, in the scribe region, the conductive layer includes a high-level portion and a low-level portion, the high-level portion covers an upper surface of the second lower structure at a second level higher than the first level, the low-level portion extends in a horizontal direction at the first level, and the step difference portion includes a portion extending in a vertical direction between the high-level portion and the low-level portion.

18. The method according to claim 11, further comprising the steps of: inspecting the photoresist pattern after forming the photoresist pattern and before etching the protective layer and the hard mask structure; and in the step of inspecting the photoresist pattern, when it is determined that the photoresist pattern is defective, removing the photoresist pattern in an oxygen-containing atmosphere in a state where the protective layer covers the hard mask structure, and performing the step of forming the photoresist layer again.

19. A method of manufacturing an integrated circuit device, the method comprising the steps of: forming a first lower structure and a second lower structure, the first lower structure including a plurality of bit lines, each of the plurality of bit lines including a metal layer on a substrate in a cell array region, the second lower structure including a trench in an upper surface of the second lower structure on a substrate in a scribe region; forming a conductive layer covering the first lower structure and the second lower structure and having a step difference portion around the trench in the scribe region; forming a hard mask structure including an amorphous silicon layer on the conductive layer in the cell array region and the scribe region; forming a protective layer covering the hard mask structure such that the amorphous silicon layer is not exposed in the cell array region and the scribe region; forming a photoresist layer on the protective layer in the cell array region; exposing and developing the photoresist layer in the cell array region by using the step difference portion in the scribe region as an alignment mark to form a photoresist pattern; inspecting the photoresist pattern; When it is determined that the photoresist pattern is defective in the step of inspecting the photoresist pattern, the photoresist pattern is removed in an oxygen-containing atmosphere with the protective layer covering the hard mask structure, and the steps of forming the photoresist layer and forming the photoresist pattern are performed again; And By transcribing the shape of the photoresist pattern onto a conductive layer in the cell array region, a plurality of landing pads including a plurality of island patterns are formed by the conductive layer. The plurality of island patterns are spaced apart from each other and regularly arranged. The plurality of landing pads are located on the buried contacts and partially vertically overlap with the buried contacts, and also vertically overlap with some of the plurality of bit lines. The lower surface of the portion of the landing pad that vertically overlaps with the buried contact is lower than the lower surface of the portion of the landing pad that vertically overlaps with the bit line.

20. The method according to claim 19, wherein, The step of forming the photoresist pattern includes: exposing the photoresist layer by using extreme ultraviolet light, and Wherein, the step of forming the protective layer includes: forming a silicon oxide layer, a silicon nitride layer or a silicon oxynitride layer by using an atomic layer deposition process.

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