Serial data transparent transmission system based on SPI bus protocol

Abstract

The present invention discloses a serial data transparent transmission system based on the SPI bus protocol, comprising: a host computer, including a microcontroller; and a slave chip unit, including a plurality of serially connected slave chips, each of which includes a master side controller, a slave side controller, and two groups of multiplexers. The slave side controller of the first slave chip in the plurality of serially connected slave chips is connected to the microcontroller of the host computer, and the slave side controllers of the remaining slave chips are respectively connected to the master side controller of the previous slave chip, so that the host computer can read and write data from all serially connected slave chips.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a serial data transparent transmission system based on an SPI bus protocol. Background Art

[0002] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus first proposed by Motorola. It only occupies 4 wires on the chip pins, saving chip pins and space on PCB layout. It is precisely because of this simple and easy-to-use feature that more and more devices now support this communication protocol.

[0003] The SPI interface is a common interface for sensor chips, and serves as a communication interface for sensor chip configuration and sensor data interaction. Traditional microcontrollers or processors communicate with chips through the SPI protocol, which can be one-to-one or one-to-many. When a one-to-N communication architecture is adopted, the MCU (Microcontroller Unit) needs to output N CSN ports, each connected to a target chip, but this will significantly increase the number of ports of the microcontroller, thereby reducing the efficiency of the MCU, and significantly restricting the expansion performance of the SPI communication system. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] Based on the above problems, the present invention provides a serial data transparent transmission system based on the SPI bus protocol to alleviate the technical problems in the prior art that the one-master-to-multiple-slave SPI communication system occupies too much interface resources of the master processor, resulting in low circuit system scalability, low communication efficiency, etc.

[0006] (II) Technical solution

[0007] The present invention provides a serial data transparent transmission system based on the SPI bus protocol, comprising: a host computer including a microcontroller; and a slave chip unit including a plurality of serially connected slave chips, each of the slave chips including a master side controller, a slave side controller, and two groups of multiplexers.

[0008] According to an embodiment of the present disclosure, the slave side controller of the first slave chip among the multiple serially connected slave chips is connected to the microcontroller of the host computer, and the slave side controllers of the remaining slave chips are respectively connected to the master side controller of the previous slave chip, thereby realizing the data reading and writing operations of the host computer on all the serially connected slave chips.

[0009] According to the embodiment of the present disclosure, the multiplexer is used to send a bypass signal to the slave chip to achieve the pass-through function of the SPI signal sent by the host computer, thereby performing a data reading operation on any designated slave chip.

[0010] According to the embodiment of the present disclosure, when the host initiates a write operation and the chip select address is 00, it means that the host needs to write to each slave chip; if the chip select address is not 00, it only writes to the slave chip corresponding to the chip select address.

[0011] According to the embodiment of the present disclosure, if the chip select address of the slave chip where the multiplexer is located is the same as the chip select address in the write operation issued by the host computer, the write operation is directly executed.

[0012] According to the embodiment of the present disclosure, if the chip select address of the slave chip where the multiplexer is located is different from the chip select address in the write operation issued by the host computer, the multiplexer sends a bypass signal to switch to the bypass mode, thereby realizing the pass-through function of the write command issued by the host computer, and transmitting the write operation to the next-level slave chip until the slave chip with the corresponding chip select address is written.

[0013] According to the embodiment of the present disclosure, when the host computer issues a read operation, the slave chip recognizes that its own chip select address is smaller than the pre-read chip select address in the read operation issued by the host computer, and then switches to bypass mode.

[0014] According to the embodiment of the present disclosure, each of the slave chips further includes an automatic addressing register, which is used to perform automatic addressing on the chip after power-on.

[0015] (III) Beneficial effects

[0016] It can be seen from the above technical solutions that the serial data transparent transmission system based on the SPI bus protocol disclosed in the present invention has at least one or part of the following beneficial effects:

[0017] (1) It can significantly save the host port resources and save system board-level wiring;

[0018] (2) It realizes reliable bidirectional data exchange in the transparent transmission system, ensures the integrity of the SPI bus protocol, and reduces the difficulty of system design;

[0019] (3) It has good scalability. Without exceeding the maximum value of the addressing register, the number of slave chips can be flexibly adjusted, thereby improving the efficiency of system design. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0021] Figure 1The schematic block diagram of the composition structure of the serial data transparent transmission system based on the SPI bus protocol of the embodiment of the present disclosure is schematically shown;

[0022] Figure 2 The typical read and write operation timing of the SPI protocol of the embodiment of the present disclosure is schematically shown;

[0023] Figure 3 The equivalent connection diagram of the write mode of the serial data transparent transmission system based on the SPI bus protocol of the embodiment of the present disclosure is schematically shown;

[0024] Figure 4 The equivalent connection diagram of the serial data transparent transmission system based on the SPI bus protocol in the read mode of the embodiment of the present disclosure is schematically shown;

[0025] Figure 5 The automatic addressing flow chart of the serial data transparent transmission system based on the SPI bus protocol of the embodiment of the present disclosure is schematically shown;

[0026] Figure 6 The chip write operation flow chart of the serial data transparent transmission system based on the SPI bus protocol of the embodiment of the present disclosure is schematically shown.

[0027] Figure 7 A system read operation flow chart of the serial data transparent transmission system based on the SPI bus protocol of an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0028] The present invention discloses a serial data transparent transmission system based on the SPI bus protocol, which is composed of a design scheme of an interface circuit in a chip supporting the system and a read and write operation process based on the SPI protocol. On the basis of complying with the content of the SPI protocol, an efficient one-to-many communication function is realized.

[0029] In the process of implementing the present disclosure, the inventors discovered that SPI communicates in a master-slave mode, with one master device and multiple slave devices, and requires at least four signal lines, namely: MOSI (Master Output / Slave Input) signal line, controlled by the master device; MISO (Master Input / Slave Output) signal line, controlled by the slave device; SCLK (clock) signal line, generated by the master device; CSN (slave enable) signal line, controlled by the master device. The CSN signal line controls whether the chip is selected, that is, when the chip select signal is a predetermined enable signal (low level), the operation on this chip is valid. This makes it possible to connect multiple SPI devices on the same bus, refer to Figure 2The figure shows a typical read and write timing diagram of an SPI interface. The serial data transparent transmission system based on the SPI bus protocol disclosed in the present invention can improve the efficiency of a one-to-many SPI communication system.

[0030] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0031] In the embodiment of the present disclosure, a serial data transparent transmission system based on the SPI bus protocol is provided. Figure 1 , Figure 3 , Figure 4 As shown, the serial data transparent transmission system based on the SPI bus protocol includes:

[0032] A host computer, including a microcontroller; and

[0033] A slave chip unit, comprising a plurality of slave chips connected in series, each of the slave chips comprising a master-side controller, a slave-side controller, and two sets of multiplexers;

[0034] The slave-side controller of the first slave chip among the plurality of serially connected slave chips is connected to the microcontroller of the host computer, and the slave-side controllers of the remaining slave chips are respectively connected to the master-side controller of the previous slave chip;

[0035] The multiplexer is controlled by the Bypass signal output by the slave side controller in the slave chip to implement the data reading operation of the host computer on any designated slave chip.

[0036] In the disclosed embodiment, Figure 1 The serial data transparent transmission system based on the SPI bus protocol in this scheme is shown, which is composed of a host computer (microcontroller MCU, etc.) and several slave chips connected in series. The serial connection method is that the SPI slave side (Slave) of this chip is connected to the master side (Master) of the upper chip, and the SPI master side of this chip is connected to the slave side of the next chip. The slave chip in the scheme includes an SPI slave side controller and an SPI master side controller, and also includes two groups of multiplexers (mux1, mux2) and is controlled by the bypass signal output by the slave side controller. When the Bypass signal is invalid, the connection method in the chip is that the master-slave protocol controller works independently, and only data is exchanged in the middle; when the Bypass signal is valid, the connection method in the chip is to bypass the master-slave controller in the chip to realize the pass-through function of the SPI signal, that is, the SPI signal group of the upper chip is directly connected to the SPI signal group of the next level.

[0037] In the embodiment of the present disclosure, the control method and Figure 3As shown, the equivalent connection diagram of the write mode of the serial data transparent transmission system based on the SPI bus described in the present disclosure can be obtained; Figure 4 As shown, taking the chip2 chip reading as an example, the equivalent connection diagram of the reading mode when the system is in bypass mode is shown, in which it can be seen that chip1 is switched to bypass mode.

[0038] In the embodiments of the present disclosure, Figure 2 As shown in the figure, the write operation of the SPI protocol only uses three signals, CSN, SCLK and MOSI, all of which are sent by the host; the read operation of the SPI protocol uses all SPI interface signals. Therefore, it can be determined that in order to be compatible with the SPI bus interface protocol, the write operation can support a one-host-to-multiple-slave mode; and the read operation of a one-host-to-multiple-slave mode must use a one-to-one mode if multiple CSN signals are not enabled.

[0039] In the embodiments of the present disclosure, Figure 5 As shown, after power-on, automatic addressing must be performed first, which utilizes a special register set in the slave chip, namely the automatic addressing register (register address is 00). The specific operation includes that after power-on, the host initiates a write operation, the chip select address is 00, the register address is 00, and the data is 01. After the SPI Slave controller of the first-level chip receives the data, it will identify and set the chip select address of the first-level chip to 01, and after adding 1 to the data (that is, the chip select address is 00, the register address is 00, and the data is 02), it will be written to the second-level chip through the SPI Master controller of the chip at this level, and the chip select address of the second-level chip will be identified and set to 02. The write operation is completed step by step, and the automatic addressing of the serially connected chips can be realized.

[0040] In the embodiments of the present disclosure, Figure 6 As shown, it is specifically shown that through the data recognition of the slave chip, the host microcontroller MCU can realize the data writing of all serial slave chips and the data writing of one slave chip. The specific operation is as follows: the host initiates a write operation, and the chip select address is 00, which means that the host needs to write to each slave chip; if the chip select address is not 00, it is only written to the specified chip. When the slave chip receives the write command, it will determine whether the chip select address is the same as the addressing of this chip (that is, whether it is consistent with the data of the address 00 register generated by the addressing). If it is consistent, it will be stored in the corresponding register and the write operation will end; if the chip select address is inconsistent with the local chip, the data will not be stored, and the SPIMaster will continue to perform the same write operation on the next level chip.

[0041] In the embodiments of the present disclosure, Figure 7As shown, it involves three stages: writing the "pre-read address" and identifying the mode switch, one-to-one read operation and mode reset. The specific operation process is as follows: the system first performs a write operation, and writes the chip select address to be read to the 01 address register (pre-read address register) of all slave chips, so that each slave chip can identify whether the host is going to perform a read operation on this chip; the chip recognizes that the local address is less than the pre-read chip select address, and switches to bypass mode; the overall serial transparent transmission system will form a temporary one-to-one SPI connection, and the host can perform normal read operations; after the read operation is completed, the host will reset the slave chip from bypass mode to serial write mode by clearing the 01 address register of all chips.

[0042] The specific implementation examples described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific implementation example of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

[0043] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0044] Based on the above description, those skilled in the art should have a clear understanding of the serial data transparent transmission system based on the SPI bus protocol disclosed in the present invention.

[0045] In summary, the present invention provides a serial data transparent transmission system based on the SPI bus protocol, which can greatly save the port resources of the host and save the system board-level wiring for one-to-many SPI system requirements. By designing a reasonable working method, including automatic addressing, write operation, read operation process, etc., the transparent transmission system realizes reliable two-way data exchange based on the SPI bus protocol, ensures the integrity of the SPI bus protocol, reduces the difficulty of system design, has good scalability, and can realize flexible adjustment of the number of slave chips without exceeding the maximum value of the addressing register, thereby improving the efficiency of system design.

[0046] It should also be noted that the directional terms mentioned in the embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only reference directions of the drawings and are not intended to limit the scope of protection of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure.

[0047] Moreover, the shapes and sizes of the components in the figures do not reflect the real size and proportion, but only illustrate the contents of the embodiments of the present disclosure. In addition, in the claims, any reference symbols between brackets shall not be constructed as limiting the claims.

[0048] Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0049] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., to modify the corresponding elements, do not themselves mean that the elements have any ordinal numbers, nor do they represent the order of one element and another element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name.

[0050] In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to the above list, and can be changed or rearranged according to the required design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0051] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and set in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into multiple submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose. Furthermore, in a unit claim that lists several devices, several of these devices may be embodied by the same hardware item.

[0052] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A serial data transparent transmission system based on SPI bus protocol, comprising: A host computer, including a microcontroller; and A slave chip unit, comprising a plurality of slave chips connected in series, each of the slave chips comprising a master-side controller, a slave-side controller, and two sets of multiplexers; When the host computer initiates a write operation and the chip select address is 00, it means that the host computer needs to write to every slave chip; if the chip select address is not 00, it will only write to the slave chip with the corresponding chip select address; if the chip select address of the slave chip where the multiplexer is located is different from the chip select address in the write operation issued by the host computer, the multiplexer will send a bypass signal to switch to bypass mode, realizing the pass-through function of the write command issued by the host computer, and transmitting the write operation to the next level slave chip until the slave chip with the corresponding chip select address is written.

2. According to the serial data transparent transmission system based on the SPI bus protocol according to claim 1, the slave side controller of the first slave chip among the multiple serially connected slave chips is connected to the microcontroller of the host computer, and the slave side controllers of the remaining slave chips are respectively connected to the master side controller of the previous slave chip, so as to realize the data reading and writing operations of the host computer on all the serially connected slave chips.

3. According to the serial data transparent transmission system based on the SPI bus protocol according to claim 1, the multiplexer is used to send a bypass signal to the slave chip where it is located, so as to realize the pass-through function of the SPI signal sent by the host computer, thereby performing data reading operations on any specified slave chip.

4. According to the serial data transparent transmission system based on the SPI bus protocol as described in claim 1, if the chip select address of the slave chip where the multiplexer is located is the same as the chip select address in the write operation issued by the host computer, the write operation is directly executed.

5. According to the serial data transparent transmission system based on the SPI bus protocol of claim 3, when the host computer issues a read operation, the slave chip recognizes that its own chip select address is less than the pre-read chip select address in the read operation issued by the host computer, and then switches to bypass mode.

6. According to the serial data transparent transmission system based on the SPI bus protocol as described in claim 3, each of the slave chips also includes an automatic addressing register, which is used to perform automatic addressing on the chip after power-on startup.

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