Optimization of vertical field effect transistor semiconductor cells

Abstract

A VFET cell implementing a vertical field-effect transistor (VFET) circuit on multiple gate grids includes: a first circuit including at least one VFET and provided on at least one gate grid; and a second circuit including at least one VFET and provided on at least one gate grid formed on the left or right side of the first circuit, wherein the gates of the VFETs of the first circuit are configured to share the gate signal or source / drain signal of the VFETs of the second circuit, and the first circuit is an (X-1) contact polypitch (CPP) circuit, which is (X-1)CPP wide, derived from an X-CPP circuit, the X-CPP circuit being X-CPP wide and performing the same logic function as the (X-1)CPP circuit, where X is an integer greater than 1.

Description

Technical Field

[0001] The apparatus and methods consistent with embodiments of the inventive concept relate to semiconductor cell architectures for circuits formed by vertical field-effect transistors (VFETs). Background Technology

[0002] Compared to lateral field-effect transistors (FETs) such as planar finFETs, VFETs are characterized by their vertical structure, in which the top source / drain, gate, and bottom source / drain are vertically overlapped.

[0003] When designing semiconductor cells formed by lateral FET circuits based on their layout or top view, it is not uncommon to allow adjacent circuits to share the source / drain of the FET by reducing the number of dummy gate structures in the cell. However, when designing semiconductor cells formed by VFET circuits, it is usually necessary to provide additional gate structures or fin structures next to the gate structure of the VFET so that metal wires and / or vias connecting the VFET's contact structure can be placed on the additional gate or fin structure to transmit the VFET's output signal. Dual-fin VFET devices (such as dual-fin inverters) are typical examples. Therefore, it is difficult to design a VFET semiconductor cell (hereinafter referred to as a "VFET cell") formed by a single-fin VFET device (such as a single-fin inverter) using only a single gate structure or fin structure for the purpose of reducing cell width or area. This is due to the inherent structure of the VFET, where the gate and source / drain overlap vertically.

[0004] Figure 1A The layout of a VFET cell, in which a dual-fin inverter is formed on two gate structures, is shown according to the relevant technology. Figure 1B A schematic diagram of an inverter that can be formed from a p-channel metal-oxide-semiconductor VFET (hereinafter referred to as "PMOS") and an n-channel metal-oxide-semiconductor VFET (hereinafter referred to as "NMOS") is shown. Figure 1C A schematic diagram of an inverter that can be formed from two PMOS and two NMOS is shown. Figure 1C The inverter shown can Figure 1A Implemented in the VFET cell shown.

[0005] refer to Figure 1AThe VFET cell 10 includes a dual-fin inverter 100, which is formed by a pair of one PMOS P and one NMOS N on the gate structure PC and another pair of one PMOS P and one NMOS N on another gate structure PC. Although in Figure 1A Not shown, but each gate structure PC is cut to a predetermined size to provide PMOS P and NMOS N on two divided portions of the corresponding gate structure PC. VFET cell 10 also includes two bottom source / drain regions RX connected to power source (Vdd) and ground source (Vss) (not shown), a gate connection pattern PB, two gate layer cuts CT from which the gate connection pattern PB is cut, a gate contact structure CB, two top source / drain contact structures CA, and three vias V.

[0006] However, even if the dual-fin inverter 100 can be changed to a single-fin inverter implemented by one PMOS and one NMOS on one of the two gate structures PC, the VFET cell 10 may still require another gate structure or fin structure, i.e., the other of the two gate structures PC, for connecting the top source / drain contact structure CA to the metal line (not shown for simplicity) and the via V. This is an example of a VFET device structure that prevents a reduction in cell width to achieve an optimized VFET cell architecture.

[0007] Therefore, there is a need for a VFET cell with a reduced cell width and its design method to overcome the aforementioned drawbacks of VFET cells. Summary of the Invention

[0008] Various embodiments of the present invention relate to semiconductor cell layout, semiconductor cell architecture, and methods for designing semiconductor cells comprising multiple VFET circuits formed by multiple VFETs.

[0009] These embodiments can provide an optimized VFET cell architecture with a reduced cell width, as well as a method for designing the improved VFET cell architecture.

[0010] According to an embodiment, a VFET cell is provided that implements a vertical field-effect transistor (VFET) circuit on a plurality of gate grids. The VFET cell may include: a first circuit including at least one VFET and provided on at least one gate grid; and a second circuit including at least one VFET and provided on at least one gate grid formed on the left or right side of the first circuit, wherein the gate of the VFET of the first circuit is configured to share the gate signal or source / drain signal of the VFET of the second circuit, and the first circuit is an (X-1) contact polypitch (CPP) circuit, which is (X-1)CPP wide and is derived from an X-CPP circuit, the X-CPP circuit being X-CPP wide and performing the same logic function as the (X-1)CPP circuit, where X is an integer greater than 1.

[0011] According to an embodiment, a vertical field-effect transistor (VFET) cell implementing a flip-flop with a reset input is provided. The flip-flop includes a plurality of circuits formed consecutively and uniformly spaced on gate grids 1 to 24 in the VFET cell, wherein the first gate grid provides a single-fin flip-flop inverter, wherein gate grids 2 to 6 provide a flip-flop stage circuit configured to receive a flip-flop input signal, a data signal, a flip-flop enable signal, and an inverted flip-flop enable signal, wherein gate grids 7 to 11 provide a master latch, wherein gate grids 12 and 13 provide a dual-fin clock inverter, wherein gate grid 14 provides an output circuit including a single-fin inverter, wherein gate grids 15 to 17 provide a slave data path circuit configured to receive a reset signal from the master latch, wherein gate grids 18 and 19 provide a master data path circuit configured to receive a reset signal from the slave latch, and wherein gate grids 20 to 24 provide a slave latch.

[0012] According to an embodiment, a vertical field-effect transistor (VFET) cell is provided in which a scan flip-flop including multiple circuits is implemented on gate grids 1 to 19. Gate grids 1 to 19 are formed consecutively and uniformly spaced in the VFET cell. The first gate grid provides a single-fin scan inverter. Gate grids 2 to 5 provide scan stage circuitry configured to receive a scan input signal, a data signal, a scan enable signal, and an inverted scan enable signal. Gate grids 6 to 9 provide a master latch. Gate grids 10 and 11 provide dual-fin clock inverters. Gate grid 12 provides a master data path circuitry including a single-fin inverter. Gate grids 13 to 16 provide slave latches. Gate grids 17 and 18 provide slave data path circuitry including dual-fin inverters. Gate grid 19 provides an output circuitry including a single-fin inverter.

[0013] According to an embodiment, a scan trigger circuit formed by a plurality of vertical field-effect transistors (VFETs) is provided. The scan trigger may include: a scan stage circuit configured to receive at least one scan input signal, at least one data signal, at least one scan enable signal, and at least one inverted scan enable signal; a master latch including a first inverter configured to receive the output signal of the scan stage circuit, a master data path circuit configured to receive the output signal of the first inverter and at least one reset signal, and a second inverter configured to receive the output signal of the master data path circuit, the output node of the second inverter being connected to the output node of the first inverter; a slave latch including a third inverter configured to receive the output signal of the first data path circuit, a slave data path circuit configured to receive the output signal of the third inverter and at least one reset signal, and a fourth inverter configured to receive the output signal of the slave data path circuit, the output node of the fourth inverter being connected to the output node of the third inverter; and an output circuit configured to receive the output signal of a second data path circuit.

[0014] According to an embodiment, a method is provided for designing a VFET cell that implements a vertical field-effect transistor (VFET) circuit comprising multiple circuits on multiple gate grids. The method may include: placing two circuits having the same net adjacent to each other in the VFET cell, wherein the gate signal or source / drain signal of one circuit is shared by the gate or source / drain signal of the other circuit, wherein one of the two circuits is an X-CPP wide X-contact polypitch (CPP) circuit in the VFET cell, where X is an integer greater than 1; changing the X-CPP circuit to a (X-1)-CPP circuit, and removing a gate structure corresponding to a gate grid occupied by the X-CPP circuit; and modifying the internal circuit wiring of at least one of the (X-1)-CPP circuit and the other circuit such that the gate signal or source / drain signal of the other circuit is shared as the gate signal of the (X-1)-CPP circuit. Attached Figure Description

[0015] The above and other aspects of the inventive concept will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0016] Figure 1A The layout of a VFET cell, in which a dual-fin inverter is formed on two gate structures, is shown according to the relevant technology;

[0017] Figure 1B A schematic diagram of an inverter that can be formed from one PMOS and one NMOS is shown;

[0018] Figure 1CA schematic diagram of an inverter that can be formed from two PMOS and two NMOS is shown;

[0019] Figure 2A The layout of a VFET cell with three dual-fin inverters placed discontinuously apart according to the relevant technology is shown;

[0020] Figure 2B The layout of a VFET cell, in which three dual-fin inverters are arranged sequentially and their bottom source / drain regions are merged, is shown according to one embodiment.

[0021] Figure 3A The layout of two dual-fin inverters placed adjacent to each other according to one embodiment and a VFET cell with the gate layer cutout formed therebetween removed is shown.

[0022] Figure 3B A VFET cell is shown according to one embodiment, in which a single-fin inverter and a dual-fin inverter are placed adjacent to each other such that the gate of the single-fin inverter shares the gate signal of the dual-fin inverter.

[0023] Figures 4A to 4D A VFET cell with a reduced number of gate structures is shown according to one embodiment, and steps for sharing gate signals and source / drain signals among VFETs in the VFET cell;

[0024] Figure 5 A schematic diagram of a multiplexer formed by multiple VFET circuits according to one embodiment is shown;

[0025] Figures 6A to 6D A VFET cell layout for an implementation multiplexer according to one embodiment is shown, wherein gate signals and source / drain signals are shared;

[0026] Figures 7A to 7D The VFET arrangement that needs to be avoided according to the embodiment is shown;

[0027] Figure 8 A schematic diagram of a scan-enable flip-flop (SDFFRPQ circuit) with a reset input, formed by a plurality of VFETs, is shown according to one embodiment;

[0028] Figures 9A to 9C A VFET cell layout for implementing an SDFFRPQ circuit according to an embodiment is shown, wherein at least one gate signal and at least one source / drain signal are shared between sub-circuits;

[0029] Figure 10 A schematic diagram of a scan-enabled trigger circuit (SDFFQ circuit) formed by a plurality of VFETs according to one embodiment is shown;

[0030] Figures 11A to 11C A VFET cell layout for implementing an SDFFQ circuit according to an embodiment is shown, wherein at least one gate signal and / or at least one source / drain signal is shared between sub-circuits;

[0031] Figure 12 A method for designing a VFET cell for a VFET circuit according to one embodiment is shown; and

[0032] Figure 13 A block diagram of a computing device comprising a VFET cell architecture designed according to an embodiment is shown. Detailed Implementation

[0033] Various embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. These embodiments are exemplary and can be implemented in many different forms, and should not be construed as limiting the inventive concept. Rather, these embodiments are provided merely to make this disclosure comprehensive and complete, and to fully convey the inventive concept to those skilled in the art. In the drawings, the dimensions and relative dimensions of various layers and regions may be enlarged for clarity; therefore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of particular components or elements. Consequently, the specific structural and functional details disclosed herein should not be construed as limiting, but merely as a representative basis for teaching those skilled in the art to use the methods and structures of the embodiments in different ways.

[0034] The embodiments provided herein are not excluded from being associated with one or more features of another example or embodiment, whether also provided herein or not but consistent with the inventive concept. For example, even if a matter described in a particular embodiment is not described in a different embodiment, it may be understood to be related to or in combination with a different embodiment, unless otherwise mentioned in its description.

[0035] For the purposes described below, the terms “upper,” “lower,” “top,” “bottom,” “left,” and “right,” and their derivatives, may be used in relation to the disclosed structure based on context, as they are oriented in the accompanying drawings. The same numbers in different drawings may denote the same structural parts or elements.

[0036] It should be understood that when a component or layer is referred to as "on another component or layer," "connected to," or "coupled to" another component or layer, it can be directly on, connected to, or coupled to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0037] As used herein, the term "and / or" includes any and all combinations of one or more related listed items. When an expression such as "at least one" is used before a list of elements, the entire list of elements is modified, without modifying any individual element within the list. Therefore, for example, "at least one of A, B, or C" and "A, B, and / or C" both mean A, B, C, or any combination thereof. When an expression such as "at least one" is used before a list of elements, the entire list of elements is modified, without modifying any individual element within the list.

[0038] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0039] Figure 2A The layout of a VFET cell, in which three dual-fin inverters are placed discontinuously apart according to the relevant technology, is shown. Figure 2B The layout of a VFET cell, according to one embodiment, is shown, in which three dual-fin inverters are arranged sequentially and their bottom source / drain regions are merged.

[0040] Notice, Figure 2A , Figure 2B The remaining figures below are top views of the VFET cell layout, therefore, the PMOS and NMOS located beneath the contact structure or via are not shown. Figure 1A The indications of PMOS and NMOS in the cell layout will be omitted. It should also be noted that, for the sake of brevity, gate wiring, connections between contact structures, metal lines, and vias have been omitted in these figures. Furthermore, many layouts have the same VFET device structure; therefore, identical or repeated reference characters have been omitted.

[0041] refer to Figure 2A and Figure 2B The VFET unit 20A contains three dual-fin inverters 210, 220, and 230, which are placed separately. Figure 2A The VFET cells 20B are converted into dual-fin inverters 210, 220, and 230, which are rearranged to be sequentially placed in the cell width direction. Figure 2B With this arrangement, the bottom source / drain regions of the dual-fin inverters 210, 220 and 230 can be combined to share a power signal or a ground signal.

[0042] Here, note that the aforementioned arrangement of the dual-fin inverters 210, 220, and 230, as well as the merging of the bottom source / drain regions RX, are possible when all these bottom source / drain regions RX are connected to the same power supply or the same ground source. The structure of each of the dual-fin inverters 210, 220, and 230 is similar to... Figure 1A The structure of the dual-fin inverter 100 is basically the same as that of the others, so its description is omitted here.

[0043] When merging the bottom source / drain regions RX, the gate layer cutout CT between the dual-fin inverters 210, 220, and 230 can be removed first because there can be a zero-diffusion break (ZDB) between two adjacent VFET devices in the cell, unlike lateral FET devices with single or double diffusion breaks. Then, the bottom source / drain regions RX of adjacent VFETs are merged. Therefore, by merging the bottom source / drain regions connected to the same power supply or ground source, it is possible to reduce the cell width of the VFET cell. However, it should be noted that the VFET cell 20 still has six gate structures PC for the rearrangement of the dual-fin inverters 210, 220, and 230. Therefore, merging the bottom source / drain regions of the VFET devices may not be sufficient to significantly reduce the cell width of the VFET cell.

[0044] Figure 3A The diagram illustrates the layout of two dual-fin inverters placed adjacent to each other according to one embodiment, and a VFET cell with the gate layer cutout formed therebetween removed. Figure 3B A VFET cell is shown according to one embodiment, in which one fin inverter and two fin inverters are placed adjacent to each other such that the gate of one fin inverter shares the gate signals of the two fin inverters.

[0045] Similar to Figure 2B , Figure 3A The VFET cell 30A is shown to include dual-fin inverters 310 and 320 arranged sequentially in the cell width direction, with the gate layer cutout CT formed therebetween removed. However, compared to... Figure 2B different, Figure 3A The bottom source / drain regions RX1 of the dual-fin inverter 310 and RX2 of the dual-fin inverter 320 are not shown. They are combined to share the source / drain signal between adjacent VFETs of the dual-fin inverters 310 and 320. This is because the dual-fin inverters 310 and 320 are placed adjacent to each other not to combine their bottom source / drain regions, but to share the gate signal input to the gate of the VFET of the dual-fin inverter 320, as described below.

[0046] refer to Figure 3BBy changing the dual-fin inverter 310 in VFET cell 30A to a single-fin inverter 310-1 that can share the gate signal of the VFET in dual-fin inverter 320 as its gate signal, VFET cell 30B is generated from VFET cell 30A to reduce the cell size, i.e., the cell width. This change is possible because one of the two gate structures PC providing the dual-fin inverter 310 in VFET cell 30A can be removed to change the dual-fin inverter 310 to a single-fin inverter 310-1. By changing the dual-fin inverter 310 to a single-fin inverter 310-1, the gate of the VFET of the single-fin inverter 310-1 can use the gate signal input to the gate of the VFET in dual-fin inverter 320 through the gate contact structure CB formed on the gate structure PC next to the single-fin inverter 310-1.

[0047] Here, a VFET circuit, such as a single-fin inverter, that shares the gate signal or source / drain signal of another VFET circuit as its gate signal can refer to a VFET circuit that uses the gate signal or source / drain signal of another VFET circuit as its gate signal.

[0048] In addition, Figure 3B In the process, when one of the two gate structures PC is removed, the bottom source / drain region RX1 and the top source / drain contact structure CA1 in the VFET cell 30A are changed to a bottom source / drain region RX1-1 with a narrower width and a top source / drain contact structure CA1-1 with a narrower width, respectively.

[0049] However, it should be noted that in Figure 3B In the VFET cell 30B, when the single-fin inverter 310-1 and the dual-fin inverter 320 are connected to the power supply or ground through different connection structures (such as bottom source / drain regions and top source / drain contact structures), the bottom source / drain regions RX-1 and RX2 do not need to be combined. Therefore, as Figure 3B As shown, even though a gate structure PC can be removed because the single-fin inverter 310-1 can share the gate signal of the dual-fin inverter 320, the bottom source / drain region RX1-1 of the single-fin inverter 310-1 may not be merged with the bottom source / drain region RX2 of the dual-fin inverter 320. Furthermore, if the bottom source / drain regions RX1-1 and RX2 cannot be merged for the aforementioned reasons, the single-fin inverter 310-1 will have a narrow bottom source / drain region RX1-1 and a small top source / drain contact structure CA1-1, which are difficult to pattern when manufacturing the VFET cell 30B.

[0050] In both of the above embodiments, the VFET cell can be designed to allow the VFET device to use a merged bottom source / drain region. Figure 2Aand Figure 2B ), or share the gate signal of the adjacent VFET ( Figure 3A and Figure 3B However, the following embodiments allow two adjacent virtual VFETs to not only have merged bottom source / drain regions but also share a single VFET gate signal, thereby improving the optimization of the VFET cell structure by reducing the number of gate structures without causing issues like... Figure 3B The bottom source / drain region is narrow, like the bottom source / drain region RX1-1 in the middle.

[0051] Figures 4A to 4D A VFET cell with a reduced number of gate structures is shown according to one embodiment, and steps are described for sharing gate signals and source / drain signals among the VFETs in the VFET cell.

[0052] Figure 4A The diagram shows a VFET cell 40A in which a dual-fin inverter 410 is placed at a predetermined location in a plurality of circuits.

[0053] Figure 4B This illustrates a conversion of VFET cell 40A into VFET cell 40B, wherein the dual-fin inverter 410 in VFET cell 40A is moved to a position where the dual-fin inverter 410 can share inputs to another circuit 420 in VFET cell 40B. Figure 4D The gate signal of the VFET included in the dual-fin inverter 410 is used as its gate signal. Then, by removing one of the two gate structures PC and converting the bottom source / drain region RX1 and the top source / drain contact structure CA1 of the VFET in the dual-fin inverter 410 into the form shown in the figure. Figure 4B The bottom source / drain region RX1 and top source / drain contact structure CA1 of the VFET shown are replaced with a single-fin inverter 410-1. In this step, the components located in the dual-fin inverter 410 are removed. Figure 4A The right side of the gate layer cut CT, and also removes the PC formed in one of the two gate structures ( Figure 4A The gate contact structure CB on the circuit 420 is shared with the gate contact structure CB formed on the circuit 420. Figure 4D The single-fin inverter 410-1 will be placed next to the circuit 420 via the gate contact structure CB1 on the gate structure PC. By sharing the gate contact structure CB1, the single-fin inverter 410-1 can share the gate signal of the VFET input to the circuit 420 through the gate contact structure CB1 as its gate signal, as shown in the following reference. Figure 4D To be described again.

[0054] Figure 4CThe diagram illustrates the conversion of VFET cell 40B into VFET cell 40C, where the two top source / drain contact structures CA1-1 of the individual VFETs (i.e., PMOS and NMOS) of the single-fin inverter 410-1 are replaced with a single extended top source / drain contact structure CA1-2 with an extended length, making it easier to pattern during the fabrication of VFET cell 40C. Due to the inverter's circuit structure, where the drains of the PMOS and NMOS are connected to each other, as... Figure 1B As shown, this configuration is possible. Furthermore, since the two top source / drain contact structures CA1-1 are converted into a single extended top source / drain contact structure CA1-2, the VFET cell 40C only requires one via V1-1 connected to the single extended top source / drain contact structure CA1-2, instead of two vias V1 connected to the two top source / drain contact structures CA1-1, to send the output signal of the single-fin inverter 410-1.

[0055] Figure 4D The diagram illustrates a VFET cell 40C being converted into a VFET cell 40D, where a single-fin inverter 410-1 shares the gate signal of the VFET included in circuit 420 as its gate signal, with circuit 420 positioned to the right next to the single-fin inverter 410-1. Furthermore, in VFET cell 40D, a dual-fin inverter 430, discontinuously separated from the dual-fin inverter 410, is moved to be positioned to the left next to the single-fin inverter 410-1, such that the bottom source / drain region RX1-1 of the single-fin inverter 410-1 can be merged with the bottom source / drain region RX of the dual-fin inverter 430 in VFET cell 40D to be connected to a common ground source.

[0056] Note that in VFET cell 40D, it is possible to merge the bottom source / drain regions RX-1 and RX between the single-fin inverter 410-1 and the dual-fin inverter 430, because both the single-fin inverter 410-1 and the dual-fin inverter 430 are connected to the power and ground sources via the same connection structure (i.e., their respective bottom source / drain regions). For this purpose, the bottom source / drain region RX1-1 of the single-fin inverter 410-1 may not be merged with the bottom source / drain region of circuit 420 (if any), which uses the top source / drain contact structure CA2 as the power and ground connector.

[0057] Therefore, according to this embodiment, the single-fin inverter 410-1 shares the gate signal of the VFET of the circuit 420 placed to its right as its gate signal. Furthermore, its bottom source / drain region RX1-1 is merged with the bottom source / drain region of the dual-fin inverter 430 to its left, thereby... Figures 2A-2B and Figures 3A-3BCompared to the previous embodiment, the VFET cell can be optimized better.

[0058] Figure 5 A schematic diagram of a multiplexer formed by multiple VFET circuits according to one embodiment is shown.

[0059] refer to Figure 5 The multiplexer 50 includes an input circuit 510 formed by inverters, a cross-coupled circuit 520 in which four PMOS and four NMOS transistors are cross-coupled, and an output circuit 530 formed by another inverter. The multiplexer 50 is configured to receive a select / non-select signal S at the input circuit 510, receive input signals A and B and the select / non-select signal S at the cross-coupled circuit 520, and transmit an output signal Y at the output circuit 530.

[0060] Figures 6A to 6D A VFET cell layout for an implementation multiplexer according to one embodiment is shown, wherein gate signals and source / drain signals are shared. Figures 6A to 6D The VFET cell layout implementation shown Figure 5 The multiplexer 50 shown.

[0061] refer to Figure 6A The multiplexer unit 600A provides nine gate grids (or strips) G1 to G9 that are continuously formed and uniformly spaced therein. Figure 5 Multiplexer 50. Each grid corresponds to Figure 1A The gate structure PC shown includes two sub-gates, one for PMOS and one for NMOS, respectively, in the vertical direction. In the multiplexer cell 600A, the input circuit 510 of the multiplexer 50 is provided as a dual-fin inverter on gate grids G1 and G2, and the cross-coupling circuit 520 of the multiplexer 50 is provided on gate grids G3 to G7. Additionally, the output circuit 530 of the multiplexer 50 is provided as a dual-fin inverter on gate grids G8 and G9 in the multiplexer cell 600A.

[0062] from Figure 6A As noted in other cell layouts mentioned below, the cell width of the VFET cell is measured in units of the aforementioned gate grid and / or contacted poly pitch (CPP). One CPP represents the horizontal length between the left edge (right edge or center) of the gate grid and the left edge (right edge or center) of the adjacent gate grid. Therefore, when including the length occupied by the gate layer cutouts formed on the left and right sides of the multiplexer cell 600A, the multiplexer cell 600A is nine CPP wide. Furthermore, a dual-fin inverter provided on two gate grids G1 and G2 can be referred to as a 2-CPP inverter, and a single-fin inverter can be referred to herein as a 1-CPP inverter.

[0063] Figure 6A The multiplexer unit 600A also includes rails M1 and M2 connected to power and ground respectively, multiple bottom source / drain regions RX1 connected to rails M1 and M2, multiple bottom source / drain regions RX2 connected to the bottom source / drain of the VFET, multiple top source / drain contact structures CA1 connected to rails M1 or M2, and multiple top source / drain contact structures CA2 connected to the top source / drain of the VFET. Furthermore, the multiplexer unit 600A includes multiple gate structures CB1 for receiving gate signals from the VFET and multiple gate layer cutouts CT disposed between and on the sides of the nine gate grids.

[0064] Figure 6B Multiplexer unit 600B is shown, which is derived from multiplexer unit 600A by rearranging the gates of input circuit 510 and cross-coupled circuit 520 and removing the gate layer cutout CT formed between input circuit 510 and cross-coupled circuit 520. Specifically, in the cross-coupled circuit 520 of multiplexer unit 600B, the gate structure CB2 on gate grid G3 is modified to receive the gate signal input through the gate structure CB1 on gate grid G4 in multiplexer unit 600A, so that the gate signal input through the modified gate structure CB2 on gate grid G3 can be shared with input circuit 510. For this gate sharing, the gate layer cutout CT between gate grids G2 and G3 in multiplexer unit 600A is removed to achieve gate rewiring between input circuit 510 and cross-coupled circuit 520.

[0065] Figure 6C Multiplexer unit 600C is shown, which is derived from multiplexer unit 600B by changing the dual-fin inverter of input circuit 510 to a single-fin inverter. Specifically, the dual-fin inverter of input circuit 510 provided on gate grids G1 and G2 is changed to a single-fin inverter provided on gate grid G1, which shares the gate signal of cross-coupled circuit 520 input through gate structure CB2 now formed on gate grid G2 as its gate signal. Furthermore, the two top source / drain contact structures CA2 provided on gate grids G1 and G2 in multiplexer unit 600B are changed to a single extended top source / drain contact structure CA2-1. With this unit conversion, multiplexer 50 is now implemented on eight gate grids G1 to G8 by reducing one gate grid from the nine gate grids of multiplexer units 600A and 600B. However, as in Figure 4C and Figure 4DAs shown in the previous embodiment, because the dual-fin inverter of the input circuit 510 is converted into a single-fin inverter, the multiplexer unit 600C now has a narrow bottom source / drain region RX1-1 for the input circuit 510.

[0066] Figure 6D Multiplexer unit 600D is shown, which is derived from multiplexer unit 600C to accommodate the narrow bottom source / drain region RX1-1 of multiplexer unit 600C. Considering that the narrow bottom source / drain region RX1-1 is connected to rails M1 and M2, the output circuit 530, which also has a bottom source / drain region RX1 connected to rails M1 and M2, is now repositioned to the left of the input circuit 510, such that the narrow bottom source / drain region RX1-1 of the input circuit 510 can be merged with the bottom source / drain region RX of the output circuit 530 to form a merged bottom source / drain region RX1-2.

[0067] As described above, this embodiment enables the removal of at least one gate structure by sharing at least one gate signal among adjacent circuits in a multiplexer cell formed by multiple VFETs, allowing the multiplexer cell to be designed with a smaller number of gate grids and CPP, i.e., a reduced cell width. Furthermore, the multiplexer cell designed according to this embodiment facilitates the patterning of the merged bottom source / drain regions and extended top source / drain contact structures of the VFETs.

[0068] The inventive concept implemented in the above embodiments of the multiplexer unit is also applicable to trigger circuits having a certain number of inverters and cross-coupled circuits as described below.

[0069] As noted from the above embodiments, when designing a VFET circuit, certain types of VFET arrangements need to be avoided in the VFET circuit to prevent an increase in the area of ​​the VFET cells implementing the VFET circuit, and to allow for the sharing of at least one gate signal or at least one source / drain between the VFETs in the VFET cells. For example, Figures 7A to 7D This VFET arrangement, which needs to be avoided according to the embodiment, is shown.

[0070] Figure 7A The diagram illustrates a first VFET arrangement to be avoided, in which the drain terminals of an even number of VFETs of the same polarity connected in series (e.g., two NMOS N1 and N2) are connected to the drain terminals of one or an odd number of VFETs of the same polarity connected in series (e.g., one NMOS N3), wherein the source terminals of the even number of VFETs and the source terminals of one or an odd number of VFETs are connected to the same power supply or ground source. Note that this VFET arrangement is also applicable to PMOS components included in a circuit.

[0071] Figure 7B The second VFET arrangement to be avoided is shown, in which three or more PMOS P1, P2 and P3 (or NMOS) are connected in series from the output node of the circuit;

[0072] Figure 7C A third VFET arrangement to be avoided is shown, in which, when implemented in a VFET cell, the power or ground source is connected to the circuit only through the bottom source / drain regions of PMOS P1 to P4 and NMOS N1 to N4.

[0073] Figure 7D The fourth VFET arrangement to be avoided is shown, in which the transmission gate is included in a sub-circuit. The transmission gate is a combination of a PMOS and an NMOS connected in parallel, such that only the drain and source of the two VFETs are connected together.

[0074] Therefore, the VFET circuits and VFET cells described in the embodiments herein are designed to avoid at least one of the VFET arrangements listed above.

[0075] Figure 8 A schematic diagram of a scan-enabled trigger with a reset input (hereinafter referred to as the "SDFFRPQ circuit") formed by a plurality of VFETs according to one embodiment is shown.

[0076] refer to Figure 8 The SDFFRPQ circuit 80 includes a scan inverter 810, a clock inverter 820, a scan stage circuit 830, a master latch 840, a master data path circuit 850, a slave latch 860, a slave data path circuit 870, and an output circuit 880.

[0077] Although the main latch 840 together with the main data path circuit 850 can be referred to as the main latch, for the purposes of description, these two circuits are referred to below (including regarding...). Figures 9A to 11C The descriptions are given differently. Similarly, although latch 860 together with data path circuit 870 can be referred to as a slave latch, for the purposes of description, these two circuits are referred to below (including...). Figures 9A to 11C It was named differently.

[0078] The scan stage circuit 830 includes a first group of two PMOS and two NMOS transistors connected in series between a power source and a ground source to receive data signal D1, scan enable signal SE, inverted scan enable signal nSE, and data signal D2, respectively. The drains of the PMOS transistors and NMOS transistors connected in series in the first group are connected to the input node of the master latch 840.

[0079] The scan stage circuit 830 also includes a second set of two PMOS and two NMOS transistors connected in series between the power supply and ground source to receive the scan input signal S1, the inverted scan enable signal nSE, the scan enable signal SE, and the scan input signal SI, respectively. The drains of the PMOS transistors and NMOS transistors connected in series in the second set are also connected to the input node of the master latch 840.

[0080] The main latch 840 includes a tri-state inverter 841 that receives the output signal of the scan stage circuit 830, and a tri-state inverter 842 whose output node is connected to the output node of the tri-state inverter 841. Each of the tri-state inverters 841 and 842 receives a clock signal CK and an inverted clock signal nCK.

[0081] According to one embodiment, the main data path circuit 850 for transmitting the output signal of the master latch 840 to the slave latch 860 is configured via a NOR circuit consisting of two PMOS and two NMOS transistors. Here, one PMOS and one NMOS transistor receive a reset signal R, and the other PMOS and the other NMOS transistor are gated to the output nodes of the tri-state inverters 841 and 842 of the master latch 840 to receive the output signal of either tri-state inverter 841 or 842 as their gate input signals. The two PMOS transistors are connected in series, the source of one PMOS transistor is connected to a power supply, and the drain of the other PMOS transistor is connected to the drains of the two NMOS transistors connected in parallel between the output node of the main data path circuit 850 and the ground source. The main data path circuit 850 transmits its output signal to the slave latch 860 and also feeds it back to the input node of the tri-state inverter 842 of the master latch 840.

[0082] The latch 860 includes a tri-state inverter 861 that receives the output signal from the main data path circuit 850, and a tri-state inverter 862 whose output node is connected to the output node of the tri-state inverter 861. Each of the tri-state inverters 861 and 862 receives a clock signal CK and an inverted clock signal nCK.

[0083] According to one embodiment, the slave data path circuit 870, which transmits the output signal from latch 860 to output circuit 880, is also configured via a NOR circuit consisting of two PMOS and two NMOS transistors. Here, one PMOS and one NMOS receive a reset signal R, and the other PMOS and the other NMOS are gated to the output nodes of tri-state inverters 861 and 862 of latch 860 to receive the output signal of tri-state inverter 861 or 862 as their gate input signal. The two PMOS transistors are connected in series, the source of one PMOS is connected to a power supply, and the drain of the other PMOS is connected to the drains of the two NMOS transistors connected in parallel between the output node of slave data path circuit 870 and ground. Slave data path circuit 870 transmits its output signal to output circuit 880 and also feeds back to the input node of tri-state inverter 862 of latch 860.

[0084] The output circuit 880 is configured using an inverter.

[0085] According to this embodiment, Figure 8 The SDFFRPQ circuit 80 shown is designed to not include Figures 7A to 7D Any of the VFET arrangements listed above shown may result in an increase in cell area in the VFET cell, such that at least one gate signal and at least one source / drain signal can be shared in the SDFFRPQ cell implementing the SDFFRPQ circuit 80.

[0086] Figures 9A to 9C A VFET cell layout for implementing an SDFFRPQ circuit according to an embodiment is shown, wherein at least one gate signal and at least one source / drain signal are shared between sub-circuits. Figures 9A to 9C VFET cell layout implementation Figure 8 The SDFFRPQ circuit 80 shown is illustrated.

[0087] refer to Figure 9A The SDFFRPQ cell 900A provides 27 gate grids G1 to G27 that are continuously formed and uniformly spaced therein. Figure 8 The SDFFRPQ circuit 80. Therefore, when considering the length occupied by the gate layer cutouts formed on the left and right sides of the SDFFRPQ cell 900A, the SDFFRPQ cell 900A is 27 CPP wide.

[0088] form Figure 8The SDFFRPQ circuit 80 is arranged in the SDFFRPQ cell 900A as follows: Scan inverter 810 is configured via bifin inverters on gate grids G1 and G2, and scan stage circuitry 830 is provided on gate grids G3 through G7. Master latch 840 is provided on gate grids G8 through G12, and master data path circuitry 850 is provided on gate grids G13 through G15. Slave latch 860 is provided on gate grids G16 through G20, and slave data path circuitry 870 is provided on gate grids G21 through G23. Clock inverter 820 is configured via bifin inverters on gate grids G24 and G25, and output circuitry 880 is also configured via bifin inverters on gate grids G26 and G27.

[0089] Figure 9A The SDFFRPQ cell 900A is also shown to include rails M1 and M2 connected to power and ground respectively, multiple bottom source / drain regions RX1 connected to rails M1 or M2, multiple bottom source / drain regions RX2 connected to the bottom source / drain of the VFET forming the SDFFRPQ circuit 80, multiple top source / drain contact structures CA1 connected to rails M1 or M2, and multiple top source / drain contact structures CA2 connected to the top source / drain of the VFET. Furthermore, the SDFFRPQ cell 900A includes multiple gate contact structures CB for receiving gate signals from the VFET and multiple gate layer cutouts CT disposed between and on the sides of the 27 gate grids.

[0090] Figure 9B The SDFFRPQ cell 900B is shown, which is derived from the SDFFRPQ cell 900A by repositioning the clock inverter 820, output circuit 880, and slave data path circuit 870 next to the master latch 840. Furthermore, the master data path circuit 850 and slave latch 860 are repositioned next to the slave data path circuit 870. Therefore, in the SDFFRPQ cell 900B, the scan inverter 810, scan stage circuit 830, master latch 840, clock inverter 820, output circuit 880, slave data path circuit 870, master data path circuit 850, and slave latch 860 are located sequentially on the gate grids G1 to G27.

[0091] Here, the main data path circuit 850 and the slave data path circuit 870, which are respectively placed on gate grids G13 to G15 and G21 to G23 in SDFFRPQ cell 900A, are now sequentially arranged adjacent to each other on gate grids G17 to G22 in SDFFRPQ cell 900B. Specifically, in SDFFRPQ cell 900A, the main data path circuit 850 (with a slave latch 860 in between), which is located to the left of the slave data path circuit 870, is now placed to the right of the slave data path circuit 870 and to the left of the slave latch 860, and its internal wiring is changed so that the main data path circuit 850 can share the gate signal of the adjacent slave data path circuit 870 as its gate signal, and the slave latch 860 can share the source / drain signal of the main data path circuit 850 as its gate signal, as will be referred to later. Figure 9C As stated above.

[0092] Furthermore, the clock inverter 820 and output circuit 880, which were placed on gate grids G24 to G27 in the SDFFRPQ cell 900A, are now placed on gate grids G13 to G16 between the master latch 840 and the slave data path circuit 870. This allows the two inverter circuits to each have a bottom source / drain region merged with the adjacent master latch 840 and to share the source / drain signal of the slave data path circuit 870, as referenced below. Figure 9C As stated above.

[0093] Figure 9C The SDFFRPQ unit 900C is shown, which... Figure 9A and Figure 9B The dual-fin inverters in each of the scan inverters 810 and output circuit 880 shown are converted from single-fin inverters to those in the SDFFRPQ cell 900B. Through this conversion, the scan inverter 810 (now a single-fin inverter) can share the gate signal of the VFET of the scan stage circuit 830 located to its right as its gate signal, which is the scan enable signal SE commonly input to both the scan inverter 810 and the scan stage circuit 830. Here, the gate signal shared by the scan inverter 810 and the scan stage circuit 830 (i.e., the scan enable signal SE) can be input to the VFET formed on the gate grid G2 of the scan stage circuit 830 in the SDFFRPQ cell 900C. Furthermore, the output circuit 880 (also now a single-fin inverter) can share the source / drain signal from the data path circuit 870 as its gate signal, as... Figure 8As shown. It should be noted here that since the gate of the output circuit 880 can receive its gate signal from the adjacent slave data path circuit 870 as described above, the dual-fin inverter of the output circuit 880 can be changed to a single-fin inverter, i.e., a 1-CPP inverter, without the need for a separate gate structure.

[0094] By changing the dual-fin inverter in scan inverter 810 and output circuit 880 to a single-fin inverter to share gate and source / drain signals with adjacent scan stage circuit 830 and data path circuit 870 respectively, the two gate layer cutouts CT between scan inverter 810 and scan stage circuit 830 and between output circuit 880 and data path circuit 870 can be removed for gate rewiring, as... Figure 9C As shown.

[0095] By making the aforementioned changes to the scanning inverter 810 and the output circuit 880, two gate grids and two CPPs can be reduced in the SDFFRPQ cell 900C.

[0096] Figure 9C Furthermore, to prevent narrow bottom source / drain regions in the SDFFRPQ cell 900C and to facilitate semiconductor patterning, the bottom source / drain region RX1 of the single-fin inverter of the output circuit 880, formed at gate grid G14 and connected to rails M1 and M2, is merged with the bottom source / drain region RX1 of the adjacent clock inverter 820, formed at gate grids G12 and G13 and connected to the same rails M1 and M2. Therefore, the clock inverter 820 and the output circuit 880 now share a common power supply signal and ground signal through the merged bottom source / drain regions.

[0097] Furthermore, since the main data path circuit 850 and the slave data path circuit 870 are placed adjacent to each other in opposite positions in the SDFFRPQ cell 900C, the NOR circuit of the main data path circuit 850 provided on the three gate grids G20 to G22 (3-CPP NOR) in the SDFFRPQ cell 900B is changed to a NOR circuit on two gate grids G18 and G19 (2-CPP NOR). This is because the 2-CPP NOR circuit can share the reset signal R received at the adjacent 3-CPP NOR circuit of the slave data path circuit 870 as its gate signal. Furthermore, the slave latch 860 placed to the right of the main data path circuit 850 can share the source / drain signal of the main data path circuit 850 as its gate signal. Figure 8 As shown, this reduces another gate grid and one CPP in the SDFFRPQ cell 900C.

[0098] The aforementioned change from a 3-CPP NOR circuit to a 2-CPP NOR circuit in the main data path circuit 850, to share the gate signal (reset signal R) of the slave data path circuit 870 and the source / drain signal of the shared 2-CPP NOR as the gate signal of the slave latch 860, allows the removal of two gate layer cutouts CT between the slave data path circuit 870 and the main data path circuit 850, and between the main data path circuit 850 and the slave latch 860, for gate rewiring. Figure 9C As shown.

[0099] By making the aforementioned changes to the main data path circuit 850 and the slave data path circuit 870, one gate grid and one CPP can be reduced in the SDFFRPQ cell 900C.

[0100] In summary, according to this embodiment, the SDFFRPQ cell 900A having 27 gate grids and 27 CPPs can be converted into the SDFFRPQ cell 900C having 24 gate grids and 24 CPPs by reducing three gate grids and three CPPs.

[0101] As described above, this embodiment enables the design of an SDFFRPQ cell formed by multiple VFETs to have a smaller number of gate grids and CPP, i.e., a reduced cell width. Furthermore, the SDFFRPQ cell designed according to this embodiment makes it easier to pattern the merged bottom source / drain regions and extended top source / drain contact structures of the VFETs.

[0102] A similar transformation of the VFET cell is now applied to another trigger circuit.

[0103] Figure 10 A schematic diagram of a scan-enabled trigger circuit (hereinafter referred to as the "SDFFQ circuit") formed by a plurality of VFETs according to one embodiment is shown.

[0104] refer to Figure 10 The SDFFQ circuit 1000 includes a scan inverter 1010, a clock inverter 1020, a scan stage circuit 1030, a master latch 1040, a master data path circuit 1050, a slave latch 1060, a slave data path circuit 1070, and an output circuit 1080.

[0105] The scan stage circuit 1030 includes a first group of two PMOS and two NMOS connected in series between the power supply and ground source to receive the data signal D1, the scan enable signal SE, the inverted scan enable signal nSE, and the data signal D2, respectively. The drains of the PMOS and NMOS connected in series in the first group are connected to the input node of the master latch 1040.

[0106] The scan stage circuit 1030 also includes a second group of two PMOS and two NMOS connected in series between the power supply and ground source to receive the scan input signal SI, the inverted scan enable signal nSE, the scan enable signal SE, and the scan input signal SI, respectively. The drains of the PMOS and NMOS connected in series in the second group are also connected to the input node of the master latch 1040.

[0107] The main latch 1040 includes a tri-state inverter 1041 that receives the output signal from the scan stage circuit 1030, and a tri-state inverter 1042 whose output node is connected to the output node of the tri-state inverter 1041. Each of the tri-state inverters 1041 and 1042 is gated to a clock signal CK and an inverted clock signal nCK. The output node of the tri-state inverter 1042 is connected to the output node of the tri-state inverter 1041.

[0108] According to one embodiment, the main data path circuit 1050 for transmitting the output signal of the master latch 1040 to the slave latch 1060 is configured via an inverter. This inverter is gated to the output nodes of the tri-state inverters 1041 and 1042 of the master latch 1040 to receive the output signal of either tri-state inverter 1041 or 1042 as its gate input signal. The main data path circuit 1050 transmits its output signal to the slave latch 1060 and also feeds it back to the input node of the tri-state inverter 1042 of the master latch 1040.

[0109] The latch 1060 includes a tri-state inverter 1061 that receives the output signal from the main data path circuit 1050, and a tri-state inverter 1062 whose output node is connected to the output node of the tri-state inverter 1061. Each of the tri-state inverters 1061 and 1062 is gated to a clock signal CK and an inverted clock signal nCK.

[0110] According to one embodiment, the slave data path circuit 1070, which transmits the output signal from latch 1060 to output circuit 1080, is configured via an inverter. This inverter is gated to the output nodes of tri-state inverters 1061 and 1062 of master latch 1060 to receive the output signal of either tri-state inverter 1061 or 1062 as its gate input signal. Slave data path circuit 1070 transmits its output signal to output circuit 1080 and also feeds it back to the input node of tri-state inverter 1062 of master latch 1060.

[0111] The output circuit 1080 is configured using an inverter.

[0112] According to this embodiment, the SDFFQ circuit 1000 is designed to not include Figures 7A to 7DAny of the VFET arrangements listed above shown may result in an increase in the cell width of the VFET cell, such that at least one gate signal and at least one source / drain signal can be shared in the SDFFQ cell implementing the SDFFQ circuit 100.

[0113] Figures 11A to 11C A VFET cell layout for implementing an SDFFQ circuit according to an embodiment is shown, wherein at least one gate signal and / or at least one source / drain signal is shared between sub-circuits. Figures 11A to 11C VFET cell layout implementation Figure 10 The SDFFQ circuit 1000 is shown.

[0114] refer to Figure 11A The SDFFQ cell 1100A provides 25 gate grids G1 to G25, which are continuously formed and uniformly spaced, including two dummy gate grids. Figure 10 The SDFFQ circuit 1000. Therefore, when considering the length occupied by the gate layer cutouts formed on the left and right sides of the SDFFPQ cell 1100A, the SDFFPQ cell 1100A is 25 CPP wide.

[0115] form Figure 10 The SDFFQ circuit 1000 is arranged in the SDFFQ cell 1100A as follows: Scan inverter 1010 is configured via bifin inverters on gate grids G1 and G2, and scan stage circuitry 1030 is provided on gate grids G3 through G7, where gate grid G5 is dummy. Master latch 1040 is provided on gate grids G8 through G12, where gate grid G10 is dummy, and master data path circuitry 1050 is configured via bifin inverters on gate grids G13 and G14. Slave latch 1060 is provided on gate grids G15 through G19, where gate grid G17 is dummy, and slave data path circuitry 1070 is configured via bifin inverters on gate grids G20 and G21. The output circuit 1080 is configured via dual-fin inverters on gate grids G22 and G23, and the clock inverter 1020 is also configured via dual-fin inverters on gate grids G24 and G25.

[0116] Figure 11AThe SDFFQ cell 1100A is also shown to include ground rails M1 and M2 connected to power and ground respectively, multiple bottom source / drain regions RX1 connected to ground rails M1 or M2, multiple bottom source / drain regions RX2 connected to the bottom source / drain of the VFET forming the SDFFQ circuit 1000, multiple top source / drain contact structures CA1 connected to ground rails M1 or M2, and multiple top source / drain contact structures CA2 connected to the top source / drain of the VFET. Furthermore, the SDFFQ cell 1100A includes multiple gate structures CB for receiving gate signals from the VFET, and multiple gate layer cutouts CT disposed between and on the sides of the 25 gate grids.

[0117] Figure 11B The SDFFQ cell 1100B is shown, which is derived from the SDFFQ cell 1100A by removing the three virtual gate grids G5, G10 and G17 in the SDFFQ cell 1100A and changing each of the dual-fin inverters of the scan inverter 1010 and the main data path circuit 1050 to a single-fin inverter, thereby reducing the number of gate grids and five CPPs.

[0118] Furthermore, in the SDFFQ cell 1100B, considering that the gate signals are shared with the adjacent scan stage circuit 1030 and slave latch 1060 respectively, when each of the dual-fin inverters of the scan inverter 1010 and the main data path circuit 1050 in the SDFFQ cell 1100A is changed to a single-fin inverter, the two gate layer cutouts CT between the scan inverter 1010 and the scan stage circuit 1030 and between the main data path circuit 1050 and the slave latch 1060 can be removed for gate rewiring.

[0119] Figure 11C The SDFFQ cell 1100C is shown, which is derived from the SDFFQ cell 1100B by repositioning the clock inverter 1020 to the left of the main data path circuit 1050 and changing the dual-fin inverter of the output circuit 1080 to a single-fin inverter to reduce another gate grid and a CPP. Therefore, in the SDFFQ cell 1100C, the scan inverter 1010, scan stage circuit 1030, main latch 1040, clock inverter 1020, main data path circuit 1050, slave latch 1060, slave data path circuit 1070, and output circuit 1080 are positioned on the gate grids G1 to G19 in this order.

[0120] With the aforementioned changes in the SDFFQ cell 1100C, the scan inverter 1010 (now a single-fin inverter) can share the gate signal of the VFET of the scan stage circuit 1030 located to its right as its gate signal. This gate signal is the common scan enable signal SE input to both the scan inverter 1010 and the scan stage circuit 1030. Here, the gate signal shared by the scan inverter 1010 and the scan stage circuit 1030 (i.e., the scan enable signal SE) can be input to the VFET formed on the gate grid G2 of the scan stage circuit 1030 in the SDFFQ cell 1100C. Furthermore, the source / drain signals of the single-fin inverter of the main data path circuit 1050 are shared as the gate signal of the VFET of the slave latch 1060 located to its right, as shown below. Figure 10 As shown. This single-fin inverter of the main data path circuit 1050 also features a narrow bottom source / drain region RX1-1 ( Figure 11B The combined bottom source / drain region RX1-2 is formed by merging the bottom source / drain region RX1 of the clock inverter 1020, which is a dual-fin inverter formed at the gate grids G10 and G11.

[0121] Furthermore, since the output circuit 1080 is gated to the output node of the data path circuit 1070, which is the source / drain of the VFET of the data path circuit 1070, the dual-fin inverter of the output circuit 1080 is changed to a single-fin inverter because it can receive its gate signal from the source / drain of the adjacent VFET of the data path circuit 1070 without requiring a separate gate structure. For this source / drain signal sharing, the gate layer cutout formed between the data path circuit 1070 and the output circuit 1080 is removed. This change from the output circuit 1080 to a single-fin inverter reduces the additional gate grid and CPP in the SDFFQ cell 1100C.

[0122] The single-fin inverter of the output circuit 1080 also has a combined bottom source / drain region RX1-3, which is obtained by merging its narrow bottom source / drain region formed at the gate grid G19 with the bottom source / drain region RX1 formed at the gate grids G17 and G18 of the data path circuit 1070.

[0123] In summary, according to this embodiment, the SDFFQ cell 1100A having 25 gate grids and 25 CPPs can be converted into the SDFFQ cell 1100C having 19 gate grids and 19 CPPs by reducing 6 gate grids and 6 CPPs.

[0124] As described above, this embodiment enables the design of an SDFFQ cell formed by multiple VFETs to have a smaller number of gate grids and CPP, i.e., a reduced cell width. Furthermore, the SDFFQ cell designed according to this embodiment facilitates the patterning of the merged bottom source / drain regions and the extended top source / drain contact structure of the VFETs.

[0125] Here, when circuits such as scan inverter 1010 and scan stage circuit 1030 share the same gate signal as described above, these two circuits are referred to as being in the same network. Furthermore, when circuits such as output circuit 1080 share the source / drain signal of another circuit such as data path circuit 1070, these two circuits are also referred to as being in the same network.

[0126] According to the above embodiments, the VFET cell of the VFET circuit can be designed through the following steps to reduce the cell area.

[0127] Figure 12 A method for designing a VFET cell for a VFET circuit according to one embodiment is illustrated. The VFET cell designed according to this embodiment implements a VFET circuit including multiple circuits on multiple gate grids in the VFET cell, each circuit being formed by one or more VFETs.

[0128] First, a VFET circuit is formed by arranging the VFET circuit in the cell width direction based on the signal path, such that the input circuit configured to receive the input signal of the VFET circuit is placed to the left of the output circuit configured to transmit the output signal of the VFET circuit (S100).

[0129] Second, in a VFET circuit with the same network, two circuits (where the gate signal or source / drain signal of one circuit is shared by the gate or source / drain of the other circuit) are placed adjacent to each other, where one of the two circuits is an X-CPP circuit, where X is an integer greater than 1, such as a dual-fin inverter or a 2-CPP inverter (S200). Another example of an X-CPP circuit could be... Figure 9B The 3-CPP NOR circuit of the main data path circuit 850 shown.

[0130] Third, the X-CPP circuit is changed to an (X-1)-CPP circuit, such as a single-fin inverter or a 1-CPP inverter, and a gate structure corresponding to a gate grid occupied by the X-CPP circuit is removed (S300).

[0131] Fourth, modify the internal circuit wiring in at least one of the (X-1)-CPP circuit and another circuit such that the gate signal or source / drain signal of the other circuit is shared by the (X-1)-CPP circuit as its gate signal (S400). An example of the (X-1)-CPP circuit could be... Figure 9C The 2-CPP NOR circuit of the main data path circuit 850 is shown.

[0132] Fifth, remove the gate layer cutout formed between the two circuits (S500).

[0133] Sixth, the top source / drain contact structure of the VFET, which forms a single-fin inverter provided on only one gate grid, is merged to form an extended top source / drain contact structure (S600).

[0134] Seventh, a circuit with a narrow bottom source / drain region (which is formed on only one gate grid and connected to a power or ground source) is placed next to another circuit with a bottom source / drain region formed on one or more gate grids and connected to the same power or ground source, so that the two bottom source / drain regions can be merged (S700).

[0135] Eighth, merge the bottom source / drain regions of the two circuits placed adjacent to each other in step seven (S800). Here, the circuit with a narrow bottom source / drain region can be a (X-1)-CPP circuit.

[0136] Although the above steps are described in sequence, the concept of the present invention is not limited thereto, at least because the order of these steps can be changed, or one or more of these steps can be omitted depending on the design choice.

[0137] The steps or operations of the above methods can be embodied in computer-readable code on a computer-readable recording medium or transmitted via a transmission medium. A computer-readable recording medium is any data storage device capable of storing data that can subsequently be read by a computer system. Examples of computer-readable recording media include, but are not limited to, read-only memory (ROM), random-access memory (RAM), compact disc (CD)-ROM, digital versatile disc (DVD), magnetic tape, floppy disk, and optical data storage devices. Transmission media can include carrier waves transmitted via the Internet or various types of communication channels. Computer-readable recording media can also be distributed across network-coupled computer systems to store and execute computer-readable code in a distributed manner.

[0138] The VFET unit designed according to the above embodiments can be used in various components of the computing device described below.

[0139] refer to Figure 13 The computing device 1300 may include at least one controller, such as a microprocessor, a communication interface, an input interface, a storage device, and a buffer memory, wherein the VFET cell architecture described above may be applied.

[0140] The controller can control the operation of the computing device 1300. The communication interface is implemented to perform wireless or wired communication with external devices. The input interface is implemented to output data processed by the controller in the form of audio and / or video, and to receive input data. The storage device is implemented to store various data, including user data. The storage device can be an embedded multimedia card (eMMC), a solid-state drive (SSD), a universal flash storage (UFS) device, etc. The storage device can perform high-speed caching of the aforementioned data.

[0141] The buffer can temporarily store data for processing operations of the computing device 1300. For example, the buffer memory can be volatile memory, such as double data rate (DDR) synchronous dynamic random-access memory (SDRAM), low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), etc.

[0142] At least one component in a computing device may include at least one unit architecture provided according to the above embodiments. The above embodiments can be applied to any electronic device and system. For example, these embodiments can be applied to devices such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable camcorders, personal computers (PCs), server computers, workstations, laptops, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, etc.

[0143] The foregoing description is illustrative of the embodiments and should not be construed as limiting them. Although several embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the above embodiments without substantially departing from the inventive concept. Therefore, the inventive concept can be applied not only to the above embodiments of multiplexers and trigger circuits, but also to many other VFET circuits.

Claims

1. A VFET cell implementing a vertical field-effect transistor (VFET) circuit on multiple gate grids, the VFET cell comprising: A first circuit includes at least one VFET and is provided on at least one gate grid; as well as The second circuit includes at least one VFET and is provided on at least one gate grid formed on the left or right side of the first circuit. Wherein, the gate or source / drain of the VFET of the first circuit disposed on the first gate grid in the gate grid is configured to share the gate signal or source / drain signal input to the gate or source / drain of the VFET of the second circuit disposed on the second gate grid in the gate grid, and The first gate grid and the second gate grid are arranged adjacent to each other in the gate grid, and each of the first gate grid and the second gate grid is formed by a p-channel metal-oxide-semiconductor PMOS VFET and an n-channel metal-oxide-semiconductor NMOS VFET. Both the first circuit and the second circuit are logic circuits configured to perform logic functions.

2. The VFET cell of claim 1 further comprises a third circuit, the third circuit including at least one VFET and provided on at least one gate grid formed on the left or right side of the first circuit, the first circuit being located between the second circuit and the third circuit. in, The bottom source / drain regions of the VFET in the first circuit and the bottom source / drain regions of the VFET in the third circuit are combined and connected to a power supply or ground source.

3. The VFET unit according to claim 2, wherein, The second circuit includes a top source / drain contact structure of a VFET connected to a power supply or ground source, and In this case, the bottom source / drain region connected to the power supply or ground source is not formed on the gate grid of the VFET on which the second circuit is formed.

4. The VFET unit according to claim 2, wherein, The VFET circuit forms a multiplexer. The first circuit includes a 1-contact polycrystalline pitch CPP inverter, which includes a p-channel metal-oxide-semiconductor PMOS VFET and an n-channel metal-oxide-semiconductor NMOS VFET configured to receive a selection signal. The second circuit includes a cross-coupling circuit configured to receive the selection signal and the input signal. The third circuit includes a 2-CPP inverter, which includes at least one PMOS VFET and at least one NMOS VFET configured to transmit an output signal.

5. The VFET cell according to claim 4, wherein, The multiplexer is provided on the first to eighth gate grids that are continuously formed and uniformly spaced in the VFET cell. In this circuit, a 1-CPP inverter of the first circuit is provided on the third gate grid, a cross-coupled circuit of the second circuit is provided on the fourth to eighth gate grids, and a 2-CPP inverter of the third circuit is provided on the first gate grid and the second gate grid.

6. The VFET cell according to claim 1, wherein, The first circuit is a 1-CPP inverter, which includes: p-channel metal-oxide-semiconductor PMOS VFET and n-channel metal-oxide-semiconductor NMOS VFET; and A top source / drain contact structure is formed on the top source / drain regions of the PMOS VFET and the NMOS VFET, and the top source / drain regions are connected in a direction intersecting the cell width direction.

7. The VFET unit according to claim 1, in, The VFET unit further includes a third circuit, which includes at least one VFET provided on at least one gate grid formed on the left or right side of the first circuit, with the first circuit positioned between the second and third circuits. In this circuit, the bottom source / drain regions of the VFET in the first circuit and the bottom source / drain regions of the VFET in the third circuit are combined and connected to a power supply or ground source.

8. The VFET cell according to claim 7, wherein, The VFET circuit forms a scan trigger circuit with a reset input. The first circuit includes a 1-CPP inverter; The second circuit includes a 3-CPP NOR circuit, which is configured to receive a reset signal and send an output signal to the first circuit forming the output circuit of the scan trigger circuit. The third circuit includes a 2-CPP clock inverter configured to receive a clock signal.

9. The VFET unit according to claim 8, further comprising: The fourth circuit includes a 2-CPP NOR circuit placed to the right of the second circuit and configured to receive a reset signal; as well as The fifth circuit includes a slave latch placed to the right of the fourth circuit, and at least one gate in the fifth circuit is configured to share the source / drain signal of the 2-CPP NOR circuit. The sixth circuit includes a scan stage circuit whose gate is configured to receive a scan enable signal; The seventh circuit includes a 1-CPP scan inverter placed to the left of the sixth circuit and configured to share the scan enable signal received at the gate of the sixth circuit at its gate. as well as The eighth circuit includes a main latch positioned to the right of the sixth circuit and to the left of the third circuit, and is configured to receive the output signal of the sixth circuit. The seventh, sixth, eighth, third, first, second, fourth and fifth circuits are sequentially provided on 24 gate grids.

10. The VFET cell according to claim 1, wherein, The source / drain of the VFET in the first circuit is configured to share the gate signal of the VFET in the second circuit. The VFET unit further includes a third circuit, which includes at least one VFET provided on at least one gate grid formed on the left or right side of the first circuit. The first circuit is placed between the second and third circuits. In this circuit, the bottom source / drain regions of the VFET in the first circuit and the bottom source / drain regions of the VFET in the third circuit are combined and connected to a power supply or ground source. The VFET circuit forms a scan trigger circuit. The first circuit includes a 1-CPP inverter; The second circuit includes a latch, and The third circuit includes a 2-CPP clock inverter configured to receive a clock signal.

11. The VFET unit of claim 10, further comprising: The fourth circuit includes a 2-CPP inverter placed to the right of the second circuit; as well as The fifth circuit includes a 1-CPP inverter placed to the right of the fourth circuit, and at least one gate in the fifth circuit is configured to share the source / drain signal of the fourth circuit. The sixth circuit includes a scan stage circuit whose gate is configured to receive a scan enable signal; The seventh circuit includes a 1-CPP scan inverter placed to the left of the sixth circuit and configured to share the scan enable signal received at the gate of the sixth circuit at its gate. as well as The eighth circuit includes a master latch placed to the right of the sixth circuit and to the left of the third circuit, and is configured to receive the output signal of the sixth circuit.

12. A vertical field-effect transistor (VFET) cell implementing a scan trigger, comprising a plurality of circuits formed sequentially and uniformly spaced on a first to nineteenth gate grid in the VFET cell. in, The first gate grid provides a single-fin scan inverter. The second to fifth gate grids provide a scan stage circuit, which is configured to receive a scan input signal, a data signal, a scan enable signal, and an inverting scan enable signal. Among them, the sixth to ninth gate grids provide the main latch. The tenth and eleventh gate grids provide a dual-fin clock inverter. The twelfth gate grid provides the main data path circuitry, including a single-fin inverter. Among them, the thirteenth to sixteenth gate grids provide a latch, The seventeenth and eighteenth gate grids provide a slave data path circuit including a dual-fin inverter, and The nineteenth gate grid provides an output circuit including a single-fin inverter.

13. A scan trigger circuit formed by a plurality of vertical field-effect transistor (VFET) units according to claim 1, the scan trigger circuit comprising: The scan stage circuit is configured to receive at least one scan input signal, at least one data signal, at least one scan enable signal, and at least one inverted scan enable signal; The master latch includes a first inverter configured to receive the output signal of the scan stage circuit, a main data path circuit configured to receive the output signal of the first inverter and at least one reset signal, and a second inverter configured to receive the output signal of the main data path circuit, wherein the output node of the second inverter is connected to the output node of the first inverter. The latch includes a third inverter configured to receive the output signal of a first data path circuit, a slave data path circuit configured to receive the output signal of the third inverter and at least one reset signal, and a fourth inverter configured to receive the output signal of the slave data path circuit, wherein the output node of the fourth inverter is connected to the output node of the third inverter. as well as The output circuit is configured to receive the output signal from the data path circuit.

14. The scan trigger circuit according to claim 13, wherein, The output circuit includes an inverter, and Each of the first to fourth inverters is a tri-state inverter, which is configured to receive a clock signal and an inverted clock signal as gate signals.

15. The scan trigger circuit according to claim 14, wherein, The main data path circuit is cross-coupled with the second inverter, such that the output node of the main data path circuit is connected to the input node of the second inverter, and the output node of the second inverter is connected to the input node of the main data path circuit. The data path circuit is cross-coupled with the fourth inverter, such that the output node of the data path circuit is connected to the input node of the fourth inverter, and the output node of the fourth inverter is connected to the input node of the data path circuit.

16. The scan trigger circuit according to claim 15, wherein, Both the master data path circuit and the slave data path circuit are NOR circuits.

17. The scan trigger circuit according to claim 15, wherein, The main data path circuit includes: Two p-channel metal-oxide-semiconductor (PMOS) vertical field-effect transistors (VFETs) are connected in series between the power supply node and the input node of the third inverter; and Two n-channel metal-oxide-semiconductor (NMOS) VFETs are connected in parallel between each other between the input node and ground node of the third inverter. The data path circuit includes: Two PMOS VFETs connected in series between the power supply node and the input node of the output circuit; and Two NMOS VFETs are connected in parallel between the input node and the ground node of the output circuit.

18. The scan trigger circuit according to claim 17, wherein, In the main data path circuit, one of the two PMOS VFETs and one of the two NMOS VFETs are configured to receive the output signal of the first inverter, and the other of the two PMOS VFETs and the other of the two NMOS VFETs are configured to receive the reset signal. In the data path circuit, one of the two PMOS VFETs and one of the two NMOS VFETs are configured to receive the output signal of the third inverter, and the other of the two PMOS VFETs and the other of the two NMOS VFETs are configured to receive the reset signal.

19. The scan trigger circuit according to claim 13, wherein, The scan trigger circuit does not include: Transmission gate; An asymmetric circuit in which the drain terminals of an even number of VFETs with the same polarity and connected in series are connected to the drain terminals of one or an odd number of VFETs with the same polarity and connected in series, wherein the source terminals of the even number of VFETs and the source terminals of the one or odd number of VFETs are connected to the same power supply or ground source. A series circuit in which three or more VFETs are connected in series between a power node or ground node and an output node of the series circuit, the output node being the drain terminal of the series-connected VFETs; or A power supply circuit, wherein when implemented in a VFET cell, the power supply or ground source is connected to the power supply circuit only through the bottom source / drain region.

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