Semiconductor storage device, electronic device, and method for setting semiconductor storage device

Abstract

A semiconductor memory device, an electronic device, and a method for configuring a semiconductor memory device are provided. The electronic device includes: a semiconductor memory device configured to store process information and output the process information to an external device; and a host configured to read the process information from the semiconductor memory device and select one of multiple operating modes based on the process information to set as the operating mode of the semiconductor memory device. The multiple operating modes may define one or more of the power consumption of the semiconductor memory device or the response characteristics of the semiconductor memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of Korean Patent Application No. 10-2019-0124370, entitled “Semiconductor Memory Device, Electronic Device and Method for Setting the Same,” filed on October 8, 2019, in the Korean Intellectual Property Office are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor memory device, an electronic device including the semiconductor memory device, and a method of providing the semiconductor memory device. Background Art

[0004] The use of mobile devices such as smartphones, tablet personal computers (PCs), digital cameras, MP3 players, personal digital assistants (PDAs), and wearable devices is increasing dramatically. Summary of the Invention

[0005] An embodiment provides an electronic device including: a semiconductor memory device configured to store process information and output the process information to an external device; and a host configured to read the process information from the semiconductor memory device and select one of a plurality of operation modes based on the process information to set as the operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or response characteristics of the semiconductor memory device.

[0006] An embodiment is intended to provide a method for setting up a semiconductor memory device, the method comprising: reading process information from the semiconductor memory device; determining whether the process information indicates an enhanced process or a traditional process; determining, based on the determined result, an operating voltage of the semiconductor memory device or a delay for data to be output in response to a read command of the semiconductor memory device; and setting a mode register group of the semiconductor memory device so that the semiconductor memory device operates according to the determined delay or the determined operating voltage.

[0007] An embodiment is intended to provide a semiconductor memory device, comprising: a cell array including a plurality of DRAM cells for storing data; a peripheral circuit configured to write data into the cell array, or sense and output data stored in the cell array; and a mode register group circuit configured to output process information about the peripheral circuit to the outside, and set the output delay of the data and the level of the operating voltage of the peripheral circuit in response to a mode register write request. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Features will become apparent to those skilled in the art by describing example embodiments in detail with reference to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating an electronic device according to example embodiments.

[0010] Figure 2 is a block diagram illustrating a structure of a system on chip according to example embodiments.

[0011] Figure 3 It shows Figure 1 A block diagram of a configuration of a storage device.

[0012] Figures 4A to 4D It shows Figure 1 A table with examples of pattern sets.

[0013] Figure 5 It shows Figure 1 A table of process information.

[0014] Figure 6 is a diagram illustrating an operation of an electronic device using process information PI according to an embodiment.

[0015] Figure 7 It shows Figure 6 A flow chart of the operation of the system-on-chip in operation.

[0016] Figure 8 It shows Figure 7 Flowchart of operation S160.

[0017] Figure 9 Reference Figure 8 A diagram illustrating a training operation of a data signal DQ and a data strobe signal DQS is described.

[0018] Figure 10 Reference Figure 8 A diagram illustrating a level training operation of a data signal DQ is described.

[0019] Figure 11 is a block diagram illustrating a computing system according to an example embodiment.

[0020] Figure 12 It shows Figure 11 A block diagram of the configuration of the storage module.

[0021] Figure 13 It shows Figure 11 A block diagram of another example of a storage module.

[0022] Figure 14 is a block diagram illustrating an electronic device according to example embodiments. DETAILED DESCRIPTION

[0023] Below, an example of a main memory or working memory will be described using DRAM as an example to describe the features and functions of the example embodiments. However, based on the content disclosed herein, those skilled in the art can easily understand other advantages and performances of the example embodiments. For example, the features of the example embodiments can be applied to phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), NOR flash memory, etc. as working storage devices. Here, the storage device can be a memory that stores instructions or data processed in an electronic device. In this specification, the term "training" can refer to an operation of searching the delay or signal level of a storage channel to provide optimized reliability.

[0024] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram illustrating an electronic device according to example embodiments.

[0026] Reference Figure 1 , an electronic device 1000 according to an example embodiment may include a system on chip (SoC) 1100 and a memory device 1200. One or more channels for exchanging signals and data may be provided between the system on chip 1100 and the memory device 1200.

[0027] The system on chip 1100 can execute various applications based on a user's request, for example. To execute the application, the system on chip 1100 can load and execute the application on the storage device 1200. The system on chip 1100 can drive an operating system (OS) and can execute various applications on the operating system. The system on chip 1100 can write data to the storage device 1200 or can read data stored in the storage device 1200. The system on chip 1100 may include a memory controller (not shown) for controlling the storage device 1200.

[0028] The system on chip 1100 may include a pattern set 1172, which is parameter information for controlling latency of the memory device 1200 with reference to process information PI provided from the memory device 1200. The system on chip 1100 may determine whether the memory device 1200 is a semiconductor device to which an enhanced process is applied through the process information PI.

[0029] For example, the memory device 1200 may be manufactured using a high-K metal gate (HKMG) process or a fin field effect transistor (FinFET) process to form a high-performance logic component. In this case, the speed and power characteristics of the memory device 1200 may be significantly improved by voltage level setting, clock frequency setting, or delay setting compared to a memory device manufactured using a conventional process. The system-on-chip 1100 may determine whether the memory device 1200 is a semiconductor device to which an enhanced process is applied based on the process information PI. When the process information PI is used to detect the process applied to the memory device 1200, the system-on-chip 1100 may set the memory device 1200 to parameters corresponding to one mode set 1172 selected by the user from a plurality of mode sets 1172 corresponding to various performance parameters (which may be predetermined).

[0030] Afterwards, communication between the system on chip 1100 and the memory device 1200 can be performed according to the set operating parameters. The system on chip 1100 can request and receive process information PI from the memory device 1200 at startup or under specific conditions. The system on chip 1100 can control the memory device 1200 based on the set operating parameters and can provide the performance required by the user.

[0031] The storage device 1200 may be set as a main memory or a working memory of the electronic device 1000. When the electronic device 1000 is started, an operating system OS or an application program may be loaded onto the storage device 1200. For example, when the system on chip 1100 is started, an OS image (OS image) stored in the storage device may be loaded onto the storage device 1200 based on the boot sequence. The operating system OS may support all input / output operations of the system on chip 1100. Similarly, an application program selected by a user or for providing basic services may be loaded onto the storage device 1200. In addition, the storage device 1200 may be used as, for example, a buffer memory to store image data provided from an image sensor such as a camera.

[0032] When the electronic device 1000 is driven, the operating system OS, running applications, update data, etc. may be stored in the storage device 1200. The storage device 1200 may also store therein process information (PI) 1285. For example, as described above, the process information (PI) 1285 may be information about the process technology used to manufacture the storage device 1200. In another embodiment, the process information (PI) 1285 may be provided in the form of a flag signal indicating whether the process applied to the storage device 1200 is an enhanced process or a conventional process.

[0033] The system on chip 1100 may provide a command CMD, an address ADD, a data strobe signal DQS, and a data signal DQ to the memory device 1200. In addition, the memory device 1200 may output process information (PI) 1285 to the system on chip 1100 through, for example, a data channel or through a separate dedicated pin.

[0034] The electronic device 1000 according to an example embodiment may receive process information (PI) 1285 of the memory device 1200 and may set parameters for adjusting the performance (e.g., power consumption and latency) of the memory device 1200. Here, latency refers to a time interval tAA from when a read command is provided to the memory device 1200 to when data is output. Therefore, when a new process technology is applied to the memory device 1200, various options may be applied to improve the performance of the electronic device 1000 or reduce the power consumption of the electronic device 1000. In addition, the latency of the memory device 1200 to which the new process technology is applied may be reduced to various levels.

[0035] Figure 2 is a block diagram illustrating a structure of a system on chip according to example embodiments.

[0036] Reference Figure 2 , the system on chip 1100 can be connected to the storage device 1180 and the storage device 1200. Although not in Figure 2 , but the system on chip 1100 can also be connected to a device such as a liquid crystal display device or a touch panel.

[0037] The system on chip 1100 may include a central processing unit (CPU) 1110, a memory controller 1120, a graphics processing unit (GPU) 1130, a user interface (UI) controller 1140, a storage interface 1150, a static random access memory (SRAM) 1160, and a system interconnect 1170. Other components may be provided on the system on chip 1100. For example, the system on chip 1100 may include a hardware codec for processing image data, a security block, and the like.

[0038] The CPU 1110 can execute software (e.g., application programs, an operating system, and device drivers) to be executed in the system-on-chip 1100. The CPU 1110 can execute the operating system OS loaded on the storage device 1200. The CPU 1110 can execute various application programs to be driven based on the operating system OS. For example, at startup, the CPU 1110 can fetch and execute the boot code or training code loaded on the SRAM 1160 or the storage device 1200. The CPU 1110 can be, for example, a homogeneous multi-core processor or a heterogeneous multi-core processor.

[0039] The memory controller 1120 may provide an interface between the memory controller 1120 and the system on chip 1100. The memory controller 1120 may access the memory device 1200 in response to a request from the CPU 1110 or another IP. For example, the memory controller 1120 may write data to the memory device 1200 in response to a write request from the CPU 1110. In addition, the memory controller 1120 may read data from the memory device 1200 and may provide the read data to the CPU 1110 or the memory interface 1150. The memory controller 1120 may release rank interleaving associated with the memory device 1200 to perform a training operation. The memory controller 1120 of the example embodiment may set parameters corresponding to a mode selected from the mode set 1172 to the memory device 1200.

[0040] The GPU 1130 can execute various graphics operations in response to requests from the CPU 1110. Thus, the GPU 1130 can convert the data requested for processing into data suitable for a display (not shown). The GPU 1130 utilizes an operational structure suitable for parallel processing to repeatedly process similar operations. Therefore, the GPU 1130 can have a structure capable of executing various operations requiring high-speed parallel processing, as well as graphics operations. In one embodiment, the system on chip 1100 can be implemented without the GPU 1130.

[0041] The user interface controller 1140 can control the user input from the user interface device (e.g., keyboard, touch panel and display), and the output to the user interface device (e.g., keyboard, touch panel and display). For example, the user interface controller 1140 can display a keyboard screen for inputting data to a display (not shown) under the control of the CPU 1110. The user interface controller 1140 can control the display to display the data requested by the user. The user interface controller 1140 can decode the data provided from the user input device (such as, keyboard, mouse and touch panel) into user input data.

[0042] The storage interface 1150 may control the storage device 1180 in response to a request from the CPU 1110. Thus, the storage interface 1150 may provide an interface between the system on chip 1100 and the storage device 1180. For example, data processed by the CPU 1110 may be stored in the storage device 1180 through the storage interface 1150. In addition, the data stored in the storage device 1180 may be provided to the CPU 1110 through the storage interface 1150. According to an example embodiment, parameters corresponding to a mode selected by a user from the mode set 1182 may be stored in the storage device 1180 through the storage interface 1150.

[0043] The SRAM 1160 may be provided as a working memory of the CPU 1110. For example, a boot loader or a code for performing booting may be loaded on the SRAM 1160.

[0044] The system interconnect 1170 may be a system bus for providing an on-chip network within the system-on-chip 1100. The system interconnect 1170 may include, for example, a data bus, an address bus, and a control bus. The data bus may be a path for data movement and may provide a memory access path for accessing the storage device 1200 or the storage device 1180. The address bus may provide a path for exchanging addresses between functional blocks (intellectual properties). The control bus may provide a path for transmitting control signals between functional blocks. The system interconnect 1170 may include an arbitration device for efficient management.

[0045] The storage device 1180 may be a storage medium of the system on chip 1100. The storage device 1180 may store applications, OS images 1184, and various data. For example, a pattern set 1182 for adjusting the performance or characteristics of the storage device 1200 may be stored in the storage device 1180. In addition, the training code TC for training the storage device 1200 may be stored in a specific area of the storage device 1180. The storage device 1180 may be implemented using a memory card (e.g., MMC, eMMC, SD, and microSD). In one embodiment, the storage device 1180 may include a next-generation non-volatile memory such as PRAM, MRAM, ReRAM, or FRAM, or a NOR flash memory. As another example, the storage device 1180 may be an embedded memory provided within the system on chip 1100.

[0046] As described above, the system on chip 1100 may adjust parameters of the memory device 1200 , such as latency, operating voltage, and speed, with reference to the process information PI provided from the memory device 1200 .

[0047] Figure 3 It shows Figure 1A block diagram of a configuration of a storage device.

[0048] Reference Figure 3 , the memory device 1200 may include a cell array 1210, a row decoder 1220, an address buffer 1230, a column decoder 1240, a sense amplifier 1250, a data input / output (DQ) buffer 1260, a command decoder 1270, and a mode register set (MRS) 1280.

[0049] The cell array 1210 may include a plurality of memory cells MC connected to word lines and bit lines and arranged in row and column directions. Each memory cell MC may include, for example, a cell capacitor and an access transistor. In each memory cell MC, the gate of the access transistor may be connected to one of the word lines arranged in the row direction. The first end of the access transistor may be connected to a bit line BL or a complementary bit line (BLB) extending in the column direction. The second end of the access transistor may be connected to the cell capacitor.

[0050] The row decoder 1220 can select the word line of the memory cell to be accessed in response to the input address ADD. The row decoder 1220 can decode the input address ADD and enable the word line corresponding to the decoded address. In addition, in the self-refresh mode of operation, the row decoder 1220 can decode the row address generated from the address counter (not shown) and enable the word line corresponding to the decoded address. The column decoder 1240 can select the bit line of the memory cell for which the read operation or write operation is targeted.

[0051] The address buffer 1230 may temporarily store an address ADD input from the outside and provide the stored address ADD to the row decoder 1220 or the column decoder 1240. The address buffer 1230 may convert the address ADD having an external signaling method into an internal signaling method of the memory device 1200.

[0052] The sense amplifier 1250 can write data into a memory cell through a selected bit line. The sense amplifier 1250 can sense the data stored in the selected memory cell and provide the sensed data to the DQ buffer 1260. The sense amplifier 1250 may include components for storing input data in the selected memory cell. The sense amplifier 1250 can perform an operation of reading data stored in the memory cell and writing the read data back to the memory cell in a self-refresh mode (e.g., a rewrite operation).

[0053] The DQ buffer 1260 may temporarily store write data input from the outside and provide the write data to the sense amplifier 1250. The DQ buffer 1260 may output sensed data provided from the sense amplifier 1250 to the outside. The DQ buffer 1260 may provide data to the sense amplifier 1250 and may output data sensed by the sense amplifier 1250 to the outside.

[0054] The command decoder 1270 can determine an input command with reference to the signals / CS, / RAS, / CAS, and / WE applied from the outside. The command decoder 1270 can write data in the cell array 1210 or read data from the cell array 1210 in response to the command provided from the outside. The command decoder 1270 can write data to the mode register group 1280 according to the command and address provided from the outside. The auto-refresh operation can be input by a combination of the control signals / CS, / RAS, / CAS, and / WE.

[0055] The mode register group 1280 can set the internal mode register in response to the MRS command and address signal ADD for specifying the operating mode of the memory device 1200. The process information (PI) 1285 of the memory device 1200 can be stored in the mode register group 1280 of the example embodiment and can be output to the outside in response to a mode register read (MRR) request. In another embodiment, the process information (PI) 1285 can be programmed separately in a programmable component and can be output in the form of a flag signal in response to an external request. In this case, a separate pin for outputting the process information PI in the form of a flag signal can be formed at the memory device 1200.

[0056] An example of the memory device 1200 implemented using DRAM is described above. However, the technology applied to the memory device 1200 of the example embodiment can be applied to various memories or storage devices in addition to DRAM.

[0057] Figures 4A to 4D It shows Figure 1 A table with examples of pattern sets.

[0058] Reference Figure 4A ,A mode set can include multiple modes based on speed or power consumption.

[0059] The first mode Mode 1 corresponding to the operation code "000" may correspond to the normal mode. Therefore, based on parameter settings corresponding to the first mode Mode 1 (e.g., clock frequency or drive voltage VDD), the memory device 1200 may operate at a maximum speed of, for example, 6400 Mbps. Therefore, the delay from when a read command is provided to the memory device 1200 to when data is output may be a time length "L" or less (e.g., L is 22 ns).

[0060] The second mode Mode2 corresponding to the operation code "001" may correspond to a high-speed mode. In the second mode Mode2, the voltage level supplied to the memory device 1200 may be the same as the voltage VDD level supplied in the normal mode. However, depending on parameter settings such as clock frequency corresponding to the second mode Mode2, the memory device 1200 may operate at a maximum speed of, for example, 7200 Mbps.

[0061] The third mode Mode3 corresponding to the operation code "010" may correspond to a boost mode. In the third mode Mode3, the voltage level provided to the memory device 1200 may be the same as the voltage VDD level provided in the normal mode. However, depending on parameter settings such as clock frequency corresponding to the third mode Mode3, the memory device 1200 may operate at a maximum speed of, for example, 8500 Mbps.

[0062] The fourth mode Mode 4 corresponding to the operation code "011" may correspond to a low power mode. In the fourth mode Mode 4, the driving voltage provided to the memory device 1200 may be a voltage lower than the voltage provided in the normal mode (e.g., 0.8×VDD). Depending on parameter settings such as clock frequency corresponding to the fourth mode Mode 4, the memory device 1200 may operate at a maximum speed of, for example, 3200 Mbps.

[0063] The fifth mode Mode5 corresponding to the operation code "100" may correspond to an extremely low power mode. In the fifth mode Mode5, the driving voltage provided to the memory device 1200 may be a voltage lower than the voltage provided in the low power mode (e.g., 0.6×VDD). Depending on parameter settings such as clock frequency corresponding to the fifth mode Mode5, the memory device 1200 may operate at a maximum speed of, for example, 1600 Mbps.

[0064] An example mode set is described above. When the process information PI of the memory device 1200 corresponds to an enhanced process, the system on chip 1100 may select a mode that can improve performance or power efficiency and set the selected mode to the memory device 1200.

[0065] Figure 4B is a table showing another embodiment of a pattern set.

[0066] Reference Figure 4B In this mode set, the driving voltage levels of the various modes may be the same. However, in this mode set, even under the same driving voltage conditions, different modes may correspond to different operating speeds.

[0067] The first mode Mode1 corresponding to the operation code “000” may correspond to a normal mode. In the first mode Mode1, the memory device 1200 may operate at a maximum speed of, for example, 6400 Mbps.

[0068] The second mode Mode2 corresponding to the operation code "001" may correspond to the first high-speed (HS1) mode. According to the parameter conditions of the second mode Mode2, the memory device 1200 may operate at a maximum speed of, for example, 7200 Mbps.

[0069] The third mode Mode3 corresponding to the operation code “010” may correspond to the second high-speed (HS2) mode. In the third mode Mode3, the memory device 1200 may operate at a maximum speed of, for example, 8000 Mbps.

[0070] The fourth mode Mode 4 corresponding to the operation code “011” may correspond to the third high-speed (HS3) mode. In the fourth mode Mode 4, the memory device 1200 may operate at a maximum speed of, for example, 8500 Mbps.

[0071] The fifth mode Mode5 corresponding to the operation code “100” may correspond to the fourth high-speed (HS4) mode. In the fifth mode Mode5, the memory device 1200 may operate at a maximum speed of, for example, 9000 Mbps.

[0072] Figure 4C is a table showing another embodiment of a pattern set.

[0073] Reference Figure 4C In this mode set, the level of the driving voltage of each mode may be fixed to a level lower than that of the normal mode (eg, 0.6×VDD). However, the delay may vary as the speed increases.

[0074] The first mode Mode1 corresponding to the operation code “000” may correspond to a first low power high speed (LPHS1) mode. In the first mode Mode1, the memory device 1200 may operate at a maximum speed of, for example, 5400 Mbps.

[0075] The second mode Mode2 corresponding to the operation code "001" may correspond to a second low-power high-speed (LPHS2) mode. In the second mode Mode2, even if the voltage level (e.g., 0.6×VDD) condition remains unchanged, the latency (e.g., 0.8×L) may be reduced, and the memory device 1200 may operate at a maximum speed of, for example, 6200 Mbps.

[0076] The third mode Mode 3 corresponding to the operation code "010" may correspond to a third low-power high-speed (LPHS3) mode. In the third mode Mode 3, even if the voltage level (e.g., 0.6×VDD) condition remains unchanged, the latency (e.g., 0.6×L) may be reduced compared to the second mode Mode 2, and the memory device 1200 may operate at a maximum speed of, for example, 7000 Mbps.

[0077] The fourth mode Mode 4 corresponding to the operation code "011" may correspond to a fourth low-power high-speed (LPHS4) mode. In the fourth mode Mode 4, under the condition that the voltage level (e.g., 0.6×VDD) remains unchanged, the latency (e.g., 0.5×L) may be reduced compared to the third mode Mode 3, and the memory device 1200 may operate at a maximum speed of, for example, 7500 Mbps.

[0078] The fifth mode Mode5 corresponding to the operation code “100” may correspond to a fifth low power high speed (LPHS5) mode. In the fifth mode Mode5, the memory device 1200 may operate at a maximum speed of, for example, 8000 Mbps.

[0079] Figure 4D is a table showing another embodiment of a pattern set.

[0080] Reference Figure 4D ,According to the size of power consumption under the same performance, the mode set can include multiple modes.

[0081] The first mode Mode1 corresponding to the operation code “000” may correspond to a normal mode. In the first mode Mode1, the memory device 1200 may operate at a maximum speed of, for example, 6400 Mbps.

[0082] The second mode Mode2 corresponding to the operation code "001" may correspond to the first low-power (LP1) mode. In the second mode Mode2, the latency (1×L) is the same as that in the first mode Mode1, but the voltage level is set to, for example, (0.9×VDD). Therefore, in the second mode Mode2, power consumption can be reduced without reducing latency compared to the first mode Mode1. In the second mode Mode2, the memory device 1200 may operate at a maximum speed of, for example, 6000 Mbps.

[0083] The third mode Mode3 corresponding to the operation code “010” may correspond to the second low power (LP2) mode. In the third mode Mode3, the voltage level may be set to (0.8×VDD), and the memory device 1200 may operate at a maximum speed of, for example, 5500 Mbps.

[0084] The fourth mode Mode4 corresponding to the operation code “011” may correspond to the third low power (LP3) mode. In the fourth mode Mode4, the voltage level may be set to (0.7×VDD), and the memory device 1200 may operate at a maximum speed of, for example, 5000 Mbps.

[0085] The fifth mode Mode5 corresponding to the operation code “100” may correspond to the fourth low power (LP4) mode. In the fifth mode Mode5, the voltage level may be set to (0.6×VDD), and the memory device 1200 may operate at a maximum speed of, for example, 4500 Mbps.

[0086] Figure 5 It shows Figure 1 The process information PI form.

[0087] Reference Figure 5 , the process information PI may include information about a process applied to the memory device 1200 .

[0088] The memory device 1200 may output the process information PI in response to a request from the system on chip 1100. The memory device 1200 may output the process information PI via a data input / output pin according to a protocol pre-set with the system on chip 1100. In another embodiment, the memory device 1200 may output the process information PI via a pin separately provided for outputting the process information PI.

[0089] The process information PI may be information indicating whether an enhanced process is applied in the manufacturing of the memory device 1200. For example, a logical value of "0" of the process information PI may indicate that the manufacturing process of the memory device 1200 corresponds to a conventional process, and a logical value of "1" of the process information PI may indicate that the manufacturing process of the memory device 1200 corresponds to an enhanced process providing higher performance.

[0090] The enhancement process may correspond to, for example, a high-K metal gate (HKMG) process or a fin field effect transistor (FinFET) process for forming high-performance logic components. Therefore, the logic circuit included in the memory device 1200 corresponding to the process information PI having a logical value of "1" may be formed using the high-K metal gate (HKMG) process or the fin field effect transistor (FinFET) process. In the memory device 1200 corresponding to the process information PI having a logical value of "1," the peripheral circuits 1220 to 1280 (i.e., circuits other than the cell array 1210) may be formed using the aforementioned enhancement process.

[0091] Figure 6 is a diagram illustrating an operation of an electronic device using process information PI according to an embodiment.

[0092] Reference Figure 6 During the startup phase of the electronic device 1000 , the storage device 1200 may provide the process information PI to the system on chip 1100 .

[0093] In operation S10, when power is supplied to the electronic device 1000 or the system-on-chip 1100 (power is turned on), a startup sequence may be started. In addition, the startup sequence may be started when the electronic device 1000 or the system-on-chip 1100 is automatically restarted, for example, due to a system error occurring in a previous operation. When power is supplied to the electronic device 1000, the system-on-chip 1100 supplies power to the memory device 1200 and initializes the memory device 1200. In this case, the voltage or clock frequency supplied to the memory device 1200 may be a default voltage or a default clock frequency.

[0094] In operation S20, the system-on-chip 1100 may receive process information PI from the storage device 1200 and may set an operating mode. Operation S20 may be further divided into operations S22, S24, S26, and S28. In operation S22, the system-on-chip 1100 may request process information PI from the storage device 1200. In operation S24, the storage device 1200 transmits the process information PI to the system-on-chip 1100, and the storage device 1200 may provide the process information PI in a mode register read (MRR) manner. In operation S26, the system-on-chip 1100 checks the process information PI. For example, the system-on-chip 1100 may determine whether the process applied to the storage device 1200 is a conventional process or an enhanced process. When it is determined that the process applied to the storage device 1200 is a conventional process, the process may proceed to operation S30. When it is determined that the process applied to the storage device 1200 is an enhanced process, the process may proceed to operation S28. In operation S28, the system on chip 1100 sets an operation mode of the memory device 1200. For example, the system on chip 1100 may adjust an operation parameter of the memory device 1200 in the operation mode selected by the user.

[0095] In operation S30, a training operation may be performed on the memory device 1200. The system-on-chip 1100 may improve the reliability of data or signals exchanged with the memory device 1200 through the training operation. For example, the system-on-chip 1100 may determine optimal clock timing or an optimal level of a reference voltage by writing training data to the memory device 1200 and reading training data from the memory device 1200 under various conditions. The training operation of the memory device 1200 may be performed after the test process (described below) is terminated.

[0096] In operation S40, a test operation may be performed on the memory device 1200. For example, first, the system on chip 1100 may write a predetermined test pattern in the memory device 1200 to test the memory device 1200. The system on chip 1100 may perform the test operation on the memory device 1200 by using a command, address, and data corresponding to the test pattern generated for the test operation.

[0097] When the test operation associated with the storage device 1200 is terminated, an operating system OS may be loaded onto the storage device 1200 provided as a main memory in operation S50. When the operating system OS is loaded, the operating system OS may have overall control authority over the system.

[0098] The above briefly describes the test process of the storage device 1200 performed when the electronic device 1000 is started. The process information PI may further include various additional information.

[0099] Figure 7 It shows Figure 6 A flow chart of the operation of the system-on-chip in operation.

[0100] Reference Figure 7 , the system on chip 1100 may receive the process information PI from the memory device 1200 and may set the performance or power level of the memory device 1200 according to the received process information PI.

[0101] In operation S110, the system on chip 1100 may supply power to the memory device 1200, for example, through a power or reset operation. In this case, the voltage or clock frequency supplied to the memory device 1200 may be a default voltage or a default clock frequency corresponding to a default operation mode.

[0102] In operation S120, the system on chip 1100 may request process information PI from the memory device 1200. The system on chip 1100 may request a mode register read MRR of the memory device 1200 and may request the process information PI programmed at the memory device 1200. The memory device 1200 may output the process information PI in response to the request of the system on chip 1100. For example, the memory device 1200 may output the process information PI to the system on chip 1100 in the form of a flag signal. The process information PI may be provided to the system on chip 1100 via a separate pin or via a side channel for purposes other than data exchange.

[0103] In operation S130 , the system on chip 1100 may receive the process information PI output from the memory device 1200 .

[0104] In operation S140, the system on chip 1100 may check the process information PI. The system on chip 1100 may determine whether the process information PI corresponds to a conventional process or an enhanced process. When the process information PI corresponds to the conventional process, the process may proceed to operation S160. When the process information PI corresponds to the enhanced process, the process may proceed to operation S150.

[0105] In operation S150, the system on chip 1100 can set the operating mode of the storage device 1200. When the storage device 1200 is manufactured by an enhanced process, the operating speed can be increased and the power consumption can be reduced. This can mean that the latency is reduced. In this case, an operating mode with a latency value pre-selected by the user can be selected. In order to set the storage device 1200 to the selected operating mode, the system on chip 1100 can use the parameters of the selected operating mode to set the storage device 1200. For example, the system on chip 1100 can set the parameters of the storage device 1200 through a mode register write (MRW) operation.

[0106] In operation S160, a training operation may be performed on the memory device 1200. When the operation mode of the memory device 1200 is set to an operation mode corresponding to the enhanced process, the memory device 1200 may be set to high-speed or low-voltage parameters. Therefore, the values used for communication between the memory device 1200 and the system-on-chip 1100, such as the reference voltage Vref and the latency, may be more finely optimized through the training operation. In addition, when the process of the memory device 1200 corresponds to the conventional process, optimization through the training operation may be performed.

[0107] In operation S170, a test operation may be performed on the memory device 1200. For example, first, the system on chip 1100 may write a predetermined test pattern into the memory device 1200 to test the memory device 1200. The system on chip 1100 may perform the test operation on the memory device 1200 by using a command, address, and data corresponding to the test pattern generated for the test operation.

[0108] When the test operation associated with the storage device 1200 is terminated, an operating system OS may be loaded onto the storage device 1200 provided as a main memory in operation S180. When the operating system OS is loaded, the operating system OS may have overall control authority over the system.

[0109] The above briefly describes the operation of the system on chip 1100 performed when the electronic device 1000 is started. Although a description is given of the process information PI being information about the process (eg, conventional or enhanced) of the memory device 1200, the process information PI may also include various information.

[0110] Figure 8 yes Figure 7 Flowchart of operation S160.

[0111] Reference Figure 8 In the training operation, the system on chip 1100 may perform the training operation by loading the training code onto the memory device 1200. In this case, the block interleaving of the memory device 1200 may be released to load the training code onto the memory device 1200.

[0112] In operation S161, the system on chip 1100 may release the block interleaving of the storage device 1200. Block interleaving is a memory management technology for efficiently managing the input / output channels of the storage device 1200 such as a DRAM. For example, in the case where the system on chip 1100 writes data into the storage device 1200, the data requested to be written may be divided in interleaving units. As an example, assume that the interleaving unit IU is 128 bytes. The data requested to be written may be divided into 128B of data corresponding to each channel (i.e., data of the interleaving unit) and may be written in a pipelined manner. In order to output data in a read operation, a channel may be selected in the same manner as described above. Block interleaving may hinder the operation of storing training code in one area, so block interleaving may be released or disabled to store the training code.

[0113] In operation S162, the system on chip 1100 may load the training code onto the memory device 1200 in a state where the block interleaving is released. The system on chip 1100 loads the training code onto a storage area corresponding to one rank of the memory device 1200. Here, the number of blocks included in each channel of the memory device 1200 may have various values.

[0114] In operation S163, the system-on-chip 1100 may access the block loaded with the training code and may retrieve and execute the training code. For example, the CPU 1110 performing the training operation may retrieve and execute the training code in the storage device 1200. When the training code is executed, the training may be performed on the storage area included in at least one block that is not loaded with the training code. The system-on-chip 1100 may evaluate the read training data to determine the optimal parameters. The system-on-chip 1100 of the example embodiment may detect the signal level of the output data of the storage device 1200 through the read training operation of the storage device 1200. The optimal reference voltage Vref may be determined based on the signal level of the output data.

[0115] In operation S164, when the training code is executed, the parameters of the input / output path or the delay state of the clock signal of the memory device 1200 can be detected. The system on chip 1100 can determine the delay value (i.e., latency) of the clock signal, data strobe signal DQS, or data signal DQ of the memory area included in at least one block that is not loaded with the training code. In the set operating mode, the clock signal, data strobe signal DQS, or data signal DQ of the memory area included in at least one block that is not loaded with the training code can be used as a more accurate parameter. For example, the timing of the strobe signal DQS that provides the highest reliability can be selected by training the data strobe signal DQS.

[0116] In operation S165, the system-on-chip 1100 may determine whether all the blocks of the memory device 1200 have been trained. For example, the system-on-chip 1100 may determine whether software training associated with all channels and all the blocks of the channels included in the memory device 1200 has been completed. If the blocks have not yet been trained (No), the process proceeds to operation S166. If all the blocks have been fully trained (Yes), the process proceeds to operation S167.

[0117] In operation S166, the system-on-chip 1100 may newly select a target block to be trained. For example, if there are only two blocks, the block to which the training code was previously loaded may be set as the target block to be trained. When the selection of the target block for training is completed, the process proceeds to operation S162 to perform training on the target block.

[0118] In operation S167, the system on chip 1100 may use the operating parameters obtained as a result of the training operation to set the memory device 1200. For example, the system on chip 1100 may use the reference voltage Vref determined for each block of the memory device 1200 in operations S163 and S164, and the delay value of the data strobe signal DQS or the data signal DQ to set the memory device 1200.

[0119] In operation S168, the system on chip 1100 may restore the block interleaving of the memory device 1200 released in operation S161. For example, the system on chip 1100 may reset the memory device 1200. In this case, the block interleaving of the memory device 1200 may be enabled.

[0120] An example of a fine training process is briefly described above. The timing or signal level of the system on chip 1100 and the memory device 1200 may be optimized through the training operation performed after the selection of the operation mode according to example embodiments is completed.

[0121] Figure 9 Reference Figure 8 A diagram illustrating a training operation of a data signal DQ and a data strobe signal DQS is described.

[0122] Reference Figure 9 In the training operation, the system on chip 1100 may perform multiple detection steps to detect the left edge LE of the data signal DQ. Figure 9 In the example, RE can represent the right edge of the unit interval UI, and CP can represent the middle position of the unit interval UI.

[0123] First, the system-on-chip 1100 can determine the starting point for detecting the left edge LE of the data signal DQ. Once the starting point of the detection step is determined, the first step of the detection step, Step_1, begins. The system-on-chip 1100 provides a command and address to the memory device 1200 to output data in a specific pattern. Here, the specific pattern refers to a predetermined training pattern for comparison with the logic value of the data signal DQ. In response to the command and address, the memory device 1200 can output the data strobe signal DQS and the data signal DQ.

[0124] In the first step, Step_1, the rising edge of the data strobe signal DQS may precede the left edge LE of the unit interval UI by a plurality of step intervals. The system-on-chip 1100 compares the read data transmitted via the data signal DQ with a predetermined reference pattern. Using the comparison result, the system-on-chip 1100 determines whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ. If it is determined that the rising edge of the data strobe signal DQS does not match the left edge LE of the data signal DQ, the system-on-chip 1100 executes the second step, Step_2, after the first step, Step_1.

[0125] To perform the second step, Step_2, the system-on-chip 1100 may transmit a command and an address to the memory device 1200. In this case, the memory device 1200 may output a specific pattern of data via the data strobe signal DQS and the data signal DQ. The system-on-chip 1100 compares the transmitted data with a reference pattern and determines whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ. If it is determined in the second step, Step_2, that the rising edge of the data strobe signal DQS does not match the left edge LE of the data signal DQ, the system-on-chip 1100 executes the third step, Step_3, after the second step, Step_2.

[0126] Step 3 can be performed in the same manner as Step 2. In one embodiment, assume that a left edge LE is detected in Step 4. As a result of executing Step 3 for detecting a left edge LE, it can be determined that the data read from storage device 1200 does not match the value corresponding to the left edge LE. In this case, Step 4 can be executed. As a result of executing Step 4, it can be determined that system-on-chip 1100 has detected a left edge LE. In this case, the operation of detecting a left edge LE is terminated.

[0127] According to example embodiments, a left edge LE of the data signal DQ may be detected according to a data training method. When the left edge LE is detected, the data signal DQ and the data strobe signal DQS can be aligned.

[0128] Figure 10 Reference Figure 8 A diagram illustrating a level training operation of a data signal DQ is described.

[0129] Figure 10 1 shows a method for training the level of the data signal DQ supplied to the memory device 1200. Here, the level of the data signal DQ may be a level corresponding to the case where the data signal DQ is transmitted from the system on chip 1100 to the memory device 1200, or may be a level of a reference voltage for sampling the data signal DQ transmitted from the system on chip 1100 to the memory device 1200.

[0130] When data transmitted from the system on chip 1100 to the memory device 1200 is transmitted using only the reference voltage Vref1, the integrity of the data of the memory device 1200 may not be guaranteed. Therefore, in order to train the reference voltage, the system on chip 1100 may write the data signal DQ into the memory device 1200 by using a plurality of reference voltages Vref1 to Vref4. A reference voltage corresponding to data having the lowest error rate among data read after writing may be selected.

[0131] The training of the reference voltage Vref can be applied to the reference voltage sampled by the system-on-chip 1100 during the read training operation and the write training operation. The system-on-chip 1100 can determine the optimal reference voltage through the training operation. The system-on-chip 1100 can set a reference voltage generator to generate the determined reference voltage.

[0132] Figure 11 is a block diagram illustrating a computing system according to an example embodiment.

[0133] The electronic device 2000 may be, for example, a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, a server, an electric vehicle, a home appliance, etc. Figure 11 , the electronic device 2000 may include a host device 2100 and a storage module 2200 .

[0134] The host device 2100 can perform various arithmetic / logical operations to control the overall operation of the electronic device 2000. The host device 2100 can include a mode set 2120, which is parameter information for controlling the performance (e.g., latency) of the memory module 2200 with reference to the process information PI provided from the memory module 2200. The mode set 2120 can include a plurality of modes for setting the performance or power consumption level of the memory module 2200. The user can select one of the plurality of modes included in the mode set 2120.

[0135] The host device 2100 can use the process information PI to determine whether the memory module 2200 includes a semiconductor device using a new process technology. For example, the memory devices 2210 to 2240 included in the memory module 2200 can be manufactured using a high-K metal gate (HKMG) process or a fin field-effect transistor (FinFET) process for forming high-performance logic components. In this case, when the power supply voltage, clock frequency, or delay is set by the host device 2100, the speed and power characteristics of the memory module 2200 can be significantly improved.

[0136] When the process applied to the memory module 2200 is detected through the process information PI, the host device 2100 can set the memory module 2200 using parameters corresponding to the operating mode selected by the user. Thereafter, communication between the host device 2100 and the memory module 2200 can be performed according to the set operating parameters. The host device 2100 can request and receive the process information PI from the memory module 2200 at startup or under specific conditions. The host device 2100 can control the memory module 2200 based on the set operating parameters and can provide the performance required by the user.

[0137] The storage module 2200 may include storage devices 2210 to 2240 and a process information (PI) memory 2250. When the electronic device 2000 is started, an operating system (OS) or an application program may be loaded onto the storage module 2200. When the electronic device 2000 is driven, the operating system (OS), running applications, update data, etc. may be stored in the storage module 2200. The storage module 2200 may include a process information memory 2250 for storing process information (PI) therein. The process information (PI) may be provided in the form of a flag signal indicating whether the process applied to the storage module 2200 is an enhanced process or a conventional process.

[0138] The host device 2100 may provide a command CMD, an address ADD, a data strobe signal DQS, and a data signal DQ to the memory module 2200. In addition, the memory module 2200 may provide process information PI to the memory module 2200 through a data channel or through a separate dedicated pin.

[0139] The electronic device 2000 according to an example embodiment may receive the process information PI of the memory module 2200 and may set parameters for adjusting the performance (e.g., power consumption and latency) of the memory module 2200. Therefore, in the case of the memory module 2200 to which a new process technology is applied, various options for improving the performance of the electronic device 2000 or reducing the power consumption of the electronic device 2000 may be provided.

[0140] Figure 12 It shows Figure 11A block diagram of the configuration of the storage module.

[0141] Reference Figure 12 , a memory module 2200 a according to example embodiments may include a plurality of memory devices 2210 to 2240 and 2260 to 2290 and a serial component identification device (hereinafter referred to as “SPD”) 2250 storing process information PI.

[0142] The SPD 2250 may store SPD information read during a startup operation and process information (PI) of an exemplary embodiment. The SPD information may include, for example, the size, capacity, drive speed, drive voltage, chip layout information, and module ID of the memory module 2200a. For example, during the manufacturing process of the memory module 2200a, the process information (PI) may be programmed into the SPD 2250. An extended storage area capable of storing the process information (PI) may be provided in the SPD 2250.

[0143] Figure 13 It shows Figure 11 A block diagram of another example of a storage module.

[0144] Reference Figure 13 , the storage module 2200b may include a plurality of storage devices 2210 to 2240 stacked on a PCB substrate 2201. The process information PI may be output from at least one storage device among the plurality of storage devices 2210 to 2240.

[0145] A plurality of memory devices 2210 to 2240 may be stacked using through silicon vias (TSVs). Memory module 2200b may provide process information (PI) to a memory controller (not shown) or a host such as a system on chip. Only one memory device (e.g., 2210) among the plurality of memory devices 2210 to 2240 may output process information (PI). For example, only memory device 2210 may provide process information (PI) through a mode register read (MRR) operation to provide notification that memory module 2200b is a memory module manufactured using an enhanced process.

[0146] The plurality of storage devices 2210 to 2240 may be chips manufactured using the same process. Alternatively, one storage device (e.g., 2210) among the plurality of storage devices 2210 to 2240 may be a chip manufactured using an enhanced process, while the remaining storage devices 2220 to 2240 may be chips manufactured using a conventional process. Hot data may be primarily stored in the storage device 2210, and cold data may be stored in the remaining storage devices 2220 to 2240.

[0147] Figure 14 is a block diagram illustrating an electronic device according to example embodiments.

[0148] Reference Figure 14 , the electronic device 3000 may include a system on chip 3100 and a memory module 3200 in which a memory controller 3210 is embedded.

[0149] The memory module 3200 may include a memory controller 3210 and a memory device 3220 embedded therein. The memory controller 3210 may include a mode set 3215 storing multiple operation modes. The memory device 3220 may provide process information PI to the memory controller 3210. The memory controller 3210 may select one of the multiple operation modes with reference to the process information PI.

[0150] By way of summary and review, an application processor ("AP") can be used as a core driving processor of a mobile device. A volatile memory device such as a dynamic random access memory (DRAM) can be used as a main memory or working memory of the AP including various functional blocks ("IPs"). The demand for high performance and high capacity memory can drive an increase in the operating frequency and storage capacity of the working memory. Generally, the operating speed of the application processor can be higher than the response speed of the working memory. In addition, the bandwidth of the working memory used under various operating conditions can be different. Therefore, the bandwidth optimized for the scenario can be ensured by changing the frequency of the working memory. However, even when the frequency is variable, some operating parameters may be difficult to adjust due to reliability limitations. The performance of the AP can be improved by developing and applying new processes for working memories (such as DRAM).

[0151] As described above, embodiments relate to a semiconductor memory device capable of adjusting delay by using process information, an electronic device including the memory device, and a method of providing the memory device.

[0152] According to example embodiments, the performance of a memory device can be maximized by adjusting latency based on performance enhanced by using advanced process manufacturing. Embodiments can also provide a semiconductor memory device capable of adjusting latency based on a process for manufacturing the memory device, an electronic device including the semiconductor memory device, and a method for configuring the semiconductor memory device.

[0153] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Accordingly, those skilled in the art will understand that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An electronic device comprising: a semiconductor storage device configured to store process information and output the process information to the outside; as well as a host configured to: read the process information from the semiconductor memory device, and select one of a plurality of operation modes according to the process information to set it as the operation mode of the semiconductor memory device, wherein the plurality of operation modes define power consumption of the semiconductor memory device and response characteristics of the semiconductor memory device, the response characteristics defining a plurality of mutually different time delays for data to be output in response to a read command of the semiconductor memory device, and The multiple operation modes include: a first operating mode, in which the semiconductor memory device is set by the host to operate at a first delay and a first voltage, a second operating mode, in which the semiconductor memory device is set by the host to operate at the first delay and a second voltage, the second voltage being lower than the first voltage, and A third operation mode is configured by the host to operate the semiconductor memory device under a second delay and the first voltage, wherein the second delay is smaller than the first delay.

2. The electronic device according to claim 1, wherein The process information corresponds to process information applied to a peripheral circuit for controlling a cell array of the semiconductor memory device.

3. The electronic device according to claim 1, wherein The semiconductor memory device includes a programmable component for storing the process information.

4. The electronic device according to claim 3, wherein The process information is read and outputted through a mode register of the host.

5. The electronic device according to claim 1, wherein The process information is information indicating whether a process for manufacturing the semiconductor memory device is an enhanced process or a conventional process. The electronic device according to claim 5 , wherein: When the process information corresponds to the enhanced process, the host sets the semiconductor memory device using operation parameters corresponding to one operation mode preselected from among the plurality of operation modes.

7. The electronic device according to claim 6, wherein: The host performs a training operation to optimize a reference voltage and a timing of the semiconductor memory device set using the operation parameters.

8. The electronic device according to claim 1, wherein The semiconductor memory device includes a mode register set storing information on one or more of an operating voltage or an operating speed corresponding to a selected operation mode.

9. A method for providing a semiconductor memory device, the method comprising: reading process information from the semiconductor storage device; determining whether the process information indicates an enhanced process or a conventional process; determining one of a plurality of operating modes based on the determined result; as well as Setting a mode register group of the semiconductor memory device so that the semiconductor memory device operates according to the determined operation mode, wherein the plurality of operation modes define power consumption of the semiconductor memory device and response characteristics of the semiconductor memory device, the response characteristics defining a plurality of mutually different time delays for data to be output in response to a read command of the semiconductor memory device, and The multiple operation modes include: a first operating mode, in which the semiconductor memory device is configured to operate at a first time delay and a first voltage, a second operating mode, in which the semiconductor memory device is configured to operate at the first time delay and a second voltage, the second voltage being lower than the first voltage, and A third operation mode, in which the semiconductor memory device is configured to operate at a second time delay and the first voltage, the second time delay being smaller than the first time delay.

10. The method according to claim 9, wherein The semiconductor memory device includes: a cell array storing the data, and a peripheral circuit configured to control the cell array and control input / output of the data, and The process information corresponds to a process for manufacturing the peripheral circuit.

11. The method according to claim 10, wherein: The enhancement process corresponds to a high-K metal gate process or a FinFET process.

12. The method according to claim 10, wherein: The reading of the process information is performed by mode register reading for reading the process information stored in the mode register set of the semiconductor memory device.

13. The method according to claim 10, wherein: The reading of the process information is performed by a control operation for reading the process information programmed in a nonvolatile memory element provided in the semiconductor memory device.

14. The method according to claim 13, wherein The semiconductor memory device includes a dedicated pin for outputting the process information.

15. The method according to claim 9, further comprising: After the mode register set of the semiconductor memory device is set, a training operation is performed to optimize timing and reference voltage levels of the semiconductor memory device.

16. A semiconductor memory device comprising: a cell array comprising a plurality of dynamic random access memory cells for storing data; a peripheral circuit configured to write data into the cell array, or sense and output data stored in the cell array; as well as a mode register set circuit configured to output process information about the peripheral circuit to the outside and set the semiconductor memory device to operate in one of a plurality of operation modes in response to a mode register write request, wherein the plurality of operation modes define power consumption of the semiconductor memory device and response characteristics of the semiconductor memory device, the response characteristics defining a plurality of mutually different time delays for data to be output in response to a read command of the semiconductor memory device, and The multiple operation modes include: a first operating mode, in which the semiconductor memory device is configured to operate at a first time delay and a first voltage, a second operating mode, in which the semiconductor memory device is configured to operate at the first time delay and a second voltage, the second voltage being lower than the first voltage, and A third operation mode, in which the semiconductor memory device is configured to operate at a second time delay and the first voltage, the second time delay being smaller than the first time delay.

17. The semiconductor memory device according to claim 16, wherein The process information is output to the outside in response to a mode register read request from the outside.

18. The semiconductor memory device according to claim 16, further comprising a dedicated pin for outputting the process information to the outside.

19. The semiconductor memory device according to claim 16, wherein The process information is provided by using a flag signal indicating whether a process for forming the peripheral circuit is an enhanced process or a conventional process, and The enhancement process includes a high-K metal gate process or a fin field effect transistor process.

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