Semiconductor Memory Device and Method of Manufacturing the Same

Abstract

A semiconductor memory device and a method of manufacturing the same are disclosed. The method may include: forming a molded structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate; patterning the molded structure to form a first trench, the first trench exposing a first inner sidewall of the molded structure; growing a vertical semiconductor layer in the first trench using the substrate as a seed such that the vertical semiconductor layer covers the first inner sidewall; patterning the molded structure to form a second trench, the second trench exposing a second inner sidewall of the molded structure; forming a plurality of recesses by selectively removing the second insulating layer from the molded structure via the second trench; and horizontally growing a plurality of horizontal semiconductor layers in the corresponding recesses using the vertical semiconductor layer as a seed.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the priority of Korean Patent Application No. 10 - 2019 - 0124864, filed with the Korean Intellectual Property Office on October 8, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to a semiconductor device and / or a method of manufacturing the same, and more particularly, to a semiconductor memory device having improved electrical characteristics and / or a method of manufacturing the same. Background art

[0004] Semiconductor devices have been highly integrated to meet the high performance and low manufacturing cost of semiconductor devices required by consumers. Since the integration of semiconductor devices is an important factor determining the product price, the demand for highly integrated semiconductor devices is continuously increasing. The integration degree of typical two - dimensional or planar semiconductor devices is mainly determined by the area occupied by a unit memory cell, and thus it is largely affected by the technical level for forming fine patterns. However, the extremely expensive processing equipment required for fine patterning may pose a practical limit to increasing the integration degree of two - dimensional or planar semiconductor devices. Therefore, three - dimensional semiconductor memory devices having three - dimensionally arranged memory cells have been proposed. Summary of the invention

[0005] Some example embodiments of the present inventive concept provide a three - dimensional semiconductor memory device having improved electrical characteristics and enhanced reliability.

[0006] Some example embodiments of the present inventive concept provide a method of manufacturing a three - dimensional semiconductor memory device having improved electrical characteristics and enhanced reliability.

[0007] According to an example embodiment of the present inventive concept, a method of manufacturing a semiconductor memory device includes: forming a molded structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate; patterning the molded structure to form a first trench that exposes a first inner wall of the molded structure; growing a vertical semiconductor layer in the first trench using the substrate as a seed such that the vertical semiconductor layer covers the first inner wall; patterning the molded structure to form a second trench that exposes a second inner wall of the molded structure; forming a plurality of recesses by selectively removing the second insulating layer from the molded structure via the second trench; and horizontally growing a plurality of horizontal semiconductor layers in the corresponding recesses using the vertical semiconductor layer as a seed.

[0008] According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a stacked structure including a plurality of layers vertically stacked on a substrate, each of the plurality of layers including bit lines extending in a first direction and semiconductor patterns extending from the bit lines in a second direction intersecting the first direction; a gate electrode penetrating the stacked structure and vertically extending along the semiconductor patterns included in each of the plurality of layers; and data storage elements electrically connected to the semiconductor patterns. The data storage elements may include: a first electrode electrically connected to the semiconductor pattern; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode. The semiconductor pattern may have lattice defects extending obliquely from a bottom surface of the semiconductor pattern toward a top surface of the semiconductor pattern.

[0009] According to an exemplary embodiment of the inventive concept, a semiconductor memory device includes: a stacked structure including a plurality of layers vertically stacked on a substrate, each of the plurality of layers including an insulating layer, bit lines extending in a first direction on the insulating layer, and semiconductor patterns extending from the bit lines in a second direction intersecting the first direction; a gate electrode penetrating the stacked structure and vertically extending along the semiconductor patterns included in each of the plurality of layers; and data storage elements electrically connected to the semiconductor patterns. The data storage elements may include: a first electrode electrically connected to the semiconductor pattern; a second electrode on the first electrode; and a dielectric layer between the first electrode and the second electrode. Lattice defects may be present in the semiconductor pattern. The lattice defects may be at an angle of 50° to 60° with respect to a top surface of the insulating layer below the semiconductor pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept is shown.

[0011] Figure 2 A perspective view for showing a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept is shown.

[0012] Figure 3 A perspective view for showing a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept is shown.

[0013] Figure 4A , Figure 4B and Figure 4C respectively show cross-sectional views taken along lines Figure 3 IVA-IVA', IVB-IVB' and IVC-IVC'.

[0014] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A show a plan view for displaying a method of forming a stacked structure according to an exemplary embodiment of the inventive concept.

[0015] Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B respectively show cross-sectional views taken along line V-V′ of Figure 5A , line VI-VI′ of Figure 6A , line VII-VII′ of Figure 7A , line VIII-VIII′ of Figure 8A , line IX-IX′ of Figure 9A and line X-X′ of Figure 10A .

[0016] Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 and Figure 23 show a plan view for displaying a method of manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept.

[0017] Figure 12A , Figure 14A , Figure 16A , Figure 18A , Figure 20A , Figure 22A and 24A respectively show cross-sectional views taken along line XIIA-XIIA′ of Figure 11 , line XIVA-XIVA′ of Figure 13 , line XVI-AXVI′ of Figure 15 , line XVIII-AXVIII′ of Figure 17 , line XXA-XXA′ of Figure 19 , line XXIIA-XXIIA′ of [[ID=~80]] Figure 21 and line XXIVA-XXIVA′ of Figure 23 .

[0018] Figure 12B , Figure 14B , Figure 16B , Figure 18B , Figure 20B , Figure 22B and Figure 24B respectively show cross-sectional views taken along Figure 11Line XIIB-XIIB′, Figure 13 Line XIVB-XIVB′, Figure 15 Line XVIB-XVIB′, Figure 17 Line XVIIIB-XVIIIB′, Figure 19 Line XXB-XXB′, Figure 21 Line XXIIB-XXIIB′, and Figure 23 a cross-sectional view taken along line XXIVB-XXIVB′. DETAILED DESCRIPTION

[0019] Figure 1 A simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept is shown.

[0020] Referring to Figure 1 , a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept may include a cell array including a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged along a second direction D2.

[0021] Each sub-cell array SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. One memory cell transistor MCT may be disposed between one word line WL and one bit line BL.

[0022] The bit line BL may be a conductive pattern (e.g., a metal line) spaced apart from the substrate and disposed on the substrate. The bit line BL may extend in a first direction D1. The bit lines BL in one sub-cell array SCA may be spaced apart from each other in a vertical direction (e.g., a third direction D3).

[0023] The word line WL may be a conductive pattern (e.g., a metal line) extending from the substrate in a vertical direction (e.g., a third direction D3). The word lines WL in one sub-cell array SCA may be spaced apart from each other in a first direction D1.

[0024] The gate of the memory cell transistor MCT may be connected to the word line WL, and the source of the memory cell transistor MCT may be connected to the bit line BL. Each memory cell transistor MCT may include a data storage element DS. For example, the data storage element DS may be a capacitor, and the drain of the memory cell transistor MCT may be connected to the capacitor.

[0025] Figure 2 A perspective view for showing a three-dimensional semiconductor memory device according to an exemplary embodiment of the inventive concept is shown.

[0026] Referring to Figure 1 and Figure 2 , a reference may be provided on the substrate SUBFigure 1 One of the multiple sub - unit arrays SCA under discussion. For example, the substrate SUB can be a silicon substrate, a germanium substrate, or a silicon - germanium substrate.

[0027] For example, a stacked structure SS including a first layer L1, a second layer L2, and a third layer L3 can be provided on the substrate SUB. The first layer L1, the second layer L2, and the third layer L3 of the stacked structure SS can be spaced apart and stacked in a vertical direction (e.g., the third direction D3). Each of the first layer L1, the second layer L2, and the third layer L3 can include a plurality of semiconductor patterns SP, a plurality of data storage elements DS, and bit lines BL.

[0028] Each semiconductor pattern SP can have one of a linear shape, a bar shape, or a columnar shape extending in the second direction D2. The semiconductor pattern SP can include, for example, silicon, germanium, or silicon - germanium. Each semiconductor pattern SP can include a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH can be inserted between the first impurity region SD1 and the second impurity region SD2. The channel region CH can correspond to the channel of the memory cell transistor MCT under discussion. Figure 1 The first impurity region SD1 and the second impurity region SD2 can correspond to the source and drain of the memory cell transistor MCT under discussion. Figure 1 under discussion.

[0029] The first impurity region SD1 and the second impurity region SD2 can be regions in which the semiconductor pattern SP is doped with impurities. The first impurity region SD1 and the second impurity region SD2 can have n - type conductivity or p - type conductivity, respectively.

[0030] The data storage element DS can be connected to the corresponding end of the semiconductor pattern SP. The data storage element DS can be correspondingly connected to the second impurity region SD2 of the semiconductor pattern SP. The data storage element DS can be a memory element capable of storing data. Each data storage element DS can be a memory element using one of a capacitor, a magnetic tunnel junction pattern, or a variable - resistance member including a phase - change material. For example, each data storage element DS can be a capacitor.

[0031] Each bit line BL can have a linear shape or a bar shape extending in the first direction D1. The bit lines BL can be spaced apart from each other and stacked along the third direction D3. The bit line BL can include a conductive material. For example, the conductive material can include one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride material (e.g., titanium nitride or tantalum nitride), a metal material (e.g., tungsten, titanium, or tantalum), and a metal - semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide). The bit line BL can correspond to the bit line BL under discussion. Figure 1 under discussion.

[0032] In the first layer L1, the second layer L2, and the third layer L3, the first layer L1 will be described in detail representatively below. The semiconductor patterns SP of the first layer L1 may be spaced apart from each other in the first direction D1. The semiconductor patterns SP of the first layer L1 may be located at the same first level. The bit lines BL of the first layer L1 may be connected to the ends of the semiconductor patterns SP of the first layer L1. For example, the bit line BL may be directly connected to the first impurity region SD1. As another example, the bit line BL may be electrically connected to the first impurity region SD1 through a metal silicide. The above detailed description of the first layer L1 may also be applied to the second layer L2 and the third layer L3 in the same or substantially similar manner.

[0033] A gate electrode GE penetrating the stacked structure SS may be provided on the substrate SUB. The gate electrode GE may have a linear shape or a bar shape extending in the third direction D3. The gate electrode GE may be arranged in the first direction D1. When observed in a plan view, the semiconductor patterns SP may be stacked between a pair of gate electrodes GE. Each gate electrode GE may vertically extend on the sidewalls of a plurality of vertically stacked semiconductor patterns SP.

[0034] For example, the first pair of gate electrodes GE may be adjacent to the first semiconductor pattern in the semiconductor patterns SP of the first layer L1, the first semiconductor pattern in the semiconductor patterns SP of the second layer L2, and the first semiconductor pattern in the semiconductor patterns SP of the third layer L3. The second pair of gate electrodes GE may be adjacent to the second semiconductor pattern in the semiconductor patterns SP of the first layer L1, the second semiconductor pattern in the semiconductor patterns SP of the second layer L2, and the second semiconductor pattern in the semiconductor patterns SP of the third layer L3.

[0035] The gate electrode GE may be adjacent to the channel region CH of the semiconductor pattern SP. The gate electrode GE may be provided on the sidewall of the channel region CH and may extend in the third direction D3. A gate insulating layer GI may be inserted between the gate electrode GE and the channel region CH. The gate insulating layer GI may include a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. For example, the high-k dielectric layer may include one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0036] The gate electrode GE may include a conductive material, which may be a doped semiconductor material, a conductive metal nitride material, a metal material, or a metal-semiconductor compound. The gate electrode GE may correspond to the word line WL discussed in reference Figure 1 discussed.

[0037] An insulating structure ISS extending in a first direction D1 along one side surface of the stacked structure SS may be disposed on the substrate SUB. The insulating structure ISS may include one or more of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0038] Although not shown, a dielectric material may fill the empty space in the stacked structure SS. For example, the dielectric material may include one or more of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0039] Figure 3 A perspective view showing a three-dimensional semiconductor memory device according to an example embodiment of the inventive concept is shown. Figure 4A 、 Figure 4B and Figure 4C Shown are the Figure 3 In the following description, the cross-sectional views taken along the lines IVA-IVA', IVB-IVB' and IVC-IVC' will be omitted. Figure 1 and Figure 2 The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail.

[0040] Reference Figure 3 and Figures 4A to 4C , a stacked structure SS may be provided on the substrate SUB. The stacked structure SS may extend in the first direction D1. Although not shown, the stacked structure SS may be provided in plurality, and the plurality of stacked structures SS may be arranged in the second direction D2.

[0041] The stacked structure SS may include a first layer L1, a second layer L2, a third layer L3, and a fourth layer L4 sequentially stacked on a substrate SUB. Each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 may include a first insulating layer IL1, a semiconductor pattern SP, and a bit line BL. The first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 are examples according to example embodiments of the present inventive concepts, and one or more additional layers may be stacked on the fourth layer L4.

[0042] The semiconductor pattern SP and the bit line BL may be disposed on the first insulating layer IL1. The semiconductor pattern SP and the bit line BL may be disposed parallel to each other on the first insulating layer IL1. The first insulating layer IL1 may vertically (e.g., in a third direction D3) separate the upper semiconductor pattern SP from the lower semiconductor pattern SP. The first insulating layer IL1 may separate the upper bit line BL from the lower bit line BL in the third direction D3.

[0043] The bit lines BL of each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can extend in the first direction D1. The bit lines BL can be located at the same level as the semiconductor pattern SP. One sidewall of the bit line BL can face one sidewall of the semiconductor pattern SP. One sidewall of the bit line BL can contact one sidewall of the semiconductor pattern SP.

[0044] The semiconductor pattern SP can include a semiconductor material such as silicon, germanium, or silicon germanium. For example, the semiconductor pattern SP can include single-crystalline silicon. At least one semiconductor pattern SP can have a lattice defect LD therein. The lattice defect LD can extend obliquely from the bottom surface of the semiconductor pattern SP toward the top surface of the semiconductor pattern SP. The lattice defect LD can be at an angle θ1 of 50° to 60° with respect to the top surface of the first insulating layer IL1. For example, the angle θ1 can be about 54.7°.

[0045] The first insulating layer IL1 can include one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer.

[0046] The semiconductor patterns SP of each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can be provided in plural. Each of the semiconductor patterns SP among the plural semiconductor patterns SP of each of the first layer L1, the second layer L2, the third layer L3, and the fourth layer L4 can have a bar shape extending from the bit line BL in the second direction D2. Each semiconductor pattern SP can include a channel region CH, a first impurity region SD1, and a second impurity region SD2. The channel region CH can be inserted between the first impurity region SD1 and the second impurity region SD2. The bit line BL can be electrically connected to the first impurity region SD1 of the semiconductor pattern SP.

[0047] The hole HO can be defined to penetrate the stacked structure SS. The hole HO can be located between a pair of adjacent semiconductor patterns SP. The gate electrode GE can extend in the vertical direction (e.g., the third direction D3) in the hole HO that penetrates the stacked structure SS. For example, the gate electrode GE can penetrate the stacked structure SS.

[0048] The gate electrode GE can include a first gate electrode GE1 and a second gate electrode GE2 on opposite sides of the channel region CH of the semiconductor pattern SP. For example, the first gate electrode GE1 and the second gate electrode GE2 can constitute a single word line WL. Again, for example, the first gate electrode GE1 can be the word line WL, and the second gate electrode GE2 can be a back gate.

[0049] The gate insulating layer GI can be inserted between each gate electrode GE and each semiconductor pattern SP. The gate insulating layer GI can include a high-k dielectric layer, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

[0050] A vertical insulating layer VIP can be provided to fill the hole HO. The vertical insulating layer VIP can cover the gate electrode GE. For example, the vertical insulating layer VIP can be inserted between a pair of gate electrodes GE facing each other in the hole HO. The vertical insulating layer VIP can be inserted between a pair of adjacent semiconductor patterns SP. The vertical insulating layer VIP can include one or more of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0051] The data storage element DS can be arranged to be electrically connected to the corresponding semiconductor pattern SP. Each data storage element DS can include a first electrode EL1, a dielectric layer DL, and a second electrode EL2. The data storage elements DS in the stacked structure SS can share a dielectric layer DL and a second electrode EL2. For example, a plurality of first electrodes EL1 can be provided in the stacked structure SS, and a dielectric layer DL can cover the surface of the first electrode EL1. A second electrode EL2 can be provided on one dielectric layer DL. Each first electrode EL1 can have a cylindrical shape with one end open. The second electrode EL2 can fill the cylindrical interior of the first electrode EL1.

[0052] Each of the first electrode EL1 and the second electrode EL2 can include one or more of a metal material (e.g., titanium, tantalum, tungsten, copper, or aluminum), a conductive metal nitride material (e.g., titanium nitride or tantalum nitride), and a doped semiconductor material (e.g., doped silicon or doped germanium). The dielectric layer DL can include a high-k dielectric material (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof).

[0053] The first silicide pattern SC1 can be inserted between the bit line BL and the semiconductor pattern SP. The second silicide pattern SC2 can be inserted between the semiconductor pattern SP and the first electrode EL1. The bit line BL can be electrically connected to the first impurity region SD1 through the first silicide pattern SC1. The first electrode EL1 can be electrically connected to the second impurity region SD2 through the second silicide pattern SC2. The first silicide pattern SC1 and the second silicide pattern SC2 can include a metal silicide (e.g., cobalt silicide).

[0054] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A show a plan view for forming a stacked structure according to an exemplary embodiment of the inventive concept. Figure 5B , Figure 6B , Figure 7B , Figure 8B ,Figure 9B and Figure 10B respectively show cross-sectional views taken along line V-V' of Figure 5A , line VI-VI' of Figure 6A , line VII-VII' of Figure 7A , line VIII-VIII' of Figure 8A , line IX-IX' of Figure 9A and line X-X' of Figure 10A .

[0055] Referring to Figure 5A and Figure 5B , a molded structure MS can be formed on the substrate SUB. The formation of the molded structure MS can include alternately stacking a first insulating layer IL1 and a second insulating layer IL2 on the substrate SUB.

[0056] The first insulating layer IL1 and the second insulating layer IL2 can include one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. The first insulating layer IL1 and the second insulating layer IL2 can have an etching selectivity with respect to each other. For example, the first insulating layer IL1 can be formed of a silicon oxide layer (e.g., SiO), and the second insulating layer IL2 can be formed of a silicon nitride layer (e.g., SiN).

[0057] The molded structure MS can be patterned to form a first trench TR1. The first trench TR1 can extend in a first direction D1. The first trench TR1 can be arranged at regular intervals in a second direction D2. The first trench TR1 can expose the top surface of the substrate SUB.

[0058] Referring to Figure 6A and Figure 6B , a vertical semiconductor layer VSL and a third insulating layer IL3 can fill each first trench TR1. For example, spacers can cover the inner walls of the first trench TR1. On the spacers, the third insulating layer IL3 can completely fill the first trench TR1. The spacers can be selectively removed, and then a vertical semiconductor layer VSL can be formed in the space where the spacers are removed.

[0059] The vertical semiconductor layer VSL can be formed by a selective epitaxial growth process using the top surface of the substrate SUB as a seed. The vertical semiconductor layer VSL can grow monocrystalline along the crystal structure of the substrate SUB. For example, the vertical semiconductor layer VSL can be a single-crystalline silicon layer. The first trench TR1 can expose the inner walls of the molded structure MS, and the vertical semiconductor layer VSL can cover the inner walls of the molded structure MS.

[0060] Referring to Figure 7A and Figure 7B, the molded structure MS can be patterned to form second trenches TR2 between adjacent first trenches TR1. The second trenches TR2 can extend in a first direction D1 parallel to the first trenches TR1. A plurality of second trenches TR2 can be arranged at regular intervals in a second direction D2. For example, the spacing between the second trenches TR2 can be the same as or substantially similar to the spacing between the first trenches TR1.

[0061] The second trenches TR2 can expose other inner walls of the molded structure MS. The second trenches TR2 can expose a second insulating layer IL2 of the molded structure MS, and the second insulating layer IL2 can be selectively removed. Removing the second insulating layer IL2 can include performing a wet etching process that selectively etches the second insulating layer IL2. A first recess RS1 can be defined at the space where the second insulating layer IL2 is removed. The first recess RS1 can expose a vertical semiconductor layer VSL.

[0062] Referring to Figure 8A and Figure 8B , a horizontal semiconductor layer HSL can fill each first recess RS1. The formation of the horizontal semiconductor layer HSL can include performing a selective epitaxial growth process using the vertical semiconductor layer VSL as a seed. The horizontal semiconductor layer HSL can be grown from the vertical semiconductor layer VSL in the second direction D2. The selective epitaxial growth process can continue until the horizontal semiconductor layer HSL completely fills the first recess RS1.

[0063] The horizontal semiconductor layer HSL can grow monocrystalline along the crystal structure of the vertical semiconductor layer VSL. For example, the horizontal semiconductor layer HSL can be a single-crystalline silicon layer. The horizontal semiconductor layer HSL can be sandwiched between first insulating layers IL1 overlying and underlying it.

[0064] When the horizontal semiconductor layer HSL is selectively epitaxially grown while filling the first recess RS1, the horizontal semiconductor layer HSL can have lattice defects LD that occur due to the difference in crystal structure between the horizontal semiconductor layer HSL and the first insulating layer IL1. For example, at least one horizontal semiconductor layer HSL can include lattice defects LD. The lattice defects LD can extend obliquely from the bottom surface to the top surface of the horizontal semiconductor layer HSL. The lattice defects LD can form an angle θ1 of 50° to 60° with respect to the top surface of the first insulating layer IL1. For example, the angle θ1 can be about 54.7°.

[0065] Referring to Figure 9A and Figure 9B, a sacrificial layer (e.g., a polysilicon layer) may partially fill the second trench TR2, and then a silicon trimming process may be performed to remove an overgrown horizontal semiconductor layer HSL. Accordingly, a stacked structure SS in which a first insulating layer IL1 and a horizontal semiconductor layer HSL are alternately stacked may be provided.

[0066] The stacked structure SS may be inserted between the first trench TR1 and the second trench TR2. The stacked structure SS may extend in a first direction D1. A plurality of stacked structures SS may be arranged at regular intervals along a second direction D2. For example, the stacked structure SS may include a first layer L1 to a fourth layer L4. Each of the first layer L1 to the fourth layer L4 may include a first insulating layer IL1 and a horizontal semiconductor layer HSL. A lattice defect LD may be included in at least one of the horizontal semiconductor layers HSL of the stacked structure SS.

[0067] Subsequently, a fourth insulating layer IL4 may fill the second trench TR2. The fourth insulating layer IL4 may be inserted between the stacked structures SS adjacent to each other in the second direction D2.

[0068] Referring to Figure 10A and Figure 10B , the third insulating layer IL3 may be selectively removed from the first trench TR1. After removing the third insulating layer IL3, the vertical semiconductor layer VSL may be selectively removed. The removal of the vertical semiconductor layer VSL may include performing a silicon trimming process. Thereafter, a fifth insulating layer IL5 may be formed to fill the first trench TR1.

[0069] Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 and Figure 23 show a plan view of a method of manufacturing a three-dimensional semiconductor memory device according to an exemplary embodiment of the present inventive concept. Figure 12A , Figure 14A , Figure 16A , Figure 18A , Figure 20A , Figure 22A and 24A respectively show cross-sectional views taken along lines XIIA-XIIA′ of Figure 11 , lines XIVA-XIVA′ of Figure 13 , lines XVI-A-XVIA′ of Figure 15 , lines XVIIIA-XVIIIA′ of Figure 17 , lines XXA-XXA′ of Figure 19 , lines XXIIA-XXIIA′ of Figure 21 and Figure 23A cross-sectional view taken along line XXIVA-XXIVA′. Figure 12B , Figure 14B , Figure 16B , Figure 18B , Figure 20B , Figure 22B and Figure 24B Shown are the Figure 11 Line XIIB-XIIB′, Figure 13 The line XIVB-XIVB′, Figure 15 The line XVIB-XVIB′, Figure 17 Line XVIIIB-XVIIIB′, Figure 19 Line XXB-XXB′, Figure 21 The line XXIIB-XXIIB′ and Figure 23 A cross-sectional view taken along line XXIVB-XXIVB′. Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 and Figure 23 Shown Figure 10A An enlarged plan view of section XI depicted in FIG.

[0070] Reference Figure 11 , Figure 12A and Figure 12B , the substrate SUB may be provided with the above Figure 10A and Figure 10B The stacked structure SS shown in FIG. The first trench TR1 and the second trench TR2 may be defined on opposite sides of the stacked structure SS. The first trench TR1 may be filled with the fifth insulating layer IL5, and the second trench TR2 may be filled with the fourth insulating layer IL4. For example, the stacked structure SS may be interposed between the fourth insulating layer IL4 and the fifth insulating layer IL5. An example in which only the first to fourth layers L1 to L4 are shown in the stacked structure SS will be described below. However, the present invention is not limited thereto, and the stacked structure SS may further include one or more additional layers repeatedly stacked on the fourth layer L4.

[0071] Each of the first to fourth layers L1 to L4 of the stacked structure SS may include a first insulating layer IL1 and a horizontal semiconductor layer HSL on the first insulating layer IL1. The horizontal semiconductor layer HSL may include a semiconductor material, for example, single crystal silicon. The first insulating layer IL1 may include one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a carbon-containing silicon oxide layer, a carbon-containing silicon nitride layer, or a carbon-containing silicon oxynitride layer. As described above, at least one horizontal semiconductor layer HSL may include a lattice defect LD. Illustration of the lattice defect LD is omitted in the following figures.

[0072] ReferenceFigure 13 , Figure 14A and Figure 14B , the stacked structure SS can be patterned to form holes HO that penetrate the stacked structure SS. Each hole HO can have a linear shape or a bar shape extending in the second direction D2. The holes HO can be arranged spaced apart from each other in the first direction D1. The holes HO can define a plurality of semiconductor patterns SP on a horizontal semiconductor layer HSL. For example, a semiconductor pattern SP can be defined by a pair of adjacent holes HO. Each semiconductor pattern SP can have a bar shape extending in the second direction D2. The semiconductor patterns SP can be arranged at regular intervals in the second direction D1.

[0073] Referring to Figure 15 , Figure 16A and Figure 16B , a gate electrode GE and a gate insulating layer GI can be formed in each hole HO. For example, a gate insulating layer and a gate electrode layer can be formed in the hole HO, and then the gate insulating layer and the gate electrode layer can be patterned to form the gate insulating layer GI and the gate electrode GE. The stacked structure SS can have an inner sidewall exposed to the hole HO, and the gate electrode GE and the gate insulating layer GI can extend in the third direction D3 along the inner sidewall of the stacked structure SS. The gate electrode GE can include a first gate electrode GE1 and a second gate electrode GE2 disposed on opposite sides of the semiconductor pattern SP.

[0074] After forming the gate electrode GE, a vertical insulating layer VIP can be formed to fill the hole HO. The vertical insulating layer VIP can include one or more of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0075] Referring to Figure 17 , Figure 18A and Figure 18B , a bit line BL can replace a portion of the horizontal semiconductor layer HSL other than the semiconductor pattern SP. For example, the fifth insulating layer IL5 can be selectively removed to expose one sidewall of the stacked structure SS exposed to the first trench TR1. A wet etching process can be performed to selectively etch the horizontal semiconductor layer HSL on the one sidewall exposed to the first trench TR1. The etching process can partially remove the horizontal semiconductor layer HSL. A conductive material can be deposited at the position where the horizontal semiconductor layer HSL is removed, thereby forming the bit line BL. The bit line BL can extend in the first direction D1. The bit line BL can be electrically connected to the semiconductor pattern SP.

[0076] A first silicide pattern SC1 can be formed between the bit line BL and each semiconductor pattern SP. The formation of the first silicide pattern SC1 can include: performing a silicidation reaction on the semiconductor pattern SP exposed by partially removing the horizontal semiconductor layer HSL before forming the first silicide pattern SC1.

[0077] The first impurity region SD1 may be formed in the corresponding semiconductor pattern SP. The formation of the first impurity region SD1 may include introducing a doped impurity into an end portion of the semiconductor pattern SP exposed by removing a portion of the horizontal semiconductor layer HSL before forming the bit line BL.

[0078] Referring to Figure 19 、 Figure 20A and Figure 20B , an insulating structure ISS may be formed to fill the first trench TR1. The insulating structure ISS may include one or more of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The fourth insulating layer IL4 may be selectively removed to expose other sidewalls of the stacked structure SS exposed to the second trench TR2. The second trench TR2 may expose the sidewalls of the vertical insulating layer VIP, the sidewalls of the first insulating layer IL1 of the stacked structure SS, and the sidewalls of the semiconductor pattern SP of the stacked structure SS.

[0079] Referring to Figure 21 、 Figure 22A and Figure 22B , the semiconductor pattern SP exposed to the second trench TR2 may be partially removed to form a second recess RS2. The formation of the second recess RS2 may include performing a wet etching process to selectively etch the semiconductor pattern SP exposed to the second trench TR2.

[0080] The second recess RS2 may extend horizontally toward the bit line BL. The second recess RS2 may be surrounded by the first insulating layer IL1 and the vertical insulating layer VIP. The second recess RS2 may have a first width W1 in a first direction D1. The first width W1 may be the same as or substantially similar to the width of the semiconductor pattern SP.

[0081] The vertical insulating layer VIP may be selectively etched through the second recess RS2, so the second recess RS2 may expand in the first direction D1. Since the vertical insulating layer VIP is selectively etched, the vertical insulating layer VIP may be removed at portions thereof adjacent to the second recess RS2. The above expansion may allow the second recess RS2 to have a second width W2 in the first direction D1. The second width W2 may be greater than the first width W1.

[0082] A second silicide pattern SC2 may be formed on the semiconductor pattern SP exposed to the second recess RS2. The formation of the second silicide pattern SC2 may include performing a silicidation reaction on the semiconductor pattern SP exposed to the second recess RS2.

[0083] A second impurity region SD2 may be formed in a corresponding semiconductor pattern SP. The formation of the second impurity region SD2 may include introducing a doped impurity into the semiconductor pattern SP exposed to the second recess RS2 before forming the second silicide pattern SC2.

[0084] Referring Figure 23 、 Figure 24A and Figure 24B , a first electrode EL1 may be formed in a corresponding second recess RS2. For example, the formation of the first electrode EL1 may include conformally forming a first electrode layer in the second recess RS2 and performing a wet etching process to divide the first electrode layer into a plurality of first electrodes EL1. Accordingly, the first electrode EL1 may have a cylindrical shape with one end open.

[0085] Return reference Figure 3 、 Figures 4A to 4C , a dielectric layer DL may be conformally formed on the first electrode EL1. The dielectric layer DL may cover an exposed surface of the first electrode EL1. A second electrode EL2 may be formed on the dielectric layer DL. The second electrode EL2 may completely fill the second trench TR2 and the second recess RS2. The first electrode EL1, the dielectric layer DL, and the second electrode EL2 may constitute a data storage element DS.

[0086] In a device manufacturing method according to some example embodiments of the inventive concept, a vertical semiconductor layer VSL and a horizontal semiconductor layer HSL may be used to form vertically stacked semiconductor patterns SP, each having the same crystal structure as that of a substrate SUB. For example, according to some example embodiments of the inventive concept, the semiconductor pattern SP may be formed of single-crystalline silicon serving as a channel of a semiconductor memory device. Accordingly, the semiconductor memory device of the inventive concept may improve reliability and electrical characteristics.

[0087] According to some example embodiments of the inventive concept, a three-dimensional semiconductor memory device may include stacked semiconductor patterns formed of single-crystalline silicon and serving as channels. Accordingly, the three-dimensional semiconductor memory device may improve electrical characteristics.

[0088] According to some example embodiments of the inventive concept, a device manufacturing method may grow a horizontal semiconductor layer simultaneously from a vertical semiconductor layer. For example, the horizontal semiconductor layer may be formed along the crystal structure of the vertical semiconductor layer. Accordingly, a three-dimensional semiconductor memory device may be easily implemented and the reliability of the device may be improved.

[0089] Although some example embodiments of the inventive concept have been discussed with reference to the accompanying drawings, it should be understood that various forms and details may be changed without departing from the spirit and scope of the inventive concept. Accordingly, it should be understood that the above-disclosed example embodiments are illustrative in all aspects and not restrictive.

Claims

1. A method of manufacturing a semiconductor memory device, the method comprising: Forming a molded structure by alternately stacking a plurality of first insulating layers and a plurality of second insulating layers on a substrate; Patterning the molded structure to form a first trench that exposes a first inner wall of the molded structure; Growing a vertical semiconductor layer in the first trench using the substrate as a seed such that the vertical semiconductor layer covers the first inner wall; Patterning the molded structure to form a second trench that exposes a second inner wall of the molded structure; Forming a plurality of recesses by selectively removing the second insulating layer from the molded structure via the second trench; And Horizontally growing a plurality of horizontal semiconductor layers in the respective recesses using the vertical semiconductor layer as a seed, Wherein, when growing the horizontal semiconductor layers, lattice defects occur in at least one of the horizontal semiconductor layers, and Wherein the lattice defects extend obliquely from a bottom surface of the corresponding horizontal semiconductor layer in the horizontal semiconductor layer toward a top surface of the corresponding horizontal semiconductor layer.

2. The method according to claim 1, wherein The vertical semiconductor layer is grown to have a single crystal structure along a first crystal structure of the substrate.

3. The method according to claim 2, wherein The horizontal semiconductor layer is grown to have a single crystal structure along a second crystal structure of the vertical semiconductor layer.

4. The method according to claim 1, wherein The horizontal semiconductor layers are grown simultaneously from the vertical semiconductor layer.

5. The method according to claim 1, wherein, Forming the vertical semiconductor layer includes: Forming a spacer covering the first inner wall in the first trench; Forming a third insulating layer filling the first trench; and Replacing the spacer with the vertical semiconductor layer.

6. The method according to claim 5, further comprising: Selectively removing the third insulating layer after horizontally growing the horizontal semiconductor layers; And Selectively removing the vertical semiconductor layer.

7. The method according to claim 1, further comprising: Patterning the horizontal semiconductor layers to form a plurality of semiconductor patterns arranged in a first direction; Forming bit lines extending in the first direction such that the semiconductor patterns are electrically connected to the bit lines; And Forming data storage elements electrically connected to each of the semiconductor patterns.

8. The method according to claim 7, further comprising: Forming gate electrodes extending vertically along the semiconductor patterns.

9. A semiconductor memory device, comprising: A stacked structure including a plurality of layers vertically stacked on a substrate, each layer of the plurality of layers including bit lines extending in a first direction and semiconductor patterns extending from the bit lines in a second direction, the second direction intersecting the first direction; Gate electrodes penetrating the stacked structure and extending vertically along the semiconductor patterns included in each layer of the plurality of layers; And Data storage elements electrically connected to the semiconductor patterns, Wherein the data storage elements include: A first electrode electrically connected to the semiconductor pattern; A second electrode on the first electrode; and A dielectric layer between the first electrode and the second electrode, and Wherein, the semiconductor pattern has lattice defects that extend obliquely from the bottom surface of the semiconductor pattern toward the top surface of the semiconductor pattern.

10. The semiconductor memory device according to claim 9, wherein, The semiconductor pattern includes single-crystalline silicon.

11. The semiconductor memory device according to claim 9, further comprising: A first silicide pattern between the semiconductor pattern and the bit line; And A second silicide pattern between the semiconductor pattern and the first electrode.

12. The semiconductor memory device according to claim 9, wherein, The semiconductor pattern includes: A first impurity region electrically connected to the bit line; A second impurity region electrically connected to the first electrode; and A channel region between the first impurity region and the second impurity region and adjacent to the gate electrode.

13. The semiconductor memory device according to claim 9, wherein, The gate electrode includes: A first gate electrode adjacent to a first side of the semiconductor pattern; and A second gate electrode adjacent to a second side of the semiconductor pattern, the second side being opposite to the first side.

14. A semiconductor memory device, comprising: A stacked structure including a plurality of layers vertically stacked on a substrate, each of the plurality of layers including an insulating layer, a bit line extending in a first direction on the insulating layer, and a semiconductor pattern extending from the bit line in a second direction intersecting the first direction; A gate electrode penetrating the stacked structure and extending vertically along the semiconductor pattern included in each of the plurality of layers; And A data storage element electrically connected to the semiconductor pattern, Wherein, the data storage element includes: A first electrode electrically connected to the semiconductor pattern; A second electrode on the first electrode; and A dielectric layer between the first electrode and the second electrode, Wherein, the semiconductor pattern has lattice defects, and Wherein, the lattice defects form an angle of 50° to 60° with respect to the top surface of the insulating layer below the semiconductor pattern.

15. The semiconductor memory device according to claim 14, wherein, The semiconductor pattern includes single-crystalline silicon.

16. The semiconductor memory device according to claim 14, further comprising: A first silicide pattern between the semiconductor pattern and the bit line; And A second silicide pattern between the semiconductor pattern and the first electrode.

17. The semiconductor memory device according to claim 14, wherein, The semiconductor pattern includes: A first impurity region electrically connected to the bit line; A second impurity region electrically connected to the first electrode; and A channel region between the first impurity region and the second impurity region and adjacent to the gate electrode.

18. The semiconductor memory device according to claim 14, wherein, The gate electrode includes: A first gate electrode adjacent to a first side of the semiconductor pattern; and A second gate electrode adjacent to a second side of the semiconductor pattern, the second side being opposite to the first side.

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