An image sensor

Abstract

An image sensor comprises: a semiconductor substrate; an overflow gate structure located in the semiconductor substrate, the overflow gate structure having a first side surface and a second side surface opposite to the first side surface; a diode doping region located in the semiconductor substrate on the first side surface of the overflow gate structure; an overflow drain region located in the semiconductor substrate on the second side surface of the overflow gate structure, the overflow drain region being electrically connected to a power line; the depth of the overflow gate structure is less than the depth of the diode doping region and greater than the depth of the overflow drain region. The performance of the image sensor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an image sensor and a method for forming the same. Background Art

[0002] Image sensors use the photoelectric conversion function of photoelectric devices to convert the light image on the photosensitive surface into an electrical signal that is proportional to the light image. Compared with photosensitive elements such as photodiodes and phototransistors, which are "point" light sources, image sensors are functional devices that divide the light image on its light-receiving surface into many small units and convert them into usable electrical signals. Image sensors are divided into photoconductive camera tubes and solid-state image sensors. Compared with photoconductive camera tubes, solid-state image sensors have the characteristics of small size, light weight, high integration, high resolution, low power consumption, long life, and low price. Therefore, they have been widely used in various industries.

[0003] However, the electrical performance of existing image sensors still needs to be improved. Summary of the invention

[0004] The problem solved by the present invention is to provide an image sensor and a method for forming the same, so as to improve the electrical performance of the image sensor.

[0005] To solve the above problems, the present invention provides an image sensor, comprising: a semiconductor substrate; an overflow gate structure, located in the semiconductor substrate, the overflow gate structure having a first side surface and a second side surface opposite to the first side surface; a diode doping region, located in the semiconductor substrate on the first side surface of the overflow gate structure; an overflow drain region, located in the semiconductor substrate on the second side surface of the overflow gate structure, the overflow drain region being electrically connected to a power line; the depth of the overflow gate structure is less than the depth of the diode doping region and greater than the depth of the overflow drain region.

[0006] Optionally, an additional doped region is further included, which is located in the semiconductor substrate below the overflow gate structure, and the additional doped region, the diode doped region and the overflow drain region are separate from each other.

[0007] Optionally, the additional doping region further includes a first additional doping region and a second additional doping region, the first additional doping region is located at the bottom center of the overflow gate structure, and the second additional doping region is located directly below the first additional doping region.

[0008] Optionally, a distance between the first additional doping region and the second additional doping region is 0.1 micrometer.

[0009] Optionally, the conductivity type of the first additional doping region and the second additional doping region is N-type, the conductivity type of the diode doping region is N-type, and the conductivity type of the overflow drain region is N-type.

[0010] Optionally, the overflow gate structure includes an overflow gate insulating layer and an overflow gate electrode located on the overflow gate insulating layer, and the overflow gate insulating layer surrounds the bottom and sidewalls of the overflow gate electrode.

[0011] The present invention also provides a method for forming an image sensor, comprising: providing a semiconductor substrate; forming a gate trench in the semiconductor substrate, forming an overflow gate insulating layer at the bottom and side of the gate trench, forming an overflow gate electrode on the overflow gate insulating layer, the overflow gate insulating layer and the overflow gate electrode forming an overflow gate structure, the overflow gate structure having a first side surface and a second side surface opposite to the first side surface; forming a diode doping region in the semiconductor substrate on the first side surface of the overflow gate structure; forming an overflow drain region in the semiconductor substrate on the second side surface of the overflow gate structure, the overflow drain region being electrically connected to a power line; the depth of the overflow gate structure is less than the depth of the diode doping region and greater than the depth of the overflow drain region.

[0012] Optionally, after forming the gate trench and before forming the overflow gate insulating layer, an additional doped region is further formed in the semiconductor substrate below the gate trench, and the additional doped region, the diode doped region and the overflow drain region are separated from each other.

[0013] Optionally, forming an additional doped region in the semiconductor substrate below the gate trench further includes forming a first additional doped region located at the bottom center of the gate trench and a second additional doped region directly below the first additional doped region.

[0014] Optionally, a distance between the first additional doping region and the second additional doping region is 0.1 micrometer.

[0015] Optionally, the conductivity type of the first additional doping region and the second additional doping region is N-type, the conductivity type of the diode doping region is N-type, and the conductivity type of the overflow drain region is N-type.

[0016] Optionally, the process of forming the additional doping region includes an ion implantation process.

[0017] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0018] In the image sensor provided by the technical solution of the present invention, the functions of the overflow transistor corresponding to the overflow gate structure include: the overflow drain region needs to be connected to the power line all the time, so that in the clearing timing step, the overflow transistor corresponding to the overflow gate structure is turned on to clear the charge in the photodiode. In the exposure timing step and the readout timing step, the overflow transistor corresponding to the overflow gate structure needs to be turned off to avoid clearing the photogenerated charge accumulated in the photodiode and avoiding affecting the readout signal. The overflow gate structure is made in the semiconductor substrate, so that by setting the depth relationship between the overflow gate structure and the overflow drain region, the channel length from the diode doping region to the overflow drain region can be lengthened, thereby effectively suppressing the leakage from the diode doping region to the overflow drain region.

[0019] Furthermore, since there is an additional doping region in the semiconductor substrate below the overflow gate structure, a potential barrier is formed between the additional doping region and the overflow drain region, so that there are two potential barriers between the diode doping region and the overflow drain region, one is the potential barrier between the diode doping region and the additional doping region, and the other is the potential barrier between the additional doping region and the overflow drain region. Even in the case where the voltage of the power line connected to the overflow drain region is relatively large, due to the provision of the additional doping region, the highest point of the potential barrier between the diode doping region and the overflow drain region is increased under the condition of the voltage of the same large power line. Furthermore, by providing the first additional doping region and the second additional doping region, the highest point will be further increased, that is, the highest point of the potential barrier between the diode doping region and the additional doping region is increased, thereby suppressing leakage from the diode doping region to the additional doping region. Secondly, even if the electrons in the diode doping region cross the potential barrier between the diode doping layer and the additional doping region, since there is still a potential barrier between the additional doping region and the overflow drain region, these electrons will not flow directly to the overflow drain region, but will accumulate in the additional doping region. Furthermore, by setting the first additional doping region and the second additional doping region, the accumulated electron capacity is further increased, which further suppresses the leakage from the diode doping region to the overflow drain region. Therefore, it has a good effect on improving the image quality when shooting in low light. In summary, the performance of the image sensor is improved.

[0020] Furthermore, since the depth of the overflow gate structure is greater than the depth of the overflow drain region, there are channel regions at the corners of the overflow gate structure close to the overflow drain region, and the channel length between the additional doped region and the overflow drain region is increased, further suppressing leakage from the additional doped region to the overflow drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a partial structure of an image sensor in the prior art;

[0022] Figures 2 to 6 It is a schematic diagram of a method for forming an image sensor in the present invention. DETAILED DESCRIPTION

[0023] As described in the background art, the performance of image sensors formed by the prior art is relatively poor.

[0024] Figure 1 Schematic diagram of a partial structure of an image sensor in the prior art, the image sensor includes: a semiconductor substrate 001; an overflow gate structure 002 located on the semiconductor substrate 001; a diode doping region 003 located in the semiconductor substrate 001 on one side of the overflow gate structure 002; and an overflow drain region 004 located in the semiconductor substrate 001 on the other side of the overflow gate structure 002, wherein the overflow drain region 004 is electrically connected to a power line.

[0025] The overflow transistor PG Y The functions of the overflow transistor PG include: Y The drain of the overflow transistor PG needs to be connected to the power line VDD at all times. Y Turn on to clear the charge in the photodiode.

[0026] In the exposure timing step and the readout timing step, the overflow transistor PG needs to be Y closure.

[0027] However, when the voltage of the power supply line VDD is high, even though the overflow transistor PG Y In the off state, the electrons in the photodiode can easily cross the potential barrier and flow to the overflow transistor PG. Y In this case, the accumulated electrons in the photodiode decrease, and the image quality is poor when shooting in low light.

[0028] On this basis, the present invention provides an image sensor, comprising: a semiconductor substrate; an overflow gate structure located in the semiconductor substrate, the overflow gate structure having a first side surface and a second side surface relative to the first side surface; a diode doping region located in the semiconductor substrate on the first side surface of the overflow gate structure; an overflow drain region located in the semiconductor substrate on the second side surface of the overflow gate structure, the overflow drain region being electrically connected to a power line; the depth of the overflow gate structure is less than the depth of the diode doping region and greater than the depth of the overflow drain region; and an additional doping region located in the semiconductor substrate below the overflow gate structure, the additional doping region, the diode doping region and the overflow drain region being separated from each other; the additional doping region further comprises a first additional doping region and a second additional doping region, the first additional doping region being located at the bottom center of the overflow gate structure, and the second additional doping region being located directly below the first additional doping region. The performance of the image sensor is improved.

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 2 to 6 It is a schematic diagram of a method for forming an image sensor in the present invention.

[0031] refer to Figure 2 , a semiconductor substrate 1 is provided.

[0032] The material of the semiconductor substrate 1 includes single crystal silicon.

[0033] The semiconductor substrate 1 has trapped ions, and the conductivity type of the trapped ions is opposite to the conductivity type of the subsequent diode doping region 3 .

[0034] In this embodiment, the conductivity type of the trapped ions is P type.

[0035] Continue to refer Figure 2 , a gate trench is formed in the semiconductor substrate 1, and the process of forming the gate trench includes an etching process, such as a dry etching process or a wet etching process, and the dry etching process includes an anisotropic dry etching process.

[0036] The gate trench 220 has a depth of 0.1 micrometer to 0.2 micrometer.

[0037] refer to Figure 3 , an additional doping region is formed in the semiconductor substrate 1 at the bottom of the gate trench, and the additional doping region also includes a first additional doping region 5 located at the bottom center of the gate trench and a second additional doping region 6 located directly below the first additional doping region. The additional doping region has the following functions: adjusting the energy band morphology of the bottom channel of the overflow transistor.

[0038] The interval between the first additional doping region 5 and the second additional doping region 6 is 0.1 micron. Under this interval, the potential barrier between the additional doping region and the overflow drain region 4, as well as the potential barrier between the additional doping region and the overflow drain diode doping region 3 can be effectively controlled, thereby improving the performance of the image sensor.

[0039] The process of forming the first additional doping region 5 and the second additional doping region 6 includes an ion implantation process, and the conductivity type of the first additional doping region 5 and the second additional doping region 6 is N type.

[0040] refer to Figure 4 After forming the first additional doping region 5 and the second additional doping region 6, an overflow gate structure 2 is formed in the gate trench.

[0041] The method for forming the overflow gate structure 2 includes: forming an overflow gate insulating layer 21 at the bottom and side of the gate trench; forming an overflow gate electrode 22 in the gate trench, wherein the overflow gate electrode 22 is located on the overflow insulating layer 21, and the overflow gate insulating layer 21 surrounds the bottom and side of the overflow gate electrode 22.

[0042] The overflow gate insulating layer 21 includes silicon oxide, silicon nitride or silicon oxynitride; and the overflow gate electrode 22 includes polysilicon.

[0043] refer to Figure 5 The overflow gate structure 2 has a first side surface and a second side surface opposite to the first side surface; a diode doping region 3 is formed in the semiconductor substrate 1 on the first side surface of the overflow gate structure 2.

[0044] The top surface of the diode doping region 3 is exposed by the semiconductor substrate 1 .

[0045] In this embodiment, a photodiode is formed. The photodiode includes a diode doping region 3 and a semiconductor substrate 1 at the bottom of the diode doping region 3 .

[0046] In this embodiment, the process of forming the diode doping region 3 is an ion implantation process, and the conductivity type of the diode doping layer 3 is N-type.

[0047] The depth of the diode doping region 3 is 0.5 micrometer to 0.6 micrometer.

[0048] refer to Figure 6 An overflow drain region 4 is formed in the semiconductor substrate 1 on the second side surface of the overflow gate structure 2 , and the depth of the overflow drain region 4 is 0.05 micrometers to 0.1 micrometers.

[0049] In this embodiment, the process for forming the overflow drain region 4 is an ion implantation process, and the conductivity type of the overflow drain region 4 of the diode doping layer 3 is N-type.

[0050] The overflow drain region 4 is electrically connected to a power source VDD, and the overflow drain region 4, the diode doping region 3, and the first additional doping region 5 and the second additional doping region 6 are separated from each other.

[0051] In this embodiment, an overflow transistor is formed. The overflow transistor includes an overflow gate structure 2 and an overflow drain region 4. The diode doping layer region 3 serves as a source region of the overflow transistor.

[0052] The functions of the overflow transistor include: the overflow drain region needs to be always connected to the power line, so that in the clearing timing step, the overflow transistor corresponding to the overflow gate structure is turned on to clear the charge in the photodiode.

[0053] In the exposure timing step and the readout timing step, the overflow transistor corresponding to the overflow gate structure needs to be turned off to avoid clearing the photogenerated charges accumulated in the photodiode and to avoid affecting the readout signal.

[0054] The functions of the overflow gate structure 2 located in the semiconductor substrate 1 include: by setting the depth relationship between the overflow gate structure and the overflow drain region, the channel length from the diode doping region to the overflow drain region can be lengthened, thereby further suppressing leakage from the diode doping layer to the overflow drain region.

[0055] In this embodiment, the depth of the diode doping region 3 is greater than the depth of the overflow gate structure 2, and the depth of the overflow gate structure 2 is greater than the depth of the overflow drain region 4. As a result, channel regions exist at the corners of the overflow gate structure 2 close to the overflow drain region 4, and the channel length from the additional doping region to the overflow drain region 4 is increased, further suppressing leakage from the additional doping region to the overflow drain region 4.

[0056] Correspondingly, this embodiment also provides an image sensor formed by the above method, please refer to Figure 6 ,include:

[0057] A semiconductor substrate 1;

[0058] An overflow gate structure 2 is located in a semiconductor substrate 1, and the overflow gate structure 2 has a first side surface and a second side surface opposite to the first side surface; the overflow gate structure 2 includes an overflow gate insulating layer 21 and an overflow gate electrode 22 located on the overflow gate insulating layer 21, and the overflow gate insulating layer 21 surrounds the bottom and side walls of the overflow gate electrode 22.

[0059] The diode doping region 3 is located in the semiconductor substrate 1 on the first side surface of the overflow gate 2 .

[0060] The overflow drain region 4 is located in the semiconductor substrate 1 on the second side surface of the overflow gate structure 2, and the overflow drain region 4 is electrically connected to the power line VDD; the depth of the overflow gate structure 2 is less than the depth of the diode doping region 3 and greater than the depth 4 of the overflow drain region.

[0061] The additional doped region is located in the semiconductor substrate 1 below the overflow gate structure 2 , and the additional doped region, the diode doped region 3 and the overflow drain region 4 are separate from each other.

[0062] The additional doping region further includes a first additional doping region 5 and a second additional doping region 6 . The first additional doping region 5 is located at the bottom center of the overflow gate structure 2 , and the second additional doping region 6 is located directly below the first additional doping region 5 .

[0063] The interval between the first additional doping region 5 and the second additional doping region 6 is 0.1 micrometer.

[0064] The conductivity type of the first additional doping region 5 and the second additional doping region 6 is N type, the conductivity type of the diode doping region 3 is N type, and the conductivity type of the overflow drain region 4 is N type.

[0065] The depth of the overflow gate structure 2 is 0.1 micrometer to 0.2 micrometer; the depth of the diode doping region 3 is 0.5 micrometer to 0.6 micrometer; the depth of the overflow drain region 4 is 0.05 micrometer to 0.1 micrometer.

[0066] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An image sensor, characterized in that: include: A semiconductor substrate having trapped ions therein, wherein the conductive type of the trapped ions is P type; An overflow gate structure is located in the semiconductor substrate, wherein the overflow gate structure has a first side surface and a second side surface opposite to the first side surface; A diode doping region, located in the semiconductor substrate on the first side surface of the overflow gate structure; an overflow drain region, located in the semiconductor substrate on the second side surface of the overflow gate structure, the overflow drain region being electrically connected to a power line; The depth of the overflow gate structure is less than the depth of the diode doping region and greater than the depth of the overflow drain region; An additional doped region, located in the semiconductor substrate below the overflow gate structure, wherein the additional doped region, the diode doped region and the overflow drain region are separate from each other; The additional doping region further comprises a first additional doping region and a second additional doping region, the first additional doping region is located at the bottom center of the overflow gate structure, and the second additional doping region is located directly below the first additional doping region; The conductivity type of the first additional doping region and the second additional doping region is N type, the conductivity type of the diode doping region is N type, and the conductivity type of the overflow drain region is N type; The interval between the first additional doping region and the second additional doping region is 0.1 micrometer; The depth of the overflow gate structure is 0.1 micrometer to 0.2 micrometer; the depth of the diode doping region is 0.5 micrometer to 0.6 micrometer; the depth of the overflow drain region is 0.05 micrometer to 0.1 micrometer; The overflow gate structure includes an overflow gate insulating layer and an overflow gate electrode located on the overflow gate insulating layer, and the overflow gate insulating layer surrounds the bottom and sidewalls of the overflow gate electrode.

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