Quantum well structure, chip processing method, chip and laser

Abstract

The application relates to the field of laser technology, in particular to a quantum well structure, a chip processing method, a chip and a laser, wherein the quantum well structure comprises InAlAs quantum well layers and InAlGaAs quantum well layers, the InAlAs quantum well layers are arranged in multiple layers, the thickness of the InAlGaAs quantum well layers is the same as that of the InAlAs quantum well layers, and the InAlGaAs quantum well layers are arranged between two adjacent InAlAs quantum well layers, wherein the thickness of the InAlAs quantum well layers is between 0.4 nm and 0.6 nm, and the number of the InAlAs quantum well layers is between 3 and 17. In the application, the thickness of the quantum well layer is small, the ratio of the thickness of the quantum well structure to the thickness of a single quantum well layer is increased under the condition that the thickness of the quantum well structure is unchanged, the value of a quantum well confinement parameter Gamma is increased, the threshold current of the chip is reduced, and the transmission rate of the chip is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of laser, in particular to a quantum well structure, a chip processing method, a chip and a laser. BACKGROUND

[0002] The DFB laser chip structure mainly comprises an N electrode, a multilayer quantum well epitaxial structure, a Bragg grating layer, a ridge waveguide and a P electrode. Laser is mainly formed by ion number inversion of the multilayer quantum well structure under the action of forward current, and the laser is generated by stimulated radiation.

[0003] The multilayer quantum well structure is the key to generate laser. According to the principle of laser, the threshold current of the laser chip is mainly related to the confinement parameter of the quantum well. The larger the confinement parameter of the quantum well is, the smaller the threshold current of the chip is. According to the existing quantum well structure and processing technology, the confinement parameter is small, and the threshold current of the chip is large, which seriously affects the transmission rate of the chip. SUMMARY

[0004] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor to attempt to determine the protection scope of the claimed technical solution.

[0005] In order to solve the technical problem that the large threshold current of the chip causes low transmission rate, the main purpose of the present application is to provide a quantum well structure, a chip processing method, a chip and a laser.

[0006] In order to achieve the above application purpose, the present application adopts the following technical solution:

[0007] A quantum well structure for a DFB laser chip, characterized in that it comprises:

[0008] An InAlAs quantum well layer, the InAlAs quantum well layer is provided with multiple layers;

[0009] An InAlGaAs quantum well layer, the thickness of the InAlGaAs quantum well layer is the same as that of the InAlAs quantum well layer, and the InAlGaAs quantum well layer is arranged between two adjacent InAlAs quantum well layers,

[0010] The thickness of the InAlAs quantum well layer is between 0.4nm and 0.6nm, and the number of the InAlAs quantum well layers is between 3 and 17.

[0011] Further, in some embodiments of the present application, the thickness of the InAlAs quantum well layer is 0.5nm.

[0012] Further, in some embodiments of the present application, the number of InAlAs quantum well layers is 6, and the number of InAlGaAs quantum well layers is 5.

[0013] Further, in some embodiments of the present application, the mass percentage of In in the InAlGaAs quantum well layer is 53%, the mass percentage of Al is 36%, and the mass percentage of Ga and As is 11%.

[0014] A chip processing method, comprising:

[0015] Processing a buffer layer and a lower graded layer group in sequence in a substrate processing;

[0016] Processing a plurality of quantum well layers by a molecular beam epitaxy process, each of the quantum well layers has a thickness of 0.4-0.6nm;

[0017] Processing an upper graded layer group;

[0018] Processing a cover layer, a etching stop layer, a top layer, a transition layer and a contact layer by a vapor phase epitaxy growth technique.

[0019] Further, in some embodiments of the present application, processing a plurality of quantum well layers by a molecular beam epitaxy process comprises:

[0020] Processing 11 quantum well layers by a molecular beam epitaxy process.

[0021] Further, in some embodiments of the present application, each of the quantum well layers has a thickness of 0.5nm.

[0022] Further, in some embodiments of the present application, processing a plurality of quantum well layers by a molecular beam epitaxy process comprises:

[0023] Processing InAlAs quantum well layers and InAlGaAs quantum well layers alternately, and the InAlAs quantum well layer is located at the outer side.

[0024] A chip processed by the chip processing method.

[0025] A laser device installed with the chip.

[0026] According to the technical solutions, the quantum well structure, the chip processing method, the chip and the laser device have the following advantages and positive effects:

[0027] The quantum well confinement parameter is increased, the threshold current of the chip is reduced, and the transmission rate of the chip is improved.

[0028] The application provides a quantum well structure, which comprises InAlAs quantum well layers and InAlGaAs quantum well layers, the InAlAs quantum well layers are arranged in multiple layers, the thickness of the InAlGaAs quantum well layers is the same as that of the InAlAs quantum well layers, and the InAlGaAs quantum well layers are arranged between two adjacent InAlAs quantum well layers, wherein the thickness of the InAlAs quantum well layers is between 0.4 nm and 0.6 nm, and the number of the InAlAs quantum well layers is between 3 and 17.

[0029] The expression of the quantum well confinement parameter Γ is as follows:

[0030] Γ=(2π 2 / λ 2 )(d / dw)(n ra 2 -n rc 2 ), λ is the lasing wavelength, d is the thickness of the active region, that is, the thickness of the entire quantum well structure, dw is the thickness of a single quantum well layer, the quantum well structure in the application is formed by alternately stacking quantum well layers of two materials, the thickness of the InAlAs quantum well layers is the same as that of the InAlGaAs quantum well layers, dw can be the thickness of the InAlAs quantum well layers or the thickness of the InAlGaAs quantum well layers, n ra is the refractive index of the InAlGaAs material, and n rc is the refractive index of the InAlAs material, in the application, the thickness of the InAlAs quantum well layers and the InAlGaAs quantum well layers is small, the quantum well confinement parameter Γ is increased, the threshold current of the chip is reduced, and the transmission rate of the chip is improved.

[0031] The application also provides a chip processing method, which comprises processing a buffer layer and a lower graded layer group on a substrate, processing multiple quantum well layers by a molecular beam epitaxy process, the thickness of each quantum well layer is between 0.4 nm and 0.6 nm, processing an upper graded layer group, and processing a cover layer, a stop layer, a top layer, a transition layer and a contact layer by a vapor phase epitaxy growth technology, the method combines the MOCVD vapor phase epitaxy growth process and the MBE molecular beam epitaxy process, adopts the MBE molecular beam epitaxy process to perform epitaxial growth of the quantum well layers, and adopts the MOCVD vapor phase epitaxy growth process to process each epitaxial growth layer except the quantum well layers, the MBE epitaxial process controls the thickness of the quantum well layers to be between 0.4 nm and 0.6 nm, the thickness of the quantum well structure of the chip is reduced, the transmission rate of the chip is improved, the quantum well confinement parameter Γ is increased, the threshold current of the chip is reduced, and the transmission rate of the chip is improved.

[0032] Another aspect of the present application provides a chip, which is processed by the above processing technology, and the chip has a small threshold current and a large transmission rate.

[0033] The present application also provides a laser, which is installed with the chip. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0036] Figure 1 is a schematic diagram of a quantum well structure according to an exemplary embodiment.

[0037] In the drawings, the reference signs are explained as follows:

[0038] 100-second lower graded layer; 200-second upper graded layer; 300-InAlAs quantum well layer; 400-InAlGaAs quantum well layer. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of protection of the present application. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of protection of the present application.

[0040] The application provides a quantum well structure, a chip processing method, a chip and a laser, wherein the quantum well structure comprises an InAlAs quantum well layer 300 and an InAlGaAs quantum well layer 400, the InAlAs quantum well layer 300 is provided with multiple layers, the thickness of the InAlGaAs quantum well layer 400 is the same as that of the InAlAs quantum well layer 300, and the InAlGaAs quantum well layer 400 is arranged between two adjacent InAlAs quantum well layers 300, wherein the thickness of the InAlAs quantum well layer 300 is between 0.4 nm and 0.6 nm, and the number of the InAlAs quantum well layers 300 is between 3 and 17. The expression of a quantum well confinement parameter Γ is as follows: Γ=(2π 2 / λ 2 )(d / dw)(n ra 2 -n rc 2 ), λ is a lasing wavelength, d is an active region thickness, i.e. the thickness of the entire quantum well structure, dw is a single layer quantum well thickness, in the application, the quantum well structure is formed by interlaced superposition of quantum well layers of two materials, i.e. the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400, the thicknesses of the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 are the same, therefore, dw can be the thickness of the InAlAs quantum well layer 300 or the thickness of the InAlGaAs quantum well layer 400, n ra is the refractive index of the InAlGaAs material, and n rc is the refractive index of the InAlAs material, according to the formula, for example, the number of the InAlAs quantum well layers is 17, the number of the InAlGaAs quantum well layers is 16, and the thickness of the InAlAs quantum well layer is 0.6, the value of d is 19.8 nm, and the ratio of d / dw is 33, therefore, under the condition that the value of d is unchanged, reducing the thicknesses of the InAlAs quantum well layer and the InAlGaAs quantum well layer can increase the value of d / dw, thereby increasing the quantum well confinement parameter Γ, reducing the chip threshold current and improving the chip transmission rate.

[0041] The scheme combines MOCVD gas phase epitaxy process and MBE molecular beam epitaxy process, adopts MBE molecular beam epitaxy process to epitaxially grow quantum well layers, adopts MOCVD gas phase epitaxy process to epitaxially grow each epitaxial growth layer except quantum well layers, and a chip processing method comprises the following steps: processing a buffer layer and a lower graded layer group on a substrate in sequence, processing a plurality of quantum well layers by a molecular beam epitaxy process, the thickness of each quantum well layer is 0.4-0.6 nm, processing an upper graded layer group, processing a cover layer, an etching stop layer, a top layer, a transition layer and a contact layer by a gas phase epitaxy technology, the MBE epitaxial process controls the thickness of the quantum well layer to be 0.4-0.6 nm, thereby reducing the thickness of the quantum well structure, improving the chip transmission rate, increasing the quantum well confinement parameter Γ, and reducing the chip threshold current, thereby improving the chip transmission rate.

[0042] Reference Figure 1 As shown in the figure, the quantum well structure is used in a DFB laser chip, and the quantum well structure comprises a plurality of quantum well layers, in the scheme, the quantum well structure comprises quantum well layers formed by two materials, namely an InAlAs quantum well layer 300 and an InAlGaAs quantum well layer 400, the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 are arranged alternately, and one layer on the outer side is the InAlAs quantum well layer 300.

[0043] In the scheme, the thickness of the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 is the same, the thickness of the InAlAs quantum well layer 300 is 0.4-0.6 nm, preferably, the thickness of the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 is 0.5 nm, and the number of the InAlAs quantum well layer 300 is 3-17, preferably 6 layers.

[0044] The thickness of the quantum well layer is defined as dw, since the thickness of the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 is the same, dw can be the thickness of the InAlAs quantum well layer 300 or the thickness of the InAlGaAs quantum well layer 400, the thickness of the quantum well structure is defined as d, when the number of the InAlAs quantum well layer 300 is 6 layers, the number of the InAlGaAs quantum well layer 400 is 5, the thickness of the InAlAs quantum well layer 300 is 0.5 nm, and the thickness of the quantum well structure is d, which is 5.5 nm, in the InAlGaAs quantum well layer 400, the mass percentage of In is 53%, the mass percentage of Al is 36%, and the mass percentage of Ga and As is 11%.

[0045] The expression of the quantum well confinement parameter Γ is as follows: Γ = (2π 2 / λ2 (d / dw)(n ra 2 -n rc 2 ), λ is the lasing wavelength, n ra is the refractive index of InAlGaAs material, n rc is the refractive index of InAlAs material, the thickness of the quantum well layer is reduced, and the ratio of d / dw is increased when the thickness of the quantum well structure is unchanged, so the value of Γ is increased, and the increase of the quantum well confinement parameter reduces the threshold current of the chip and improves the transmission rate of the chip.

[0046] As shown in Figure 1 , the embodiment also provides a chip processing method, comprising:

[0047] Step 1: processing an InP buffer layer on a substrate;

[0048] Specifically, an InP buffer layer with a thickness of 1 μm is grown on the substrate by a MOCVD gas phase epitaxy growth process.

[0049] Step 2: processing a lower graded layer group on the InP buffer layer;

[0050] Specifically, the lower graded layer group comprises a first lower graded layer and a second lower graded layer 100, the thickness of the first lower graded layer is 50 nm, the thickness of the second lower graded layer 100 is 10 nm, the first lower graded layer is processed on the InP buffer layer by a MOCVD gas phase epitaxy growth process, the second lower graded layer 100 is processed on the first lower graded layer by an MBE epitaxy process, and the materials of the first lower graded layer and the second lower graded layer are both InAlxGaAs.

[0051] The second lower graded layer with a relatively thin thickness is grown by an MBE process, so as to prepare for the subsequent MBE growth of an InAlAs quantum well layer and an InAlGaAs quantum well layer, and avoid the oxidation of Al elements in the growth process when the InAlAs quantum well layer or the InAlGaAs quantum well layer is directly grown, thereby causing the failure of the device.

[0052] Step 3: processing a multilayer quantum well layer by a molecular beam epitaxy process, and the thickness of each quantum well layer is 0.4-0.6 nm;

[0053] Specifically, an InAlAs quantum well layer 300 with a thickness of 0.5 nm and an InAlGaAs quantum well layer 400 with a thickness of 0.5 nm are alternately grown by an MBE molecular beam epitaxy process, the InAlAs quantum well layer 300 is processed for 6 layers, the InAlGaAs quantum well layer 400 is processed for 5 layers, and one layer located at the outer side is the InAlAs quantum well layer 300.

[0054] Step 4: processing the upper graded layer group;

[0055] Specifically, the upper graded layer group includes a 50nm-thick first upper graded layer and a 10nm-thick second upper graded layer 200, the second upper graded layer 200 is processed on the outer InAlAs quantum well layer 300 by MBE molecular beam epitaxy process, the first upper graded layer is processed on the second upper graded layer 200 by MOCVD gas phase epitaxy process, and the material of the first upper graded layer and the first lower graded layer is InAlxGaAs.

[0056] By first generating a relatively thin first upper graded layer by MBE process, the oxidation failure of the InAlAs quantum well layer or the InAlGaAs quantum well layer can be avoided when transferring from the MBE device to the MOVCD device.

[0057] Step 5: processing an InP cover layer;

[0058] Specifically, the 30nm-thick InP cover layer is processed by MOCVD gas phase epitaxy process.

[0059] Step 6: processing an etching stop layer;

[0060] Specifically, the 15nm-thick InGaAsP etching stop layer is processed by MOCVD gas phase epitaxy process.

[0061] Step 7: processing a top layer;

[0062] Specifically, the 16μm-thick InP top layer is processed by MOCVD gas phase epitaxy process.

[0063] Step 8: processing a transition layer;

[0064] Specifically, the 10nm-thick InGaAsP transition layer is processed by MOCVD gas phase epitaxy process.

[0065] Step 9: processing a contact layer;

[0066] Specifically, the 0.2μm-thick InGaAs contact layer is processed by MOCVD gas phase epitaxy process.

[0067] Step 10: performing ridge waveguide back thinning, polishing, positive and negative electrodes, cleavage, end face coating and other process processing to complete chip processing.

[0068] In the scheme, the MOCVD is a new type of vapor phase epitaxy growth technology developed on the basis of vapor phase epitaxy growth, the MOCVD is to take the organic compounds of group III, group II elements and hydride of group V, group VI elements as the crystal growth source material, to carry out vapor phase epitaxy on the substrate 100 in a thermal decomposition reaction mode, and to grow thin layer single crystal materials of various group III-V, group II-VI compound semiconductors and their multi-element solid solutions. MBE refers to a molecular beam epitaxy process. In represents the chemical element indium, P represents the chemical element phosphorus, AI represents the chemical element aluminum, Ga represents the chemical element gallium, and As represents the chemical element arsenic.

[0069] In the embodiment, the MOCVD process is combined with the MBE process to process the chip, the quantum well layer thickness is controlled to be between 0.4nm-0.6nm through the MBE epitaxy process, the thickness of the quantum well structure is reduced, the chip transmission rate is improved, at the same time, the quantum well confinement parameter Γ is increased, the chip threshold current is reduced, and the chip transmission rate is improved.

[0070] The embodiment also provides a chip, which is processed by the chip processing method.

[0071] The embodiment also provides a laser, which is installed with the chip.

[0072] To sum up, the application provides a quantum well structure, a chip processing method, a chip and a laser, the chip processing method adopts the MOCVD process and the MBE process, wherein the MBE process processes the quantum well structure, the MOCVD process processes other epitaxial layers except the quantum well structure, the quantum well structure includes quantum well layers formed by two materials, which are an InAlAs quantum well layer 300 and an InAlGaAs quantum well layer 400, the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 are staggered, one layer on the outer side is the InAlAs quantum well layer 300, the thicknesses of the InAlAs quantum well layer 300 and the InAlGaAs quantum well layer 400 are the same, the thickness of the InAlAs quantum well layer 300 is between 0.4nm-0.6nm, the number of the InAlAs quantum well layer 300 is between 3-17, and the expression of the quantum well confinement parameter Γ is as follows: Γ=(2π 2 / λ 2 )(d / dw)(n ra 2 -n rc 2 ), λ is the lasing wavelength, n ra is the refractive index of the InAlGaAs material, and n rcThe ratio of the thickness d of the quantum well structure to the thickness dw of the single quantum well layer is increased without changing the thickness of the quantum well structure, and thus the value of Γ is increased, and the quantum well confinement parameter is increased, which reduces the threshold current of the chip and improves the transmission rate of the chip.

[0073] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0074] The above description is merely that of the specific embodiments of the present application, allowing those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the generic principles defined herein can be implemented in other embodiments without departing from the general scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip, characterized by: The system comprises a substrate, an InP buffer layer, a lower gradient layer group, and a multilayer quantum well layer. The InP buffer layer is fabricated on the substrate. The lower gradient layer group includes a first lower gradient layer and a second lower gradient layer. The first lower gradient layer is fabricated on the InP buffer layer using MOCVD (Modular Chemical Vapor Deposition) epitaxy, and the second lower gradient layer is fabricated on the first lower gradient layer using MBE (Modular Beam Epitaxy). The thickness of the first lower gradient layer is 50 nm, and the thickness of the second lower gradient layer is 10 nm. The quantum well layer consists of an InAlAs quantum well layer and an InAlGaAs quantum well layer grown alternately using MBE. The expression for the quantum well confinement parameter Γ is as follows: Γ = (2π... 2 / λ 2 )(d / dw)(n ra 2 -n rc 2 ), where λ is the lasing wavelength, d is the thickness of the active region, dw is the thickness of the single-layer quantum well, and n ra n is the refractive index of InAlGaAs material. rc The refractive index of the InAlAs material is given. The number of InAlAs quantum well layers is 17, the number of InAlGaAs quantum well layers is 16, and the thickness of both the InAlAs and InAlGaAs quantum well layers is 0.6 nm.

2. The chip of claim 1, wherein, Comprise: InAlAs quantum well layer, the InAlAs quantum well layer is provided with multiple layers; And the InAlGaAs quantum well layer is arranged between two adjacent InAlAs quantum well layers, The number of the InAlAs quantum well layer is between 3-17.

3. The chip of claim 2, wherein, The number of the InAlAs quantum well layer is 6, and the number of the InAlGaAs quantum well layer is 5.

4. The chip of claim 1, wherein, The mass percentage of In in the InAlGaAs quantum well layer is 53%, the mass percentage of Al is 36%, and the mass percentage of Ga and As is 11% in total.

5. A laser characterized by, The chip of claim 1 is installed.

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