storage device

Abstract

A novel storage device is provided. The storage device includes a plurality of first wirings extending in a first direction, a plurality of storage element groups each including a plurality of storage elements each including a first transistor and a capacitor, and an oxide layer extending along a side surface of the first wirings. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between adjacent storage element groups. One or both of a source electrode and a drain electrode of the second transistor is supplied with a high power supply potential.

Description

Technical Field

[0001] One aspect of the present invention relates to a storage device, a semiconductor device, or an electronic device using such devices.

[0002] Note that one aspect of the present invention is not limited to the aforementioned technical fields. One aspect of the invention disclosed in this specification relates to an object, method, or manufacturing method. Additionally, one aspect of the invention disclosed in this specification relates to a process, machine, manufacture, or composition.

[0003] Note that in this specification, etc., a semiconductor device refers to all devices capable of operating by utilizing the characteristics of semiconductors. Transistors and semiconductor circuits are types of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices sometimes include semiconductor devices. Furthermore, display devices, projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices can also be considered semiconductor devices. Background Technology

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, while oxide semiconductors are attracting attention as other materials. Among oxide semiconductors, in addition to single-metal oxides such as indium oxide and zinc oxide, multi-metal oxides are also known. Among multi-metal oxides, research on In-Ga-Zn oxides (hereinafter also referred to as IGZO) is particularly active.

[0005] Through research on IGZO, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single-crystal nor amorphous, were discovered in oxide semiconductors (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing transistors using oxide semiconductors with CAAC structures. Non-Patent Documents 4 and 5 disclose oxide semiconductors with lower crystallinity than CAAC and nc structures, which also exhibit minute crystals.

[0006] Transistors using IGZO as the active layer have extremely small off-state currents (see Non-Patent Document 6), and LSIs and displays that utilize this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] In addition, a variety of semiconductor devices have been proposed that utilize transistors (hereinafter also referred to as "OS transistors") whose channel formation regions contain oxide semiconductors.

[0008] Patent Document 1 discloses an example of using an OS transistor in a memory cell (memory element) of a memory device. The current flowing between the source and drain of an OS transistor in the off-state (also known as "off-state current") is very small, thus reducing or eliminating the need for a holding capacitor in the memory element. By reducing or eliminating the holding capacitor in the memory element, a highly integrated memory device can be realized.

[0009] [Preliminary Technology Documents]

[0010] [Patent Literature]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2012-256400

[0012] [Non-patent literature]

[0013] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186

[0014] [Non-Patent Literature 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10

[0015] [Non-Patent Literature 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, pp. 151-154

[0016] [Non-Patent Literature 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, pp. Q3012-Q3022

[0017] [Non-Patent Literature 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164

[0018] [Non-Patent Literature 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7

[0019] [Non-Patent Literature 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217

[0020] [Non-Patent Literature 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 Summary of the Invention

[0021] The technical problem that the invention aims to solve

[0022] One objective of this invention is to provide a novel memory device or semiconductor device. Another objective of this invention is to provide a highly reliable memory device or semiconductor device. Another objective of this invention is to provide a memory device or semiconductor device with high integration density. Another objective of this invention is to provide a memory device or semiconductor device with high operating speed. Another objective of this invention is to provide a memory device or semiconductor device with reduced power consumption.

[0023] The description of the aforementioned objectives does not preclude the existence of each other. One embodiment of the invention does not necessarily need to achieve all of the aforementioned objectives. Objectives beyond those described above will naturally be apparent from the specification, drawings, claims, etc., and these objectives may also be objectives of one embodiment of the invention.

[0024] means of solving technical problems

[0025] One aspect of the present invention is a storage device comprising: a plurality of first wirings extending in a first direction; a plurality of storage element groups; and an oxide layer extending along the side of the first wirings, each of the storage element groups comprising a plurality of storage elements, each of the storage elements comprising a transistor and a capacitor. The gate electrode of the transistor is electrically connected to the first wirings. The oxide layer includes a region in contact with a semiconductor layer of the transistor. The shortest distance between the gate electrode of a transistor included in a storage element disposed at one end of a storage element group and the gate electrode of a transistor included in a storage element disposed at an adjacent end of a storage element group is less than 3.5 μm.

[0026] Additionally, one aspect of the present invention is a storage device comprising: a plurality of first wirings extending in a first direction; a plurality of oxide layers; a first group of storage elements; and a second group of storage elements, wherein the plurality of first wirings includes: a region overlapping with the first group of storage elements; and a region overlapping with the second group of storage elements; one of the plurality of oxide layers includes a region extending along a side of one of the first wirings; the first group of storage elements and the second group of storage elements include a plurality of storage elements; each of the plurality of storage elements includes a transistor and a capacitor; in each of the plurality of storage elements, the gate electrode of the transistor is electrically connected to one of the plurality of first wirings; the semiconductor layer of the transistor includes a region contacting one of the plurality of oxide layers; and the shortest distance between the gate electrode of the transistor included in the storage element disposed at the end of the first group of storage elements and the gate electrode of the transistor included in the storage element disposed at the end of the second group of storage elements is less than 3.5 μm.

[0027] The aforementioned minimum distance can also be less than 2.3 μm. Additionally, in one embodiment of the invention described above, a plurality of second wirings extending in the second direction are included, and one of the source and drain electrodes of the transistor can also be electrically connected to one of the plurality of second wirings. In this case, the other of the source and drain electrodes of the transistor is electrically connected to a capacitor.

[0028] Additionally, the oxide layer may include a region that overlaps with the first wiring through an insulating layer. The oxide layer sometimes contains one or both of indium and zinc. The semiconductor layer of the transistor preferably contains at least one of indium and zinc.

[0029] Alternatively, in one of the above methods, a plurality of third wirings extending in the first direction may be provided. Preferably, one of the plurality of third wirings includes an area that overlaps with one of the plurality of first wirings.

[0030] Another aspect of the present invention is a storage device comprising: a plurality of first wirings extending in a first direction; a plurality of oxide layers; a first group of storage elements; a second group of storage elements; and a first region, wherein the plurality of first wirings includes: a region overlapping with the first group of storage elements; a region overlapping with the second group of storage elements; and a region overlapping with the first region, one of the plurality of oxide layers includes a region extending along a side of one of the first wirings, the first group of storage elements and the second group of storage elements include a plurality of storage elements, each of the plurality of storage elements including a first transistor and a capacitor, in each of the plurality of storage elements, the gate of the first transistor is electrically connected to one of the plurality of first wirings, the semiconductor layer of the first transistor includes a region contacting one of the plurality of oxide layers, the first region includes a plurality of second transistors, in each of the plurality of second transistors, the gate electrode is electrically connected to one of the plurality of first wirings, one or both of the source electrode and the drain electrode are electrically connected to a fourth wiring, and the storage device has the function of supplying a high power supply potential to the fourth wiring.

[0031] Invention Effects

[0032] According to one aspect of the present invention, a novel memory device or semiconductor device can be provided. Additionally, according to one aspect of the present invention, a highly reliable memory device or semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a memory device or semiconductor device with high integration density can be provided. Furthermore, according to one aspect of the present invention, a memory device or semiconductor device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a memory device or semiconductor device with reduced power consumption can be provided.

[0033] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the invention does not necessarily require all of the aforementioned effects. Moreover, effects other than those described above are clearly present in the specification, drawings, and claims, and can be obtained from the description in the specification, drawings, and claims.

[0034] Brief description of the attached figures

[0035] Figure 1 This is a diagram illustrating an example of the structure of a storage device.

[0036] Figure 2A and Figure 2B This is a diagram illustrating an example of the structure of a storage block.

[0037] Figure 3 This is an enlarged view of a portion of the cell array.

[0038] Figure 4A and Figure 4BThis is a diagram illustrating an example of the circuit structure of a memory cell.

[0039] Figures 5A to 5C This is a diagram illustrating an example of the structure of two adjacent transistors.

[0040] Figure 6A and Figure 6B This diagram illustrates the process of writing data to a storage unit.

[0041] Figure 7A and Figure 7B This diagram illustrates the process of writing data to a storage unit.

[0042] Figure 8 This is a timing diagram illustrating the process of writing data to a storage unit.

[0043] Figure 9A and Figure 9B This diagram illustrates the process of writing data to a storage unit.

[0044] Figure 10 This is a timing diagram illustrating the process of writing data to a storage unit.

[0045] Figures 11A to 11C This diagram illustrates the process of writing data to a storage unit.

[0046] Figure 12 This is a timing diagram illustrating the process of writing data to a storage unit.

[0047] Figure 13A and Figure 13B This is a diagram illustrating the relationship between the distance between adjacent sub-cell arrays and the holding potential of node ND.

[0048] Figure 14A and Figure 14B This is a diagram illustrating an example of the circuit structure of a pseudo-memory cell.

[0049] Figure 15A and Figure 15B This is a diagram illustrating an example of the circuit structure of a pseudo-memory cell.

[0050] Figure 16A and Figure 16B This is a diagram illustrating the relationship between the spacing of memory cells and the holding potential of the node ND.

[0051] Figure 17A and Figure 17B This is a diagram illustrating the relationship between the height of the word line and the holding potential of the node ND.

[0052] Figure 18A and Figure 18B This diagram illustrates the process of writing data to a storage unit.

[0053] Figure 19 This diagram illustrates the process of writing data to a storage unit.

[0054] Figure 20 This is a timing diagram illustrating the process of writing data to a storage unit.

[0055] Figure 21A and Figure 21B It is a graph illustrating the relationship between data retention time and capacitor leakage current.

[0056] Figure 22 This is a cross-sectional view of the storage device.

[0057] Figure 23 This is a cross-sectional view of the storage device.

[0058] Figure 24 This is a cross-sectional view of the storage device.

[0059] Figures 25A to 25C This is a diagram illustrating an example of a transistor.

[0060] Figures 26A to 26C This is a diagram illustrating an example of a transistor.

[0061] Figure 27A and Figure 27B It is a diagram illustrating electronic components.

[0062] Figure 28 It is a diagram illustrating an electronic device.

[0063] Figures 29A to 29E It is a diagram illustrating an electronic device.

[0064] Figures 30A to 30C It is a diagram illustrating an electronic device.

[0065] Figures 31A to 31C It is a diagram illustrating an electronic device.

[0066] Methods of implementing the invention

[0067] The embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments and examples shown below.

[0068] Note that in the inventive structure described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0069] In the various figures of this specification, the size of the constituent elements, the thickness of the layers, and the area are sometimes exaggerated for ease of understanding. Therefore, the present invention is not limited to the dimensions shown in the figures.

[0070] In addition, in this specification, a high power supply potential is sometimes referred to as "H level" (also known as "VDD" or "H potential") and a low power supply potential is referred to as "L level" (also known as "VSS" or "L potential").

[0071] Note that voltage refers to the potential difference between two points, while potential refers to the electrostatic energy (potential energy) of a unit charge at a point in an electrostatic field. Generally, the potential difference between a point and a reference potential (e.g., ground potential) is simply referred to as potential or voltage; usually, potential and voltage are synonymous. Therefore, in this specification, unless specifically specified, "potential" may be referred to as "voltage," and "voltage" may be referred to as "potential."

[0072] Furthermore, the following embodiments in this specification can be appropriately combined. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0073] In this specification and the like, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors. For example, when a metal oxide is used as the semiconductor layer of a transistor, it is sometimes referred to as an oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor containing either a metal oxide or an oxide semiconductor. In this specification and the like, nitrogen-containing metal oxides are sometimes collectively referred to as metal oxides.

[0074] Furthermore, unless otherwise stated, the transistors shown in this specification are enhancement-mode (normally off) n-channel field-effect transistors. Therefore, their threshold voltage (also referred to as "Vth") is greater than 0V.

[0075] (Implementation Method 1)

[0076] The following describes one embodiment of the storage device of the present invention.

[0077] Storage Device 100

[0078] Figure 1 This is a block diagram illustrating a structural example of a storage device 100 according to one aspect of the present invention.

[0079] The storage device 100 includes an input / output circuit 111 (IO Circuit), a control circuit 112 (Controller), an I2C receiver 113 (I2C Receiver), a setting register 114 (Setting Register), an LVDS circuit 115 (transmission circuit LVDS_rx), an LVDS circuit 116 (transmission circuit LVDS_tx), a decoder 117 (Decoder), a memory block array 210 (Memory Block Array), and a negative voltage generation circuit 218.

[0080] Furthermore, the control circuit 112 has registers 118 (Reg_r) and 119 (Reg_w). Additionally, the memory block array 210 has n (n is an integer greater than or equal to 1) memory blocks 211. In this specification, the first memory block 211 is referred to as memory block 211_1, and the i-th (i is an integer greater than or equal to 1 and less than or equal to n) memory block 211 is referred to as memory block 211_i.

[0081] The input / output circuit 111 has the function of transmitting signals with external devices. The operating conditions of the storage device 100 are determined by the setting parameters stored in the setting register 114. The setting parameters are written to the setting register 114 through the output circuit 111 and the I2C receiver 113. In addition, the I2C receiver 113 may be omitted depending on the purpose or use.

[0082] As an example of setting parameters, there are specified information such as the execution interval of refresh operations or the working sequence of circuit operations. The control circuit 112 has the function of processing setting parameters and instruction signals from the outside and determining the operating mode of the storage device 100. The control circuit 112 also has the function of generating various control signals to control the overall operation of the storage device 100.

[0083] In addition, the reset signal res, address signals ADDR[16:0], row address strobe signal RAS (Row Address Strobe), column address strobe signal CAS (Column Address Strobe), write enable signal WE (Write Enable), data read clock signal clk_r, and write data WDATA[7:0] are input to the control circuit 112 from the outside through the output circuit 111. The data read clock signal clk_r is input to the control circuit 112 through the LVDS circuit 115.

[0084] Furthermore, the data writing clock signal clk_w and the read data RDATA[7:0] are input from the control circuit 112 to the input / output circuit 111. The data writing clock signal clk_w is input to the input / output circuit 111 via the LVDS circuit 116. The LVDS circuits 115 and 116 are transmission circuits that operate according to the Low Voltage Differential Signaling (LVDS) specification. Alternatively, one or both of the LVDS circuits 115 and 116 may be omitted depending on the purpose or application.

[0085] The written data WDATA[7:0] is transmitted synchronously with the data write clock signal clk_w and stored in register 119 within the control circuit 112. The control circuit 112 has the function of supplying the data stored in register 119 to the memory block array 210.

[0086] Furthermore, the data read from the memory block array 210 is stored as read data RDATA[7:0] in register 118 within the control circuit 112. The control circuit 112 has the function of synchronously transmitting the read data RDATA[7:0] and the data read clock signal clk_r to the input / output circuit 111.

[0087] In addition, the control circuit 112 has the functions of outputting column address signal C_ADDR[6:0], column selection enable signal CSEL_EN, data latch signal DLAT, global write enable signal GW_EN, global read enable signal GR_EN, global read amplification enable signal GSA_EN, global equalization enable signal GEQ_ENB, local read amplification enable signal LSA_EN, local equalization enable signal LEQ_ENB, and word line address selection signal WL_ADDR[7:0].

[0088] The column address signal C_ADDR and the column select enable signal CSEL_EN are input to decoder 117.

[0089] Storage Blocks

[0090] Figure 2A This is a block diagram showing an example of the structure of storage block 211_i. Figure 2B This is a perspective block diagram illustrating a structural example of the local sense amplifier array 214 and the cell array 221 included in storage block 211_i. Furthermore, in Figure 2B The diagram shows arrows indicating the X, Y, and Z directions. The X, Y, and Z directions are orthogonal to each other.

[0091] The storage block 211_i includes a word line driver 212 (WL Driver), a local sense amplifier driver 213 (LSA Driver), a local sense amplifier array 214, a global sense amplifier 215 (Global SA), a read / write selector 216 (R / W Selector), and a cell array 221.

[0092] The data latch signal DLAT, the global write enable signal GW_EN, and the global read enable signal GR_EN are input to the read / write selector 216. The global read amplification enable signal GSA_EN and the global equalization enable signal GEQ_ENB are input to the global read amplifier 215. The local read amplification enable signal LSA_EN and the local equalization enable signal LEQ_ENB are input to the local read amplifier array 214. The word line address selection signal WL_ADDR[7:0] is input to the word line driver 212.

[0093] The local sense amplifier array 214 has a plurality of sense amplifiers 127 configured in a matrix shape of f rows and g columns (where f and g are both integers greater than or equal to 1). In this specification, sense amplifier 127 in the first row and first column is referred to as sense amplifier 127[1,1]. Furthermore, sense amplifier 127 in the k-th row and h-th column is referred to as sense amplifier 127[k,h] (where k is an integer greater than or equal to 1 and less than f, and h is an integer greater than or equal to 1 and less than g).

[0094] The cell array 221 is stacked on top of the local sense amplifier array 214. By stacking the cell array 221 on top of the sense amplifier array 214, the wiring length of the bit lines can be shortened.

[0095] Cell array 221 has a plurality of storage cells 10 arranged in a matrix of p rows and q columns (where p and q are both integers greater than or equal to 1). In this specification, the storage cell 10 in the first row and first column is referred to as storage cell 10[1, 1]. Furthermore, the storage cell 10 in the j-th row and t-th column (where j is an integer greater than or equal to 1 and less than p, and t is an integer greater than or equal to 1 and less than q) is referred to as storage cell 10[j, t]. Storage cells 10 are used as storage elements.

[0096] Furthermore, the cell array 221 includes multiple word lines WL and wiring BGL extending in the X direction (row direction), multiple bit lines BL extending in the Y direction (column direction), and multiple bit lines BLB extending in the Y direction (column direction). Figure 2B (Not illustrated in the figure). In addition, in this specification, for example, the j-th word line WL (j is an integer greater than 1 and less than p) is represented as word line WL[j].

[0097] A memory cell 10 is electrically connected to any one of the word lines WL extending in the X direction (row direction). Furthermore, a memory cell 10 is electrically connected to any one of the wiring BGL extending in the X direction (row direction). Additionally, a memory cell 10 is electrically connected to any one of the bit lines BL and BLB.

[0098] The cell array 221 is composed of multiple sub-cell arrays 223. Figure 2B An example is shown where the cell array 221 is composed of four sub-cell arrays 223. Figure 2B The four sub-cell arrays 223 are shown as sub-cell arrays 223_1 to 223_4.

[0099] Each of the multiple sub-cell arrays 223 consists of multiple storage cells 10. Therefore, the sub-cell array can also be referred to as a storage element group.

[0100] The sub-cell arrays 223_1 and 223_2, 223_2 and 223_3, and 223_3 and 223_4 all include adjacent regions 226. Figure 3 Show Figure 2B An enlarged view of region 225 is shown. Region 225 includes a portion of sub-cell array 223_2, a portion of sub-cell array 223_3, and a portion of adjacent region 226 that is adjacent to both of them.

[0101] Adjacent region 226 is a region used to electrically connect word line WL to wiring above or below it. For example, by placing wiring above word line WL and parallel to it, and electrically connecting word line WL and the wiring in adjacent region 226, the wiring resistance of word line WL can be substantially reduced.

[0102] Figure 4A An example circuit structure of memory cells 10[j,t-1], 10[j,t], and 10[j,t+1] electrically connected to word line WL[j] is shown. Memory cell 10 includes transistor M1 and storage capacitor Cs. Storage capacitor Cs is used as a storage capacitor. Figure 4A Transistor M1 is exemplified as a transistor including a back gate (a 4-terminal transistor, also known as a "4-terminal element").

[0103] One of the source or drain terminals of transistor M1 is electrically connected to one electrode of the storage capacitor Cs. The other electrode of transistor M1 is electrically connected to the bit line BL (or bit line BLB). The gate of transistor M1 is electrically connected to the word line WL. The back gate of transistor M1 is electrically connected to the wiring BGL. The other electrode of the storage capacitor Cs is electrically connected to the wiring CAL. The node where one of the source or drain terminals of transistor M1 is electrically connected to one electrode of the storage capacitor Cs is called node ND.

[0104] In actual transistors, the gate and back gate overlap each other through channel formation regions separated by semiconductor layers. Both the gate and back gate can be used as gates. Therefore, one is sometimes called the "back gate" and the other is called the "gate" or "front gate". In addition, one is sometimes called the "first gate" and the other is called the "second gate".

[0105] The back gate potential can be the same as the gate potential, or it can be ground potential or any other potential. Furthermore, the threshold voltage of the transistor can be changed by independently altering the back gate potential without being linked to the gate electrode.

[0106] By setting a back gate and making the potentials of the gate and back gate equal, the area through which charge carriers flow in the semiconductor layer is further expanded in the film thickness direction, thus increasing the amount of charge carrier migration. As a result, the on-state current of the transistor increases, and the field-effect mobility also increases.

[0107] Therefore, transistors with large on-state currents relative to their occupied area can be manufactured. That is, the transistor's occupied area can be reduced relative to the required on-state current. Thus, highly integrated semiconductor devices can be realized.

[0108] The BGL wiring is used to apply a potential to the back gate of transistor M1. By applying any potential to the BGL wiring, the threshold voltage of transistor M1 can be increased or decreased.

[0109] Data writing and reading are performed as follows: A high-level potential (e.g., 3.3V) is applied to the word line WL to turn on transistor M1, thereby electrically connecting the bit line BL to node ND. After the data writing is complete, a low-level potential is applied to the word line WL to turn off transistor M1. The low-level potential can be, for example, a reference potential or a negative potential. In this specification, a negative potential refers to a potential lower than the reference potential. Therefore, when the reference potential is 0V, a negative potential is a potential lower than 0V. Furthermore, "large negative potential" or "large negative potential" means that the potential difference between the reference potential and the negative potential is large. Conversely, "small negative potential" or "small negative potential" means that the potential difference between the reference potential and the negative potential is small.

[0110] Wiring CAL is used as wiring to apply a specified potential to the other electrode of the storage capacitor Cs. Preferably, a fixed potential is applied to wiring CAL.

[0111] The storage unit 10 shown in this embodiment is a DRAM (Dynamic Random Access Memory) type storage element.

[0112] In this specification, the transistor M1 included in the memory cell 10[j,t] is sometimes referred to as transistor M1[j,t]. Furthermore, the storage capacitor Cs included in the memory cell 10[j,t] is sometimes referred to as storage capacitor Cs[j,t]. Additionally, Figure 4A The circuit diagram shown can be as follows Figure 4B That's how it's expressed.

[0113] The semiconductor layer forming the channel of transistor M1 is preferably an oxide semiconductor, which is a type of metal oxide. In this specification, a transistor in which the semiconductor layer forming the channel includes an oxide semiconductor is referred to as an "OS transistor".

[0114] For example, as an oxide semiconductor, a metal oxide comprising any one of indium, element M (element M being selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) and zinc can be used. In particular, an oxide semiconductor is preferably a metal oxide comprising indium, gallium, and zinc.

[0115] OS transistors have extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. This means that transistor M1 can retain written data for extended periods. Therefore, the refresh frequency of the memory element can be reduced, or even eliminated altogether. Furthermore, due to the very low leakage current, memory elements capable of holding multiple values ​​or analog data can be easily implemented.

[0116] In this specification and other documents, DRAM using OS transistors will be referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

[0117] Figure 5A and Figure 5B Examples of the structures of transistors M1[j,t] and M1[j,t+1] are shown. Figure 5A These are 3D diagrams of transistors M1[j,t] and M1[j,t+1]. Figure 5BThis is a top view. Additionally, for ease of understanding, some of the constituent elements have been omitted from the accompanying drawings.

[0118] Transistor M1[j,t] includes an oxide layer 261 (oxide layer 261a, oxide layer 261b, and oxide layer 261c). The oxide layer 261 serves as a semiconductor layer. Furthermore, a conductive layer 342 (conductive layer 342a and conductive layer 342b) is disposed on the oxide layer 261b. One of the conductive layers 342a and 342b serves as a source electrode, and the other serves as a drain electrode.

[0119] Furthermore, a conductive layer 360, an insulating layer 349, and an oxide layer 261c are disposed between conductive layers 342a and 342b. The insulating layer 349 includes a region overlapping the side surface of the conductive layer 360 and a region overlapping the bottom surface of the conductive layer 360. The oxide layer 261c includes a region overlapping the side surface of the conductive layer 360 with the insulating layer 349 and a region overlapping the bottom surface of the conductive layer 360 with the insulating layer 349. The oxide layer 261c also includes a region in contact with the oxide layer 261b.

[0120] Furthermore, the region in the conductive layer 360 that overlaps with the oxide layer 261c is used as a gate electrode.

[0121] Furthermore, an insulating layer 366 is disposed beneath the oxide layer 261a, and an insulating layer 365 is disposed beneath the insulating layer 366. A conductive layer 305 is disposed beneath the insulating layer 365. The conductive layer 305 is disposed at a position overlapping with the conductive layer 360. The conductive layer 305 is used as wiring BGL[j]. Furthermore, the conductive layer 305 is used as the back gate electrode of transistor M1[j,t]. By supplying a negative voltage to the conductive layer 305, the Vth of transistor M1 can be increased and the constant-on state of transistor M1 can be suppressed.

[0122] Conductive layer 360 is used as the word line WL[j]. Furthermore, conductive layer 360 is used as the gate electrode of transistor M1[j,t]. Insulating layer 349 is used as the gate insulating layer of transistor M1[j,t]. Transistor M1[j,t+1] has the same structure as transistor M1[j,t]. Therefore, conductive layer 360 is used as the gate electrode of transistor M1[j,t+1]. Furthermore, insulating layer 349 is used as the gate insulating layer of transistor M1[j,t+1]. The transistor structure will be described in detail later.

[0123] <Parasitic transistor Trp, parasitic capacitor Cp>

[0124] In the above structure, oxide layer 261c overlaps with word line WL[j] through insulating layer 349, and oxide layer 261c is in contact with oxide layers 261b of transistors M1[j,t] and M1[j,t+1]. Therefore, a parasitic transistor Trp sometimes forms between transistors M1[j,t] and M1[j,t+1]. When the parasitic transistor Trp forms, oxide layers 261b of transistors M1[j,t] and M1[j,t+1] are electrically connected, thus easily creating a leakage path (current path) along word line WL[j] (see reference). Figure 5B ).

[0125] Furthermore, during the generation of the parasitic transistor Trp, a parasitic capacitor Cp is formed with the word line WL[j] as one electrode and the oxide layer 261c as the other electrode (parasitic node NDp). The parasitic capacitor Cp is equivalent to the gate capacitance of the parasitic transistor Trp (see reference). Figure 5A ).

[0126] Figure 5C This is a circuit diagram showing memory cell 10[j,t], memory cell 10[j,t+1], parasitic transistor Trp, and parasitic capacitor Cp. Furthermore, in this embodiment, wiring BGL[j] is always supplied with a negative voltage. Therefore, in the following circuit diagrams, etc., for ease of understanding of the drawings, the description of wiring BGL[j] is sometimes omitted. For example, Figure 5C The description of the wiring BGL is omitted.

[0127] also, Figure 5C The parasitic transistor Trp is shown in two separate configurations. Furthermore, Figure 5C The parasitic transistor Trp and parasitic capacitor Cp are shown by dashed lines.

[0128] The field-effect mobility of the parasitic transistor Trp is significantly lower than that of the transistor M1. Therefore, when the data write speed to memory cell 10 is fast (at high operating frequency), the effect of the aforementioned leakage path is minor. On the other hand, when the data write speed to memory cell 10 is slow (at low operating frequency, for example, below 10MHz), the effect of the leakage path is significant, so sometimes sufficient data writes to memory cell 10 cannot be performed.

[0129] <Writing data to storage unit 10>

[0130] Next, the data writing operation to storage unit 10[j,t] when the operating frequency is low will be explained. Figure 6AThis is a circuit diagram showing memory cells 10[j,t-1], 10[j,t], 10[j,t+1], parasitic transistor Trp, and parasitic capacitor Cp. Memory cells 10[j,t-1] and 10[j,t] are memory cells included in sub-cell array 223_2, and memory cell 10[j,t+1] is a memory cell included in sub-cell array 223_3.

[0131] exist Figure 6A In this diagram, the parasitic transistor, parasitic capacitor, and parasitic node generated between memory cell 10[j, t-1] and memory cell 10[j, t] are represented as parasitic transistor TrpA, parasitic capacitor CpA, and parasitic node NDpA, respectively. Furthermore, the parasitic transistor, parasitic capacitor, and parasitic node generated between memory cell 10[j, t] and memory cell 10[j, t+1] are represented as parasitic transistor TrpB, parasitic capacitor CpB, and parasitic node NDpB, respectively.

[0132] In this embodiment, the potential corresponding to "0" in the data written to the memory cell 10 is 0V or higher and lower than 0.6V, and the potential corresponding to "1" is 0.6V or higher and lower than 1.2V. Furthermore, the storage capacitor Cs is 3.5fF, the parasitic capacitor CpA is 1.0fF, and the parasitic capacitor CpB is 3.0fF. Additionally, to make transistor M1 turn on (conduct), the potential WLH supplied to the word line WL is 3.3V, and to make transistor M1 turn off (non-conducting), the potential WLL supplied to the word line WL is 0V. Furthermore, the Vth of parasitic transistors TrpA and TrpB is 1.5V.

[0133] Reference Figure 6B , Figure 7A , Figure 7B and Figure 8 Explain the cases of writing "0" to storage cell 10[j,t-1], writing "1" to storage cell 10[j,t], and writing "0" to storage cell 10[j,t+1]. Figure 8 This is a timing diagram used to illustrate the data writing process. Additionally, in accompanying figures, the reference numerals are sometimes omitted for ease of understanding. Regarding... Figure 6B , Figure 7A and Figure 7B The omitted reference numerals in the attached figures can be found in the following references. Figure 6A Please understand. Furthermore, the black line surrounding the area represents fluctuating electrical potential.

[0134] First, during period T11, bit lines BL[t-1] and BL[t+1] are supplied with 0V, and bit line BL[t] is supplied with 1.2V. Additionally, word line WL[j] is supplied with potential WLH (3.3V). At this time, transistors M1[j,t-1], M1[j,t], and M1[j,t+1] are turned on, nodes ND[j,t-1] and ND[j,t+1] are written with 0V, and node ND[j,t] is written with 1.2V (refer to...). Figure 6B , Figure 8 ).

[0135] As mentioned above, the field-effect mobility of the parasitic transistor Trp is significantly smaller than that of the transistor M1. When the potentials of parasitic nodes NDpA and NDpB are -1.5V just before entering period T11, the charge on word line WL[j] has not had time to move after the potential changes from 0V to 3.3V, and the potentials of parasitic nodes NDpA and NDpB are -1.5V + 3.3V = 1.8V. Then, the potentials of both parasitic nodes NDpA and NDpB are 0.6V.

[0136] Next, during period T12, a potential WLL (0V) is supplied to word line WL[j], causing transistors M1[j,t-1], M1[j,t], and M1[j,t+1] to be turned off. Figure 7A The diagram shows the states of transistors M1[j,t-1], M1[j,t], and M1[j,t+1] immediately after they become off (the states immediately after T12 begins). As mentioned above, the field-effect mobility of the parasitic transistor Trp is significantly smaller than that of transistor M1. Therefore, after the potential of word line WL[j] changes from 3.3V to 0V, the charge does not have time to move, and the potentials of parasitic nodes NDpA and NDpB are 0.6V - 3.3V = -2.7V.

[0137] The potential of word line WL[j] is 0V, and the potentials of parasitic nodes NDpA and NDpB are -2.7V, which means that 2.7V is applied to the gates of parasitic transistors TrpA and TrpB. Therefore, parasitic transistors TrpA and TrpB are turned on.

[0138] When parasitic transistors TrpA and TrpB are in the ON state, charge movement (charge redistribution) occurs between nodes ND[j,t-1], ND[j,t], ND[j,t+1], parasitic nodes NDpA and NDpB. Charge movement continues until the potentials of parasitic nodes NDpA and NDpB reach -1.5V.

[0139] After the charge transfer ends, the potentials of nodes ND[j,t-1], ND[j,t], and ND[j,t+1] depend on the electrostatic capacitances of the storage capacitor Cs, parasitic capacitor CpA, and parasitic capacitor CpB. In this circuit structure, the potentials of nodes ND[j,t-1] and ND[j,t+1] after the charge transfer ends are below 0V, and the potential of node ND[j,t] is 0.51V (refer to...). Figure 7B , Figure 8 ).

[0140] When the potential of node ND is below 0V during data reading, the data stored in storage cell 10 is identified as "0". Furthermore, when the potential of node ND is 0.51V during data reading, the data stored in storage cell 10 is also identified as "0". In other words, although storage cells 10[j, t-1] and 10[j, t+1] are normally written with data, storage cell 10[j, t] is not normally written with data.

[0141] In other words, although the data "0" written to storage unit 10[j,t-1] and storage unit 10[j,t+1] can be read as "0" when reading data, the data "1" written to storage unit 10[j,t] is read as "0".

[0142] Next, refer to Figure 9A , Figure 9B and Figure 10 Explain the scenarios where storage units 10[j, t-1], 10[j, t], and 10[j, t+1] are written with "1". Note that... Figure 6B , Figure 7A and Figure 7B Same, can be referenced Figure 6A Wait for understanding Figure 9A and Figure 9B The figure labels are omitted in the text. Figure 10 This is a sequence diagram illustrating the data writing process.

[0143] First, during period T21, bit lines BL[t-1], BL[t], and BL[t+1] are supplied with 1.2V, and word line WL[j] is supplied with 3.3V. At this time, transistors M1[j,t-1], M1[j,t], and M1[j,t+1] are turned on, and nodes ND[j,t-1], ND[j,t], and ND[j,t+1] are written with 1.2V (refer to...). Figure 9A , Figure 10 ).

[0144] As described above, when the potentials of parasitic nodes NDpA and NDpB immediately preceding period T21 are -1.5V, after the potential of the rigid line WL[j] changes from 0V to 3.3V, the potentials of parasitic nodes NDpA and NDpB are 1.8V. Then, the potentials of parasitic nodes NDpA and NDpB are both 1.2V.

[0145] Next, during period T22, 0V is supplied to word line WL[j], causing transistors M1[j,t-1], M1[j,t], and M1[j,t+1] to be turned off. As mentioned above, after the potential of word line WL[j] changes from 3.3V to 0V, the potentials of parasitic nodes NDpA and NDpB are 1.2V - 3.3V = -2.1V.

[0146] Then, until the parasitic transistors NDpA and NDpB are -1.5V, charge movement (charge redistribution) occurs between nodes ND[j,t-1], ND[j,t], ND[j,t+1], parasitic node NDpA, and parasitic node NDpB.

[0147] After the charge transfer ends, the potentials of nodes ND[j,t-1], ND[j,t], and ND[j,t+1] depend on the electrostatic capacitances of the storage capacitor Cs, parasitic capacitor CpA, and parasitic capacitor CpB. In this circuit structure, the potential of node ND[j,t] is 0.85V (refer to...). Figure 9B , Figure 10 Furthermore, the potential of node ND[j, t-1] after the charge transfer ends is affected by node ND[j, t-2] and is above 0.86V (refer to...). Figure 12 And below 1.2V. In addition, the potential of node ND[j,t+1] after the charge movement ends is affected by node ND[j,t+2] and is above 0.86V but below 1.2V.

[0148] Thus, the potentials of nodes ND[j, t-1], ND[j, t], and ND[j, t+1] are all above 0.6V. Therefore, data written as "1" can be read back as "1" normally.

[0149] Next, the same write operation in sub-cell array 223 will be described. Figure 11AThis is a circuit diagram showing memory cells 10[j,t-3], 10[j,t-2], 10[j,t-1], parasitic transistor TrpA, and parasitic capacitor CpA. Memory cells 10[j,t-3], 10[j,t-2], and 10[j,t-1] are the memory cells included in sub-cell array 223_2.

[0150] Furthermore, the electrostatic capacitance of the parasitic capacitor CpA generated between storage cell 10[j,t-3] and storage cell 10[j,t-2] and the electrostatic capacitance of the parasitic capacitor CpA generated between storage cell 10[j,t-2] and storage cell 10[j,t-1] are both 1.0fF.

[0151] Reference Figure 11B , Figure 11C and Figure 12 This describes the cases of writing "0" to memory cell 10[j, t-3], writing "1" to memory cell 10[j, t-2], and writing "0" to memory cell 10[j, t-1]. Additionally, in the accompanying drawings, reference numerals are sometimes omitted for ease of understanding. Regarding... Figure 11B and Figure 11C The omitted reference numerals in the attached figures can be found in the following references. Figure 11A Wait for an understanding. Figure 12 This is a sequence diagram illustrating the data writing process.

[0152] First, during period T31, bit lines BL[t-3] and BL[t-1] are supplied with 0V, and bit line BL[t-2] is supplied with 1.2V. Additionally, word line WL[j] is supplied with 3.3V. At this time, transistors M1[j,t-3], M1[j,t-2], and M1[j,t-1] are turned on, nodes ND[j,t-3] and ND[j,t-1] are written with 0V, and node ND[j,t-2] is written with 1.2V (refer to...). Figure 11B , Figure 12 ).

[0153] As described in period T11, when the potential of the parasitic node NDpA is -1.5V just before entering period T31, the potential of the word line WL[j] changes from 0V to 3.3V, and then the potential of the parasitic node NDpA is -1.5V + 3.3V = 1.8V. Then, as... Figure 11B As shown, the potentials of both parasitic nodes NDpA are 0.6V.

[0154] Next, during period T32, 0V is supplied to word line WL[j], causing transistors M1[j,t-3], M1[j,t-2], and M1[j,t-1] to be turned off. As described above, immediately after supplying 0V to word line WL[j] (just after period T32 begins), the potential of parasitic node NDpA is -2.7V. Then, due to charge redistribution, the potential of parasitic node NDpA becomes -1.5V.

[0155] In this circuit structure, the electrostatic capacitance of the parasitic capacitor CpA generated between storage cells 10[j,t-3] and 10[j,t-2], and the electrostatic capacitance of the parasitic capacitor CpA generated between storage cells 10[j,t-2] and 10[j,t-1], are both 1.0fF. Therefore, in this circuit structure, after the charge movement ends, the potentials of nodes ND[j,t-3] and ND[j,t-1] are below 0V, and the potential of node ND[j,t-2] is 0.86V (refer to...). Figure 11C , Figure 12 ).

[0156] As described above, when the potential of node ND is below 0V during data readout, the data stored in storage cell 10 is identified as "0". Furthermore, when the potential of node ND is 0.86V during data readout, the data stored in storage cell 10 is identified as "1".

[0157] Therefore, it can be concluded that the data written to storage units 10[j,t-3], 10[j,t-2] and 10[j,t-1] was written normally.

[0158] Thus, write errors are prone to occur in the memory cells 10 located at the ends of the sub-cell array 223 due to the parasitic capacitance generated in the adjacent adjacent regions 226. In other words, write errors can be suppressed by reducing the parasitic capacitance of the adjacent regions 226.

[0159] The parasitic capacitance generated between adjacent memory cells 10 along the word line WL varies proportionally to the length of the word line WL between the adjacent memory cells 10. Therefore, this parasitic capacitance can be reduced by shortening the length of the word line WL between adjacent memory cells 10.

[0160] like Figure 13A As shown, the length of the word line WL[j] from the gate electrode of transistor M1[j,t-1] included in memory cell 10[j,t-1] in the sub-cell array to the gate electrode of transistor M1[j,t] included in memory cell 10[j,t] in the same sub-cell array is the distance DA.

[0161] Furthermore, the length of the word line WL[j] from the gate electrode of the transistor M1[j,t] included in the memory cell 10[j,t] at the end of the sub-cell array to the gate electrode of the transistor M1[j,t+1] included in the memory cell 10[j,t+1] at the end of the adjacent sub-cell array is the distance DB. The distance DB can also be described as the shortest distance between adjacent sub-cell arrays.

[0162] Furthermore, generally speaking, in a cell array, transistors and capacitors constituting the memory cell 10, as well as wiring connected to the memory cell 10, are arranged at a fixed period. Therefore, distance DA can also be described as the shortest distance between adjacent bit lines BL[t-1] and BL[t] in the sub-cell array. Similarly, distance DB can also be described as the shortest distance between a bit line BL[t] located at one end of the sub-cell array and a bit line BL[t+1] located at the end of an adjacent sub-cell array.

[0163] The parasitic capacitor CpA is proportional to the distance DA, and the parasitic capacitor CpB is proportional to the distance DB. Figure 13B It is a graph that calculates the relationship between the distance DB and the holding potential of node ND[j,t] when performing the above data writing operation. Figure 13B The chart shown is calculated based on the following conditions: the electrostatic capacitance of the storage capacitor Cs is 3.5 fF, the electrostatic capacitance of the parasitic capacitor CpA is 1.0 fF, and the distance DA is 1.4 μm.

[0164] As mentioned above, when writing a "1" to node ND[j,t] and reading a "1" from node ND[j,t], the holding potential of node ND[j,t] needs to be above 0.6V. Figure 13B It can be seen that in order to keep the potential of the node ND[j,t] which is written with "1" above 0.6V, the distance from DB needs to be below 3.5μm.

[0165] Furthermore, to ensure more stable operation of the storage device 100, the holding potential of the node ND[j,t] where a "1" is written is preferably 0.75V or higher. Figure 13B It can be seen that in order to maintain the potential of node ND[j,t] above 0.75V, the distance from DB needs to be below 2.3μm.

[0166] Furthermore, the distance DB is preferably more than 1 and less than 3.5 times the distance DA, and more preferably more than 1 and less than 2.3 times.

[0167] By bringing the distance from DB close to the distance from DA, write errors of storage device 100 can be reduced. The reliability of storage device 100 can be improved by bringing the distance from DB close to the distance from DA.

[0168] In addition, such as Figure 14A As shown, a pseudo memory cell 10d can also be provided in the adjacent region 226. The pseudo memory cell 10d includes a transistor M1d and a storage capacitor Csd. One of the source and drain of the transistor M1d is electrically connected to one electrode of the storage capacitor Csd through a node NDd. The other electrode of the storage capacitor Csd is electrically connected to the wiring CAL. The gate of the transistor M1d is electrically connected to the word line WL[j]. The other of the source and drain of the transistor M1d is supplied with VDD (1.2V in this embodiment).

[0169] By setting a pseudo-memory cell 10d in the adjacent region 226, the parasitic capacitor CpB can be divided into parasitic capacitor CpB1 and parasitic capacitor CpB2. In the word line WL[j] of the region overlapping with the adjacent region 226, by setting a pseudo-memory cell 10d in the center of the word line WL[j], the parasitic capacitor CpB can be divided in half. Similarly, the parasitic transistor TrpB can be divided into parasitic transistor TrpB1 and parasitic transistor TrpB2. Furthermore, the parasitic node NDpB can be divided into parasitic node NDpB1 and parasitic node NDpB2.

[0170] In addition, such as Figure 14B As shown, multiple pseudo-memory cells 10d can also be set in the adjacent region 226. Furthermore, as... Figure 15A As shown, it is also possible to omit the storage capacitor Csd in the pseudo-memory cell 10d and make node NDd a floating state. Furthermore, as... Figure 15B As shown, it is also possible to omit the storage capacitor Csd in the pseudo storage cell 10d and supply VDD to the source and drain of the transistor M1d.

[0171] By setting pseudo-memory cells 10d in the adjacent region 226, write errors of the storage device 100 can be reduced. By setting pseudo-memory cells 10d in the adjacent region 226, the reliability of the storage device 100 can be improved.

[0172] like Figure 16A As shown, the distance DA can be considered as the spacing (arrangement period) of the storage cells 10 configured in a matrix.

[0173] Figure 16B This is a graph showing the relationship between the distance DA and the holding potential of node ND[j, t-2] when the electrostatic capacitance of the storage capacitor Cs is 3.5fF. Figure 16B It can be seen that in order to maintain the holding potential of the node ND[j,t-2] which has been written with "1" at a level above 0.6V, the distance from DA needs to be less than 2.5μm. In addition, in order to maintain the holding potential of the node ND[j,t-2] which has been written with "1" at a level above 0.75V, the distance from DA needs to be less than 1.8μm.

[0174] In other words, in order to maintain a holding potential of 0.6V or higher for the node ND[j,t-2] where a "1" is written, the spacing between the matrix-structured memory cells 10 needs to be 2.5μm or less. Furthermore, in order to maintain a holding potential of 0.75V or higher for the node ND[j,t-2] where a "1" is written, the spacing between the matrix-structured memory cells 10 needs to be 1.8μm or less.

[0175] By making the spacing between the matrix-configured storage cells 10 2.5 μm or less, preferably 1.8 μm or less, write errors of the storage device 100 can be reduced. By making the spacing between the matrix-configured storage cells 10 2.5 μm or less, preferably 1.8 μm or less, the reliability of the storage device 100 can be improved.

[0176] Figure 17A yes Figure 5B A cross-sectional view of the Y1-Y2 section, indicated by the dashed line. The electrostatic capacitances of parasitic capacitors CpA and CpB are proportional to the area overlapping the word line WL[j] and the oxide layer 261c. When a negative voltage is supplied to wiring BGL[j], carriers are less likely to be generated in the oxide layer 261c overlapping the bottom surface of the word line WL[j]. Therefore, when the distances DA and DB are fixed, the potential for charge carriers to be generated can be reduced. Figure 5B The height H of the word line WL[j] shown is used to reduce the electrostatic capacitance of parasitic capacitors CpA and CpB.

[0177] Figure 17B This is a graph showing the relationship between the height H of the word line WL[j] and the holding potential of the node ND[j,t] during the above data writing operation. Figure 17B The chart shown was calculated under the following conditions: the electrostatic capacitance of the storage capacitor Cs is 3.5 fF, the electrostatic capacitance of the parasitic capacitor CpA at a height H of 120 nm is 1.0 fF, the electrostatic capacitance of the parasitic capacitor CpB at a height H of 120 nm is 3.0 fF, the distance DA is 1.4 μm, and the distance DB is 4.2 μm.

[0178] Depend on Figure 17B It can be seen that in order to maintain the holding potential of the node ND[j,t] written with "1" at a level above 0.6V, the height H needs to be below 105nm. Furthermore, it can also be seen that in order to maintain the holding potential of the node ND[j,t] written with "1" at a level above 0.75V, the height H needs to be below 79nm.

[0179] By reducing the height H of the word line WL[j], write errors in the storage device 100 can be reduced. The reliability of the storage device 100 can be improved by reducing the height H of the word line WL[j].

[0180] Furthermore, by increasing the Vth of the parasitic transistor Trp, the amount of charge movement between node ND and the parasitic node NDp can be reduced. Therefore, the decrease in the holding potential of node ND can be mitigated.

[0181] For example, by using a material with a low electron affinity for oxide layer 261c, the Vth of the parasitic transistor Trp can be increased. In this case, the electron affinity of oxide layer 261c is preferably less than that of oxide layer 261b. By making the electron affinity of oxide layer 261c less than that of oxide layer 261b, the Vth of the parasitic transistor Trp can be made greater than that of transistor M1.

[0182] For example, when an In-M-Zn oxide (element M is selected from one or more of gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) is used as oxide layer 261b, the atomic ratio of element M to In in the metal oxide used for oxide layer 261c is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide layer 261b. Alternatively, M-Zn oxide or M oxide is preferably used as the metal oxide used for oxide layer 261c.

[0183] By increasing the Vth of the parasitic transistor Trp, write errors in the memory device 100 can be reduced. Therefore, the reliability of the memory device 100 can be improved.

[0184] Alternatively, the potentials WLH and WLL can be reduced without altering the potential difference between the potentials WLH and WLL supplied to the word line WL. This can reduce write errors in the storage device 100.

[0185] This describes the data writing operation to memory cell 10[j,t] under the following conditions: storage capacitor Cs is 3.5fF, parasitic capacitor CpA is 1.0fF, parasitic capacitor CpB is 3.0fF, potential WLH is 3.0V, and potential WLL is -0.3V. (Refer to...) Figure 18A , Figure 18B , Figure 19 and Figure 20 This describes the scenarios where storage cell 10[j, t-1] is written with "0", storage cell 10[j, t] is written with "1", and storage cell 10[j, t+1] is written with "0". Figure 20 This is a sequence diagram illustrating the data writing process. Figure 18A , Figure 18B and Figure 19 It is equivalent to Figure 6A The circuit diagram is attached for easy understanding. Figure 18A , Figure 18B and Figure 19 Sometimes the reference numerals in the accompanying drawings are omitted. Figure 18A , Figure 18B and Figure 19 The omitted reference numerals in the attached figures can be referred to Figure 6A Wait for an understanding.

[0186] First, during period T41, bit lines BL[t-1] and BL[t+1] are supplied with 0V, and bit line BL[t] is supplied with 1.2V. Additionally, word line WL[j] is supplied with potential WLH (3.0V). At this time, transistors M1[j,t-1], M1[j,t], and M1[j,t+1] are turned on, nodes ND[j,t-1] and ND[j,t+1] are written with 0V, and node ND[j,t] is written with 1.2V.

[0187] When the potentials of parasitic nodes NDpA and NDpB before entering period T41 are -1.8V, the potential of word line WL[j] changes from -0.3V to 3.0V, and then the potentials of parasitic nodes NDpA and NDpB are 1.5V. Then, the potentials of parasitic nodes NDpA and NDpB are both 0.6V (refer to...). Figure 18A , Figure 20 ).

[0188] Next, during period T42, a potential WLL (-0.3V) is supplied to word line WL[j], and transistors M1[j,t-1], M1[j,t], and M1[j,t+1] are turned off. Figure 18B The diagram shows the states of transistors M1[j,t-1], M1[j,t], and M1[j,t+1] immediately after they become off (the states immediately after T42 starts). As mentioned above, after the potential of word line WL[j] changes from 3.0V to -0.3V, the charge does not have time to move, and the potentials of parasitic nodes NDpA and NDpB are 0.6V - 3.3V = -2.7V.

[0189] The potential of word line WL[j] is -0.3V, and the potentials of parasitic nodes NDpA and NDpB are -2.7V, which means that the gates of parasitic transistors TrpA and TrpB are applied with 2.4V. Therefore, parasitic transistors TrpA and TrpB are turned on.

[0190] When parasitic transistors TrpA and TrpB are in the ON state, charge movement (charge redistribution) occurs between nodes ND[j, t-1], ND[j, t], ND[j, t+1], parasitic nodes NDpA and NDpB. Since the potential of word line WL[j] is -0.3V, charge movement continues until the potential of parasitic nodes NDpA and NDpB becomes -1.8V.

[0191] After the charge transfer ends, the potentials of nodes ND[j,t-1], ND[j,t], and ND[j,t+1] depend on the electrostatic capacitances of the storage capacitor Cs, parasitic capacitor CpA, and parasitic capacitor CpB. In this circuit structure, the potentials of nodes ND[j,t-1] and ND[j,t+1] after the charge transfer ends are below 0V, and the potential of node ND[j,t] is 0.69V (refer to...). Figure 19 , Figure 20 ).

[0192] Because the potential of node ND[j,t] is above 0.6V, the data written to node ND[j,t] can be read as "1". Therefore, by lowering potentials WLH and WLL, data can be written to memory cell 10 normally.

[0193] By reducing potentials WLH and WLL, the amount of charge moving between parasitic nodes NDpA and NDpB is reduced, thereby reducing the potential decrease of nodes ND[j,t-1], ND[j,t], and ND[j,t+1].

[0194] By lowering potentials WLH and WLL, write errors in the storage device 100 can be reduced. Lowering potentials WLH and WLL can also improve the reliability of the storage device 100.

[0195] By further reducing the potentials WLH and WLL, write errors in the storage device 100 can be further reduced. For example, when the potential WLH is 2.8V and the potential WLL is -0.5V, the potential of the node ND[j,t] where the data "1" is written can be 0.8V.

[0196] On the other hand, in order to reliably turn on transistor M1, the potential WLH needs to be greater than or equal to the potential of the supply bit line BL plus the potential of transistor M1's Vth. For example, when the Vth of transistor M1 is 0.5V, since the data "1" is 1.2V in this embodiment, the potential WLH needs to be greater than or equal to 1.7V.

[0197] Furthermore, by reducing the potential difference between potentials WLH and WLL, an effect equivalent to reducing both potentials WLH and WLL can be achieved.

[0198] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0199] (Implementation Method 2)

[0200] This embodiment explains the relationship between the retention time of data written to the storage cell 10 and the leakage current of the storage capacitor Cs.

[0201] Figure 21A An example of the circuit structure of memory cell 10 is shown. Memory cell 10 includes transistor M1 and storage capacitor Cs.

[0202] One of the source or drain terminals of transistor M1 is electrically connected to one electrode of the storage capacitor Cs, and the other of the source or drain terminal of transistor M1 is electrically connected to one of the bit lines BL. The gate of transistor M1 is electrically connected to the word line WL. The node where one of the source or drain terminals of transistor M1 is electrically connected to one electrode of the storage capacitor Cs is called node ND.

[0203] Wiring CAL is used as wiring to apply a specified potential to the other electrode of the storage capacitor Cs. Preferably, a fixed potential (e.g., 0V) is applied to wiring CAL.

[0204] Data is written as follows: a high-level potential is applied to the word line WL to turn on transistor M1, thereby electrically connecting the bit line BL to node ND. After the data writing is complete, a low-level potential (e.g., 0V or a negative potential) is applied to the word line WL to turn off transistor M1. The data written to memory cell 10 is retained as charge in node ND.

[0205] As described in the above embodiment, an OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. Therefore, data written to node ND can be retained for a long time.

[0206] In addition, in order to retain data written to node ND for a long time, it is important to reduce the leakage current flowing from one electrode of storage capacitor Cs to the other (also known as "CsI_leak").

[0207] Figure 21BThis is a graph showing the relationship between the hold time and CsI_leak of data written to node ND for storage capacitors Cs with capacitance values ​​of 35fF, 3.5fF, or 0.35fF. In this embodiment, the hold time is defined as the time until the potential of node ND decreases by 0.2V.

[0208] Depend on Figure 21B It can be seen that, for example, when the capacitance of the storage capacitor Cs is 3.5fF, in order to achieve a retention time of 1 minute, CsI_leak needs to be 1.2 × 10⁻⁶. -17 Below A. Similarly, it can be seen that in order to maintain the duration for 1 hour, CsI_leak needs to be 1.9 × 10. -19 Below A. Similarly, it can be seen that in order to maintain the value for 1 day, CsI_leak needs to be 8.1 × 10. -21 Below A. Similarly, it can be seen that in order to maintain the value for 1 year, CsI_leak needs to be 2.2 × 10. -23 Below A.

[0209] Furthermore, by multiplying the capacitance of the storage capacitor Cs by 10, the allowable current of CsI_leak can be multiplied by 10. For example, when the capacitance of the storage capacitor Cs is 35fF, CsI_leak would be 1.9 × 10⁻⁶ to achieve a retention time of 1 hour. - 18 Anything below A is acceptable.

[0210] Furthermore, when the capacitance of the storage capacitor Cs is 0.1 times, the allowable current of CsI_leak needs to be 0.1 times. For example, when the capacitance of the storage capacitor Cs is 0.35fF, in order to achieve a retention time of 1 hour, CsI_leak needs to be 1.9 × 10⁻⁶. -20 Below A.

[0211] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0212] (Implementation Method 3)

[0213] The input / output circuit 111, control circuit 112, I2C receiver 113, setting register 114, LVDS circuit 115, LVDS circuit 116, decoder 117, memory block array 210, negative voltage generation circuit 218, word line driver 212, local sense amplifier driver 213, sense amplifier 127, global sense amplifier 215, and read / write selector 216 described in the above embodiments are sometimes required to have high current drive capability and / or high-speed operation. In this case, Si transistors are preferably used as transistors to constitute these circuits. Furthermore, OS transistors are preferably used as transistors to constitute the memory cell 10.

[0214] OS transistors and Si transistors can be stacked. Therefore, an integrated circuit including OS transistors can be placed on an integrated circuit including Si transistors. By stacking various circuits, the memory device 100 can be miniaturized. In other words, the area occupied by the memory device 100 can be reduced.

[0215] For example, as the storage device 100, an integrated circuit including the storage cell 10 can also be provided on an integrated circuit including the readout amplifier 127. By stacking various circuits, the storage device 100 can be miniaturized. Therefore, the semiconductor device including the storage device 100 can be miniaturized. In other words, the area occupied by the storage device 100 can be reduced. Thus, the area occupied by the semiconductor device including the storage device 100 can be reduced.

[0216] Examples of storage device structures

[0217] Figure 22 A partial cross-section of the storage device 100 is shown. Figure 22 In the storage device 100 shown, a local sense amplifier array 214 and a cell array 221 are stacked on a substrate 231. In addition, the circuits other than the cell array 221 are disposed on the substrate 231 in the same manner as the local sense amplifier array 214. Figure 22 This illustration shows a case where a single-crystal semiconductor substrate (e.g., a single-crystal silicon substrate) is used as substrate 231. The sources, drains, and channels of the transistors included in the local sense amplifier array 214 are formed in a portion of substrate 231. Furthermore, cell array 221 includes thin-film transistors (e.g., OS transistors).

[0218] <Local readout amplifier array 214>

[0219] exist Figure 22 In the local readout amplifier array 214, transistors 233a, 233b and 233c are included on substrate 231. Figure 22The cross-sections of transistors 233a, 233b, and 233c along their channel length are shown.

[0220] As described above, the channels of transistors 233a, 233b, and 233c are formed in a portion of substrate 231. When high-speed operation of the integrated circuit is required, a single-crystal semiconductor substrate is preferably used as substrate 231.

[0221] Transistors 233a, 233b, and 233c are electrically separated from other transistors by the device separation layer 232. The device separation layer can be formed using methods such as LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation).

[0222] In addition, transistors 233a, 233b, and 233c are provided with insulating layers 234, 235, and 237, respectively, and an electrode 238 is embedded in the insulating layer 237. The electrode 238 is electrically connected to one of the source and drain terminals of transistor 233a via a contact plug 236.

[0223] In addition, insulating layers 239, 240, and 241 are provided on electrode 238 and insulating layer 237, and electrode 242 is embedded in insulating layers 239, 240, and 241. Electrode 242 is electrically connected to electrode 238.

[0224] In addition, insulating layers 243 and 244 are provided on electrode 242 and insulating layer 241, and electrode 245 is embedded in insulating layer 243 and insulating layer 244. Electrode 245 is electrically connected to electrode 242.

[0225] In addition, insulating layers 246 and 247 are provided on electrode 245 and insulating layer 244, and electrode 249 is embedded in insulating layer 246 and insulating layer 247. Electrode 249 is electrically connected to electrode 245.

[0226] In addition, insulating layers 248 and 250 are provided on electrode 249 and insulating layer 247, and electrode 251 is embedded in insulating layer 248 and insulating layer 250. Electrode 251 is electrically connected to electrode 249.

[0227] <Unit Array 221>

[0228] The unit array 221 is disposed on the local sense amplifier array 214. Figure 22 In the unit array 221, transistors 200 and capacitors 220 are included. Figure 22 A cross-section of the transistor 200 along its channel length is shown. Furthermore, the transistor 200 includes a back gate.

[0229] For example, transistor 200 is equivalent to transistor M1, and capacitor 220 is equivalent to storage capacitor Cs.

[0230] Preferably, an oxide semiconductor, one of the metal oxides, is used in the semiconductor layer of transistor 200. That is, an OS transistor is preferably used as transistor 200.

[0231] Transistor 200 is disposed on insulating layer 361. Insulating layer 362 is disposed on insulating layer 361. The back gate of transistor 200 is embedded in insulating layer 362. Insulating layer 371 and insulating layer 380 are disposed on insulating layer 362. The gate of transistor 200 is embedded in insulating layer 380.

[0232] Insulating layer 374 and insulating layer 381 are disposed on insulating layer 380. Electrode 355 is embedded in insulating layers 361, 362, 365, 366, 371, 380, 374, and 381. Electrode 355 is electrically connected to electrode 251. Electrode 355 can be used as a contact plug.

[0233] An electrode 152 is disposed on the insulating layer 381. The electrode 152 is electrically connected to the electrode 355. Insulating layers 272, 273, and 130 are disposed on the insulating layer 381 and the electrode 152.

[0234] The capacitor 220 includes: an electrode 110 disposed in an opening formed in an insulating layer 272 and an insulating layer 273; an insulating layer 130 on the electrode 110 and the insulating layer 273; and an electrode 120 on the insulating layer 130. At least a portion of the electrode 110, at least a portion of the insulating layer 130, and at least a portion of the electrode 120 are disposed in the opening formed in the insulating layer 272 and the insulating layer 273.

[0235] Electrode 110 serves as the lower electrode of capacitor 220, electrode 120 serves as the upper electrode of capacitor 220, and insulating layer 130 serves as the dielectric of capacitor 220. Capacitor 220 has a structure in which the upper and lower electrodes are separated by a dielectric material not only on the bottom surface but also on the side surfaces within openings in insulating layers 272 and 273, thus increasing the electrostatic capacitance per unit area. Therefore, the deeper the opening, the greater the electrostatic capacitance of capacitor 220. In this way, by increasing the electrostatic capacitance per unit area of ​​capacitor 220, miniaturization or high integration of semiconductor devices can be advanced.

[0236] The top view of the openings formed in the insulating layer 272 and the insulating layer 273 can be a quadrilateral, a polygon other than a quadrilateral, a polygon with arc-shaped corners, or a circular shape such as an ellipse.

[0237] Insulating layers 274 and 154 are included on insulating layer 130 and electrode 120. Electrode 271 is embedded in insulating layers 272, 273, 130, 274, and 154. Electrode 271 is electrically connected to electrode 152. Electrode 271 can be used as a contact plug. Electrode 153 is disposed on insulating layer 154. Electrode 153 is electrically connected to electrode 271.

[0238] An insulating layer 156 is provided on the insulating layer 154 and the electrode 153.

[0239] [Example of variation 1]

[0240] Figure 23 The storage device 100A is shown as a modified example of the storage device 100. A local sense amplifier array 214A and a cell array 221 are stacked in the storage device 100A. The local sense amplifier array 214A uses OS transistors, such as transistors 233a and 233b included in the local sense amplifier array 214A. When all transistors included in the storage device 100 are OS transistors, the storage device 100 can be made into a unipolar integrated circuit.

[0241] [Variation Example 2]

[0242] Figure 24 Storage device 100B is shown as a modified example of storage device 100A. When all transistors included in storage device 100B are OS transistors, the local sense amplifier array 214A and the cell array 221 can be fabricated on substrate 231 in the same process. This improves the productivity of the semiconductor device. Furthermore, it reduces the manufacturing cost of the semiconductor device.

[0243] Furthermore, when a substrate with high thermal conductivity, such as a silicon substrate, is used as substrate 231, the cooling efficiency of the semiconductor device can be improved compared to using an insulating substrate. Therefore, the reliability of the semiconductor device can be improved.

[0244] Materials

[0245] <Substrate>

[0246] There are few restrictions on the substrate material. For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates.

[0247] Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium oxide stabilized zirconium oxide substrates, etc.), and resin substrates.

[0248] Furthermore, examples of semiconductor substrates include those made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Additionally, examples of semiconductor substrates having insulating regions within the aforementioned semiconductor substrates include SOI (Silicon On Insulator) substrates.

[0249] As mentioned above, when high-speed operation of integrated circuits is required, single-crystal semiconductor substrates are preferred as substrates.

[0250] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements. Additionally, substrates on which semiconductor elements such as strain gauge transistors or Fin-type transistors are disposed can be used. In other words, the substrate can be not only a supporting substrate but also a substrate on which transistors or other devices are formed.

[0251] <Insulating layer>

[0252] Materials used for insulating layers include oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, all of which possess insulating properties.

[0253] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material as the insulating layer used as the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a low relative permittivity as the insulating layer used as the interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials according to the function of the insulating layer.

[0254] In addition, examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0255] In addition, examples of insulating materials with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with pores, etc.

[0256] Furthermore, when using an OS transistor, the transistor's electrical characteristics can be stabilized by surrounding it with an insulating layer (insulating layer 361 and insulating layer 374, etc.) that functions to suppress the permeation of impurities such as hydrogen and oxygen. As an insulator that functions to suppress the permeation of impurities such as hydrogen and oxygen, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in a stack. Specifically, as an insulating layer that functions to suppress the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, as well as metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0257] Furthermore, the insulating layer used as the gate insulating layer is preferably an insulator having regions containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having regions containing oxygen that has been removed by heating is contacted with the semiconductor layer 260, oxygen vacancies contained in the semiconductor layer 260 can be filled.

[0258] Note that in this specification, nitrogen oxides refer to compounds in which the nitrogen content is greater than the oxygen content. Furthermore, oxynitrides refer to compounds in which the oxygen content is greater than the nitrogen content. Additionally, the content of each element can be determined, for example, using Rutherford backscattering spectrometry (RBS).

[0259] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, it is preferable to reduce the hydrogen concentration in the insulating layer to prevent an increase in the hydrogen concentration in the semiconductor layer. Specifically, the hydrogen concentration in the insulating layer, as measured by secondary ion mass spectrometry (SIMS), is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is a further preferred option: 5×10 18 atoms / cm 3 The following is particularly important. It is preferable to reduce the hydrogen concentration in the insulating layer that contacts the semiconductor layer.

[0260] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, it is preferable to reduce the nitrogen concentration in the insulating layer to prevent an increase in the nitrogen concentration in the semiconductor layer. Specifically, the nitrogen concentration in the insulating layer, as measured by SIMS, is 5 × 10⁻⁶. 19 atoms / cm 3 The following is preferred: 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0261] Furthermore, the region in the insulating layer that is in contact with at least the semiconductor layer preferably has few defects, typically indicating a low level of signal observed by electron spin resonance (ESR). For example, the E' center observed at a g value of 2.001 can be cited as an example of such a signal. The E' center originates from dangling bonds in silicon. For example, when using a silicon oxide layer or a silicon oxynitride layer as the insulating layer, a spin density of 3 × 10⁻⁶ originating from the E' center can be used. 17 spins / cm 3 The following, preferably 5×10 16 spins / cm 3 The following silicon oxide layer or silicon oxynitride layer.

[0262] Sometimes, in addition to the signals mentioned above, signals originating from nitrogen dioxide (NO2) are observed. This signal splits into three signals due to the nuclear spin of N: a g value greater than or equal to 2.037 and less than 2.039 (first signal), a g value greater than or equal to 2.001 and less than 2.003 (second signal), and a g value greater than or equal to 1.964 and less than 1.966 (third signal).

[0263] For example, as an insulating layer, it is preferable to use a signal originating from nitrogen dioxide (NO2) with a spin density of 1×10⁻⁶. 17 spins / cm 3 Above and less than 1×10 18 spins / cm 3 The insulating layer.

[0264] Nitrogen dioxide (NO2) and nitrogen oxides (NO) x An energy level is formed in the insulating layer. This energy level is located in the bandgap of the oxide semiconductor layer. Therefore, when nitrogen oxides (NO...)... xWhen electrons diffuse to the interface between the insulating layer and the oxide semiconductor layer, this energy level sometimes traps electrons on the insulating layer side. As a result, the trapped electrons remain near the interface between the insulating layer and the oxide semiconductor layer, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, when a film with a low content of nitrogen oxides is used as the insulating layer, the drift of the transistor's threshold voltage can be reduced.

[0265] As nitrogen oxides (NO) x For insulating layers with low ammonia release, silicon oxynitride layers can be used, for example. These silicon oxynitride layers exhibit a lower ammonia release compared to nitrogen oxides (NOx) as measured by thermal desorption spectroscopy (TDS). x Membranes that release a large amount of ammonia, typically 1×10⁻⁶. 18 pcs / cm 3 Above and 5×10 19 pcs / cm 3 The following is a summary. Furthermore, the ammonia release mentioned above refers to the total amount released in TDS within a temperature range of 50°C to 650°C or 50°C to 550°C during heat treatment.

[0266] Because when heat treatment is performed, nitrogen oxides (NOx) x It reacts with ammonia and oxygen, so using an insulating layer with high ammonia release can reduce nitrogen oxides (NOx). x ).

[0267] At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer that releases oxygen upon heating. Specifically, an insulating layer is preferably used where the amount of oxygen removed, converted to oxygen atoms, is 1.0 × 10⁻⁶ when performing TDS analysis (wherein a heat treatment is performed at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower). 18 atoms / cm 3 The preferred value is 1.0 × 10⁴. 19 atoms / cm 3 or above 1.0×10 20 atoms / cm 3 That's all. Furthermore, in this specification and other materials, the oxygen released by heating is referred to as "excess oxygen".

[0268] Furthermore, an insulating layer containing excess oxygen can be formed by adding oxygen to the insulating layer. As an oxygen addition treatment, heat treatment under an oxidizing atmosphere, plasma treatment, etc., can be used. Alternatively, oxygen addition can be performed using ion implantation, ion doping, plasma immersion ion implantation, etc. Examples of gases used in the oxygen addition treatment include... 16 O2 or18 Oxygen gases such as O2, nitrous oxide, or ozone are also oxygen-containing gases. Note that in this specification, the process of adding oxygen is sometimes referred to as "oxygen doping." Oxygen doping can also be performed while the substrate is heated.

[0269] As an insulating layer, heat-resistant organic materials such as polyimide, acrylic resins, benzocyclobutene resins, polyamides, and epoxy resins can be used. In addition to the above-mentioned organic materials, low-dielectric-constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass) can also be used. Furthermore, an insulating layer can be formed by stacking multiple insulating layers made of these materials.

[0270] Siloxane resins are resins containing Si-O-Si bonds formed from siloxane materials as starting materials. Siloxane resins may include organic groups (e.g., alkyl or aryl) or fluorine groups as substituents. Furthermore, the organic groups may also have fluorine groups.

[0271] There are no particular restrictions on the method for forming the insulating layer. Note that sometimes a baking process is required depending on the material used in the insulating layer. In this case, transistors can be manufactured efficiently by combining the baking process of the insulating layer with another heat treatment process.

[0272] There are no particular restrictions on the method for forming the insulating layer. Note that sometimes a baking process is required depending on the material used in the insulating layer. In this case, transistors can be manufactured efficiently by combining the baking process of the insulating layer with another heat treatment process.

[0273] <Conductive Layer>

[0274] As the conductive layer, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides can also be used.

[0275] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0276] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material is preferably adopted as the conductive layer used as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on the channel formation region side. By providing the oxygen-containing conductive material on the channel formation region side, oxygen detached from the conductive material can be easily supplied to the channel formation region.

[0277] In particular, as the conductive layer used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can be used. Furthermore, indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Or, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0278] Furthermore, highly embedded conductive materials such as tungsten or polycrystalline silicon can be used as conductive materials for the contact plug. Alternatively, a combination of highly embedded conductive materials with barrier layers (diffusion prevention layers) such as titanium layers, titanium nitride layers, or tantalum nitride layers can also be used.

[0279] <Semiconductor layer>

[0280] As the semiconductor layer, one or more of the following can be used: single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, silicon or germanium can be used, for example. Furthermore, compound semiconductors or organic semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0281] Furthermore, when using organic semiconductors as semiconductor layers, low-molecular-weight organic materials with aromatic rings or π-electron conjugated conductive polymers can be used. For example, red fluorene, tetraphenylene, pentaphenylene, perylene diimide, tetracyanoquinone dimethyl ether, polythiophene, polyacetylene, and poly(p-phenylene vinylidene) can be used.

[0282] Semiconductor layers can also be stacked. When semiconductor layers are stacked, semiconductors with different crystal states can be used, as can different semiconductor materials.

[0283] Furthermore, since oxide semiconductors, as a type of metal oxide, have a band gap of 2 eV or more, transistors with extremely low off-state currents can be realized when oxide semiconductors are used as the semiconductor layer. Specifically, the off-state current can be set to less than 1 × 10⁻⁶ eV for a source-drain voltage of 3.5 V and a channel width of 1 μm at room temperature (typically 25 °C). -20 A. Less than 1×10 -22 A or less than 1×10 -24 A. That is to say, the switching ratio can be 20 digits or more. Furthermore, in transistors using oxide semiconductors (OS transistors) as the semiconductor layer, the insulation withstand voltage between the source and drain is high. Therefore, transistors with high reliability can be provided. Furthermore, transistors with high output voltage and high withstand voltage can be provided. Furthermore, memory devices with high reliability can be provided, etc. Furthermore, memory devices with high output voltage and high withstand voltage can be provided.

[0284] Compared to OS transistors, crystalline Si transistors readily achieve higher mobility. However, crystalline Si transistors struggle to achieve the extremely low off-state currents of OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer based on its purpose and application. For example, depending on the purpose or application, a combination of OS transistors and crystalline Si transistors may be used.

[0285] When using an oxide semiconductor layer as the semiconductor layer, it is preferable to form the oxide semiconductor layer by sputtering. Oxide semiconductor layers formed by sputtering have a higher density, making it preferred. When forming the oxide semiconductor layer by sputtering, a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen can be used as the sputtering gas. Furthermore, it is necessary to ensure the high purity of the sputtering gas. For example, a high-purity gas with a dew point of -60°C or below, preferably -100°C or below, is used as the oxygen or rare gas used as the sputtering gas. By using a high-purity sputtering gas to form a thin film, the incorporation of moisture and other contaminants into the oxide semiconductor layer can be minimized.

[0286] When forming an oxide semiconductor layer by sputtering, it is preferable to remove as much moisture as possible from the film-forming chamber of the sputtering apparatus. For example, it is preferable to use an adsorption vacuum pump, such as a cryogenic pump, to perform high-vacuum evacuation (evacuating to 5 × 10⁻⁶ m³ / s) of the film-forming chamber. -7 Pa to 1×10 -4(Approximately Pa). In particular, during the standby period of the sputtering apparatus, the partial pressure of gas molecules equivalent to H2O (equivalent to gas molecules with m / z = 18) in the film formation chamber is preferably 1 × 10⁻⁶ Pa. -4 Pa or less, more preferably 5×10 Pa -5 Below Pa.

[0287] <Metal Oxides>

[0288] By changing the composition of the elements contained in a metal oxide, conductors, semiconductors, and insulators can be formed, respectively. Sometimes, metal oxides with conductive properties are called "conductive oxides." Sometimes, metal oxides with semiconductor properties are called "oxide semiconductors." Sometimes, metal oxides with insulating properties are called "insulating oxides."

[0289] Oxide semiconductors, as one type of metal oxide, preferably contain indium or zinc. Indium and zinc are particularly preferred. In addition, aluminum, gallium, yttrium, or tin are also preferred. Alternatively, one or more of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium may be included.

[0290] Here, we consider the case where the oxide semiconductor contains indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M.

[0291] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0292] [Structure of metal oxides]

[0293] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0294] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, resulting in a distorted crystal structure. Distortion refers to the change in the orientation of the lattice arrangement between regions with consistent lattice alignment and other regions with consistent lattice alignment within the linked nanocrystal region.

[0295] Nanocrystals are primarily hexagonal, but not limited to regular hexagons; sometimes they are non-regular hexagonal. Furthermore, nanocrystals sometimes exhibit pentagonal or heptagonal lattice arrangements during distortion. Moreover, in CAAC-OS, clear grain boundaries are difficult to observe even near the distortion. That is, it is known that lattice distortion can suppress grain boundary formation. This is because CAAC-OS can contain distortion due to the low density of oxygen atoms along the ab-plane or changes in interatomic bonding distance caused by the substitution of metal elements.

[0296] CAAC-OS tends to have a layered crystalline structure (also called a layered structure), in which layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. Furthermore, indium and element M can be substituted for each other; when element M in a (M, Zn) layer is replaced by indium, the layer can also be represented as an (In, M, Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0297] CAAC-OS is a highly crystalline metal oxide. Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Additionally, the crystallinity of metal oxides can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides containing CAAC-OS possess excellent heat resistance and high reliability.

[0298] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed throughout the film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0299] Furthermore, In-Ga-Zn oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is formed from the aforementioned nanocrystals. In particular, IGZO tends to not readily undergo crystal growth in the atmosphere, so it is sometimes structurally more stable when formed from small crystals (e.g., the aforementioned nanocrystals) compared to when it is formed from large crystals (here, crystals a few millimeters or a few centimeters).

[0300] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0301] Oxide semiconductors (metal oxides) have various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0302] [Transistors containing metal oxides]

[0303] Next, the use of the aforementioned metal oxide in the channel formation region of a transistor will be explained.

[0304] By using the aforementioned metal oxides in the channel formation region of a transistor, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can also be achieved.

[0305] Furthermore, it is preferable to use metal oxides with low carrier density in transistors. Reducing the carrier density of the metal oxide film lowers the impurity concentration and thus the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in the metal oxide can be lower than 8 × 10⁻⁶. 11 cm -3 Preferably less than 1×10 11 cm -3 More preferably, less than 1×10 10 cm -3 And it is 1×10 -9 cm -3 above.

[0306] Because high-purity intrinsic or substantially high-purity intrinsic metal oxide films have a low defect state density, they may have a low trap state density.

[0307] Furthermore, the charge trapped in the trap levels of metal oxides takes a relatively long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors with channel formation regions in metal oxides with high trap state densities are sometimes unstable.

[0308] Therefore, reducing the impurity concentration in the metal oxide is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0309] [Impurities]

[0310] Here, we will explain the effects of various impurities in metal oxides.

[0311] Furthermore, when the metal oxide contains alkali metals or alkaline earth metals, defect energy levels can sometimes be formed, leading to the formation of charge carriers. Therefore, transistors using metal oxides containing alkali metals or alkaline earth metals as the channel formation region tend to exhibit always-on characteristics. Consequently, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of alkali metals or alkaline earth metals in the metal oxide, as measured by SIMS, should be 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0312] Hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When the channel-forming region in a metal oxide contains oxygen vacancies, the transistor tends to have always-on characteristics. When hydrogen enters this oxygen vacancy, electrons are sometimes generated as charge carriers. Furthermore, sometimes electrons are generated as charge carriers due to partial bonding of hydrogen with oxygen bonded to metal atoms. Therefore, transistors using metal oxides containing hydrogen as the channel-forming region tend to have always-on characteristics.

[0313] Therefore, it is preferable to minimize the amount of hydrogen in metal oxides. Specifically, the hydrogen concentration in metal oxides, as measured by SIMS analysis, is set to be below 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3By using metal oxides with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0314] As a semiconductor used in transistors, a metal oxide film with high crystallinity is preferred. Using this film can improve the stability or reliability of the transistor. Examples of such films include, for instance, single-crystal metal oxide films or polycrystalline metal oxide films. However, forming single-crystal or polycrystalline metal oxide films on a substrate requires high-temperature or laser heating processes. Therefore, the manufacturing process becomes more expensive and throughput decreases.

[0315] Non-patent documents 1 and 2 report the discovery of In-Ga-Zn oxides (also known as CAAC-IGZO) with a CAAC structure in 2009. These documents report that CAAC-IGZO exhibits c-axis orientation, indistinct grain boundaries, and can be formed on substrates at low temperatures. Furthermore, transistors using CAAC-IGZO are reported to possess excellent electrical characteristics and reliability.

[0316] Furthermore, in 2013, an In-Ga-Zn oxide with an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Literature 3). It is reported here that the atomic arrangement of nc-IGZO in small regions (e.g., regions above 1 nm and below 3 nm) is periodic, and no regularity of crystal orientation is observed between different regions.

[0317] Non-Patent Documents 4 and 5 show the shift in average crystal size when the aforementioned CAAC-IGZO, nc-IGZO, and low-crystallinity IGZO films are irradiated with an electron beam, respectively. In the low-crystallinity IGZO film, approximately 1 nm of crystalline IGZO can be observed before electron beam irradiation. Therefore, Non-Patent Documents 4 and 5 report that the presence of a completely amorphous structure could not be confirmed in the IGZO. Furthermore, it is disclosed that CAAC-IGZO and nc-IGZO films exhibit higher stability relative to electron beam irradiation compared to the low-crystallinity IGZO film. Therefore, CAAC-IGZO or nc-IGZO films are preferably used as semiconductors for transistors.

[0318] Non-Patent Document 6 discloses a transistor using metal oxides with extremely low leakage current in the non-conducting state; specifically, the off-state current of the transistor is yA / μm per channel width of 1μm (10). -24(A / μm) level (order). For example, a low-power CPU that utilizes the characteristic of low leakage current of transistors using metal oxides has been disclosed (see Non-Patent Document 7).

[0319] Furthermore, there are reports of applying transistors using metal oxide transistors to display devices, taking advantage of their low leakage current (see Non-Patent Document 8). In display devices, the displayed image is switched dozens of times per second. The number of image switches per second is called the "refresh rate." The refresh rate is sometimes referred to as the "drive frequency." Such high-speed image switching, which is difficult for the human eye to perceive, is considered a cause of eye fatigue. Therefore, a technique has been proposed to reduce the refresh rate of the display device to decrease the number of image rewrites. A drive with a lower refresh rate can reduce the power consumption of the display device. This drive method is called "idle stop (IDS) drive."

[0320] The discovery of CAAC and nc structures has contributed to improving the electrical characteristics and reliability of metal-oxide transistors using CAAC or nc structures, reducing manufacturing costs, and increasing throughput. Furthermore, research has been conducted on utilizing the low leakage current of these transistors for application in display devices and LSIs.

[0321] [Film Formation Method]

[0322] Insulating materials used to form insulating layers, conductive materials used to form conductive layers, and semiconductor materials used to form semiconductor layers can be formed using methods such as sputtering, spin coating, CVD (Chemical Vapor Deposition) (including thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition), PECVD (Plasma Enhanced CVD), High-density plasma CVD, LPCVD (low-pressure CVD), APCVD (atmospheric pressure CVD), ALD (Atomic Layer Deposition) or MBE (Molecular Beam Epitaxy), PLD (Pulsed Laser Deposition), dip coating, spraying, droplet jetting (inkjet printing, etc.), and printing (screen printing, offset printing, etc.).

[0323] High-quality films can be obtained at lower temperatures using plasma CVD. In film deposition methods that do not use plasma, such as MOCVD, ALD, or thermal CVD, damage is less likely to occur on the formed surface. For example, wiring, electrodes, and components (transistors, capacitors, etc.) included in storage devices can sometimes accumulate charge due to receiving charge from the plasma. This accumulated charge can sometimes damage these components. On the other hand, in film deposition methods that do not use plasma, this plasma damage does not occur, thus improving the yield of storage devices. Furthermore, the absence of plasma damage during film deposition results in films with fewer defects.

[0324] ALD (Alternating Layer Deposition) utilizes the self-regulating nature of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films formed at low temperatures. Furthermore, ALD also includes PEALD (Plasma Enhanced ALD), which utilizes plasma. By using plasma, film deposition can be performed at even lower temperatures, making it sometimes preferred. Note that the precursors used in ALD sometimes contain impurities such as carbon. Therefore, films formed using ALD sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Moreover, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0325] Unlike film deposition methods that use particles released from a target material, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed by ALD have excellent step coverage and thickness uniformity, making ALD suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other film deposition methods, such as CVD, which has a faster deposition rate.

[0326] The composition of the resulting membrane can be controlled by adjusting the flow rate ratio of the source gas in CVD or ALD methods. For example, when using CVD or ALD methods, membranes with arbitrary compositions can be formed by adjusting the flow rate ratio of the source gas. Furthermore, for example, when using CVD or ALD methods, membranes with continuously varying compositions can be formed by changing the flow rate ratio of the source gas while forming the membrane. When forming a membrane while changing the flow rate ratio of the source gas, the time required for conveying and adjusting the pressure can be eliminated, thus shortening the membrane formation time compared to using multiple membrane chambers. Therefore, the productivity of storage devices can sometimes be improved.

[0327] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0328] (Implementation Method 4)

[0329] In this embodiment, structural examples of transistors 200A and 200B that can be applied to transistor 200 are described with reference to the accompanying drawings.

[0330] Example 1 of a transistor structure

[0331] Reference Figure 25A , Figure 25B and Figure 25C This section provides an example illustrating the structure of a transistor 200A. Figure 25A This is a top view of the transistor 200A. Figure 25B Is Figure 25A A cross-sectional view of the portion indicated by the dashed lines L1-L2. Figure 25C Is Figure 25A A cross-sectional view of the portion indicated by the dashed lines W1-W2. Figure 25A In the top view, for ease of understanding, some of the constituent elements are omitted and represented.

[0332] exist Figure 25A , Figure 25B and Figure 25C The diagram shows a transistor 200A, and insulating layers 361, 362, 365, 366, 371, 380, 374, and 381 serving as interlayer insulating layers. It also shows conductive layers 340 (conductive layers 340a and 340b) that are electrically connected to the transistor 200A and serve as contact plugs. Furthermore, insulating layers 341 (insulating layers 341a and 341b) are provided that contact the sides of the conductive layers 340 serving as contact plugs.

[0333] As interlayer insulating layers, single layers or stacks of insulators such as silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to these insulators. Furthermore, these insulators can be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can also be stacked on top of the aforementioned insulators.

[0334] The transistor 200A includes: a conductive layer 360 (conductive layer 360a and conductive layer 360b) serving as a first gate electrode; a conductive layer 305 serving as a second gate electrode; an insulating layer 349 serving as a first gate insulating film; insulating layers 365 and insulating layers 366 serving as a second gate insulating layer; a semiconductor layer 260 (semiconductor layer 260a, semiconductor layer 260b and semiconductor layer 260c) including a region forming a channel; a conductive layer 342a serving as one of the source and drain electrodes; a conductive layer 342b serving as the other of the source and drain electrodes; and an insulating layer 371.

[0335] Furthermore, semiconductor layers 260a, 260b, and 260c are respectively equivalent to Figure 5A and Figure 5B The oxide layers 261a, 261b, and 261c are shown. Therefore, oxide layer 261c can also be referred to as semiconductor layer 260c, for example. Furthermore, a portion of oxide layer 261c can be considered as semiconductor layer 260c. Alternatively, a portion of oxide layer 261c can be considered as including semiconductor layer 260c.

[0336] The conductive layer 305 is disposed in a manner that embeds the insulating layer 362, and the insulating layer 365 is disposed on the insulating layer 362 and the conductive layer 305. The insulating layer 366 is disposed on the insulating layer 365. Furthermore, the semiconductor layer 260 is disposed on the insulating layer 366. The insulating layer 349 is disposed on the semiconductor layer 260, and the conductive layers 360 (conductive layers 360a and 360b) are disposed on the insulating layer 349.

[0337] The conductive layers 342a and 342b are configured to contact a portion of the top surface of the semiconductor layer 260b, and the insulating layer 371 is configured to contact a portion of the top surface of the insulating layer 366, the side surface of the semiconductor layer 260a, the side surface of the semiconductor layer 260b, the side surface of the conductive layer 342a, the top surface of the conductive layer 342a, the side surface of the conductive layer 342b, and the top surface of the conductive layer 342b.

[0338] An insulating layer 341 is provided in contact with the sidewalls of openings formed in insulating layers 380, 374, and 381. A first conductor of a conductive layer 340 is provided in contact with its sidewalls, and a second conductor of the conductive layer 340 is provided inside it. Here, the height of the top surface of the conductive layer 340 can be approximately the same as the height of the top surface of the insulating layer 381. Furthermore, in transistor 200A, the first conductor of the conductive layer 340 and the second conductor of the conductive layer 340 are stacked, but the present invention is not limited to this. For example, the conductive layer 340 may also have a single-layer structure or a stacked structure of three or more layers. When the structure has a stacked structure, sometimes ordinal numbers are assigned according to the order of formation for differentiation.

[0339] Semiconductor layer 260 preferably includes semiconductor layer 260a disposed on insulating layer 366, semiconductor layer 260b disposed on semiconductor layer 260a, and semiconductor layer 260c disposed on semiconductor layer 260b, at least a portion of which contacts the top surface of semiconductor layer 260b. When semiconductor layer 260a is disposed below semiconductor layer 260b, the diffusion of impurities from structures formed below semiconductor layer 260a to semiconductor layer 260b can be suppressed. When semiconductor layer 260c is disposed above semiconductor layer 260b, the diffusion of impurities from structures formed above semiconductor layer 260c to semiconductor layer 260b can be suppressed.

[0340] The semiconductor layer 260 of transistor 200A is preferably an oxide semiconductor, which is one of the metal oxides.

[0341] Transistors using oxide semiconductors to form the channel semiconductor layer exhibit extremely low leakage current (off-state current) in the non-conducting state, thus enabling low-power semiconductor devices. Furthermore, since oxide semiconductors can be formed using methods such as sputtering, highly integrated semiconductor devices can be easily realized.

[0342] For example, In-M-Zn oxide (where element M is selected from one or more of gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used as the semiconductor layer 260. In particular, gallium, yttrium, or tin is preferably used as element M. Furthermore, In-M oxide, In-Zn oxide, and M-Zn oxide can also be used as the semiconductor layer 260.

[0343] Furthermore, when an oxide semiconductor is used as semiconductor layer 260, a stacked structure made of oxides with different atomic ratios of each metal atom is preferred. Specifically, in the metal oxide used for semiconductor layer 260a, the atomic ratio of element M in the constituent elements is preferably greater than that of element M in the constituent elements of the metal oxide used for semiconductor layer 260b. Additionally, the atomic ratio of element M relative to In in the metal oxide used for semiconductor layer 260a is preferably greater than that of element M relative to In in the metal oxide used for semiconductor layer 260b. Furthermore, in the metal oxide used for semiconductor layer 260b, the atomic ratio of In relative to element M is preferably greater than that of In relative to element M in the metal oxide used for semiconductor layer 260a. Furthermore, semiconductor layer 260c can use a metal oxide that can be used for semiconductor layer 260a or semiconductor layer 260b.

[0344] Semiconductor layers 260a, 260b, and 260c are preferably crystalline, and CAAC-OS is particularly preferred. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen vacancies). Therefore, the extraction of oxygen from the semiconductor layer 260b by the source or drain electrode can be suppressed. Thus, even with heat treatment, the extraction of oxygen from the semiconductor layer 260b can be suppressed, and the transistor 200A is also stable against the high temperatures (so-called thermal budget) in the manufacturing process.

[0345] Alternatively, one or both of semiconductor layers 260a and 260c may be omitted. Semiconductor layer 260 may also be a single-layer structure of semiconductor layer 260b. When semiconductor layer 260 employs a stacked structure of semiconductor layers 260a, 260b, and 260c, the conduction band bottom energy of semiconductor layers 260a and 260c is preferably higher than that of semiconductor layer 260b. Furthermore, in other words, the electron affinity of semiconductor layers 260a and 260c is preferably lower than that of semiconductor layer 260b. In this case, semiconductor layer 260c preferably uses a metal oxide suitable for semiconductor layer 260a. Specifically, the atomic ratio of element M in the constituent elements of the metal oxide used in semiconductor layer 260c is preferably greater than the atomic ratio of element M in the constituent elements of the metal oxide used in semiconductor layer 260b. Furthermore, the atomic ratio of element M relative to In in the metal oxide used for semiconductor layer 260c is preferably greater than the atomic ratio of element M relative to In in the metal oxide used for semiconductor layer 260b. Additionally, in the metal oxide used for semiconductor layer 260b, the atomic ratio of In relative to element M is preferably greater than the atomic ratio of In relative to element M in the metal oxide used for semiconductor layer 260c.

[0346] Here, the energy level of the conduction band bottom in the junction of semiconductor layers 260a, 260b, and 260c changes gradually. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of semiconductor layers 260a, 260b, and 260c changing continuously or continuously joining. For this purpose, it is preferable to reduce the defect state density of the mixed layer formed at the interface between semiconductor layers 260a and 260b and at the interface between semiconductor layers 260b and 260c.

[0347] Specifically, when semiconductor layers 260a and 260b, and semiconductor layers 260b and 260c, contain a common element other than oxygen (with the common element other than oxygen as the main component), a mixed layer with low defect state density can be formed. For example, when semiconductor layer 260b is an In-Ga-Zn oxide, In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide can be used as semiconductor layers 260a and 260c. Furthermore, semiconductor layer 260c can also have a stacked structure. For example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide can be used, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a stacked structure of In-Ga-Zn oxide and an oxide not containing In can also be used as semiconductor layer 260c.

[0348] Specifically, for semiconductor layer 260a, a metal oxide with an In:Ga:Zn ratio of 1:3:4 or 1:1:0.5 (atomic ratio) can be used. Furthermore, for semiconductor layer 260b, a metal oxide with an In:Ga:Zn ratio of 4:2:3 or 3:1:2 (atomic ratio) can be used. Furthermore, for semiconductor layer 260c, a metal oxide with an In:Ga:Zn ratio of 1:3:4, 4:2:3, 2:1, or 2:5 (atomic ratio) can be used. Furthermore, as specific examples of semiconductor layer 260c having a stacked structure, we can cite stacked structures with In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:1 [atomic ratio], stacked structures with In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:5 [atomic ratio], and stacked structures with In:Ga:Zn = 4:2:3 [atomic ratio] and gallium oxide, etc.

[0349] At this point, the primary path for charge carriers is through semiconductor layer 260b. By equipping semiconductor layers 260a and 260c with the aforementioned structure, the defect state density at the interface between semiconductor layers 260a and 260b, and at the interface between semiconductor layers 260b and 260c, can be reduced. Therefore, the influence of interface scattering on charge carrier conduction is reduced, resulting in high on-state current and high frequency characteristics for transistor 200A. Furthermore, when semiconductor layer 260c employs a stacked structure, the following two effects can be expected: reducing the defect state density at the interface between semiconductor layers 260b and 260c, and suppressing the diffusion of constituent elements from semiconductor layer 260c to the insulating layer 349. More specifically, when semiconductor layer 260c has a stacked structure, because the oxide that does not contain In is located on top of the stacked structure, In diffusion to the insulating layer 349 can be suppressed. Since the insulating layer 349 is used as a gate insulator, In diffusion within it leads to poor transistor characteristics. Therefore, by giving the semiconductor layer 260c a stacked structure, a highly reliable semiconductor device can be provided.

[0350] The semiconductor layer 260 preferably uses a metal oxide that is used as an oxide semiconductor. For example, the metal oxide that will form the channel region of the semiconductor layer 260 preferably has a band gap of 2 eV or more, and more preferably 2.5 eV or more. In this way, by using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced. By using such a transistor, a low-power memory device can be provided.

[0351] In transistor 200A, a conductive layer 360 serving as a first gate (also called a top gate) electrode is formed in a self-aligned manner by filling an opening formed in an insulating layer 380, etc. By forming the conductive layer 360 in this way, the conductive layer 360 can be reliably disposed in the region between the conductive layers 342a and 342b without positional alignment.

[0352] The conductive layer 360 preferably includes a conductive layer 360a and a conductive layer 360b on the conductive layer 360a. For example, the conductive layer 360a is preferably disposed in a manner that surrounds the bottom surface and side surfaces of the conductive layer 360b. Figure 25B As shown, the top surface of the conductive layer 360 is roughly the same as the top surface of the insulating layer 349 and the top surface of the oxide 260c.

[0353] Conductive layer 305 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage (Vth) of transistor 200A can be controlled by individually changing the potential applied to conductive layer 305 without linking it to the potential applied to conductive layer 360. In particular, by applying a negative potential to conductive layer 305, the Vth of transistor 200A can be made greater than 0V, thereby reducing the off-state current. Therefore, applying a negative potential to conductive layer 305 can reduce the leakage current when conductive layer 360 is applied at a potential of 0V, compared to not applying a negative potential to conductive layer 305.

[0354] Furthermore, for example, when the conductive layer 305 and the conductive layer 360 overlap across the channel formation region of the semiconductor layer 260, when a voltage is applied to the conductive layer 305 and the conductive layer 360, the electric field generated in the conductive layer 360 and the electric field generated in the conductive layer 305 can be connected to cover the channel formation region of the semiconductor layer 260.

[0355] In other words, a region can be formed around the channel by the electric field of the conductive layer 360 used as the first gate electrode and the electric field of the conductive layer 305 used as the second gate electrode. In this specification, the structure of a transistor in which the electric fields of the first gate electrode and the second gate electrode form a region around the channel is referred to as a surround channel (S-channel) structure.

[0356] Insulating layers 365 and 371 preferably have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, insulating layers 365 and 371 preferably have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, compared to insulating layer 366, insulating layers 365 and 371 preferably have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Compared to insulating layer 349, insulating layers 365 and 371 preferably have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Compared to insulating layer 380, insulating layers 365 and 371 preferably have the function of suppressing the diffusion of one or both of hydrogen and oxygen.

[0357] Furthermore, in this specification and other materials, a membrane that has the function of inhibiting the diffusion of hydrogen or oxygen is sometimes referred to as a membrane that is not easily permeable to hydrogen or oxygen, a membrane with low permeability to hydrogen or oxygen, a membrane that blocks hydrogen or oxygen, or a barrier membrane for hydrogen or oxygen. Additionally, when the barrier membrane is conductive, it is sometimes referred to as a conductive barrier membrane.

[0358] In addition, such as Figure 25B As shown, the insulating layer 371 preferably contacts the top surfaces of conductive layers 342a and 342b, the sides of conductive layers 342a and 342b other than the sides opposite to the conductive layers 342a and 342b, the sides of semiconductor layers 260a and 260b, and a portion of the top surface of the insulating layer 366. Thus, the insulating layer 380 is separated from the insulating layer 366, semiconductor layers 260a and 260b by the insulating layer 371. Therefore, impurities such as hydrogen contained in the insulating layer 380 can be suppressed from intruding into the insulating layer 366, semiconductor layers 260a and 260b.

[0359] In addition, such as Figure 25B As shown, transistor 200A has a structure in which insulating layer 374 contacts the top surfaces of conductive layer 360, insulating layer 349, and semiconductor layer 260c. By employing this structure, impurities such as hydrogen from insulating layer 381 can be suppressed from entering insulating layer 349. This helps to prevent negative impacts on the electrical characteristics and reliability of the transistor.

[0360] By having the above structure, a transistor with a large on-state current can be provided. Furthermore, a transistor with a small off-state current can be provided. Moreover, a semiconductor device that achieves stable electrical characteristics while suppressing variations in electrical characteristics can be provided, thereby improving reliability.

[0361] Example 2 of transistor structure

[0362] Reference Figure 26A , Figure 26B and Figure 26CThis section provides an example illustrating the structure of the transistor 200B. Figure 26A This is a top view of the transistor 200B. Figure 26B Is Figure 26A A cross-sectional view of the portion indicated by the dashed lines L1-L2. Figure 26C Is Figure 26A A cross-sectional view of the portion indicated by the dashed lines W1-W2. Figure 26A In the top view, for ease of understanding, some of the constituent elements are omitted and represented.

[0363] Transistor 200B is a variation of transistor 200A. Therefore, to avoid repetition, we will mainly explain its differences from transistor 200A.

[0364] The conductive layer 360 used as the first gate electrode includes a conductive layer 360a and a conductive layer 360b on the conductive layer 360a. The conductive layer 360a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0365] When the conductive layer 360a has the function of inhibiting oxygen diffusion, the material selectivity of the conductive layer 360b can be improved. That is, by including the conductive layer 360a, the oxidation of the conductive layer 360b can be inhibited, thereby preventing a decrease in conductivity.

[0366] Furthermore, it is preferable to provide the insulating layer 371 in a manner that covers the top and side surfaces of the conductive layer 360, the side surfaces of the insulating layer 349, and the side surfaces of the semiconductor layer 260c. The insulating layer 371 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferred. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, as well as silicon oxynitride or silicon nitride, can be used.

[0367] By providing the insulating layer 371, oxidation of the conductive layer 360 can be suppressed. Furthermore, by including the insulating layer 371, the diffusion of impurities such as water and hydrogen contained in the insulating layer 380 into the transistor 200B can be suppressed.

[0368] Because a portion of conductive layer 342a and a portion of conductive layer 342b overlap with conductive layer 360 in transistor 200B, the parasitic capacitance of transistor 200B tends to be larger compared to transistor 200A. Therefore, it tends to have a lower operating frequency compared to transistor 200A. However, transistor 200B does not require the process of embedding conductive layer 360 or insulating layer 349 by creating openings in insulating layer 380, etc., thus it has higher productivity compared to transistor 200A.

[0369] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0370] (Implementation Method 5)

[0371] In this embodiment, electronic components and electronic devices of a storage device or semiconductor device to which one aspect of the present invention can be applied are described.

[0372] The storage device or semiconductor device according to one aspect of the present invention can be installed in various electronic devices. In particular, the storage device or semiconductor device according to one aspect of the present invention can be used as a memory built into an electronic device. Examples of electronic devices include, in addition to electronic devices with large screens such as television sets, desktop or laptop personal computers, displays for computers, digital signage, and large game machines such as pinball machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0373] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or data can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0374] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0375] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various data (static images, animated images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc.

[0376] Electronic Components

[0377] First, refer to Figure 27A and Figure 27B An example of an electronic component assembled with storage device 100 will be described.

[0378] Figure 27A A perspective view of the electronic component 700 and the substrate (circuit board 704) on which the electronic component 700 is mounted is shown. Figure 27A The electronic component 700 shown is an IC semiconductor device, including leads and circuitry. The electronic component 700 is mounted, for example, on a printed circuit board 702. Circuit board 704 is completed by combining multiple such IC semiconductor devices and electrically connecting them respectively on the printed circuit board 702.

[0379] The storage device 100 shown in the above embodiment is provided as the circuit section of the electronic component 700. Although Figure 27A The electronic component 700 is packaged using QFP (Quad Flat Package), but the packaging method is not limited to this.

[0380] Figure 27B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple memory devices 100 are disposed on the interposer 731.

[0381] Electronic component 730 illustrates an example of using storage device 100 as high-bandwidth memory (HBM). Furthermore, semiconductor device 735 may utilize integrated circuits (semiconductor devices) such as CPUs, GPUs, and FPGAs (Field Programmable Gate Arrays).

[0382] The packaging substrate 732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The through-hole board 731 can be a silicon through-hole board, a resin through-hole board, etc.

[0383] The through-hole board 731 has multiple wirings capable of electrically connecting to multiple integrated circuits with different terminal spacings. These wirings can be composed of a single layer or multiple layers. Furthermore, the through-hole board 731 functions to electrically connect integrated circuits disposed on the through-hole board 731 to electrodes disposed on the packaging substrate 732. Therefore, the through-hole board is sometimes referred to as a "redistribution substrate" or "intermediate substrate." Additionally, sometimes a through-electrode is provided in the through-hole board 731 to electrically connect the integrated circuit to the packaging substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV (Through Silicon Via) can also be used as the through-electrode.

[0384] Silicon interposers are preferred for the 731 interposer. Since silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. Wiring formation on silicon interposers can be performed during semiconductor processes, and resin interposers are easier to form with fine wiring.

[0385] In HBM, a large number of wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM needs to be able to form fine wirings at high density. Thus, silicon mounting boards are preferred as mounting boards for HBM.

[0386] Furthermore, in SiP or MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged and configured on the interposer.

[0387] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 are at the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the storage device 100 and the semiconductor device 735 are at the same height.

[0388] In order to mount the electronic component 730 on another substrate, an electrode 733 can be provided on the bottom of the package substrate 732. Figure 27B An example of forming electrode 733 using solder balls is shown. BGA (Ball Grid Array) mounting can be achieved by arranging solder balls in a matrix on the bottom of the package substrate 732. Alternatively, electrode 733 can also be formed using conductive pins. PGA (Pin Grid Array) mounting can be achieved by arranging conductive pins in a matrix on the bottom of the package substrate 732.

[0389] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0390] Electronic Equipment

[0391] Next, refer to Figures 28 to 3 1. An example of an electronic device equipped with the above-mentioned electronic components will be described.

[0392] Figure 28 The robot 7100 shown includes an illuminance sensor, microphone, camera, speaker, display, various sensors (infrared sensor, ultrasonic sensor, accelerometer, piezoelectric sensor, light sensor, gyroscope sensor, etc.) and a movement mechanism. The electronic component 730 includes a processor and has the function of controlling these peripheral devices. For example, the electronic component 700 has the function of storing data measured by the sensors.

[0393] The microphone detects audio signals such as the user's voice and ambient sounds. The speaker emits audio signals such as sounds and warning tones. Robot 7100 can analyze the audio signals input through the microphone and emit the necessary audio signals from the speaker. Robot 7100 can communicate with the user using both the microphone and speaker.

[0394] The camera has the function of capturing images of the surroundings of robot 7100. Furthermore, robot 7100 has the function of moving using a locomotion mechanism. Robot 7100 can analyze the images captured by the camera to determine the presence or absence of obstacles during movement.

[0395] The flying object 7120 includes a propeller, camera, and battery, and has autonomous flight capabilities. The electronic component 730 has the function of controlling the aforementioned peripheral equipment.

[0396] For example, image data captured by the camera is stored in electronic component 700. Electronic component 730 can analyze the image data to determine the presence or absence of obstacles during movement. Furthermore, electronic component 730 can use changes in battery capacity to estimate the remaining battery power.

[0397] The 7140 robotic vacuum cleaner includes a display on the top surface, multiple cameras on the sides, brushes, control buttons, and various sensors. Although not shown, the 7140 is equipped with tires and a suction inlet. The 7140 can move automatically, detect debris, and suck it up from the suction inlet on the bottom.

[0398] For example, the electronic component 730 can determine the presence or absence of obstacles such as walls, furniture, or steps by analyzing images captured by the camera. Furthermore, if image analysis detects objects such as wiring that might get tangled in the brush, the brush rotation can be stopped.

[0399] An example of a moving body is shown: a car 7160. The car 7160 includes an engine, tires, brakes, a steering system, a camera, etc. For example, electronic component 730 performs control to optimize the driving state of the car 7160 based on data such as navigation information, speed, engine status, gear selection status, and brake usage frequency. For example, image data captured by the camera is stored in electronic component 700.

[0400] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies. The computer of one aspect of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0401] Electronic components 700 and / or 730 can be installed in television receiver (TV) device 7200, smartphone 7210, PC 7220 (personal computer), PC 7230, game console 7240, game console 7260, etc.

[0402] For example, the electronic component 730 installed in the TV device 7200 can be used as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

[0403] Smartphone 7210 is an example of a portable information terminal. Smartphone 7210 includes a microphone, camera, speaker, various sensors, and a display. Electronic components 730 control the aforementioned peripheral devices.

[0404] PC7220 and PC7230 are examples of a notebook PC and a desktop PC, respectively. The keyboard 7232 and the display device 7233 can be connected to the PC7230 wirelessly or wiredly.

[0405] Game console 7240 is an example of a portable game console. Game console 7260 is an example of a home-based stationary game console. Game console 7260 connects to controller 7262 wirelessly or via wired connection. Electronic components 700 and / or 730 may be installed on controller 7262.

[0406] Game machines using a storage device or semiconductor device according to one aspect of the present invention are not limited thereto. Examples of game machines using a storage device or semiconductor device according to one aspect of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0407] A storage device or semiconductor device according to one aspect of the present invention can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB storage devices, and SSDs (solid-state drives). Figure 29 schematically illustrates several structural examples of removable storage devices. A storage device or semiconductor device according to one aspect of the present invention can be used in various storage devices or removable memories.

[0408] Figure 29A This is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. A storage device or semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1105, etc., on the substrate 1104.

[0409] Figure 29B This is a schematic diagram of the SD card's appearance. Figure 29C This is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, data can be read from and written to the memory chip 1114 via wireless communication between the host device and the SD card 1110. A storage device or semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1114, etc., on the substrate 1113.

[0410] Figure 29D This is a schematic diagram of the SSD's appearance. Figure 29EThis is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A storage device or semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1154, etc., on the substrate 1153.

[0411] Figure 30A The alarm device 8100 shown is a residential fire alarm device, including a detection unit and a semiconductor device 8101. By incorporating the aforementioned electronic components 700 and / or 730 into the semiconductor device 8101, the power consumption of the alarm device 8100 can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the alarm device 8100 can be improved.

[0412] Figure 30A The air conditioner shown includes an indoor unit 8200 and an outdoor unit 8204. The indoor unit 8200 includes a casing 8201, an air vent 8202, and a semiconductor device 8203, etc. Although in Figure 30A The diagram shows a case where the semiconductor device 8203 is installed in the indoor unit 8200, but the semiconductor device 8203 can also be installed in the outdoor unit 8204. Alternatively, the semiconductor device 8203 can be installed in both the indoor unit 8200 and the outdoor unit 8204. By incorporating the aforementioned electronic components 700 and / or 730 into the semiconductor device 8203, the power consumption of the air conditioner can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the air conditioner can be improved.

[0413] Figure 30A The electric refrigerator / freezer 8300 shown includes an outer casing 8301, a refrigerator door 8302, a freezer door 8303, a semiconductor device 8304, etc. Figure 30A In this design, a semiconductor device 8304 is disposed inside the housing 8301. By incorporating the aforementioned electronic components 700 and / or 730 into the semiconductor device 8304, the power consumption of the electric refrigerator / freezer 8300 can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the electric refrigerator / freezer 8300 can be improved.

[0414] In this embodiment, an electric refrigerator / freezer and an air conditioner are described as examples of electrical products. The storage device or semiconductor device of one aspect of the present invention can also be applied to other electrical products. Examples of other electrical products include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cooking appliances, water dispensers, air conditioners (including air conditioners), washing machines, dryers, and audio-visual equipment.

[0415] Figure 30B , Figure 30C An example of an electric vehicle is shown. The electric vehicle 9700 is equipped with a secondary battery 9701. The power from the secondary battery 9701 is adjusted by a control circuit 9702 and supplied to the drive unit 9703. The control circuit 9702 is controlled by a processing unit 9704, which includes semiconductor devices (not shown). By using the aforementioned electronic components 700 and / or 730 in the control circuit 9702 or the processing unit 9704, the power consumption of the electric vehicle 9700 can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the electric vehicle 9700 can be improved.

[0416] The drive unit 9703 utilizes a DC motor or an AC motor, or a combination of an electric motor and an internal combustion engine. The processing unit 9704 outputs control signals to the control circuit 9702 based on input data such as driver operation data (acceleration, deceleration, stopping, etc.) and driving data (climbing hills, descending hills, or loads on the wheels during driving). The control circuit 9702 uses the control signals from the processing unit 9704 to adjust the output of the drive unit 9703 by controlling the electrical energy supplied from the secondary battery 9701. When an AC motor is installed, although not shown, an inverter that converts DC to AC is also installed.

[0417] Figure 31A The computer 5400 shown is an example of a mainframe computer. In computer 5400, multiple rack-mounted computers 5420 are housed in rack 5410.

[0418] Computer 5420, for example, can have Figure 31B The structure shown in the 3D diagram. In Figure 31B In the computer 5420, a motherboard 5430 is included, which includes multiple slots 5431 and multiple connection terminals. A personal computer card 5421 is inserted into the slots 5431. Furthermore, the personal computer card 5421 includes connection terminals 5423, 5424, and 5425, all of which are connected to the motherboard 5430.

[0419] Figure 31CThe personal computer card 5421 shown is an example of a processing board including a CPU, GPU, storage device, etc. The personal computer card 5421 has a board 5422. Furthermore, the board 5422 includes connection terminals 5423, 5424, and 5425, semiconductor devices 5426, 5427, and 5428, and a connection terminal 5429. Note that... Figure 31C Semiconductor devices other than semiconductor devices 5426, 5427 and 5428 are shown. For a description of these semiconductor devices, please refer to the description of semiconductor devices 5426, 5427 and 5428 described below.

[0420] The connection terminal 5429 has a shape that allows it to be inserted into a slot 5431 of the motherboard 5430. The connection terminal 5429 is used as an interface for connecting the personal computer card 5421 to the motherboard 5430. Examples of specifications for the connection terminal 5429 include PCIe.

[0421] Connection terminals 5423, 5424, and 5425 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5421. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5421. Examples of specifications for connection terminals 5423, 5424, and 5425 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connection terminals 5423, 5424, and 5425, examples of specifications include HDMI (registered trademark).

[0422] Semiconductor device 5426 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into a socket (not shown) included in board 5422, semiconductor device 5426 and board 5422 can be electrically connected.

[0423] Semiconductor device 5427 includes multiple terminals, which can be electrically connected to board 5422 by reflow soldering the terminals to wiring provided on board 5422. Examples of semiconductor devices 5427 include FPGAs, GPUs, and CPUs. Electronic component 730 can also be used as a semiconductor device 5427.

[0424] Semiconductor device 5428 includes multiple terminals, which can be electrically connected to board 5422 by reflow soldering the terminals to wiring provided on board 5422. Examples of semiconductor devices 5428 include memory devices. Electronic component 700 can also be used as a semiconductor device 5428.

[0425] The Computer 5400 can be used as a parallel computer. By using the Computer 5400 as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0426] By using the storage device or semiconductor device of one aspect of the present invention in the aforementioned various electronic devices, miniaturization, high speed, or low power consumption of the electronic devices can be achieved. Furthermore, the semiconductor device of one aspect of the present invention consumes little power, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Moreover, stable operation can be achieved even in high-temperature environments. This improves the reliability of the electronic devices.

[0427] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0428] [Symbol Explanation]

[0429] 10: Memory cell; 100: Memory device; 110: Electrode; 111: Input / output circuit; 112: Control circuit; 113: C receiver; 114: Setting register; 115: LVDS circuit; 116: LVDS circuit; 117: Decoder; 118: Register; 119: Register; 120: Electrode; 127: Sensing amplifier; 130: Insulating layer; 152: Electrode; 153: Electrode; 154: Insulating layer; 156: Insulating layer; 200: Transistor; 210: Memory block array; 211: Memory block; 212: Word line driver; 213: Partial sense amplifier driver; 214: Partial sense amplifier array; 215: Global sense amplifier; 216: Selector; 218: Negative voltage generation circuit; 220: Capacitor; 221: Cell array; 223: Sub-cell array

Claims

1. A memory device comprising: a plurality of first wirings extending in a first direction; a plurality of oxide layers; a first memory element group; and a second memory element group, wherein the plurality of first wirings includes: a region overlapping with the first memory element group; and a region overlapping with the second memory element group, one of the plurality of oxide layers includes a region extending along a side surface of one of the first wirings to be separated from the one of the first wirings by a gate insulating layer, the first memory element group and the second memory element group include a plurality of memory elements, each of the plurality of memory elements includes a transistor and a capacitor, in each of the plurality of memory elements, a gate electrode of the transistor is electrically connected to one of the plurality of first wirings, a semiconductor layer of the transistor includes a region in contact with one of the plurality of oxide layers, and a shortest distance between a gate electrode of a transistor included in a memory element arranged at an end portion of the first memory element group and a gate electrode of a transistor included in a memory element arranged at an end portion of the second memory element group is 3.5 μm or less.

2. The memory device according to claim 1, wherein the shortest distance is 2.3 μm or less.

3. The memory device according to claim 1 or claim 2, wherein a plurality of second wirings extending in a second direction are included, and in each of the plurality of memory elements, one of a source electrode and a drain electrode of the transistor is electrically connected to one of the plurality of second wirings.

4. The memory device according to claim 3, wherein in each of the plurality of memory elements, the other of the source electrode and the drain electrode of the transistor is electrically connected to the capacitor.

5. The memory device according to claim 1, wherein one of the plurality of oxide layers includes a region overlapping with one of the first wirings by an insulating layer.

6. The memory device according to claim 1, wherein the oxide layer contains one or both of indium and zinc.

7. The memory device according to claim 1, wherein the semiconductor layer contains one or both of indium and zinc.

8. The memory device according to claim 1, further comprising a plurality of third wirings extending in the first direction, wherein one of the plurality of third wirings includes a region overlapping with one of the plurality of first wirings with each other.

9. A memory device comprising: a plurality of first wirings extending in a first direction; a plurality of oxide layers; a first memory element group; a second memory element group; and a first region, wherein the plurality of first wirings includes: a region overlapping with the first memory element group; a region overlapping with the second memory element group; and a region overlapping with the first region, one of the plurality of oxide layers includes a region extending along a side surface of one of the first wirings to be separated from the one of the first wirings by a gate insulating layer, the first memory element group and the second memory element group include a plurality of memory elements, ​ ​ Each of the plurality of storage elements includes a first transistor and a capacitor, In each of the plurality of storage elements, a gate of the first transistor is electrically connected to one of the plurality of first wirings, a semiconductor layer of the first transistor includes a region in contact with one of the plurality of oxide layers, the first region includes a plurality of second transistors, In each of the plurality of second transistors, a gate electrode is electrically connected to one of the plurality of first wirings, and one or both of a source electrode and a drain electrode is electrically connected to a fourth wiring, and has a function of supplying a high power supply potential to the fourth wiring.

10. The storage device according to claim 9, further comprising a plurality of second wirings extending in a second direction, and in each of the plurality of storage elements, one of a source electrode and a drain electrode of the first transistor is electrically connected to one of the plurality of second wirings.

11. The storage device according to claim 10, wherein in each of the plurality of storage elements, the other of the source electrode and the drain electrode of the first transistor is electrically connected to the capacitor.

12. The storage device according to claim 9, wherein one of the plurality of oxide layers includes a region overlapping one of the first wirings with an insulating layer interposed.

13. The storage device according to claim 9, wherein the oxide layer contains one or both of indium and zinc.

14. The storage device according to claim 9, wherein the semiconductor layer contains one or both of indium and zinc.

15. The storage device according to claim 9, further comprising a plurality of third wirings extending in a first direction, wherein one of the plurality of third wirings includes a region overlapping one of the plurality of first wirings with each other.

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