Semiconductor devices

Abstract

An area capable of arranging elements such as transistors is ensured in a semiconductor device. A semiconductor device is provided, the semiconductor device comprising: a semiconductor substrate, an emitter electrode having at least two partial electrodes arranged at intervals when the semiconductor substrate is viewed from above, and an active-side gate wiring and an active-side dummy wiring arranged to be sandwiched by the two partial electrodes, the semiconductor substrate having: a gate groove portion connected to the active-side gate wiring and having a long side in a first direction when viewed from above, and a dummy groove portion connected to the active-side dummy wiring and having a long side in the first direction, one of the active-side gate wiring and the active-side dummy wiring being entirely covered by the other of the active-side gate wiring and the active-side dummy wiring in the first direction.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Conventionally, there is known a structure in which a semiconductor device having a gate trench and a dummy trench is provided with a wiring for screening the dummy trench (for example, refer to Patent Documents 1 to 3).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-25124

[0006] Patent Document 2: Japanese Patent Application Publication No. 2015-207736

[0007] Patent Document 3: Japanese Patent Application Publication No. 2014-53552

[0008] Patent Document 4: Japanese Patent Application Publication No. 2018-174295 Summary of the invention

[0009] Technical issues

[0010] If a screening wiring is provided in an active portion where elements such as transistors are formed, the area in which elements such as transistors can be arranged will be reduced.

[0011] Technical Solution

[0012] In order to solve the above-mentioned problems, a semiconductor device having a semiconductor substrate is provided in one embodiment of the present invention. The semiconductor device may have an emitting electrode, and the emitting electrode has at least two partial electrodes arranged at intervals when the semiconductor substrate is viewed from above. The semiconductor device may have an active side gate wiring and an active side dummy wiring. The active side gate wiring and the active side dummy wiring may be arranged to be sandwiched by two partial electrodes. The semiconductor substrate may have a gate groove portion connected to the active side gate wiring and having a long side in a first direction when viewed from above. The semiconductor substrate may have a dummy groove portion connected to the active side dummy wiring and having a long side in the first direction. One of the active side gate wiring and the active side dummy wiring may be completely covered by the other of the active side gate wiring and the active side dummy wiring in the first direction.

[0013] The entire active-side gate wiring may be covered by the active-side dummy wiring arranged above the active-side gate wiring in the first direction.

[0014] The active-side dummy wiring may be connected to the dummy trench portion at a portion that does not overlap with the active-side gate wiring.

[0015] The active-side gate wiring may be a wiring made of a semiconductor material, and the active-side dummy wiring may be a wiring made of a metal material.

[0016] The emitter electrode may include a bridge portion connecting the two partial electrodes to each other. The active-side dummy wiring may be divided into at least two partial wirings by the bridge portion. The semiconductor device may include a crossing dummy wiring of a semiconductor material arranged to intersect the bridge portion and connect the two partial wirings to each other.

[0017] The crossing dummy wiring may be connected to the dummy trench portion.

[0018] The semiconductor substrate may include a transistor portion provided with a gate trench portion and a dummy trench portion, and a diode portion provided with a dummy trench portion. The intersecting dummy wiring may be connected to the dummy trench portion of the diode portion.

[0019] The dummy trench portion of the transistor portion may be connected to the active-side dummy wiring.

[0020] The active-side gate wiring may be provided to intersect the bridge portion.

[0021] The semiconductor device may include an interlayer insulating film. The interlayer insulating film may be provided between the semiconductor substrate and the emitter electrode. The interlayer insulating film may have a contact hole for connecting the emitter electrode to the semiconductor substrate. The active-side dummy wiring may be provided in a range that does not overlap with the contact hole when the semiconductor substrate is viewed from above.

[0022] The semiconductor device may include a peripheral gate wiring. The peripheral gate wiring may be arranged between the emitter electrode and the edge of the semiconductor substrate when viewed from above. The peripheral gate wiring may be connected to the active-side gate wiring. The semiconductor device may include a peripheral dummy wiring. The peripheral dummy wiring may be arranged between the emitter electrode and the edge of the semiconductor substrate when viewed from above. The peripheral dummy wiring may be connected to the active-side dummy wiring. The peripheral dummy wiring may be arranged so as not to overlap with the peripheral gate wiring when the semiconductor substrate is viewed from above.

[0023] The semiconductor device may include a screening pad connected to the peripheral dummy wiring.

[0024] It should be noted that the above-mentioned summary of the invention does not list all the essential features of the present invention. In addition, sub-combinations of these feature groups can also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0026] Figure 2 yes Figure 1 Magnified view of area A in FIG.

[0027] Figure 3 Yes means Figure 2 A diagram showing an example of the bb cross section in FIG.

[0028] Figure 4 It is a diagram showing an example of element arrangement in the active portion 120 .

[0029] Figure 5 yes Figure 4 Magnified view of area C in FIG.

[0030] Figure 6 Yes means Figure 5 A diagram showing an example of a dd cross section in FIG.

[0031] Figure 7 1 is a diagram showing another configuration example of the emitter electrode 52 .

[0032] Figure 8 It is an enlarged view of the vicinity of the bridge portion 53 .

[0033] Fig. 9 Yes means Figure 8 A diagram of an example of an hh cross section in .

[0034] Fig.10 Yes means Figure 8 A diagram showing an example of the ii section in FIG.

[0035] Fig.11 yes Figure 7 Magnified view of area F in FIG.

[0036] Fig.12 yes Figure 7 Magnified view of area G in FIG.

[0037] Explanation of symbols

[0038] 10…semiconductor substrate, 11…well region, 12…emitter region, 14…base region, 15…contact region, 18…drift region, 20…buffer region, 21…upper surface, 22…collector region, 23…lower surface, 24…collector electrode, 25…connecting portion, 29…straight portion, 30…dummy groove portion, 31…front end portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 40…gate groove portion, 42…gate insulating film, 44…gate conductive portion, 52…emitter electrode, 52-1, 52-2, 52-3…partial electrodes, 54, 55, 56, 57…contact hole, 60, 61…table , 70…transistor portion, 80…diode portion, 81…extension region, 82…cathode region, 90…edge terminal structure portion, 100…semiconductor device, 102…end edge, 111…gate pad, 112…screening pad, 113…anode pad, 114…cathode pad, 117…temperature sensing portion, 118, 119…wiring, 120…active portion, 130…peripheral dummy wiring, 131…active side dummy wiring, 131-1, 131-2…partial wiring, 132…cross dummy wiring, 140…peripheral gate wiring, 141…active side gate wiring, 144…second peripheral wiring, 150…partial DETAILED DESCRIPTION

[0039] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the inventions involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the solution of the invention.

[0040] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0041] In this specification, sometimes the orthogonal coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The orthogonal coordinate axes are only used to determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. In the case where the positive and negative are not recorded but the Z-axis direction is recorded, it refers to the direction parallel to the +Z-axis and the -Z-axis. In addition, in this specification, the situation of observing from the +Z-axis direction is sometimes referred to as a top view.

[0042] In this specification, the term "same" or "equal" may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0043] In this specification, the conductivity type of the doped region doped with impurities is set to P type or N type for description. However, the conductivity type of each doped region may also be opposite in polarity. In addition, in this specification, the case described as P+ type or N+ type means that the doping concentration is higher than that of P type or N type, and the case described as P- type or N- type means that the doping concentration is lower than that of P type or N type.

[0044] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between donors and acceptors is sometimes used as doping concentration. This concentration difference can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by the spreading resistance measurement (SR) can be used as the doping concentration. In addition, in the case where the doping concentration distribution has a peak, the peak value can also be used as the doping concentration in the region. In the case where the doping concentration in the region where the donor or acceptor exists is basically equal, the average value of the doping concentration can be used as the doping concentration in the region. In addition, in this specification, the concentration of the dopant refers to the respective concentrations of the donor and the acceptor.

[0045] Figure 1 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 Only a part of the components of the semiconductor device 100 is shown, and a part of the components is omitted.

[0046] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has an edge 102 when viewed from above. In this specification, the term "viewed from above" refers to the state of viewing from the upper surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two sets of edges 102 facing each other when viewed from above. Figure 1 In the embodiment, the X-axis and the Y-axis are parallel to the certain end side 102. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0047] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. An emitter electrode 52 is provided above the active portion 120. Figure 1 In FIG. 1 , the emitter electrode 52 is marked with oblique hatching.

[0048] The emitting electrode 52 is Figure 1In the example of , there are three partial electrodes 52-1, 52-2 and 52-3. Each partial electrode is a part of the emitting electrode 52. The plurality of partial electrodes may be separated from each other or connected to each other. The active portion 120 may refer to a region overlapping with the emitting electrode 52 when viewed from above. In this example, the region sandwiched by the emitting electrode 52 when viewed from above is also included in the active portion 120. The active portion 120 of this example may also be a quadrilateral region circumscribing the emitting electrode 52 when viewed from above.

[0049] A transistor section including a transistor element such as an IGBT is provided in the active section 120. A diode section including a diode element such as a FWD may also be provided in the active section 120. A gate groove section and a dummy groove section are provided on the upper surface of the semiconductor substrate 10 in the active section 120. The gate groove section functions as a gate electrode to which a gate potential is applied in the transistor section. The dummy groove section is provided in the transistor section or the diode section and an emitter potential is applied. The dummy groove section is electrically connected to the emitter electrode.

[0050] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 111, a screening pad 112, an anode pad 113, and a cathode pad 114. In addition, a pad for current detection may also be provided. When the semiconductor device 100 is installed, each pad may be connected to an external circuit via wiring such as a wire.

[0051] A gate potential is applied to the gate pad 111. The gate pad 111 is electrically connected to a conductive portion of a gate trench portion of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 111 to the gate trench portion. Figure 1 In FIG. 1 , the gate wiring is marked with oblique hatching.

[0052] The gate wiring of this example includes a peripheral gate wiring 140 and an active-side gate wiring 141. The peripheral gate wiring 140 is arranged between the emitter electrode 52 and the edge 102 of the semiconductor substrate 10 in a plan view. The peripheral gate wiring 140 of this example surrounds the active portion 120 in a plan view. In addition, the peripheral gate wiring 140 is connected to the gate pad 111. The peripheral gate wiring 140 is arranged above the semiconductor substrate 10. The peripheral gate wiring 140 can be a metal wiring.

[0053] The active side gate wiring 141 is arranged to be sandwiched by two partial electrodes in a plan view. That is, the active side gate wiring 141 is provided in the active portion 120. By providing the active side gate wiring 141 in the active portion 120, the variation of the wiring length from the gate pad 111 in each region of the semiconductor substrate 10 can be reduced.

[0054] The active-side gate wiring 141 is connected to the gate trench portion of the active portion 120. The active-side gate wiring 141 is disposed above the semiconductor substrate 10. The active-side gate wiring 141 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0055] The active side gate wiring 141 may be connected to the peripheral gate wiring 140. The active side gate wiring 141 of this example is provided to extend from the peripheral gate wiring 140 to the inside of the active portion 120 in the X-axis direction. The active side gate wiring 141 of this example is provided between the partial electrode 52-1 and the partial electrode 52-2 and between the partial electrode 52-1 and the partial electrode 52-3. The active side gate wiring 141 may also be provided to cross the active portion 120. Figure 1 In the example of , the active-side gate wiring 141 is divided by the temperature sensing portion 117 described later. That is, the active-side gate wiring 141 is arranged so as to sandwich the temperature sensing portion 117.

[0056] When inspecting the semiconductor device 100, a potential for screening is applied to the screening pad 112. The screening pad 112 is electrically connected to the conductive portion of the dummy groove portion of the active portion 120. The dummy groove portion has a conductive portion and an insulating film. The insulating film is provided between the conductive portion and the semiconductor substrate 10. When inspecting the semiconductor device 100, an emitter potential is applied to the semiconductor substrate 10 and a screening potential is applied to the conductive portion of the dummy groove portion. The emitter potential can be applied to the semiconductor substrate 10 from the emitter electrode 52. Thus, a predetermined voltage is applied to the insulating film of the dummy groove portion, so that the quality of the insulating film can be inspected. When installing the semiconductor device 100, the screening pad 112 is electrically connected to the emitter electrode 52. Thus, an emitter potential is applied to the dummy groove portion.

[0057] The semiconductor device 100 is provided with a dummy wiring. The dummy wiring connects the screening pad 112 to the dummy groove portion. The dummy wiring of this example includes a peripheral dummy wiring 130 and an active side dummy wiring 131. The peripheral dummy wiring 130 is arranged between the emitter electrode 52 and the end 102 of the semiconductor substrate 10 when viewed from above. The peripheral dummy wiring 130 of this example surrounds the active portion 120 when viewed from above. The peripheral dummy wiring 130 can be arranged between the active portion 120 and the peripheral gate wiring 140. The peripheral dummy wiring 130 can also be arranged between the peripheral gate wiring 140 and the end 102 of the semiconductor substrate 10. The peripheral dummy wiring 130 is connected to the screening pad 112. The peripheral dummy wiring 130 is arranged above the semiconductor substrate 10. The peripheral dummy wiring 130 can be a metal wiring.

[0058] The active-side dummy wiring 131 is arranged to be sandwiched by two partial electrodes in a plan view. That is, the active-side dummy wiring 131 is provided in the active portion 120. By providing the active-side dummy wiring 131 in the active portion 120, the deviation of the wiring length from the screening pad 112 in each region of the semiconductor substrate 10 can be reduced.

[0059] The active-side dummy wiring 131 is connected to the dummy trench portion of the active portion 120. The active-side dummy wiring 131 is disposed above the semiconductor substrate 10. The active-side dummy wiring 131 may be a metal wiring.

[0060] The active-side dummy wiring 131 may be connected to the peripheral dummy wiring 130. The active-side dummy wiring 131 of this example is provided to extend from the peripheral dummy wiring 130 to the inside of the active portion 120 in the X-axis direction. The active-side dummy wiring 131 of this example is provided between the partial electrodes 52-1 and 52-2 and between the partial electrodes 52-1 and 52-3. The active-side dummy wiring 131 may also be provided to cross the active portion 120. Figure 1 In the example of , the active-side dummy wiring 131 is divided by the temperature sensing portion 117 described later. That is, the active-side dummy wiring 131 is arranged so as to sandwich the temperature sensing portion 117.

[0061] One of the active-side gate wiring 141 and the active-side dummy wiring 131 is completely covered by the other of the active-side gate wiring 141 and the active-side dummy wiring 131 in a first direction. The first direction in this example is the Y-axis direction. In this example, the active-side gate wiring 141 is completely covered by the active-side dummy wiring 131 in the Y-axis direction. That is, the two ends of the active-side gate wiring 141 in the Y-axis direction are arranged in an area sandwiched by the two ends of the active-side dummy wiring 131 in the Y-axis direction. The active-side gate wiring 141 may also have an area that is not covered by the active-side dummy wiring 131 at a certain position in the X-axis direction. Figure 1 In the example, a portion 150 of the active-side gate wiring 141 that contacts the peripheral gate wiring 140 is neither covered by the active-side dummy wiring 131 nor by the peripheral dummy wiring 130. The length in the X-axis direction of the portion of the active-side gate wiring 141 covered by the active-side dummy wiring 131 and the peripheral dummy wiring 130 may be 5 times or more, or 10 times or more, the length in the X-axis direction of the portion 150 that is not covered by the active-side dummy wiring 131 and the peripheral dummy wiring 130. The length in the X-axis direction of the portion 150 is equivalent to the interval between the peripheral gate wiring 140 and the peripheral dummy wiring 130.

[0062] By arranging the active side gate wiring 141 and the active side dummy wiring 131 to overlap, the area occupied by the active side gate wiring 141 and the active side dummy wiring 131 can be reduced. Thus, the area of ​​the elements such as transistors can be ensured in the active part 120. One of the active side gate wiring 141 and the active side dummy wiring 131 can be a metal wiring, and the other can be a semiconductor wiring. Thus, it is easy to overlap the two wirings. The metal wiring can be arranged at a position above the semiconductor wiring. An interlayer insulating film is provided between the two wirings.

[0063] In this example, the active-side dummy wiring 131 is a metal wiring, and the active-side gate wiring 141 is a semiconductor wiring. In other examples, the active-side dummy wiring 131 may also be a semiconductor wiring, and the active-side gate wiring 141 may also be a metal wiring. In this case, the peripheral dummy wiring 130 may be arranged between the peripheral gate wiring 140 and the edge 102 of the semiconductor substrate 10.

[0064] The temperature sensing portion 117 is a PN junction diode formed of polysilicon or the like. The temperature sensing portion 117 is disposed above the semiconductor substrate 10. The temperature sensing portion 117 can be disposed between the partial electrodes 52-1, 52-2, and 52-3, that is, approximately at the center of the active portion 120. An interlayer insulating film is provided between the temperature sensing portion 117 and the semiconductor substrate 10. The anode pad 113 and the cathode pad 114 are connected to the anode region and the cathode region of the temperature sensing portion 117 through wiring 118 and wiring 119.

[0065] The semiconductor device 100 of this example includes an edge termination structure portion 90 between the peripheral gate wiring 140 and the edge 102. The edge termination structure portion 90 alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion 90 includes, for example, a guard ring that surrounds the active portion 120 and is provided in an annular shape, a field plate, and at least one structure for reducing the surface electric field, or a combination of a plurality of these structures.

[0066] The screening pad 112 and the gate pad 111 of this example are arranged near the common edge 102. The vicinity of the edge 102 refers to the area between the edge 102 and the emitter electrode 52. In addition, the anode pad 113 and the cathode pad 114 can be arranged near the edge 102 on the side opposite to the gate pad 111.

[0067] Figure 2 yes Figure 1 A magnified view of area A in the figure. Figure 2 , the partial electrodes 52-1 and 52-2, the active-side gate wiring 141, the active-side dummy wiring 131, the connection portion 25, the gate trench portion 40, and the dummy trench portion 30 are shown, and other components are omitted. Figure 2 In FIG. 1 , the gate trench portion 40 is marked with a symbol G, and the dummy trench portion 30 is marked with a symbol E.

[0068] The gate trench portion 40 and the dummy trench portion 30 have long sides in the Y-axis direction when viewed from above. That is, the gate trench portion 40 and the dummy trench portion 30 are provided to extend in the Y-axis direction. The gate trench portion 40 and the dummy trench portion 30 may have a straight line portion parallel to the Y-axis direction.

[0069] The gate trench portions 40 and the dummy trench portions 30 are arranged at predetermined intervals in the X-axis direction. Figure 2 The group including one or more gate trench portions 40 and the group including one or more dummy trench portions 30 may be alternately arranged along the X-axis direction. In this specification, a region of the semiconductor substrate 10 sandwiched between two trench portions in the X-axis direction is sometimes referred to as a mesa portion.

[0070] The front ends of the two straight line portions of at least one groove portion may be connected by a curved front end portion. Figure 2 In the example shown in FIG. 2 , the dummy groove portion 30 has two straight line portions 29 and one front end portion 31 .

[0071] The gate groove portion 40 is connected to the active side gate wiring 141. The gate groove portion 40 may also have a region overlapping with the active side gate wiring 141 when viewed from above. The gate groove portion 40 may be connected to the active side gate wiring 141 in the region overlapping with the active side gate wiring 141. The gate groove portion 40 of this example is extended from a position overlapping with the partial electrode 52-1 to a position overlapping with the partial electrode 52-2 in the Y-axis direction, and intersects with the active side gate wiring 141 and the active side dummy wiring 131 extending in the X-axis direction. That is, the gate groove portion 40 crosses the active side gate wiring 141 and the active side dummy wiring 131 in the Y-axis direction.

[0072] The dummy groove portion 30 is connected to the active-side dummy wiring 131. The dummy groove portion 30 may have a region overlapping with the active-side dummy wiring 131 in a plan view. The dummy groove portion 30 may not overlap with the active-side gate wiring 141 in a plan view, and may be connected to the active-side dummy wiring 131 in a region overlapping with the active-side dummy wiring 131. The end portion of the dummy groove portion 30 in the Y-axis direction may not overlap with the active-side gate wiring 141 in a plan view, and may be arranged in a region overlapping with the active-side dummy wiring 131. In this example, the front end portion 31 of the dummy groove portion 30 is arranged in this region.

[0073] The dummy groove portion 30 may be arranged so as not to overlap with the active-side gate wiring 141. In this example, the active-side gate wiring 141 is arranged between the dummy groove portion 30 overlapping with the partial electrode 52-1 and the dummy groove portion 30 overlapping with the partial electrode 52-2. That is, the active-side gate wiring 141 is provided so as to divide the dummy groove portion 30 extending in the Y-axis direction.

[0074] The semiconductor device 100 may include a connection portion 25. The connection portion 25 is formed of polysilicon doped with impurities or the like. The connection portion 25 connects the conductive portion of the dummy groove portion 30 to the active-side dummy wiring 131. The width of the connection portion 25 in the X-axis direction is greater than the width of the dummy groove portion 30 in the X-axis direction. By providing the connection portion 25, the dummy groove portion 30 can be easily connected to the active-side dummy wiring 131.

[0075] Figure 3 Yes means Figure 2 bb is a diagram of an example of a cross section in FIG. The cross section bb is a YZ cross section passing through the partial electrodes 52 - 1 , 52 - 2 , the active-side gate wiring 141 , and the active-side dummy wiring 131 . In this cross section, the semiconductor device 100 includes the semiconductor substrate 10 , the interlayer insulating film 38 , the partial electrodes 52 - 1 , 52 - 2 , and the collector electrode 24 .

[0076] The interlayer insulating film 38 is provided to cover the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be a thermal oxide film, glass such as BPSG, or other insulating films. In addition, the interlayer insulating film 38 may be a film formed by stacking a plurality of insulating films.

[0077] The partial electrodes 52-1, 52-2, 52-3 of the emitter electrode 52 and the active-side dummy wiring 131 are provided on the upper surface of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24, the emitter electrode 52, and the active-side dummy wiring 131 are provided by a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (i.e., the Z-axis direction) is referred to as the depth direction.

[0078] The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 provided in the interlayer insulating film 38. The emitter electrode 52 can contact the P-type base region 14 provided on the upper surface 21 of the semiconductor substrate 10. The base region 14 functions as, for example, an anode region of a diode portion. In addition, the base region 14 functions as, for example, a channel region of a transistor portion.

[0079] The active-side dummy wiring 131 is arranged between the partial electrode 52-1 and the partial electrode 52-2 in the Y-axis direction. The active-side dummy wiring 131 is connected to the connection portion 25 via the contact hole 55 provided in the interlayer insulating film 38. The connection portion 25 connects the active-side dummy wiring 131 to the dummy conductive portion 34 of the dummy groove portion 30 (in this example, the front end portion 31).

[0080] The active-side gate wiring 141 is arranged between the partial electrode 52-1 and the partial electrode 52-2 in the Y-axis direction. The active-side gate wiring 141 is entirely covered by the active-side dummy wiring 131 arranged above the active-side gate wiring 141 in the Y-axis direction. The active-side gate wiring 141 and the active-side dummy wiring 131 are insulated by the interlayer insulating film 38. In addition, the active-side gate wiring 141 and the semiconductor substrate 10 are insulated by the interlayer insulating film 38. However, the active-side gate wiring 141 is not insulated from the semiconductor substrate 10 by the interlayer insulating film 38. Figure 3 In a cross section different from the cross section shown, the gate electrode is connected to the gate trench portion 40 via a contact hole provided in the interlayer insulating film 38 .

[0081] The front end portion 31 of the dummy trench portion 30 may be covered by the P+ type well region 11. The well region 11 is a region having a higher doping concentration than the base region 14, formed in contact with the upper surface 21 of the semiconductor substrate 10, and formed to a position deeper than the bottom of the base region 14. By arranging the front end portion 31 inside the well region 11, the concentration of the electric field on the front end portion 31 can be alleviated.

[0082] The well region 11 may be provided in a wider range in the Y-axis direction than the active-side gate wiring 141. The well region 11 may be provided continuously from one front end portion 31 to the other front end portion 31 arranged across the active-side gate wiring 141 in the Y-axis direction.

[0083] The active-side dummy wiring 131 may be provided in a range overlapping with the well region 11 in the Y-axis direction, or may be provided in a range wider than the well region 11. However, the active-side dummy wiring 131 is provided in a range not overlapping with the contact hole 54.

[0084] According to this example, the active-side gate wiring 141 is entirely arranged to overlap with the active-side dummy wiring 131. Therefore, the area occupied by the active-side gate wiring 141 and the active-side dummy wiring 131 in the active portion 120 can be reduced. Therefore, the area of ​​the element region such as the transistor in the active portion 120 can be ensured.

[0085] A P+ type collector region 22 is provided on the lower surface 23 of the semiconductor substrate 10. The collector region 22 functions as a collector of an IGBT (insulated gate bipolar transistor). An N- type drift region 18 is provided above the collector region 22. An N+ type cathode region that functions as a cathode of a diode may be provided on the lower surface 23 of the semiconductor substrate 10, and an N+ type drain region that functions as a drain of a MOS transistor may also be provided.

[0086] Figure 4 1 is a diagram showing an example of element arrangement in the active section 120. The active section 120 of this example includes a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a FWD (freewheeling diode).

[0087] exist Figure 4 In FIG. 1 , a region where the transistor portion 70 is disposed is marked with a symbol “I”, and a region where the diode portion 80 is disposed is marked with a symbol “F”. The transistor portion 70 and the diode portion 80 are arranged along a predetermined direction (in Figure 4 The transistor portion 70 and the diode portion 80 may be alternately arranged side by side in the X-axis direction. In this specification, the direction perpendicular to the arrangement direction in a plan view is sometimes referred to as an extension direction (in the X-axis direction). Figure 1 The transistor portion 70 and the diode portion 80 may each have a long side in the extending direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of the groove portion.

[0088] The diode portion 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is a region overlapping with the cathode region when viewed from above. On the lower surface of the semiconductor substrate 10, a collector region 22 may be provided in a region other than the cathode region. In this specification, an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring or the dummy wiring is sometimes also included in the diode portion 80. The collector region 22 is provided on the lower surface of the extension region 81.

[0089] Figure 5 yes Figure 41 is an enlarged view of region C in FIG. Region C is a region including a transistor portion 70, a diode portion 80, an active side gate wiring 141, and an active side dummy wiring 131. The semiconductor substrate 10 of this example is provided with a gate groove portion 40, a dummy groove portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 in contact with the upper surface of the semiconductor substrate 10. In addition, the semiconductor substrate 10 of this example is provided with a cathode region 82 and a collector region 22 in contact with the lower surface of the semiconductor substrate 10.

[0090] In addition, an emitter electrode 52, an active-side dummy wiring 131, and an active-side gate wiring 141 are provided above the semiconductor substrate 10. Although an interlayer insulating film is provided between the emitter electrode 52 and the upper surface of the semiconductor substrate 10, Figure 5 In the interlayer insulating film of this example, the contact hole 56 and the contact hole 54 are provided to penetrate the interlayer insulating film.

[0091] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 in the upper surface of the semiconductor substrate 10 through the contact hole 54. In addition, the active-side dummy wiring 131 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole 56. A connection portion 25 may be provided between the active-side dummy wiring 131 and the dummy conductive portion.

[0092] An insulating film such as a thermal oxide film is provided between the active side gate wiring 141 and the semiconductor substrate 10. The active side gate wiring 141 is connected to the gate conductive portion in the gate groove portion 40 on the upper surface of the semiconductor substrate 10. The active side gate wiring 141 is not connected to the dummy conductive portion in the dummy groove portion 30. The active side gate wiring 141 is connected to the gate conductive portion in the gate groove portion 40 through a contact hole 56 provided in the insulating film. The gate groove portion 40, the dummy groove portion 30, the active side gate wiring 141, and the active side dummy wiring 131 have the same Figure 2 The examples shown have the same configuration and structure.

[0093] The transistor portion 70 is provided with the gate trench portion 40. The diode portion 80 is provided with the dummy trench portion 30. The transistor portion 70 may also be provided with the dummy trench portion 30.

[0094] The region sandwiched between the grooves in the semiconductor substrate 10 is called a mesa portion. The transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. The mesa portion is a region located closer to the upper surface than the deepest bottom of the groove in the portion sandwiched between the grooves of the semiconductor substrate 10.

[0095] A P-type base region 14 is provided in each mesa portion. The base region 14 is exposed at a portion of the upper surface of the mesa portion. A contact region 15 and an emitter region 12 are provided on the upper surface of the base region 14 of the transistor portion 70. The contact region 15 in this example is a P+ type with a higher doping concentration than the base region 14. The emitter region 12 in this example is a P+ type with a higher doping concentration than the base region 14. Figure 3 The drift region 18 shown is doped with a high N+ type doping concentration.

[0096] The emitter region 12 is provided on the upper surface of the semiconductor substrate 10 in contact with the gate groove portion 40. The emitter region 12 and the contact region 15 of this example are provided from one groove portion to the other groove portion sandwiching the mesa portion 60. On the upper surface of the mesa portion 60 of this example, the contact regions 15 and the emitter region 12 are alternately arranged along the Y-axis direction. Among the contact regions 15 provided on the mesa portion 60, the contact region 15 arranged at the endmost portion in the Y-axis direction can be provided at a position overlapping with the end portion of the contact hole 54 in the Y-axis direction. The emitter region 12 is arranged in the range where the contact hole 54 is provided in the Y-axis direction.

[0097] In other examples, the contact region 15 and the emitter region 12 may be arranged in a stripe shape along the Y-axis direction in the mesa portion 60. For example, one emitter region 12 may be arranged in contact with one of the two groove portions sandwiching the mesa portion 60, and the other emitter region 12 may be arranged in contact with the other groove portion. The contact region 15 is arranged in a region sandwiched between the one emitter region 12 and the other emitter region 12. The base region 14 may be arranged on the upper surface of the mesa portion 60 so as to sandwich a region where the contact region 15 and the emitter region 12 are arranged in the Y-axis direction.

[0098] The emitter region 12 may not be provided in the mesa portion 61 of the diode portion 80. A base region 14 is provided on the upper surface of the mesa portion 61 in this example. The base region 14 may occupy more than half of the area of ​​the upper surface of the mesa portion 61. A contact region 15 may be arranged on the upper surface of the mesa portion 61. The contact region 15 of the mesa portion 61 may be provided at a position overlapping with the end of the contact hole 54 in the Y-axis direction. The base region 14 may be provided on the upper surface of the mesa portion 61 so as to sandwich the contact region 15 in the Y-axis direction.

[0099] The contact hole 54 provided in the transistor portion 70 and the contact hole 54 provided in the diode portion 80 may have the same length in the Y-axis direction or different lengths. In the transistor portion 70, the contact hole 54 is provided above each region of the contact region 15 and the emitter region 12. The contact hole 54 of this example may not be provided in the region corresponding to the base region 14 and the well region 11 of the mesa portion 60. In the diode portion 80, the contact hole 54 is provided above the contact region 15 and the base region 14. However, the contact hole 54 is not provided above the base region 14 sandwiched between the contact region 15 and the well region 11 in the mesa portion 61.

[0100] In the diode portion 80, an N+ type cathode region 82 is provided in a region in contact with the lower surface of the semiconductor substrate 10. In a region in contact with the lower surface of the semiconductor substrate 10, a collector region 22 is provided in a region where the cathode region 82 is not provided. In the Y-axis direction, the cathode region 82 is provided separately from the active-side dummy wiring 131. Between the cathode region 82 and the active-side dummy wiring 131, at least one of the base region 14 and the contact region 15 may be provided in a plan view. In this example, the distance between the cathode region 82 and the active-side dummy wiring 131 in the Y-axis direction is greater than the distance between the contact hole 54 and the active-side dummy wiring 131 in the Y-axis direction.

[0101] Figure 6 Yes means Figure 5 dd is a diagram of an example of a cross section in FIG. dd is an XZ plane passing through the emitter region 12. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in this cross section.

[0102] A P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in this cross section. In this cross section, an N+ type emitter region 12 and a P-type base region 14 are provided in order from the upper surface 21 of the semiconductor substrate 10 on the upper surface 21 side of the semiconductor substrate 10 in the transistor portion 70. An N+ type storage region may also be provided below the base region 14. In this cross section, a P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the diode portion 80.

[0103] In the transistor section 70 and the diode section 80, an N-type drift region 18 is provided below the base region 14. In the transistor section 70 and the diode section 80, an N+ type buffer region 20 is provided below the drift region 18.

[0104] The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 can function as a field stop layer that prevents a depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0105] In the transistor portion 70 , a P+ type collector region 22 is provided below the buffer region 20 . In the diode portion 80 , a cathode region 82 is provided below the buffer region 20 .

[0106] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each groove portion is provided to penetrate the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reach the drift region 18. In the region where at least any one of the emitter region 12 and the contact region 15 is provided, each groove portion also penetrates these regions and reaches the drift region 18. The structure in which the groove portion penetrates the doped region is not limited to the structure obtained by forming the doped region and then forming the groove portion. The structure in which the doped region is formed between the groove portions after the groove portion is formed is also included in the structure in which the groove portion penetrates the doped region.

[0107] The gate trench portion 40 includes a gate insulating film 42 and a gate conductive portion 44 provided on the upper surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate trench portion 40. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench portion 40. The gate conductive portion 44 is provided inside the gate trench portion 40 at a position closer to the inner side than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0108] The gate conductive portion 44 includes a region sandwiching a gate insulating film 42 and facing the base region 14. The gate groove portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface in contact with the gate groove in the base region 14.

[0109] The dummy groove portion 30 may also have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0110] Figure 7 : is a diagram showing another structural example of the emitting electrode 52. The emitting electrode 52 of this example has a bridge portion 53 connecting two partial electrodes to each other. The emitting electrode 52 of this example has a bridge portion 53 connecting the partial electrode 52-1 and the partial electrode 52-2 to each other and a bridge portion 53 connecting the partial electrode 52-1 and the partial electrode 52-3 to each other. The bridge portion 53 can be formed of the same material as the partial electrodes.

[0111] Each active-side dummy wiring 131 is divided into at least two partial wirings by the bridge portion 53. Figure 7 In the example of FIG. 1 , each active-side dummy wiring 131 is divided into a partial wiring 131 - 1 and a partial wiring 131 - 2. That is, the bridge portion 53 is provided between the partial wiring 131 - 1 and the partial wiring 131 - 2.

[0112] Figure 8 yes Figure 7 : This is an enlarged view of region E in FIG. Region E is a region near the bridge portion 53. Figure 8 , partial electrodes 52 - 1 , 52 - 2 , bridge 53 , active-side gate wiring 141 , active-side dummy wiring 131 , at least one crossing dummy wiring 132 , and each groove portion are shown, and other components are omitted. Figure 8 In FIG. 1 , the active-side gate wiring 141 and the intersecting dummy wiring 132 are all marked with oblique hatching. In addition, the partial electrodes 52 - 1 , 52 - 2 , the bridge 53 , and the active-side dummy wiring 131 are marked with oblique hatching only at the end portions.

[0113] As described above, the active-side dummy wiring 131 is divided into the partial wiring 131-1 and the partial wiring 131-2 by the bridge portion 53. The bridge portion 53 passes between the partial wiring 131-1 and the partial wiring 131-2 to connect the partial electrode 52-1 and the partial electrode 52-2.

[0114] The cross dummy wiring 132 is arranged to cross the bridge portion 53, and connects the partial wiring 131-1 and the partial wiring 131-2 to each other. The cross dummy wiring 132 of this example is arranged to cross under the bridge portion 53 from the partial wiring 131-1 to the partial wiring 131-2 in the X-axis direction. The cross dummy wiring 132 can be a wiring of a semiconductor material such as polysilicon doped with impurities. The cross dummy wiring 132 is arranged between the semiconductor substrate 10 and the active side dummy wiring 131 and the bridge portion 53.

[0115] The intersecting dummy wiring 132 is insulated from the semiconductor substrate 10, the active-side dummy wiring 131, and the bridge 53 by the interlayer insulating film. The intersecting dummy wiring 132 is connected to the active-side dummy wiring 131 at a position overlapping with the active-side dummy wiring 131 via a contact hole provided in the interlayer insulating film.

[0116] Providing the bridge 53 can reduce the potential variation in the emitter electrode 52. Providing the cross dummy wiring 132 can connect the active-side dummy wiring 131 divided by the bridge 53. Thus, the potential for screening can be transmitted to the inside of the active portion 120.

[0117] It should be noted that the active side gate wiring 141 is not divided by the bridge portion 53. The active side gate wiring 141 of this example is provided to intersect the bridge portion 53. That is, the active side gate wiring 141 crosses below the bridge portion 53 in the X-axis direction. Thus, the gate potential can be transmitted to the inside of the active portion 120.

[0118] Note that, by using the active-side gate wiring 141 as a semiconductor wiring, the bridge portion 53 can easily intersect the active-side gate wiring 141. Therefore, the gate potential can be transmitted through the single active-side gate wiring 141, and attenuation of the gate potential can be suppressed.

[0119] The intersecting dummy wiring 132 can be connected to the dummy groove portion 30. Thus, even in the region where the bridge portion 53 is provided, a voltage for screening can be applied to the dummy groove portion 30. The intersecting dummy wiring 132 can be arranged to sandwich the active-side gate wiring 141 in the Y-axis direction. Thus, each of the dummy groove portion 30 on the partial electrode 52-1 side and the dummy groove portion 30 on the partial electrode 52-2 side can be easily connected to the intersecting dummy wiring 132.

[0120] The dummy trench portion 30 may be disposed below the bridge portion 53. The gate trench portion 40 may also be disposed below the bridge portion 53. In this example, the dummy trench portion 30 is disposed below the bridge portion 53, but the gate trench portion 40 is not disposed.

[0121] The bridge portion 53 may be provided in the diode portion 80. In this case, the intersecting dummy wiring 132 is connected to the dummy trench portion 30 of the diode portion 80. The dummy trench portion 30 may have a front end portion at a position overlapping with the intersecting dummy wiring 132.

[0122] The dummy groove portion 30 of the transistor portion 70 is connected to the active-side dummy wiring 131 (in this example, the partial wiring 131-1 and the partial wiring 131-2). With such a structure, each dummy groove portion 30 can be easily connected to the dummy wiring. In addition, since the active-side gate wiring 141 is not divided, each gate groove portion 40 can be easily connected to the active-side gate wiring 141.

[0123] Fig. 9 Yes means Figure 8FIG. 1 is a diagram of an example of an hh cross section in FIG. The hh cross section is a YZ cross section passing through two intersecting dummy wirings 132 and an active side gate wiring 141. The two intersecting dummy wirings 132 and the active side gate wiring 141 are arranged between the bridge portion 53 and the semiconductor substrate 10. The two intersecting dummy wirings 132 and the active side gate wiring 141 can be arranged at the same height position. The two intersecting dummy wirings 132 and the active side gate wiring 141 are insulated from the bridge portion 53 by the interlayer insulating film 38. In addition, the two intersecting dummy wirings 132 and the active side gate wiring 141 are also insulated from the semiconductor substrate 10 by the interlayer insulating film 38. However, the intersecting dummy wiring 132 is connected to the dummy conductive portion 34 of the dummy groove portion 30 through a contact hole 56 provided in the interlayer insulating film 38.

[0124] Fig.10 Yes means Figure 8 ii is an example of a cross section in FIG. The cross section ii is an XZ cross section including the partial wiring 131-1, the partial wiring 131-2, and the bridge 53. The partial wiring 131-1, the partial wiring 131-2, and the bridge 53 are arranged above the interlayer insulating film 38. The partial wirings 131-1, 131-2, and the bridge 53 can be arranged at the same height position.

[0125] The crossing dummy wiring 132 is provided between the partial wiring 131-1, the partial wiring 131-2, the bridge portion 53, and the semiconductor substrate 10. The crossing dummy wiring 132 is insulated from the partial wiring 131-1, the partial wiring 131-2, and the bridge portion 53 by the interlayer insulating film 38. However, the crossing dummy wiring 132 is connected to the partial wiring 131-1 and the partial wiring 131-2 through the contact hole 57 provided in the interlayer insulating film 38.

[0126] The crossing dummy wiring 132 extends from the partial wiring 131 - 1 to the partial wiring 131 - 2 in the X-axis direction through the bottom of the bridge portion 53 , thereby connecting the partial wiring 131 - 1 to the partial wiring 131 - 2 .

[0127] Fig.11 yes Figure 7 1 is an enlarged view of region F in FIG. Region F is a region near a portion 150 where the peripheral gate wiring 140 and the active-side gate wiring 141 are connected. Fig.11 In FIG. 1 , only the ends of the peripheral gate wiring 140 , the peripheral dummy wiring 130 , the active-side dummy wiring 131 , and the emitter electrode 52 are hatched obliquely. In addition, the active-side gate wiring 141 is hatched obliquely throughout.

[0128] The peripheral gate wiring 140 and the peripheral dummy wiring 130 are arranged so as not to overlap when viewed from above. The peripheral gate wiring 140 of this example is arranged at a position closer to the outside than the peripheral dummy wiring 130. The outside refers to the side away from the active part 120. The active side dummy wiring 131 is connected to the peripheral dummy wiring 130. The active side dummy wiring 131 and the peripheral dummy wiring 130 of this example are both metal wirings.

[0129] The active-side gate wiring 141 is provided from below the active-side dummy wiring 131 across the peripheral dummy wiring 130 to below the peripheral gate wiring 140. The active-side gate wiring 141 is connected to the peripheral gate wiring 140 at a position overlapping with the peripheral gate wiring 140. The active-side gate wiring 141 of this example has a portion 150 not covered by the dummy wiring between the peripheral dummy wiring 130 and the peripheral gate wiring 140.

[0130] The gate wiring may include a second peripheral wiring 144 disposed along the peripheral gate wiring 140 below the peripheral gate wiring 140. The second peripheral wiring 144 may be formed of the same material as the active-side gate wiring 141 and at the same height as the active-side gate wiring 141. The second peripheral wiring 144 is connected to the active-side gate wiring 141. The second peripheral wiring 144 and the peripheral gate wiring 140 are connected via a contact hole disposed in the interlayer insulating film. Fig.11 In FIG. 1 , the second peripheral wiring 144 is entirely marked with oblique hatching.

[0131] Fig.12 yes Figure 7 1 is an enlarged view of the region G in FIG. As described above, the active side gate wiring 141 and the active side dummy wiring 131 are divided by the temperature sensing portion 117. Therefore, the active side gate wiring 141 and the active side dummy wiring 131 terminate in the vicinity of the temperature sensing portion 117. The active side dummy wiring 131 can be provided at a position closer to the temperature sensing portion 117 than the active side gate wiring 141. That is, the distance between the active side dummy wiring 131 and the temperature sensing portion 117 can be smaller than the distance between the active side gate wiring 141 and the temperature sensing portion 117. Thus, the active side gate wiring 141 can be covered with the active side dummy wiring 131.

[0132] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is also clear to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, it is known that the various changes or improvements made in this way can also be included in the technical scope of the present invention.

[0133] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the apparatus, system, program and method shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated "before...", "before", etc., and the result of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications and drawings is described using "first", "next", etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: Semiconductor substrates; an emitting electrode having at least two partial electrodes arranged at intervals when looking down at the semiconductor substrate; an active-side gate wiring arranged to be sandwiched by the two partial electrodes; as well as an active-side dummy wiring arranged to be sandwiched between the two partial electrodes, The semiconductor substrate has: a gate trench portion connected to the active-side gate wiring and having a long side in the first direction in the plan view; as well as a dummy groove portion connected to the active-side dummy wiring and having a long side in the first direction, One of the active-side gate wiring and the active-side dummy wiring is entirely covered by the other of the active-side gate wiring and the active-side dummy wiring in the first direction, The active-side gate wiring is a wiring of a semiconductor material, and the active-side dummy wiring is a wiring of a metal material. The emitting electrode has a bridge portion connecting the two partial electrodes to each other, The active-side dummy wiring is divided into at least two partial wirings by the bridge portion, The semiconductor device further includes a crossing dummy wiring made of a semiconductor material, the crossing dummy wiring being provided to cross the bridge portion and connecting the two partial wirings to each other.

2. The semiconductor device according to claim 1, wherein: The active-side gate wiring is entirely covered by the active-side dummy wiring arranged above the active-side gate wiring in the first direction.

3. The semiconductor device according to claim 2, wherein: The active-side dummy wiring is connected to the dummy trench portion at a portion that does not overlap with the active-side gate wiring.

4. The semiconductor device according to claim 1, wherein: The intersecting dummy wiring is connected to the dummy trench portion.

5. The semiconductor device according to claim 4, wherein: The semiconductor substrate includes a transistor portion and a diode portion, the transistor portion is provided with the gate trench portion and the dummy trench portion, and the diode portion is provided with the dummy trench portion. The intersecting dummy wiring is connected to the dummy trench portion of the diode portion.

6. The semiconductor device according to claim 5, wherein: The dummy trench portion of the transistor portion is connected to the active-side dummy wiring.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that The active-side gate wiring is provided to intersect the bridge portion.

8. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device further includes an interlayer insulating film, the interlayer insulating film being provided between the semiconductor substrate and the emitter electrode and having a contact hole connecting the emitter electrode to the semiconductor substrate. The active-side dummy wiring is provided in a range that does not overlap with the contact hole when the semiconductor substrate is viewed in plan.

9. The semiconductor device according to claim 7, wherein: The semiconductor device further includes an interlayer insulating film, the interlayer insulating film being provided between the semiconductor substrate and the emitter electrode and having a contact hole connecting the emitter electrode to the semiconductor substrate. The active-side dummy wiring is provided in a range that does not overlap with the contact hole when the semiconductor substrate is viewed in plan.

10. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor device further comprises: a peripheral gate wiring arranged between the emitter electrode and an edge of the semiconductor substrate in the plan view and connected to the active-side gate wiring; and a peripheral dummy wiring, which is arranged between the emitter electrode and the edge of the semiconductor substrate in the plan view and is connected to the active-side dummy wiring, The peripheral dummy wiring is arranged so as not to overlap with the peripheral gate wiring when the semiconductor substrate is viewed in a plan view.

11. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises: a peripheral gate wiring arranged between the emitter electrode and an edge of the semiconductor substrate in the plan view and connected to the active-side gate wiring; and a peripheral dummy wiring, which is arranged between the emitter electrode and the edge of the semiconductor substrate in the plan view and is connected to the active-side dummy wiring, The peripheral dummy wiring is arranged so as not to overlap with the peripheral gate wiring when the semiconductor substrate is viewed in a plan view.

12. The semiconductor device according to claim 8, wherein: The semiconductor device further comprises: a peripheral gate wiring arranged between the emitter electrode and an edge of the semiconductor substrate in the plan view and connected to the active-side gate wiring; and a peripheral dummy wiring, which is arranged between the emitter electrode and the edge of the semiconductor substrate in the plan view and is connected to the active-side dummy wiring, The peripheral dummy wiring is arranged so as not to overlap with the peripheral gate wiring when the semiconductor substrate is viewed in a plan view.

13. The semiconductor device according to claim 9, wherein: The semiconductor device further comprises: a peripheral gate wiring arranged between the emitter electrode and an edge of the semiconductor substrate in the plan view and connected to the active-side gate wiring; and a peripheral dummy wiring, which is arranged between the emitter electrode and the edge of the semiconductor substrate in the plan view and is connected to the active-side dummy wiring, The peripheral dummy wiring is arranged so as not to overlap with the peripheral gate wiring when the semiconductor substrate is viewed in a plan view.

14. The semiconductor device according to claim 10, wherein: The semiconductor device further includes a screening pad connected to the peripheral dummy wiring.

15. The semiconductor device according to claim 11, wherein: The semiconductor device further includes a screening pad connected to the peripheral dummy wiring.

16. The semiconductor device according to claim 12, wherein: The semiconductor device further includes a screening pad connected to the peripheral dummy wiring.

17. The semiconductor device according to claim 13, wherein: The semiconductor device further includes a screening pad connected to the peripheral dummy wiring.

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