Vertical field effect transistor device and semiconductor cell structure

Abstract

A vertical field effect transistor (VFET) device and semiconductor cell structure are provided, the VFET device including a fin structure protruding from a substrate and having an H-shape in a plan view; a gate including a fin sidewall portion formed on a sidewall of the fin structure and a field gate portion extending from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a location inside the lower half of the fin structure; a bottom epitaxial layer including a bottom source / drain (S / D) region and formed underneath the fin structure; a power supply contact landing on the bottom epitaxial layer and configured to receive a power supply signal; a top S / D region formed on top of the fin structure; and a top S / D contact landing on the top S / D region.

Description

Technical Field

[0001] The apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to contacts or contact structures (hereinafter referred to as "contacts") of vertical field-effect transistors (VFETs), and more specifically, to self-aligned contact structures and layouts of bidirectional VFETs. Background Technology

[0002] In VFETs, unlike existing planar FETs or finFETs, current flows through channels formed at fin structures that protrude vertically from the substrate. To provide an enhanced current path between the bottom source / drain (S / D) region and the top S / D region by increasing the effective channel width, H-shaped fin structures have been introduced for VFETs in a planar configuration, such as... Figure 1 As shown.

[0003] Figure 1 This diagram shows a layout of a semiconductor cell structure in which VFET devices are arranged, according to the prior art.

[0004] Reference Figure 1 A VFET device 100 is disposed in a semiconductor cell 10, the VFET device 100 including a fin structure 102 formed on a substrate 101. The fin structure 102 has an H-shape in the plan view and is used to surround the gate 103 of the VFET device 100. Although in the plan view Figure 1 Not shown in the figures, but the fin structure 102 protrudes vertically from the substrate 101. The VFET device 100 also includes a top source / drain (S / D) region 104 formed on the fin structure 102 and a bottom epitaxial layer 105 formed below the fin structure 102, including a bottom S / D region (not shown). For the sake of brevity in the figures, Figure 1 The top S / D region 104 is shown to overlap with the fin structure 102 in the plan view, so the two elements are not distinguishable from each other.

[0005] VFET device 100 further includes: a top S / D contact CA, which lands on the top S / D region 104 above the horizontal portion of the H-shaped fin structure 102; a power contact CR, which lands on the bottom epitaxial layer 105 including the bottom S / D region; and a gate contact CB, which lands on the gate 103 to receive and transmit the gate input signal to the gate 103.

[0006] However, from Figure 1Note that although the gate 103 is divided into a fin sidewall portion 103FS formed on the fin structure 102 and a field gate portion 103FG extending from the fin sidewall portion 103FS, the gate contact CB rests on the field gate portion 103FG outside the H-shaped fin structure 102, and the power contact CR rests on the bottom epitaxial layer 105 outside the H-shaped fin structure 102. That is, both the gate contact CB and the power contact CR are disposed outside the H-shaped fin structure 102. Therefore, as... Figure 1 As shown, there is an area penalty in the semiconductor cell 10 including the VFET device 100 because, in the plan view, the semiconductor cell 10 must provide space for the gate contact CB and space for the power contact CR outside the region of the H-shaped fin structure 102.

[0007] Therefore, there is a need to further reduce the size of existing VFET devices and semiconductor cells including such VFET devices by setting gate contacts and power contacts in different regions. Summary of the Invention

[0008] Various embodiments of the present invention provide a structure for a vertical field-effect transistor (VFET) that provides area gain by arranging gate contacts and / or power contacts inside a fin structure having multiple linear portions connected to each other in a planar view, such as an H-shaped fin structure.

[0009] According to an exemplary embodiment, a VFET device is provided, which may include: a fin structure protruding from a substrate and having an H-shape in a plan view; a gate including a fin sidewall portion formed on a sidewall of the fin structure and a field gate portion extending from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact located inside the lower half of the fin structure and resting on the field gate portion; a bottom epitaxial layer including a bottom source / drain (S / D) region and formed below the fin structure; a power contact resting on the bottom epitaxial layer and configured to receive a power signal; a top S / D region formed above the fin structure; and a top S / D contact resting on the top S / D region.

[0010] According to an exemplary embodiment, a VFET device is provided, which may include: a fin structure protruding from a substrate and having a plurality of linear portions connected to each other in a planar view; a gate including fin sidewall portions formed on the sidewalls of the fin structure and field gate portions connected to the fin sidewall portions and filling the space between two or more of the plurality of linear portions; a gate contact resting on the gate; a bottom epitaxial layer including a bottom S / D region and formed below the fin structure; a power contact resting on the bottom epitaxial layer and configured to receive a power signal; a top S / D region formed above the fin structure; and a top S / D contact resting on the top S / D region, wherein at least one of the gate contact and the power contact is disposed within a virtual two-dimensional shape formed by connecting the outer ends of the plurality of linear portions of the fin structure.

[0011] According to an exemplary embodiment, a semiconductor cell structure is provided, which may include a first VFET device and a second VFET device arranged in the cell height direction. The first VFET device may include: a first fin structure protruding from a substrate and having an H-shape in a plan view; a first gate including a first fin sidewall portion formed on a sidewall of the lower half of the first fin structure and a first field gate portion extending from the first fin sidewall portion and filling a space inside the lower half of the first fin structure; a first bottom epitaxial layer including a bottom source / drain (S / D) region and formed below the first fin structure; a first power contact resting on the first bottom epitaxial layer; a first top S / D region formed above the first fin structure; and a first top S / D contact resting on the first top S / D region. The second VFET device may include: a second fin structure protruding from a substrate and having an H-shape in a plan view; a second gate including a second fin sidewall portion formed on a sidewall of the upper half of the second fin structure and a second field gate portion extending from the second fin sidewall portion and filling a space within the upper half of the second fin structure; a second bottom epitaxial layer including a bottom source / drain (S / D) region and formed below the second fin structure; a second power contact resting on the second bottom epitaxial layer; a second top S / D region formed above the second fin structure; and a second top S / D contact resting on the second top S / D region. Here, the first field gate portion and the second field gate portion are merged to form a merged field gate portion, wherein the first VFET device and the second VFET device share a gate contact resting on the merged field gate portion, and wherein at least one of the first power contact and the second power contact rests on at least one of the first bottom epitaxial layer and the second bottom epitaxial layer at a location within at least one of the upper half of the first fin structure and the lower half of the second fin structure, respectively. Attached Figure Description

[0012] The above and other aspects of the present invention will become more apparent to those skilled in the art from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0013] Figure 1 A layout diagram of a semiconductor cell structure in which VFET devices are arranged, according to the prior art;

[0014] Figure 2 A layout diagram of a semiconductor cell structure in which VFET devices are arranged according to one embodiment is shown;

[0015] Figure 3 A layout diagram of a semiconductor cell structure in which two VFET devices are arranged according to one embodiment is shown;

[0016] Figure 4 A schematic diagram of an inverter formed by a PMOS VFET device and an NMOS VFET device according to one embodiment is shown; and

[0017] Figure 5 A layout diagram of a semiconductor cell structure in which two VFET devices are arranged, according to another embodiment, is shown. Detailed Implementation

[0018] Various embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. These embodiments are exemplary and can be implemented in many different forms, and should not be construed as limiting the inventive concept. Rather, these embodiments are provided only to make this disclosure thorough and complete, and to fully convey the inventive concept to those skilled in the art. In the drawings, the dimensions and relative dimensions of various layers and regions may have been exaggerated for clarity; therefore, the drawings are not necessarily to scale, and some features may be exaggerated to show details of particular parts or elements. Therefore, the specific structural and functional details disclosed herein are not to be construed as limiting, but merely as a representative basis for teaching those skilled in the art to use the methods and structures of the embodiments in various ways.

[0019] The embodiments provided herein are not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the inventive concept. For example, even if a matter described in a particular embodiment is not described in other embodiments, such matter may be understood to be related to or in combination with different embodiments, unless otherwise mentioned in its description.

[0020] For the purposes of the description below, the terms “upper,” “lower,” “top,” “bottom,” “left,” and “right,” and their derivatives, may be associated with the disclosed structure based on context, as they are oriented in the accompanying drawings. The same reference numerals in different drawings may refer to the same structural component or element thereof.

[0021] It will be understood that when an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, it can be directly on, directly connected to, or directly attached to that other element or layer, or there can be an intervening element or layer. Conversely, when an element is referred to as being "directly on," "directly connected to," or "directly attached to" another element or layer, there is no intervening element or layer.

[0022] As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Expressions such as "at least one of..." modify the entire list of elements, not the individual elements in the list, when following a list of elements. Thus, for example, both "at least one of A, B, or C" and "A, B, and / or C" mean A, B, C, or any combination thereof. Expressions such as "at least one of..." modify the entire list of elements, not the individual elements in the list, when following a list of elements.

[0023] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. It will also be understood that terms belonging to such definitions as in general dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant art and shall not be interpreted as having idealized or overly formalized meanings, unless expressly defined herein.

[0025] Figure 2 A layout diagram of a semiconductor cell structure in which VFET devices are arranged according to one embodiment is shown.

[0026] Reference Figure 2A VFET device 200, including a fin structure 202 formed on a substrate 201, is disposed in a semiconductor cell 20. The fin structure 202 may be patterned on the substrate 201, which is a wafer formed of silicon (Si), germanium (Ge), or a combination thereof, but is not limited thereto.

[0027] Although not included as a floor plan Figure 2 As shown, however, the fin structure 202 protrudes from the substrate 201 in the vertical direction. Like Figure 1 Similar to the fin structure 102 of the VFET device 100 shown, the H-shaped fin structure 202 of the VFET device 200 in the plan view is used to surround the gate 203 of the VFET device 200. The gate 203 may include multiple layers, including a dielectric layer and a conductor layer (not shown) formed of metal or metal compound.

[0028] In addition, like Figure 1 Like the VFET device 100, the VFET device 200 includes a top S / D region 204 formed on the fin structure 202 and a bottom epitaxial layer 205 formed below the fin structure 202, containing a bottom S / D region (not shown). The top S / D region 204 and the bottom S / D region can be formed by doping corresponding epitaxial layers formed of Si, Ge, SiGe, etc. (but not limited thereto). For example, the bottom S / D region can be formed by doping the bottom epitaxial layer 205 with one or more dopants (such as boron (B) for p-channel VFETs and phosphorus (P) for n-channel VFETs, but not limited thereto).

[0029] For the sake of brevity in the accompanying diagram, Figure 2 The top S / D region 204 is also shown to overlap with the fin structure 202 in the plan view, thus the two elements are not distinguishable from each other. However, in the plan view, the area of ​​the fin structure 202 is not necessarily the same as the area of ​​the top S / D region 204. Therefore, for design purposes, the area of ​​the top S / D region 204 in the plan view can be larger or smaller than the area of ​​the fin structure 202.

[0030] VFET device 200 also includes: a top S / D contact CA, resting on the top S / D region 204; a power contact CR, resting on the bottom epitaxial layer 205 including the bottom S / D region; and a gate contact CB, resting on the gate 203 to receive and transmit the gate input signal to the gate 203. These contacts CA, CR, and CB may be formed of one or more metals (such as tungsten) or metal compounds, and are not limited thereto.

[0031] Figure 2The gate 203 is shown to be divided into a fin sidewall portion 203FS formed on the sidewall 202S of the fin structure 202 and a field gate portion 203FG extending from the fin sidewall portion 203FS to at least fill the space in the lower half of the H-shaped fin structure 202 where the fin sidewall portion 203FS is not formed.

[0032] The fin sidewall portion 203FS of the gate 203 can be formed on all the sidewalls 202S of the fin structure 202. The gate contact CB rests on the field gate portion 203FG to receive the gate input signal. With this structure in which the gate contact CB rests on the field gate portion 203FG at a position inside the lower half of the H-shaped fin structure 202, area gain can be provided to the VFET device 200 and the semiconductor cell 20 including the VFET device 200.

[0033] Furthermore, the power contact CR rests on the bottom epitaxial layer 205 within the upper half of the H-shaped fin structure 202, thereby providing additional area gain for the VFET device 200 and the semiconductor cell 20 including the VFET device 200. Here, no portion of the gate 203 is formed at the location where the power contact CR rests in the semiconductor cell 20.

[0034] according to Figure 2 The location where the top S / D contact CA falls is restricted to the portion of the top S / D region that overlaps with a portion of the H-shaped fin structure 202 (where the horizontal portion of the H-shaped fin structure 202 connects with its vertical portion).

[0035] According to one embodiment, the field gate portion 203FG of the gate 203 can be formed by a gate pattern mask, while the fin sidewall portion 203FS of the gate 203 can be formed by a top-self-alignment method. Furthermore, according to one embodiment, the power contact CR and the gate contact CB can be formed inside the upper and lower halves of the H-shaped fin structure 202, respectively, by a top-self-alignment method.

[0036] Figure 3 This diagram illustrates a semiconductor cell structure according to one embodiment, in which two VFET devices are arranged. The materials used for the various elements forming the two VFET devices described below can be compatible with those used for… Figure 2 The materials of the VFET device 200 are the same or substantially similar, so a description of them is omitted here.

[0037] Reference Figure 3A semiconductor cell structure includes: an upper cell 30, in which a p-channel metal-oxide-semiconductor (PMOS) VFET device 300 is disposed; and a lower cell 40, in which an n-channel metal-oxide-semiconductor (NMOS) VFET device 400 is disposed. The PMOS VFET device 300 and NMOS VFET device 400, formed on the same substrate 301, are arranged in the cell height direction to form an inverter, as shown in the schematic diagram. Figure 4 As shown in [the image]. Figure 4 In this circuit, the gates of the PMOS VFET and the NMOS VFET are connected to each other to form the input terminal In, the source of the PMOS VFET is connected to the power supply Vdd, the source of the NMOS VFET is connected to ground Gnd, and the drains of the PMOS VFET and the NMOS VFET are connected to each other to form the output terminal Out.

[0038] The PMOS VFET device 300 includes a fin structure 302 formed on a substrate 301 and having an H-shape in a plan view. Although not shown in the plan view... Figure 3 As shown, however, the fin structure 302 protrudes from the substrate 301 in the vertical direction, just like the fin structure 202 of the VFET device 200 in the previous embodiment.

[0039] In addition, like Figure 2 Similar to the VFET device 200, the PMOS VFET device 300 includes a top S / D region 304 formed on the fin structure 302 and a bottom epitaxial layer 305 forming below the fin structure 302, containing a bottom S / D region (not shown). Furthermore, for the sake of brevity in the figures, Figure 3 As shown in the plan view, the top S / D region 304 overlaps with the fin structure 302, therefore, the two elements are not distinguishable from each other. However, in the plan view, the area of ​​the fin structure 302 is not necessarily the same as the area of ​​the top S / D region 304. Therefore, for design purposes, the area of ​​the top S / D region in the plan view can be larger or smaller than the area of ​​the fin structure 302.

[0040] The PMOS VFET device 300 also includes a top S / D contact CA1 resting on the top S / D region 304 and a power contact CR1 resting on the bottom epitaxial layer 305 including the bottom S / D region. The power contact CR1 is disposed inside the upper half of the H-shaped fin structure 302 in the plan view, thereby providing area gain for the PMOS VFET device 300 and the upper cell 30 including the PMOS VFET device 300.

[0041] However, the PMOS VFET device 300 has a gate 303, which has a relationship with... Figure 2The gate 203 of the VFET device 200 has a different structure. First, although like Figure 2 Similar to the gate 203 of the PMOS VFET device 200, the gate 303 is divided into a fin sidewall portion 303FS and a field gate portion 303FG, but the fin sidewall portion 303FS is formed only on the lower half of the fin structure 302. Next, the field gate portion 303FG extends from the fin sidewall portion 303FS to at least fill the space inside the lower half of the H-shaped fin structure 302. Furthermore, this field gate portion 303FG is connected to or merged with the field gate portion 403FG of the gate 403 of the NMOS VFET device 400, such that the common gate contact CB resting on the field gate portion 303FG can be shared by both the PMOS VFET device 300 and the NMOS VFET device 400. This gate structure can be considered as a gate shared by both the PMOS VFET device 300 and the NMOS VFET device 400.

[0042] The NMOS VFET device 400 has the same structure as the PMOS VFET device 300, except that the NMOS VFET device 400 is symmetrically arranged in the lower cell 40 with respect to the boundary line between the upper cell 30 and the lower cell 40. Therefore, in the plan view, the power contact CR2 of the NMOS VFET device 400 is located inside the lower half of the H-shaped fin structure 402, thereby also providing area gain for the NMOS VFET device 400 and the lower cell 40 including the NMOS VFET device 400. However, the top S / D region 404, the bottom epitaxial layer 405 including the bottom S / D region (not shown), and the top S / D contact CA2 resting on the top S / D region 404 of the NMOS VFET device 400 have the same structure as the corresponding element of the PMOS VFET device 300.

[0043] The gate 403 of the NMOS VFET device 400 is also divided into a fin sidewall portion 403FS and a field gate portion 403FG. Symmetrically relative to the PMOS VFET device 300, the fin sidewall portion 403FS is formed only on the upper half of the fin structure 402, and the field gate portion 403FG extends from the fin sidewall portion 403FS to at least fill the space inside the upper half of the H-shaped fin structure 402. Furthermore, as described above, the field gate portion 403FG is connected to or merged with the field gate portion 303FG of the gate 303 of the PMOS VFET device 300, and the NMOS VFET device 400 and the PMOS VFET device 300 may have only one gate contact (i.e., a common gate contact CB), according to... Figure 4The inverter schematic shown inputs the gate input signal to both gate 303 and gate 403. This gate structure provides additional area gain to the inverter formed by the PMOS VFET device 300 and the NMOS VFET device 400, as well as to the upper cell 30 and the lower cell 40.

[0044] According to this embodiment, the common gate contact CB is positioned between the lower half of the H-shaped fin structure 302 and the upper half of the H-shaped fin structure 402, resting on the merged field gate portion 303FG and field gate portion 403FG. However, the inventive concept is not limited thereto. Utilizing the area gain discussed above, the area gain can be modified by increasing the vertical length of at least one of the H-shaped fin structure 302 and H-shaped fin structure 402. Figure 3 In the semiconductor cell structure shown, the common gate contact CB can be located inside the lower half of the H-shaped fin structure 302 or the upper half of the H-shaped fin structure 402, or overlap with the boundary line between the upper cell 30 and the lower cell 40, as shown. Figure 5 As shown.

[0045] Figure 5 A layout diagram of a semiconductor cell structure in which two VFET devices are arranged, according to another embodiment, is shown.

[0046] Reference Figure 5 The semiconductor unit structure shown therein is similar to Figure 3 The same as shown constitutes Figure 4 The inverter shown, except for the one with Figure 3 Compared to the H-shaped fin structures 302 and 402 in the upper unit 50 and lower unit 60, the two H-shaped fin structures 502 and 602 have longer vertical portions. Therefore, the common gate contact CB is positioned between the lower half of the H-shaped fin structure 502 and the upper half of the H-shaped fin structure 602 on the merged field gate portions 503FG and 603FG. Figure 5 Other components of the semiconductor unit structure shown are Figure 3 The components shown are the same; therefore, the structures of the substrate 501, gates 503 and 603, fin sidewall portions 503FS and 603FS, bottom epitaxial layers 505 and 605 including their respective bottom S / D regions, and top S / D regions 504 and 604 of the PMOS VFET device 500 and NMOS VFET device 600 can be the same as those shown. Figure 3 The corresponding structures shown are the same or substantially similar.

[0047] Note that, as Figure 5 The semiconductor cell structure with elongated H-shaped fins shown can be considered to further improve the performance characteristics of VFET devices included in the semiconductor cell structure, and such as Figure 3 The semiconductor cell structure shown, with its non-elongated H-shaped fin structure, can be considered for the realization of high-density VFET devices.

[0048] Therefore, according to one embodiment, Figure 3 The semiconductor unit structure shown and Figure 5 The semiconductor cell structure shown can be formed on the same wafer to realize both high-density VFET devices and high-performance VFET devices.

[0049] In the above embodiments, for the sake of brevity, the additional components constituting each VFET device have been omitted. For example, for the sake of brevity, the bottom spacer and top spacer that separate each gate from the bottom S / D region and the top S / D region, respectively, have not been described.

[0050] According to the above embodiments, the gate contact CB and the power supply contact CR are in Figure 2 The gate contact CB is located in the space inside the H-shaped fin structure. Figure 3 and Figure 5 The middle part is located at the boundary between the upper unit 30 (or 50) and the lower unit 40 (or 60), with power contact CR1 or CR2 at... Figure 3 and Figure 5 The space located inside the H-shaped fin structure. However, the inventive concept is not limited thereto. According to one embodiment, the gate contact CB, power contact CR, CR1 and / or CR2 located in the aforementioned space may also overlap with a portion of the corresponding fin structure.

[0051] according to Figure 2 , Figure 3 and Figure 5 The above embodiments describe the inventive concept based on an H-shaped fin structure. However, according to embodiments, the inventive concept is applied not only to the H-shape but also to fin structures having multiple interconnected linear (or strip-shaped) portions (hereinafter referred to as "linear portions"), such as shapes having the characters E, X, and +. Therefore, when a VFET device has a fin structure having said linear portions, gate contacts and / or power contacts can be disposed within a virtual two-dimensional shape formed by connecting the outer ends of the linear portions of the fin structure to provide area gain to the VFET device and the cells in which the VFET device is disposed.

[0052] The foregoing description is of exemplary implementation and should not be construed as limiting it. Although some exemplary implementations have been described, those skilled in the art will readily understand that many modifications can be made to the above implementations without substantially departing from the inventive concept.

Claims

1. A vertical field effect transistor device, comprising: a fin structure protruding from a substrate and having an H-shape in plan view; a gate, comprising: a fin sidewall portion formed on sidewalls of the fin structure; and a field gate portion extending from the fin sidewall portion and filling a space inside a lower half of the fin structure; a gate contact landing on the field gate portion at a location inside the lower half of the fin structure; a bottom epitaxial layer comprising a bottom source / drain region and formed underneath the fin structure; a power supply contact landing on the bottom epitaxial layer and configured to receive a power supply signal; a top source / drain region formed above the fin structure; and a top source / drain contact landing on the top source / drain region.

2. The vertical field effect transistor device of claim 1, wherein the power supply contact lands on the bottom epitaxial layer at a location inside an upper half of the fin structure.

3. The vertical field effect transistor device of claim 2, wherein the fin sidewall portion of the gate is formed by top-down self-alignment, and the field gate portion of the gate is formed by a gate pattern mask, and wherein the gate contact and the power supply contact are formed by top-down self-alignment.

4. The vertical field effect transistor device of claim 2, wherein the field gate portion of the gate is not formed inside the upper half of the fin structure.

5. The vertical field effect transistor device of claim 2, wherein the top source / drain contact lands on the top source / drain region at a location overlapping a portion of the fin structure at which one vertical portion of the fin structure connects to a horizontal portion thereof.

6. The vertical field effect transistor device of claim 2, wherein at least one of the gate contact and the power supply contact overlaps a portion of the fin structure.

7. The vertical field effect transistor device of claim 1, wherein the fin sidewall portion of the gate is formed on all of the sidewalls of the fin structure.

8. The vertical field effect transistor device of claim 1, wherein, in the plan view, the gate surrounds the fin structure.

9. A vertical field effect transistor device, comprising: a fin structure protruding from a substrate and having multiple linear portions connected to each other in plan view; a gate, comprising: a fin sidewall portion formed on sidewalls of the fin structure; and a field gate portion connected to the fin sidewall portion and filling a space between two or more of the multiple linear portions; a gate contact landing on the gate; a bottom epitaxial layer comprising a bottom source / drain region and formed underneath the fin structure; a power supply contact landing on the bottom epitaxial layer and configured to receive a power supply signal; a top source / drain region formed above the fin structure; and a top source / drain contact landing on the top source / drain region, wherein at least one of the gate contact and the power contact is disposed within a virtual two-dimensional shape formed by connecting outer ends of the plurality of linear portions of the fin structure.

10. The vertical field effect transistor device of claim 9, wherein the gate contact lands on the field gate portion at a location between the two or more of the plurality of linear portions.

11. The vertical field effect transistor device of claim 10, wherein the power contact lands on the bottom epitaxial layer at a location within two or more of the plurality of linear portions in which the field gate portion is not formed.

12. The vertical field effect transistor device of claim 9, wherein the field gate portion is not formed outside of the virtual two-dimensional shape.

13. A semiconductor cell structure comprising a first vertical field effect transistor device and a second vertical field effect transistor device arranged in a cell height direction, wherein the first vertical field effect transistor device comprises: a first fin structure protruding from a substrate and having an H-shape in a plan view; a first gate comprising a first fin sidewall portion formed on sidewalls of a lower half of the first fin structure and a first field gate portion extending from the first fin sidewall portion and filling a space inside the lower half of the first fin structure; a first bottom epitaxial layer comprising a bottom source / drain region and formed underneath the first fin structure; a first power contact landing on the first bottom epitaxial layer; a first top source / drain region formed above the first fin structure; and a first top source / drain contact landing on the first top source / drain region, wherein the second vertical field effect transistor device comprises: a second fin structure protruding from the substrate and having an H-shape in the plan view; a second gate comprising a second fin sidewall portion formed on sidewalls of an upper half of the second fin structure and a second field gate portion extending from the second fin sidewall portion and filling a space inside the upper half of the second fin structure; a second bottom epitaxial layer comprising a bottom source / drain region and formed underneath the second fin structure; a second power contact landing on the second bottom epitaxial layer; a second top source / drain region formed above the second fin structure; and a second top source / drain contact landing on the second top source / drain region, wherein the first field gate portion and the second field gate portion merge to form a merged field gate portion, wherein the first vertical field effect transistor device and the second vertical field effect transistor device share a gate contact landing on the merged field gate portion, and wherein at least one of the first power contact and the second power contact lands on at least one of the first bottom epitaxial layer and the second bottom epitaxial layer at a location inside at least one of an upper half of the first fin structure and a lower half of the second fin structure, respectively.

14. The semiconductor cell structure of claim 13, wherein the gate contact lands on the merged field gate portion at a location outside both the first fin structure and the second fin structure.

15. The semiconductor cell structure of claim 14, wherein the first power supply contact lands on the first bottom epitaxial layer at a location inside the upper half of the first fin structure, and the second power supply contact lands on the second bottom epitaxial layer at a location inside the lower half of the second fin structure.

16. The semiconductor cell structure of claim 13, wherein the gate contact lands on the merged field gate portion at a location inside one of the lower half of the first fin structure and the upper half of the second fin structure.

17. The semiconductor cell structure of claim 13, wherein the first power supply contact is configured to receive a power supply signal, and the second power supply contact is configured to receive a ground signal, and wherein the first vertical field effect transistor device and the second vertical field effect transistor device are connected to constitute an inverter.

18. The semiconductor cell structure of claim 13, further comprising a third vertical field effect transistor device and a fourth vertical field effect transistor device arranged in a cell height direction, wherein the third vertical field effect transistor device has the same structure as the first vertical field effect transistor device, and the fourth vertical field effect transistor device has the same structure as the second vertical field effect transistor device, except that each of a length of a vertical portion of a third fin structure of the third vertical field effect transistor device corresponding to the first fin structure and a length of a vertical portion of a fourth fin structure of the fourth vertical field effect transistor device corresponding to the second fin structure is greater than the length of the vertical portion of the first fin structure or the vertical portion of the second fin structure.

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