Semiconductor substrate on diamond, precursor for manufacturing semiconductor substrate on diamond and manufacturing method thereof

Abstract

The present invention provides a method 100 for manufacturing a precursor 105a for manufacturing a semiconductor substrate 110 on diamond, the method comprising: a) starting from a base substrate 112; b) forming a sacrificial carrier layer 114 on the base substrate, the sacrificial carrier layer comprising a single crystal semiconductor; c) forming a single crystal nucleation layer 116 on the sacrificial carrier layer, the single crystal nucleation layer being arranged to allow diamond nucleation growth; and d) forming a device layer 118 on the single crystal nucleation layer, the device layer comprising a single crystal semiconductor layer or a plurality of single crystal semiconductor layers.

Description

Technical Field

[0001] The present invention relates to a semiconductor substrate on diamond, a precursor for manufacturing the semiconductor substrate on diamond and a manufacturing method thereof. Background Art

[0002] Semiconductor wafers can be used to make electronic devices, including power supplies, RF and microwave devices, and also to make optical devices, including light emitting diodes and laser diodes. The efficiency and capacity of such devices are limited by how much waste heat can be extracted from them. Diamond is a good candidate for heat extraction, particularly for use as a heat transfer layer within these wafers.

[0003] FIG1 schematically shows a known method for producing semiconductors on a diamond substrate 10. The substrate production method starts with providing a growth structure including a Si (or other) substrate 12, providing one or more transition layers 14 on the Si substrate 12, and providing a semiconductor device layer 16, such as a GaN device layer, on the transition layer 14. The semiconductor device layer 16 may include different epitaxial layers, such as GaN, AlGaN, InGaN or others. The device layer is arranged to form a circuit thereon, for example by deposition, removal, patterning or electrical property changes. The transition layer 14 is arranged to provide some lattice matching or strain matching between the Si substrate 12 and the semiconductor device layer 16.

[0004] In step 40, handle wafer 18 is attached to device layer 16. This typically involves an attachment layer such as spin-on-glass, or in other embodiments, attachment may be provided by a wafer bonded interface.

[0005] In step 42 , the Si substrate 12 is removed.

[0006] In step 44 , the or each transition layer 14 is removed.

[0007] In step 46, an amorphous nucleation layer 20 is deposited on the exposed side of the semiconductor device layer 16. The exposed side is the side opposite to the side to which the handle wafer 18 is attached. The amorphous nucleation layer 20 is arranged to allow diamond nucleation and growth.

[0008] In step 48 , a diamond layer 22 is grown onto the amorphous nucleation layer 20 .

[0009] In step 50, the handle wafer 18 is removed. After removing the handle wafer 18, a semiconductor substrate on diamond 10 is provided. The exposed surface of the semiconductor device layer 16 can be prepared for further processing, such as by cleaning, such as to remove a protective layer. The semiconductor substrate structure on diamond 10 can then be used for processing of high-end RF and other devices. Summary of the invention

[0010] According to one aspect, the present invention provides a method of manufacturing a precursor for manufacturing a semiconductor substrate on diamond, the method comprising:

[0011] a) Starting with a base substrate;

[0012] b) forming a sacrificial carrier layer on the base substrate, the sacrificial carrier layer comprising a single crystal semiconductor;

[0013] c) forming a single crystal nucleation layer on the sacrificial carrier layer, the single crystal nucleation layer being arranged to nucleate diamond growth; and

[0014] d) forming a device layer on the single crystal nucleation layer, wherein the device layer includes one single crystal semiconductor layer or multiple single crystal semiconductor layers.

[0015] Advantageously, the method of the present invention results in an improved precursor which subsequently results in better or more efficient production of the final semiconductor on a diamond substrate than the prior art. The precursor is better because it is formed according to the method of the present invention. In particular, as will become apparent, the surface boundaries between the layers of the precursor and at the exposed surface of the precursor are better than prior art wafers due to their subsequent intended use (in conjunction with providing a suitable device layer surface, forming a suitable surface for diamond growth nucleation).

[0016] The method optionally comprises successively growing a sacrificial carrier layer, then a nucleation layer, then a device layer to achieve steps b) to d). Optionally, the consecutive growth comprises performing steps b) to d) in a growth chamber and not removing the precursor being produced from the growth chamber during performing steps b) to d).

[0017] Optionally, the step of forming a single crystalline nucleation layer comprises depositing the nucleation layer via 2D or 3D growth or layer-by-layer growth, preferably by 2D or layer-by-layer growth.

[0018] Optionally, the continuous growth includes properly lattice matching the sacrificial carrier layer with the single crystal nucleation layer, and the single crystal nucleation layer with the device layer.

[0019] The method may optionally include:

[0020] Step b) comprises forming the single crystal sacrificial carrier layer, wherein the single crystal sacrificial carrier layer has a dislocation density less than a first threshold dislocation density, for example 10 9 cm -2 ;

[0021] Step c) comprises forming the single crystal nucleation layer, wherein the single crystal nucleation layer has a dislocation density less than a second threshold dislocation density, for example, 0.5×10 9cm -2 ;as well as

[0022] Step d) comprises forming the single crystalline device layer, wherein the single crystalline device layer has a dislocation density less than a third threshold dislocation density, for example 10 8 cm -2 .

[0023] Optionally, after step a) and before step b), the method includes forming one or more transition layers between the base substrate and the sacrificial carrier layer, the one or more transition layers being arranged to facilitate transition from the base substrate to the sacrificial carrier layer, and optionally, wherein facilitating the transition includes alleviating strain or nucleation growth or both of the sacrificial carrier layer.

[0024] The method optionally includes bonding or forming a handle layer on the device layer.

[0025] The method optionally includes removing the base substrate, further optionally chemically or by mechanical polishing or by a combination thereof.

[0026] Optionally, the method comprises selectively removing one or more transition layers, for example by selective etching.

[0027] Optionally, the method comprises selectively removing the sacrificial carrier layer, for example by selective etching, wherein the selective removal process stops at the nucleation layer or the transition layer.

[0028] Optionally, step b) includes forming a sacrificial carrier layer from a first material so that the sacrificial carrier layer has a first removal rate, and wherein step c) includes forming a nucleation layer from a second material so that the nucleation layer has a second removal rate, wherein the first removal rate is different from the second removal rate.

[0029] According to another aspect, there is provided a method of manufacturing a semiconductor substrate on diamond, the method comprising the method of the above-mentioned aspect, and further comprising growing a diamond layer (e.g., a synthetic diamond layer) onto a nucleation layer after selectively removing the sacrificial carrier layer. Optionally, the method comprises pre-treating the nucleation layer with plasma or the like before growing the diamond layer thereon - further optionally, in the case of an AlN nucleation layer, the method comprises pre-treating the nucleation layer by treating the AlN nucleation layer with N2 and / or H2 plasma for a period of time.

[0030] The method optionally includes removing the treatment layer, optionally selectively.

[0031] Optionally, step d) includes forming a device layer from a third material so that the device layer has a third removal rate, and bonding or forming a processing layer includes bonding or forming a processing layer including a fourth material so that the processing layer has a fourth removal rate, wherein the fourth removal rate is different from the third removal rate.

[0032] The method may optionally include any one or more of the following:

[0033] The base substrate includes a Si substrate, a SiC substrate, an AlN composite material or a sapphire substrate;

[0034] The single crystal sacrificial carrier layer comprises SiC, GaN, AlN, InN, AlGaN, InGaN, BN, BAlN, ScN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof; and optionally, the single crystal sacrificial carrier layer has a thickness exceeding 100 nm;

[0035] The single crystal nucleation layer comprises SiC, GaN, AlN, AlGaN, ScN, BN, HfN, ZrN, InN, Si, Ge, TiN or alloys thereof, and oxide-based materials such as Ga2O3, Al2O3, MgO and alloys thereof, and optionally:

[0036] ◆ the single crystal nucleation layer has a thickness of 5nm to 100nm, for example 5nm to 50nm; and / or

[0037] ◆The single crystal nucleation layer has a thermal conductivity of 5 to 600 W / m·K;

[0038] The single crystal device layer comprises SiC, GaN, AlN, InN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, or comprises a multilayer structure, such as a 25nm AlGaN layer or a 3nmGaN-20nm AlGaN-GaN layer or a GaN-InGaN-GaN layer combination on GaN, and optionally the single crystal device layer has a thickness of up to 5000nm; and the one or more transition layers comprise one or more of SiC, AlN, GaN, AlGaN, or AlGaN / AlGaN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, such as:

[0039] ◆5nm to 200nm thick AlN or AlGaN layer with 3D morphology and grown on SiC or sapphire substrate for subsequent growth of GaN sacrificial carrier layer;

[0040] ◆On the Si substrate, an AlN transition layer is first formed, followed by a GaN / AlN superlattice transition layer for the subsequent growth of the GaN sacrificial carrier layer;

[0041] ◆On the Si substrate, an AlN transition layer is first formed, and then an AlN / AlGaN / GaN gradient alloy transition layer is formed for the subsequent growth of the GaN sacrificial carrier layer.

[0042] According to another aspect, the present invention provides a layered precursor which is subsequently used to prepare a semiconductor substrate on diamond, the precursor comprising, in sequence, a base substrate, a sacrificial single crystal semiconductor carrier layer, a single crystal nucleation layer arranged to nucleate diamond growth, a single crystal semiconductor device layer or a semiconductor device multilayer structure.

[0043] Optionally, the layered precursor further comprises one or more transition layers between the base substrate and the sacrificial carrier layer, wherein the one or more transition layers are arranged to facilitate transition from the base substrate to the sacrificial carrier layer, and optionally, wherein facilitating the transition comprises alleviating strain or nucleation growth or both of the sacrificial carrier layer.

[0044] The lamellar precursor may optionally include any one or more of the following:

[0045] The base substrate includes a Si substrate, a SiC substrate, an AlN composite material or a sapphire substrate;

[0046] The single crystal sacrificial carrier layer comprises SiC, GaN, AlN, InN, AlGaN, InGaN, BN, BAlN, ScN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof; and optionally, the single crystal sacrificial carrier layer has a thickness exceeding 100 nm;

[0047] The single crystal nucleation layer comprises SiC, GaN, AlN, AlGaN, ScN, BN, HfN, ZrN, InN, Si, Ge, TiN or alloys thereof, and oxide-based materials such as Ga2O3, Al2O3, MgO and alloys thereof, and optionally:

[0048] ◆ the single crystal nucleation layer has a thickness of 5nm to 100nm, for example 5nm to 50nm; and / or

[0049] ◆The single crystal nucleation layer has a thermal conductivity of 5 to 600 W / m·K;

[0050] The single crystal device layer comprises SiC, GaN, AlN, InN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, or the semiconductor device multilayer structure comprises a multilayer structure, such as a 25nm AlGaN layer or a 3nmGaN-20nm AlGaN-GaN layer or a GaN-InGaN-GaN layer combination on GaN, and optionally the single crystal device layer has a thickness of up to 5000nm; and

[0051] The one or more transition layers include one or more of SiC, AlN, GaN, AlGaN, or AlGaN / AlGaN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, for example:

[0052] ◆A 5nm to 200nm thick AlN layer with 3D morphology and grown on SiC or sapphire substrate for the subsequent growth of GaN sacrificial carrier layer;

[0053] On a Si substrate, an AlN transition layer is first formed, followed by a GaN / AlN superlattice transition layer for subsequent growth of a GaN sacrificial carrier layer;

[0054] On a Si substrate, an AlN transition layer is first formed, followed by an AlN / AlGaN / GaN gradient alloy transition layer for subsequent growth of a GaN sacrificial carrier layer.

[0055] The layered precursor may optionally include:

[0056] The single crystal sacrificial carrier layer has a dislocation density less than a first threshold dislocation density, for example, 10 9 cm -2 ;

[0057] The single crystal nucleation layer has a dislocation density less than the second threshold dislocation density, for example, 0.5×10 9 cm -2 ;and

[0058] The single crystal device layer or semiconductor device multilayer structure has a dislocation density less than a third threshold dislocation density, for example, 10 8 cm -2 .

[0059] According to another aspect, the present invention provides a semiconductor substrate on diamond, comprising a single crystal device layer or semiconductor device multilayer structure, a single crystal nucleation layer arranged to nucleate diamond growth, and a diamond layer, wherein the thermal resistance of the interface between the device layer or semiconductor device multilayer structure and the diamond layer is improved relative to existing systems. The improved results that can be obtained using the present invention are given in Table 1 of the specification below. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0061] FIG. 1 (Prior Art) schematically shows a known technique for forming a semiconductor-on-diamond substrate.

[0062] Figure 2 A method of forming a semiconductor-on-diamond substrate is schematically shown, including a method for forming a precursor according to an embodiment of the present invention.

[0063] Figure 3 A method of forming a semiconductor-on-diamond substrate is schematically shown, including a method for forming a precursor according to another embodiment of the present invention.

[0064] Figure 4 A method of forming a semiconductor-on-diamond substrate is schematically shown, the method comprising a method for forming a precursor according to another embodiment of the present invention. DETAILED DESCRIPTION

[0065] In one embodiment, the present invention provides a method 100 of forming a semiconductor-on-diamond substrate 110. The initial portion of the method 100 includes a method 100a of making a precursor 105a, followed by making the semiconductor-on-diamond substrate 110. Advantageously, the method 100a of the present invention results in an improved precursor 105a, which subsequently results in a better or more efficient production of the final semiconductor-on-diamond substrate 110 compared to the prior art. The precursor 105a is better because it is formed according to the method 100a of the present invention. In particular, as will become apparent, the surface boundaries between the layers of the precursor 105a and at the exposed surface of the precursor 105a are better than previous wafers due to their subsequent intended use (forming a suitable surface for diamond growth nucleation in conjunction with providing a suitable device layer surface).

[0066] The method 100a of making a precursor 105a begins with a base substrate 112. The base substrate may include any suitable material that can be used for subsequent layer growth. The base substrate may include any of a Si substrate, a SiC substrate, a GaN substrate, an AlN substrate, an AlN composite material, or a sapphire substrate. Alternatives include oxide-based substrates such as Ga2O3, MgO. SiC substrates generally provide the highest quality GaN layers, while Si or AlN composite substrates result in much lower production costs, but at the expense of a slightly increased defect density in the GaN layer.

[0067] The next step of the method 100 a includes forming a sacrificial carrier layer 114 on the base substrate 112 .

[0068] There are many known methods for forming or depositing layers. Layers can be deposited or grown. Two common growth options are metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). MOCVD is more commonly used for growth on multiple large substrates in a single reactor. The skilled reader will be able to use and adapt standard techniques for layer formation. Different layers and layer compositions are made by changing the source materials or precursors in the growth system. These layers are, for example, GaN, AlN, InN, ScN, BN and their alloys. Oxide-based layers can also be considered. Other methods can also be used, such as pulsed laser deposition, sputtering, magnetic sputtering, atomic layer deposition (ALD) (using this method, part or even the entire epitaxial layer can be grown in a thin layer), etc.

[0069] The sacrificial carrier layer 114 includes a single crystal semiconductor. In this embodiment, the sacrificial carrier layer 114 may include any suitable material that a) is attached to the substrate 112 and b) can be selectively removed relative to an adjacent nucleation layer 116 in a subsequent process (described below). The sacrificial carrier layer 114 may include any one of single crystal GaN, single crystal AlN, single crystal InN, single crystal AlGaN, single crystal InGaN, single crystal BN, single crystal BAlN, and oxide-based materials may also be considered. In this embodiment, the single crystal sacrificial carrier layer has a thickness of more than 100nm. However, depending on the etching selectivity, the thickness may also be less than 100nm. In the case where the sacrificial layer and the substrate are the same material, the growth of the sacrificial layer may be omitted in some embodiments.

[0070] For the purpose of this specification, a single crystal layer refers to a layer formed essentially of one crystal. Although it may contain defects, such as dislocations, slip planes, point defects, etc., it can also be described as a single crystal layer. Relative to conventional technology, the density of the defects is low enough to provide improved heat transfer and growth characteristics. The layer can be formed by a single or multiple single crystal parts (with or without defects). The advantage of this is that a better quality interface is provided between the layers by maintaining crystallinity. It is necessary to have a single crystal layer (or as close as possible by multiple single crystal parts) to seed further single crystal material layers at a later stage of the process (excluding the growth of the diamond layer).

[0071] If the intermediate layer (nucleation layer) is lattice matched (strained), it will not generate additional dislocations in the subsequently grown layers. In contrast, if a lattice mismatched layer is grown, dislocations will be generated and propagate into the device layers, which will be detrimental to the electrical and thermal properties - this is undesirable. Therefore, advantageously, the intermediate layer matches the lattice of the upper and lower layers.

[0072] The single crystal sacrificial carrier layer 114 of this embodiment has a dislocation density less than a first threshold dislocation density. In this example, the first threshold dislocation density is 10 9 cm -2 In some embodiments, the first threshold dislocation density is between 10 10 cm -2 and 10 12 cm -2 but it can also be lower.

[0073] The next step of method 100a includes forming a single crystal nucleation layer 116 on the sacrificial carrier layer 114. The single crystal nucleation layer 116 is configured to enable (at a subsequent stage) diamond nucleation and growth. In particular, in this embodiment, the single crystal nucleation layer includes any material suitable for nucleation synthesis of diamond growth. The single crystal nucleation layer may include any of AlN, GaN, InN, AlGaN, ScN, BN, HfN, ZrN, Ge or their alloys, as well as an oxide-based layer. In other embodiments, the nucleation layer may include metals such as Ir, W, Mo and Nb. Ir can grow single crystals on materials such as MgO. As previously described, the single crystal nature of this layer allows for enhanced bonding with adjacent single crystal sacrificial carrier layers (better surface connection and better transition performance). The single crystal nucleation layer may have a thickness of 5nm to 100nm, for example 5nm to 50nm. In some example embodiments, if the nucleation layer is an AlN layer, allowing it to relax has potential advantages because it will help suppress the formation of parasitic lateral leakage channels. This will require some dislocations; however, the screw dislocations will bend into the plane of the layer to release the strain, so the density of screw dislocations does not have to increase significantly. In fact, sometimes a relaxed AlN intermediate layer is used as a growth tool to reduce the density and termination of screw dislocations and reduce strain by bending these dislocations to combine them. Therefore, in these examples, for the strained layer, its thickness can be 5-8nm, which is thick enough to act as an etch stop layer, or for the relaxed layer, its thickness can be 8-50nm. In terms of heat transfer, thin dislocation-free (strained) layers are preferred. For the AlN example, the thickness will be the lower 5-8nm range. Thicker layers containing dislocations (relaxation) will have higher thermal resistance. In other examples, if AlGaN is used as the nucleation layer, the critical thickness before relaxation occurs is thicker, so in order to avoid a significant thermal resistance, the layer may be strained.

[0074] The thermal conductivity of the nucleation layer is between 5-400 W / (m·K). In some example embodiments, the thermal conductivity can be 300 W / (m·K) for an AlN nucleation layer, or 400 W / (m·K) for a BN nucleation layer (this is the value in the basal plane direction. The thermal conductivity is close to 10 W / (m·K) in the through-plane direction (heat flow direction)), or close to 10 W / (m·K) for a ScN nucleation layer and close to 50 W / (m·K) for a ZrN nucleation layer. The higher the thermal conductivity of the material, the better the heat transfer in the device. Similarly, it is important to consider the lattice mismatch of the nucleation layer with the sacrificial carrier layer - it is best to keep it below 15%; however, typically the mismatch is only a few percent to minimize any additional dislocations introduced in the growth of the nucleation layer.

[0075] In other examples, the thermal conductivity based on these bulk thermal conductivity values ​​at 300K is as follows:

[0076] AlN: about 20 W / m·K at 5 nm thickness and about 180 W / m·K at 100 nm thickness; and

[0077] BN: About 12W / m·K when 5nm thick, about 27W / m·K when 100nm thick.

[0078] Other examples will be apparent to the skilled reader. Preferably, the single crystal nucleation layer has a dislocation density less than a second threshold dislocation density. In this example, the second threshold dislocation density is 0.5×10 9 cm -2 This level may be advantageous for the GaN HEMT example. In some embodiments, the second threshold dislocation density is between 0.5×10 10 cm -2 and 0.5×10 11 cm -2 For example, when applied to the manufacture of laser diodes or microelectronics, the second threshold dislocation density can be lower, such as 10 4 cm -2 or 10 8 cm -2 .

[0079] In general, it is preferred that the dislocation density decreases throughout the device structure, but in some cases, for one of the layer boundaries, the dislocation density may actually increase between device structures. Therefore, in some other examples, the second threshold dislocation density can be higher than the first threshold density because additional dislocations may form due to the large strain mismatch. For example, if AlN is grown on a GaN sacrificial layer, as the AlN layer becomes thicker, defects will appear, so the defect density will increase. However, as described above, in the case of dislocation bending, the defect density may also decrease depending on the specific situation. In general, it is desirable to keep the defect density low.

[0080] In some examples covered by the present invention, the defect density in the sacrificial layer can be 10 8 cm -2 , the defect density in the AlN layer can be 10 9 cm -2 - Even if the dislocation density in the nucleation layer is greater than the dislocation density in the sacrificial carrier layer, the final product will still benefit from the method of the present invention.

[0081] The inventors have considered a critical thickness for the nucleation interlayer. AlN can be grown on GaN to about 10 nm thick before strain relaxation occurs. Making it thicker than 10 nm may not provide greater benefit because the relationship between the thermal conductivity and the thermal conductivity of the layer is nonlinear, i.e., the thermal resistance of the layer increases even though the thermal conductivity increases with thickness.

[0082] The next step of the method 100a includes forming a single crystal device layer 118 on the single crystal nucleation layer 116. The device layer 118 includes a single crystal semiconductor. The device layer 118 can be any single crystal semiconductor that can achieve the desired effect of providing a suitable surface in which or on which a circuit is formed. The device layer 118 can include any one of GaN, AlN, InN, BN and alloys thereof, as well as oxide-based materials such as Ga2O3, MgO. In some embodiments, the single crystal device layer has a thickness of 100nm to 5000nm. In other embodiments, the device layer can be a multilayer structure. For example, the device layer can be a GaN / AlGaN layer (for example, this type of layer is suitable for forming a transistor). In other embodiments, the device layer can be a GaN / InGaN / GaN layer (for example, this type of layer can be used for light-emitting devices). In such an example, each different layer of the multilayer structure is a single crystal layer. The multilayer device layer may include, for example, a 25nm AlGaN layer on a GaN layer or a 3nmGaN-20nmAlGaN-GaN layer or a GaN-InGaN-GaN layer combination, and in some embodiments may also include a SiC-based device structure or a Ga2O3 and related device structure. In this embodiment, the dislocation density of the single crystal device layer is less than a third threshold dislocation density. In this example, the third threshold dislocation density is 10 8 cm -2 In other embodiments, the third threshold dislocation density may be lower or higher. Typically, if the third threshold dislocation density is greater than 10 10 cm -2 , the device will not be able to operate normally. The present invention helps to more effectively manufacture high-quality finished devices by means of the improved precursor manufacturing method, and controls the dislocation density in the device structure with the additional potential of the included nucleation layer.

[0083] exist Figure 2In the embodiment, the starting structure includes another layer between the base substrate 112 and the sacrificial carrier layer 114. In most but not all embodiments, a transition layer (or multiple transition layers) 113 is provided before the sacrificial carrier layer is formed. The transition layer 113 is formed between the base substrate 112 and the sacrificial carrier layer 114. One or more transition layers 113 are arranged to promote a smooth growth transition from the base substrate 112 to the sacrificial carrier layer 114. The transition layer provides strain relief and ensures that the layer grows well. Promoting the transition includes alleviating strain and / or nucleation growth of the carrier layer 114 or both. The transition layer may include any one or more of AlN, GaN, AlGaN, or AlGaN / AlGaN, BN or their alloys. In some embodiments, the transition layer includes a 5nm to 200nm thick AlN or AlGaN layer having a 3D morphology and has been grown on a SiC or sapphire substrate (for subsequent GaN sacrificial carrier layer growth). In other examples, the transition layer includes an AlN transition layer on a silicon substrate, followed by a GaN / AlN superlattice transition layer, a transition layer (112) for subsequent growth of a GaN or other material sacrificial carrier layer. In yet another example, on a Si substrate, the transition layer includes an AlN transition layer, followed by an AlN / AlGaN / GaN gradient alloy transition layer (for subsequent growth of a GaN sacrificial carrier layer). In one example, the transition layer is a very thin (e.g., 10 nm) single crystal semiconductor layer with an extremely high defect density. In some embodiments of GaN on Si, the transition layer can be as thick as 4 microns. For embodiments of GaN on SiC, the transition layer can be between 10 nm and 30 nm. This layer nucleates the growth of a GaN sacrificial carrier layer.

[0084] The or each transition layer assists in any one or combination of lattice matching, strain matching and nucleation between boundary layers.

[0085] In some embodiments, there is no transition layer between the substrate and the sacrificial carrier layer.

[0086] In this embodiment, sacrificial carrier layer 114, nucleation layer 116 and device layer 118 are grown continuously on the substrate or on the substrate and transition layer. In this example, the continuous growth includes performing the relevant formation steps in the growth chamber and not removing the precursor being manufactured from the growth chamber during the execution of the steps.

[0087] In some embodiments, during fabrication, the precursor may be moved from one growth chamber to another under controlled conditions to ensure consistent growth. For example, in two connected growth chambers connected via a vacuum channel, the growth of the precursor may be stopped in one chamber and then moved to the other chamber to continue growth.

[0088] In other embodiments, the precursor 105a may not be grown continuously.

[0089] By growing these layers sequentially, advantageously, a precursor is provided that has good surface matching properties between its layers. Not removing the precursor from the growth chamber during the sequential growth provides further benefits, for example, preventing surface reconstruction or contamination. In combination with the use of single crystalline carrier layers, nucleation layers and device layers, a precursor is provided that has good strain and lattice matching properties.

[0090] In this example, the nucleation layer 116 is deposited via 2D layer-by-layer growth. In other embodiments, 3D growth may also be used. In order to avoid introducing defects into the layer, 2D growth of the nucleation layer is preferred. For the growth of the transition layer 113, 3D growth is more practical.

[0091] In this example, sequential growth includes reasonably lattice matching the sacrificial carrier layer to the single crystal nucleation layer, and the single crystal nucleation layer to the device layer (in some embodiments, the lattice constants of the two materials differ by less than 15%; preferably less than 1-3%, although larger is possible). For example, for AlN, the lattice constant difference can be 2.4%, which allows an intermediate layer of about 10nm thick.

[0092] In this embodiment, the method 100a also includes a step 140 of bonding or forming a handle layer 120 on the device layer 118. The handle layer includes any layer suitable for subsequent gripping of the device layer or device at a subsequent stage of the manufacturing process. In some embodiments, the handle layer is attached to the device layer with a spin-on glass. The handle layer is also a sacrificial layer. In this specification, the sacrificial layer is to be removed at a subsequent stage of the manufacturing process and does not appear in the final semiconductor on the diamond substrate 110. Example handle wafers may include Si, GaAs, Ge (but Si is used in most cases because it is relatively cheap and easy to remove).

[0093] The method 100a also includes a step 142 of removing the base substrate 112. In this example, the base substrate is removed by a chemical or mechanical polishing process or a combination thereof. This can be a selective or non-selective removal process.

[0094] In an embodiment where one or more transition layers 113 are present, the method 100a includes a step 144 of removing the or each transition layer 113. In this example, the step 144 of removing the transition layer 113 is achieved by selectively removing (e.g., by selectively etching) the transition layer 113. Selective etching techniques include reactive ion etching (e.g., using a tailored gas for the GaN / AlN interface) and liquid-based etching. For the purposes of this specification, selective removal, such as selective etching, refers to the removal of a material from an adjacent material, where the materials have significantly different removal rates from each other for a particular removal process. For example, GaN has a significantly different removal rate from AlN for a particular gas or liquid, i.e., reactive ion etching or wet etching process. Examples of liquid-based etching may include KOH under ultraviolet irradiation (photon energy greater than the band gap of GaN, but less than the band gap of AlN, SiC, BN, etc.). Selective removal techniques are apparent to a skilled reader familiar with clean room processes.

[0095] In contrast, non-selective removal may be achieved, for example, by mechanical etching or polishing or a non-selective chemical process.

[0096] For example, the method 100a includes removing the sacrificial carrier layer 114 and any transition layer 113 that may be present in some embodiments at step 144. After step 144, a precursor 105a (see Figure 2 In other examples (see Figure 3 and 4 ), as will be discussed in further detail below, it is conceivable that the precursors were formed at an earlier stage.

[0097] In this example, the sacrificial carrier layer 114 is formed of a first material, such that the sacrificial carrier layer has a first removal rate. The nucleation layer 116 is formed of a second material, such that the nucleation layer has a second removal rate. The first removal rate is different from the second removal rate, such that the sacrificial carrier layer can be effectively removed using a selective removal technique such as a selective etching removal technique, and cleanly and effectively leaves a good, clean and atomically smooth nucleation layer surface for subsequent diamond growth. Advantageously, the method 100a of the present invention provides this advantage, which is not available in any other known method. This advantage comes from Figure 2The essence of the initial single crystal layer growth in the first stage is schematically given in . The nucleation layer is sandwiched between the device layer and the sacrificial carrier layer with removal characteristics, so that the subsequent selective etching (step 144) is effectively possible. This arrangement results in allowing the use of an effective technology (selective removal) to provide a high-quality nucleation surface. This arrangement also allows the manufacture of a semiconductor on diamond, such as a GaN device layer with a determined thickness, without the use of any timed etching. In the prior art, the thickness of the GaN layer in the final product can almost only be controlled by timed etching. Introducing selective etching at a critical stage is a technical advantage. Avoiding the use of timed etching provides a simplified manufacturing process.

[0098] The method 100 of manufacturing the semiconductor substrate 110 on diamond also includes a step 146 of growing a diamond layer 122 on the nucleation layer 116 after selectively removing the sacrificial carrier layer 114. In this example, the diamond layer includes a synthetic diamond layer. In this example, the diamond layer can be effectively grown without further preparation of the nucleation surface according to step 144. In other examples, little or no preparation may be required between steps 144 and 146, especially when compared to prior art techniques for growing diamond on nucleation surfaces prepared in different ways.

[0099] In one example, the preparation work may include treating the AlN nucleation surface with plasma. The plasma treatment may include treating the AlN nucleation surface with N2 and / or H2 plasma. In a specific case, the treatment may include treating the AlN nucleation layer with 10% N2 / H2 plasma for 10 minutes. The inventors have shown that such pretreatment can increase the oxygen content of the AlN nucleation surface. Such a pretreated surface allows a thick (in some examples, >10μm; or, in some examples, >50μm; or, in some examples, >100μm) diamond layer to be grown thereon.

[0100] The method 100 further includes a step 148 of removing the handle layer 120. It will be appreciated that up until this stage, the handle layer 120 is necessary to process the precursor during the manufacturing process to avoid damage to the device layer 118, which is part of the final semiconductor substrate 110 on diamond. In this particular example, the handle layer is removed by a selective removal process. In this example, the device layer 118 is formed of a third material such that the device layer has a third removal rate. The handle layer includes a fourth material such that the handle layer has a fourth removal rate. The fourth removal rate is different from the third removal rate, thereby making it effective and possible to selectively remove the handle layer from the device layer in step 148. As shown in FIG. Figure 2As shown, the device layer 118 has an exposed surface in the semiconductor substrate 110 on diamond. Due to the selective removal process used in step 148, it is necessary to reduce processing (or in some examples, no further processing) of the exposed surface to make it in a state that can be used as a device layer later.

[0101] In some embodiments, the top surface of the device layer is protected with SiN, for example, before attaching a handle wafer. Once the handle wafer (or the spin glass used to attach the handle wafer) is removed, the SiN layer (which can be broadly referred to as a protective layer) is removed before device processing of the wafer. The protective layer protects the top surface of the device-level material. In some embodiments, the SiN layer is retained during device manufacturing.

[0102] In other embodiments, it may be considered that the precursor 105 is formed at an earlier stage.

[0103] exist Figure 3 In the example of FIG. 1 , it can be considered that the precursor is formed before removing the sacrificial carrier layer 114 , that is, before step 144 and after step 142 .

[0104] exist Figure 4 In the example of FIG. 1 , it can be considered that the precursor is formed before step 142 and after step 140 , ie, before the base substrate 112 is removed.

[0105] In other embodiments, it may be considered that the precursor is formed before adding the treatment layer 120 , ie, before step 140 .

[0106] In these various examples and embodiments, the initial stage of providing a sandwich nucleation layer (having a device layer 118 on one side and a sacrificial carrier layer 114 on the other side) has provided a useful and technically advantageous starting point for efficiently implementing subsequent steps of a method that is not yet known in existing precursors for manufacturing semiconductors on diamond substrates.

[0107] Some specific example embodiments of this precursor configuration will now be described in more detail.

[0108] Example 1

[0109] Substrate = Si

[0110] Sacrificial carrier layer = single crystal GaN with AlGaN based strain relief layer. Properties include thickness = 1 μm; dislocation density = 10 9 cm -2 .

[0111] Nucleation layer = single crystal AlN. Properties include dislocation density = 10 9cm -2 .

[0112] Device layer = single crystal GaN with 25nm AlGaN on top. Properties include dislocation density = 10 9 cm -2 ;wait.

[0113] Example 2

[0114] Substrate = SiC

[0115] Sacrificial carrier layer = single crystal GaN with AlN nucleation layer. Properties include thickness = 1 μm; dislocation density = 10 8 cm -2 .

[0116] Nucleation layer = single crystal AlN. Properties include dislocation density = 10 8 cm -2 .

[0117] Device layer = single crystal GaN with 25nm AlGaN on top. Properties include dislocation density = 10 8 cm -2 ;wait.

[0118] Example 3

[0119] Substrate and sacrificial carrier layer = GaN (the GaN layer is formed integrally, serving as both the substrate and the sacrificial carrier layer).

[0120] Nucleation layer = single crystal AlN. Properties include dislocation density = 10 6 cm -2 .

[0121] Device layer = single crystal GaN containing InGaN quantum wells. Properties include dislocation density = 10 6 cm -2 ;wait.

[0122] Example 4

[0123] Substrate and sacrificial carrier layer = Ga2O3 (the Ga2O3 layer is formed integrally and serves as both the substrate and the sacrificial carrier layer).

[0124] Nucleation layer = single crystal GaAlO. Properties include dislocation density = 10 6 cm -2 .

[0125] Device layer = single crystal Ga2O3. Properties include dislocation density = 10 6 cm -2 ;wait.

[0126] Embodiments of the present invention allow for selective removal to the nucleation layer. This results in providing a good nucleation surface for diamond growth, which in turn provides better heat transfer in the final product. One of the advantages is that the selective etching stops at the nucleation layer, so the manufacture of a single crystal nucleation layer can be easily performed. In some examples, the nucleation layer, when single crystal, has a higher thermal conductivity (>10W / mK) than the amorphous nucleation layers (such as SiO2 and Si3N4) commonly used in the prior art, which helps to transfer heat through the nucleation layer. Considering that the surface of the nucleation layer made in this way is smooth, due to the interface roughness, almost no phonons will be scattered, which in turn will hinder heat transfer.

[0127] In some examples, the inventors have considered the interfacial thermal resistance between the GaN device layer and the diamond substrate.

[0128] Consider case (1) - existing technology:

[0129] For an amorphous core layer (50 nm thick silicon nitride), the effective thermal resistance of the interface would be 5 × 10 -8 m 2 K / W (this value will vary with the thickness of the layer). This will account for about 40% of the total thermal resistance at chip level, for example, for an 8-finger, 125 μm wide GaN transistor with a 35 μm gate finger pitch device geometry.

[0130] Consider case (2):

[0131] For an identical 8-finger, 125μm wide GaN transistor with a 35μm gate finger pitch device geometry, we estimate the thermal conductivity to be about 20W / mK for a 10nm thick crystalline AlN nucleation layer (due to the reduced phonon mean free path). This leads to an effective value of 0.5×10 -9 m 2 The intrinsic thermal resistance (phonon mismatch) between GaN and diamond is about 2×10 -9 m 2 ·K / W.

[0132] Therefore, the thin crystalline AlN nucleation layer (effectively formed according to the present method) does not significantly increase the thermal resistance of the device. In fact, this is the case as long as the thermal conductivity of the 10 nm thick layer is >5 W / m·K.

[0133] Comparing case (1) (prior art) with case (2) (an example of the proposed inventive method), the inventors reduced the chip temperature rise by 40% (excluding package thermal resistance, etc.).

[0134] The invention can be used to manufacture components such as electronic, optical, and optoelectronic components.

[0135] As previously described, the present invention allows efficient fabrication of structures having excellent thermal conductivity. The present invention provides a semiconductor substrate on diamond, comprising a single crystal device layer or a semiconductor device multilayer structure, a single crystal nucleation layer arranged to nucleate diamond growth, and a diamond layer, wherein the interfacial thermal resistance between the device layer or the semiconductor device multilayer structure and the diamond layer is improved relative to existing systems.

[0136] The inventors have studied the expected thermal conductivity and thermal boundary resistance properties of the different materials mentioned, as shown in the following table.

[0137] The phonon mean free path is calculated using the following formula: Where K = thermal conductivity, v s = speed of sound, c v = volumetric heat capacity.

[0138] The Landauer model is used to calculate the thermal conductivity of the film, which is applicable to ballistic heat conduction in the film. The effective phonon mean free path is calculated using the bulk phonon mean free path (l ph ) and boundary length (L).

[0139]

[0140] The following table gives the values ​​of thermal conductivity and effective thermal boundary resistance for assumed defect-free materials. Most of these values ​​are from http: / / www.ioffe.ru / SVA / NSM / Semicond / . The values ​​are obtained at room temperature.

[0141] Table 1

[0142]

[0143] In general, the inventors' studies show that even a material with low thermal conductivity like Ga2O3 will not become a major thermal barrier at a thickness of 50nm, as long as the layer is free of dislocations / defects. This factor will determine the maximum thickness that the layer can be grown.

[0144] When used in this specification and claims, the terms "comprises" and "comprising" and variations thereof mean that the specified features, steps or integers are included. These terms should not be interpreted as excluding other features, steps or components.

[0145] The features disclosed in the preceding description, or in the following claims, or in the accompanying drawings, in their specific form or as a means for performing the disclosed functions, or as a method or process for obtaining the disclosed results, may be used alone or in any combination of these features to implement the invention in multiple forms.

Claims

1. A method for manufacturing a semiconductor substrate on diamond, the method comprising: a) Starting with a base substrate; b) forming a sacrificial carrier layer on the base substrate, wherein the sacrificial carrier layer comprises a single crystal semiconductor; c) forming a single crystal nucleation layer on the sacrificial carrier layer, the single crystal nucleation layer being arranged to nucleate diamond growth; d) forming a device layer on the single crystal nucleation layer, wherein the device layer includes one single crystal semiconductor layer or multiple single crystal semiconductor layers; e) removing the base substrate; f) selectively removing the sacrificial carrier layer, wherein the selective removal process stops at the nucleation layer; g) growing a diamond layer onto the nucleation layer after the selective removal of the sacrificial carrier layer; Wherein step b) comprises forming the sacrificial carrier layer from a first material so that the sacrificial carrier layer has a first removal rate, and wherein step c) comprises forming the nucleation layer from a second material so that the nucleation layer has a second removal rate, wherein the first removal rate is different from the second removal rate. 2 . The method according to claim 1 , comprising successively growing the sacrificial carrier layer, then the nucleation layer, and then the device layer to achieve steps b) to d).

3. The method of claim 2, wherein the continuous growth comprises performing steps b) to d) in a growth chamber and the precursor being produced is not removed from the growth chamber during the performance of steps b) to d). 4 . The method of claim 1 , wherein the step of forming the single crystalline nucleation layer comprises depositing the nucleation layer via 2D or 3D growth or layer-by-layer growth. 5 . The method of claim 4 , wherein the step of forming the single crystalline nucleation layer comprises depositing the nucleation layer via 2D or layer-by-layer growth. 6 . The method according to claim 2 , wherein the continuous growth comprises reasonably lattice matching the sacrificial carrier layer with the single crystal nucleation layer, and the single crystal nucleation layer with the device layer.

7. The method according to any one of claims 1 to 5, wherein: Step b) comprises forming the single crystal sacrificial carrier layer, the single crystal sacrificial carrier layer having a dislocation density less than a first threshold dislocation density; Step c) comprises forming the single crystal nucleation layer, the single crystal nucleation layer having a dislocation density less than a second threshold dislocation density; and Step d) comprises forming a single crystalline device layer having a dislocation density less than a third threshold dislocation density.

8. According to the method described in any one of claims 1 to 5, after step a) and before step b), one or more transition layers are formed between the base substrate and the sacrificial carrier layer, and the one or more transition layers are arranged to promote the transition from the base substrate to the sacrificial carrier layer, wherein promoting the transition includes alleviating the strain or nucleation growth of the sacrificial carrier layer, or both.

9. A method according to any one of claims 1 to 5, comprising bonding or forming a handle layer on the device layer.

10. The method according to claim 8, comprising: The one or more transition layers are selectively removed by selective etching.

11. The method of claim 9 including removing the handle layer.

12. The method of claim 11, wherein step d) comprises forming the device layer from a third material so that the device layer has a third removal rate, and bonding or forming the processing layer comprises bonding or forming the processing layer with a fourth material so that the processing layer has a fourth removal rate, wherein the fourth removal rate is different from the third removal rate.

13. The method according to claim 7, wherein: The base substrate includes a Si substrate, a SiC substrate, an AlN composite material or a sapphire substrate; the sacrificial carrier layer includes SiC, GaN, AlN, InN, AlGaN, InGaN, BN, BAlN, ScN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof; the sacrificial carrier layer has a thickness of more than 100 nm; @The single crystal nucleation layer includes SiC, GaN, AlN, AlGaN, ScN, BN, HfN, ZrN, InN, Si, Ge, TiN or their alloys, and oxide-based materials, wherein the oxide-based materials include Ga2O3, Al2O3, MgO and their alloys: ◆The single crystal nucleation layer has a thickness of 5nm to 100nm; and / or ◆Has a thermal conductivity of 5 to 600 W / m·K; The single crystal device layer comprises SiC, GaN, AlN, InN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, or comprises a multilayer structure comprising a 25nm AlGaN layer or a 3nm GaN-20nm AlGaN-GaN layer or a GaN-InGaN-GaN layer combination on GaN, and the single crystal device layer has a thickness of up to 5000nm; and The one or more transition layers include one or more of SiC, AlN, GaN, AlGaN or AlGaN / AlGaN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, and the one or more transition layers include: ◆5nm to 200nm thick AlN or AlGaN layer with 3D morphology and grown on a SiC or sapphire substrate for subsequent growth of GaN sacrificial carrier layer; ◆On the Si substrate, an AlN transition layer is first formed, followed by a GaN / AlN superlattice transition layer for the subsequent growth of a GaN sacrificial carrier layer; ◆On the Si substrate, an AlN transition layer is first formed, and then an AlN / AlGaN / GaN gradient alloy transition layer is formed for the subsequent growth of a GaN sacrificial carrier layer.

14. A layered precursor manufactured by the method described in any one of claims 1 to 13, which is subsequently used to prepare a semiconductor substrate on diamond, the precursor comprising, in sequence, a base substrate, a sacrificial single crystal semiconductor carrier layer, a single crystal nucleation layer arranged to nucleate diamond growth, a single crystal semiconductor device layer or a semiconductor device multilayer structure.

15. The layered precursor according to claim 14 further includes one or more transition layers between the base substrate and the sacrificial carrier layer, and the one or more transition layers are arranged to facilitate the transition from the base substrate to the sacrificial carrier layer, wherein facilitating the transition includes alleviating the strain or nucleation growth of the sacrificial carrier layer or both.

16. The layered precursor according to claim 15, wherein @The base substrate includes a Si substrate, a SiC substrate, an AlN composite material or a sapphire substrate; The sacrificial carrier layer includes SiC, GaN, AlN, InN, AlGaN, InGaN, BN, BAlN, ScN, Si and its alloys, Ga2O3, Al2O3, MgO and its alloys; The sacrificial carrier layer has a thickness of more than 100 nm; @The single crystal nucleation layer includes SiC, GaN, AlN, AlGaN, ScN, BN, HfN, ZrN, InN, Si, Ge, TiN or their alloys, and oxide-based materials, wherein the oxide-based materials include Ga2O3, Al2O3, MgO and their alloys: ◆The single crystal nucleation layer has a thickness of 5nm to 100nm; and / or ◆Has a thermal conductivity of 5 to 600 W / m·K; The single crystal device layer comprises SiC, GaN, AlN, InN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, or comprises a multilayer structure comprising a 25nm AlGaN layer or a 3nm GaN-20nm AlGaN-GaN layer or a GaN-InGaN-GaN layer combination on GaN, the single crystal device layer having a thickness of up to 5000nm; and The one or more transition layers include one or more of SiC, AlN, GaN, AlGaN, or AlGaN / AlGaN, BN, Si and alloys thereof, Ga2O3, Al2O3, MgO and alloys thereof, and the one or more transition layers include: ◆5nm to 200nm thick AlN layer with 3D morphology and grown on SiC or sapphire substrate for the subsequent growth of GaN sacrificial carrier layer; ◆On the Si substrate, an AlN transition layer is first formed, followed by a GaN / AlN superlattice transition layer for the subsequent growth of a GaN sacrificial carrier layer; ●On the Si substrate, an AlN transition layer is first formed, and then an AlN / AlGaN / GaN gradient alloy transition layer is formed for the subsequent growth of a GaN sacrificial carrier layer.

17. The layered precursor according to claim 16, wherein: @The single crystal sacrificial carrier layer has a dislocation density less than a first threshold dislocation density; the single crystal nucleation layer has a dislocation density less than a second threshold dislocation density; and @The single crystal device layer or the semiconductor device multilayer structure has a dislocation density less than a third threshold dislocation density.

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