A method and device for improving read and write speed and NAND flash memory

Abstract

The embodiment of the present invention provides a method, device and NAND flash memory for improving the read and write speed. The NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one. The cycles of the N charging selection signals include a delay time. There is a time delay between the N charging selection signals. The delay time in the N charging selection signal cycles is superimposed to be equal to the wiring delay of the register selection signals of the N register areas. The method includes: receiving a register address; determining a register area to be read and written according to the register address; and setting the charging selection signal corresponding to the register area to be read and written to be effective. The present invention effectively reduces the time for SRAM to read and write registers, and greatly improves the speed of SRAM to read and write registers.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a method for improving reading and writing speed, a device for improving reading and writing speed, and a NAND flash memory. Background Art

[0002] NAND Flash is a non-volatile memory with advantages such as large storage capacity and high data throughput, and is widely used in various electronic products. NAND Flash reads and writes storage array units according to the Page capacity. Common Page capacities include 1KB / 2KB / 4KB / 16KB, etc. The number of NAND Flash registers is consistent with the Page capacity. Registers are used to store data input and output according to the read and write addresses. Thousands of registers in NAND Flash are arranged horizontally in sequence.

[0003] The prior art uses the following method to implement SRAM reading and writing registers: set the charge selection signal PREB' to be valid, charge the bus nodes Q and QB between the SRAM and the register, decode the register selection signal SELC' corresponding to the register according to the register address, set the register selection signal SELC' to be valid, connect the register corresponding to the register selection signal SELC' to the bus nodes Q and QB, and SRAM reads and writes the register. Among them, the circuit structure of NAND Flash reading and writing data from the register through SRAM is as follows Figure 1 shown.

[0004] The prior art method of reading and writing registers by SRAM also has the following defects: Since thousands of registers in NAND Flash are arranged horizontally in sequence, there is a fixed total wiring delay time tdly' between the register selection signal SELC1' with the closest wiring in NAND Flash and the register selection signal SELCN' with the farthest wiring. Since one SRAM in NAND Flash is connected to many registers, that is, the bus nodes Q and QB between the SRAM and the registers are connected to many registers, in order to ensure that the charging selection signal PREB' and the register selection signal SELCN' are not valid at the same time, the falling edge of the charging selection signal PREB' must cover the falling edge of the register selection signal SELCN' with the farthest wiring. At this time, the waveforms of the charging selection signal PREB', the register selection signal SELC1', and the register selection signal SELCN' are as shown below. Figure 2As shown in the figure, the cycle of the SRAM read and write register increases by tdly', and the speed of the SRAM read and write register slows down. In addition, the larger the Page capacity of the NAND Flash, the longer the routing of the register selection signal SELCN' will be. The larger the tdly', the longer the cycle of the SRAM read and write register will be, thus limiting the read and write frequency on the large-capacity NAND Flash interface. Summary of the invention

[0005] In view of the above problems, the purpose of the embodiments of the present invention is to provide a method for improving the reading and writing speed, a device for improving the reading and writing speed and a NAND flash memory to solve the problem of slow reading and writing speed in the way SRAM reads and writes registers in the prior art.

[0006] In order to solve the above problems, an embodiment of the present invention discloses a method for improving the read and write speed, which is applied to a NAND flash memory, wherein the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one by one, wherein the cycles of the N charge selection signals include a delay time, and there is a time delay between the N charge selection signals. The delay times in the cycles of the N charge selection signals are superimposed and equal to the total delay time of the register selection signal routing of the N register areas. The method includes:

[0007] Receive register address;

[0008] Determine the register area to be read and written according to the register address;

[0009] The charging selection signal corresponding to the register area to be read and written is set to be valid.

[0010] Optionally, determining a register area to be read or written according to the register address includes:

[0011] The register area to be read and written is determined according to the high K bit address of the register address; wherein N=2 K .

[0012] Optionally, the falling edge of the charging selection signal corresponding to the register area to be read or written is after the falling edge of the register selection signal of the Mth register in the register area to be read or written; the Mth register is the register with the farthest register selection signal routing in the register area to be read or written.

[0013] Optionally, the rising edge of the charging selection signal corresponding to the register area to be read or written is before the rising edge of the register selection signal of the first register in the register area to be read or written; the first register is the register closest to the register selection signal in the register area to be read or written.

[0014] In order to solve the above problems, an embodiment of the present invention further discloses a device for improving the read and write speed, which is applied to a NAND flash memory, wherein the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one by one, wherein the cycles of the N charge selection signals include a delay time, and there is a time delay between the N charge selection signals. The delay times in the cycles of the N charge selection signals are superimposed and equal to the total delay time of the register selection signal routing of the N register areas. The device includes:

[0015] A receiving module, used for receiving a register address;

[0016] A register area determination module, used to determine the register area to be read and written according to the register address;

[0017] The setting module is used to set the charging selection signal corresponding to the register area to be read and written to be valid.

[0018] Optionally, the register area determination module includes:

[0019] A register area determination unit is used to determine the register area to be read and written according to the high K bit address of the register address; wherein N=2 K .

[0020] Optionally, the falling edge of the charging selection signal corresponding to the register area to be read or written is after the falling edge of the register selection signal of the Mth register in the register area to be read or written; the Mth register is the register with the farthest register selection signal routing in the register area to be read or written.

[0021] Optionally, the rising edge of the charging selection signal corresponding to the register area to be read or written is before the rising edge of the register selection signal of the first register in the register area to be read or written; the first register is the register closest to the register selection signal in the register area to be read or written.

[0022] In order to solve the above problems, an embodiment of the present invention further discloses a NAND flash memory, wherein the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one, wherein the cycles of the N charging selection signals include delay times, and there is a time delay between the N charging selection signals. The delay times in the cycles of the N charging selection signals are superimposed and equal to the total delay time of the register selection signal routing of the N register areas.

[0023] Optionally, the N register areas are of the same size, and the delay time difference between the charging selection signals corresponding to two adjacent register areas is the total delay time of the register selection signal routing / N, and the total delay time of the register selection signal routing is the register selection signal routing delay between the register closest to the register selection signal routing in the N register areas and the register farthest from the register selection signal routing.

[0024] The embodiment of the present invention includes the following advantages: the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one, the cycles of the N charging selection signals include a delay time, there is a time delay between the N charging selection signals, and the delay times in the cycles of the N charging selection signals are superimposed to be equal to the total delay time of the register selection signal routing of the N register areas. After receiving the register address, the register area to be read and written is determined according to the register address, and then the charging selection signal corresponding to the register area to be read and written is set to be effective. In this way, the present invention selects the charging selection signal by region through the register address, and the delay time in the charging selection signal cycle is much smaller than the routing delay, which effectively reduces the time of the SRAM reading and writing register, greatly improves the speed of the SRAM reading and writing register, facilitates the improvement of the reading and writing frequency on the large-capacity NAND flash memory interface, and is simple to implement. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the circuit structure of NAND Flash reading and writing data from a register through SRAM in the prior art;

[0026] Figure 2 Schematic diagram of the waveform of the charging selection signal PREB', the waveform of the register selection signal SELC1' and the waveform of the register selection signal SELCN' in the prior art;

[0027] Figure 3 is a flow chart of steps of an embodiment of a method for improving reading and writing speed of the present invention;

[0028] Figure 4 is a flowchart of another method for improving reading and writing speed according to an embodiment of the present invention;

[0029] Figure 5 It is a structural block diagram of an embodiment of a device for improving reading and writing speed of the present invention;

[0030] Figure 6 It is a structural block diagram of another embodiment of a device for improving reading and writing speed of the present invention;

[0031] Figure 7 is a structural block diagram of a NAND flash memory embodiment of the present invention;

[0032] Figure 8 It is a schematic diagram of a circuit structure in which an SRAM reads data from a register in a NAND flash memory embodiment of the present invention;

[0033] Fig. 9 It is a timing diagram of SRAM reading and writing the first register in the first register area in a NAND flash memory embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] Reference Figure 3 , which shows a flow chart of steps of an embodiment of a method for improving read and write speed of the present invention, the method for improving read and write speed is applied to NAND flash memory, the NAND flash memory includes SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one, the cycle of the N charging selection signals includes a delay time, there is a time delay between the N charging selection signals, and the delay time in the N charging selection signal cycle is superimposed to equal the total delay time of the register selection signal routing of the N register areas. Among them, the N register areas are horizontally distributed in a row in sequence. N is an integer greater than or equal to 2.

[0036] Optionally, when the sizes of the N register areas are the same, the delay time difference of the charging selection signals corresponding to the two adjacent register areas is the total delay time of the register selection signal routing / N. The total delay time of the register selection signal routing is the register selection signal routing delay between the register with the closest register selection signal routing and the register with the farthest register selection signal routing in the N register areas.

[0037] For example, assuming that the N register areas are four register areas, and the four register areas are the same size, the total delay time of the register selection signal routing of the four register areas is tdly, then the delay time included in the cycle of the N charging selection signals is tdly / 4, and the delay time difference between the charging selection signals corresponding to two adjacent register areas is tdly / 4. At this time, the cycle of the N charging selection signals is reduced by 3tdly / 4.

[0038] Reference Figure 3 , the method may specifically include the following steps:

[0039] S1, receive register address.

[0040] The register address is the read and write address of the register.

[0041] S2, determining the register area to be read or written according to the register address.

[0042] For example, assuming that the N register areas are 2 register areas (a first register area and a second register area), if the register address is the address of the first register area, step S2 determines that the register area to be read and written is the first register area; if the register address is the address of the second register area, step S2 determines that the register area to be read and written is the second register area.

[0043] S3, setting the charge selection signal corresponding to the register area to be read and written to be valid.

[0044] Specifically, although the delay time in the charging selection signal cycle corresponding to the register area to be read and written in step S3 is much smaller than the total wiring delay time, since the size of the register area to be read and written is much smaller than the size of all registers in the NAND flash memory, the register selection signal routing delay between the register closest to the register selection signal routing in the register area and the register farthest from the register selection signal routing is also much smaller than the total wiring delay time. Therefore, after step S3, the SRAM can still correctly read and write the register area to be read and written. Since the delay time in the charging selection signal cycle corresponding to the register area to be read and written is much smaller than the total wiring delay time, the method for improving the read and write speed of the embodiment of the present invention effectively reduces the time for the SRAM to read and write registers, and greatly improves the speed of the SRAM to read and write registers.

[0045] Optionally, in another embodiment of the present invention, referring to Figure 4 Step S2 determines the register area to be read or written according to the register address, which may include:

[0046] S21, determine the register area to be read or written according to the high K bits of the register address; wherein N=2K .

[0047] For example, if N=2, that is, the NAND flash memory includes two register areas (a first register area and a second register area), then K=1. At this time, if the high K bit address of the register address is 0, step S21 determines that the register area to be read and written is the first register area, and if the high K bit address of the register address is 1, step S21 determines that the register area to be read and written is the second register area; or, if the high K bit address of the register address is 1, step S21 determines that the register area to be read and written is the first register area, and if the high K bit address of the register address is 0, step S21 determines that the register area to be read and written is the second register area.

[0048] Optionally, in one embodiment of the present invention, the falling edge of the charge selection signal corresponding to the register area to be read or written is after the falling edge of the register selection signal of the Mth register in the register area to be read or written; the Mth register is the register with the farthest register selection signal routing in the register area to be read or written. In this way, it can be ensured that when the register area to be read or written is read or written, the charge selection signal and the register selection signal will not be valid at the same time, thereby protecting the data in the register.

[0049] Optionally, in one embodiment of the present invention, the rising edge of the charge selection signal corresponding to the register area to be read or written is before the rising edge of the register selection signal of the first register in the register area to be read or written; the first register is the register with the closest register selection signal routing in the register area to be read or written. In this way, it can be ensured that when the register area to be read or written is read or written, the charge selection signal and the register selection signal will not be valid at the same time, thereby protecting the data in the register.

[0050] The method for improving the read and write speed of the embodiment of the present invention includes the following advantages: the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one, the cycle of the N charging selection signals includes a delay time, there is a time delay between the N charging selection signals, and the delay time in the N charging selection signal cycle is superimposed to be equal to the total delay time of the register selection signal routing of the N register areas. After receiving the register address, the register area to be read and written is determined according to the register address, and then the charging selection signal corresponding to the register area to be read and written is set to be effective. In this way, the present invention selects the charging selection signal by region through the register address, and the delay time in the charging selection signal cycle is much smaller than the routing delay. Even if the Page capacity of the NAND Flash and the total delay time of the register selection signal routing of the N register areas are large, the time of the SRAM reading and writing register can still be effectively reduced, and the speed of the SRAM reading and writing register is greatly improved, which is convenient for improving the reading and writing frequency on the large-capacity NAND flash memory interface, and the implementation is simple.

[0051] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0052] Reference Figure 5 , which shows a structural block diagram of an embodiment of a device for improving read / write speed of the present invention, the device for improving read / write speed is applied to NAND flash memory, the NAND flash memory includes SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one, the cycle of the N charging selection signals includes a delay time, there is a time delay between the N charging selection signals, and the delay time in the N charging selection signal cycle is superimposed to be equal to the total delay time of the register selection signal routing of the N register areas. Wherein, N is an integer greater than or equal to 2.

[0053] Optionally, in one embodiment of the present invention, the N register areas have the same size, and the delay time difference of the charging selection signals corresponding to two adjacent register areas is the total delay time of the register selection signal routing / N. The total delay time of the register selection signal routing is the register selection signal routing delay between the register with the closest register selection signal routing and the register with the farthest register selection signal routing in the N register areas.

[0054] Reference Figure 5 , the device for improving the reading and writing speed may specifically include the following modules:

[0055] The receiving module 1 is used for receiving a register address.

[0056] The register area determination module 2 is used to determine the register area to be read or written according to the register address.

[0057] The setting module 3 is used to set the charging selection signal corresponding to the register area to be read and written to be valid.

[0058] Optionally, in another embodiment of the present invention, referring to Figure 6 , the register area determination module 2 may include:

[0059] The register area determination unit 21 is used to determine the register area to be read and written according to the high K bits of the register address; wherein N=2 K .

[0060] Optionally, in one embodiment of the present invention, the falling edge of the charging selection signal corresponding to the register area to be read or written is after the falling edge of the register selection signal of the Mth register in the register area to be read or written; the Mth register is the register with the farthest register selection signal routing in the register area to be read or written.

[0061] Optionally, in one embodiment of the present invention, the rising edge of the charging selection signal corresponding to the register area to be read or written is before the rising edge of the register selection signal of the first register in the register area to be read or written; the first register is the register closest to the register selection signal in the register area to be read or written.

[0062] The device for improving the read and write speed of the embodiment of the present invention includes the following advantages: the NAND flash memory includes SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one, the cycle of the N charging selection signals includes a delay time, there is a time delay between the N charging selection signals, and the delay time in the N charging selection signal cycle is equal to the total delay time of the register selection signal routing of the N register areas after superposition. After receiving the register address, the register area to be read and written is determined according to the register address, and then the charging selection signal corresponding to the register area to be read and written is set to be effective. In this way, the present invention selects the charging selection signal by region through the register address, and the delay time in the charging selection signal cycle is much smaller than the routing delay. Even if the Page capacity of the NAND Flash and the total delay time of the register selection signal routing of the N register areas are large, the time of the SRAM reading and writing register can still be effectively reduced, and the speed of the SRAM reading and writing register is greatly improved, which is convenient for improving the reading and writing frequency on the large-capacity NAND flash memory interface, and the implementation is simple.

[0063] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0064] Reference Figure 7 , which shows a block diagram of a NAND flash memory embodiment of the present invention. The NAND flash memory includes an SRAM, N register areas (e.g., a first register area, ..., an Nth register area) connected to the SRAM, and N charging selection signals (e.g., a first charging selection signal PREB1, ..., an Nth charging selection signal PREBN) corresponding to the N register areas one by one, the cycles of the N charging selection signals include a delay time, the N charging selection signals have a time delay with each other, and the delay times in the N charging selection signal cycles are superimposed to be equal to the total delay time of the register selection signal routing of the N register areas. Wherein, N is an integer greater than or equal to 2.

[0065] Specifically, when the SRAM reads and writes N register areas, it first receives the register address, then determines the register area to be read and written according to the register address, and then sets the charge selection signal corresponding to the register area to be read and written to be valid. Since the delay time in the charge selection signal cycle corresponding to the register area to be read and written is much shorter than the total wiring delay time, the NAND flash memory of the embodiment of the present invention can effectively reduce the time of the SRAM reading and writing registers, and greatly improve the speed of the SRAM reading and writing registers.

[0066] Optionally, in one embodiment of the present invention, the NAND flash memory can determine the register area to be read and written according to the register address through a decoder, wherein the decoder can determine the register area to be read and written according to the high K bit address of the register address. Optionally, in one embodiment of the present invention, the NAND flash memory can delay N charge selection signals through a delay circuit so that there is a time delay between the N charge selection signals. Optionally, in one embodiment of the present invention, the NAND flash memory can select the charge selection signal corresponding to the register area to be read and written through a selector, and set the charge selection signal corresponding to the register area to be read and written to be valid.

[0067] Optionally, in one embodiment of the present invention, the N register areas have the same size, and the delay time difference of the charging selection signals corresponding to two adjacent register areas is the total delay time of the register selection signal routing / N. The total delay time of the register selection signal routing is the register selection signal routing delay between the register with the closest register selection signal routing and the register with the farthest register selection signal routing in the N register areas.

[0068] Optionally, in one embodiment of the present invention, the falling edge of the charge selection signal is after the falling edge of the register selection signal of the Mth register in the corresponding register area; the Mth register is the register with the farthest register selection signal routing in the register area.

[0069] Optionally, in one embodiment of the present invention, the rising edge of the charge selection signal is before the rising edge of the register selection signal of the first register in the corresponding register area; the first register is the register in the register area that is closest to the register selection signal routing.

[0070] In one embodiment of the present invention, the circuit structure of the SRAM in the NAND flash memory reading data from the register can be as follows: Figure 8 As shown, the PREB signal is a charge selection signal corresponding to the register area to be read or written among the N charge selection signals, and the SELC signal is a register selection signal corresponding to the register to be read or written. It is assumed that the NAND flash memory includes four register areas (a first register area, a second register area, a third register area, and a fourth register area), the N charge selection signals are PREB1, PREB2, PREB3, and PREB4, and the NAND flash memory includes W registers (a first register, ..., a Wth register).

[0071] Example Figure 8 The process of reading and writing the first register in the first register area of ​​SRAM is:

[0072] SRAM reads the first register: the charging selection signal PREB1=0, the power supply charges the bus nodes Q and QB between the SRAM and the first register to the voltage VDD. The selection signal SELC1 of the first register=1, if FLG=0, INV=1, the bus node Q discharges FLG, and the bus node QB voltage is maintained at VDD. The selection signal SELC1 of the first register=0, the SRAM amplifies the voltage difference of QB-Q (for example, 100mv) to a full-swing signal "0" and outputs it through DOUT. The selection signal SELC of the first register=1, if FLG=1, INV=0, the bus node Q is maintained at VDD, and the bus node QB discharges INV. The selection signal SELC1 of the first register=0, the SRAM amplifies the voltage difference of Q-QB to a full-swing signal "1" and outputs it through DOUT.

[0073] SRAM writes the first register: the charging selection signal PREB1 = 0, the power supply charges the bus nodes Q and QB between the SRAM and the first register to the voltage VDD. The selection signal SELC1 of the first register = 1, if DIN = 0, the SRAM discharges the bus node Q voltage to 0, and the bus node QB is maintained at VDD, thereby inputting 0 to FLG, SELC1 is closed, and the writing of "0" is completed.

[0074] Turn on SELC1. If DIN=1, SRAM discharges QB to 0, Q remains at VDD, and thus 1 is input to FLG. SELC1 is turned off, completing writing "1".

[0075] Among them, the timing of SRAM reading and writing the first register is as follows Fig. 9 As shown, the cycle (trd) of PREB1 is the cycle of the SRAM read and write register, which is composed of the minimum high level time (th) of SELC1, the minimum low level time (tl) of PREB1 and the delay time (total routing delay time / 4). The minimum high level time of SELC1 is limited by the read accuracy of the SRAM. For example, if the read accuracy of the SRAM is 100mV, the minimum high level time (th) of SELC1 is the time for the bus nodes Q and QB to discharge to a voltage difference of 100mV. The minimum low level time of PREB1 is limited by the time it takes for PREB1 to recharge the bus node Q voltage and QB voltage back to the voltage VDD. Since the delay time is only 1 / 4 of the total routing delay time, the cycle of PREB1 is effectively reduced, that is, the speed of the SRAM reading and writing the first register is effectively improved. Fig. 9 In the figure, tdly is the total delay time of the routing.

[0076] The NAND flash memory of the embodiment of the present invention includes the following advantages: the NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one, the cycle of the N charging selection signals includes a delay time, there is a time delay between the N charging selection signals, and the delay time in the N charging selection signal cycles is superimposed to be equal to the total delay time of the register selection signal routing of the N register areas. After receiving the register address, the register area to be read and written is determined according to the register address, and then the charging selection signal corresponding to the register area to be read and written is set to be effective. In this way, the present invention selects the charging selection signal by region through the register address, and the delay time in the charging selection signal cycle is much smaller than the routing delay. Even if the Page capacity of the NAND Flash and the total delay time of the register selection signal routing of the N register areas are large, the time of the SRAM reading and writing register can still be effectively reduced, and the speed of the SRAM reading and writing register is greatly improved, which is convenient for improving the reading and writing frequency on the large-capacity NAND flash memory interface, and the implementation is simple.

[0077] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0078] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0079] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0083] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0084] A method and a device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for improving read and write speed, applied to a NAND flash memory, wherein the NAND flash memory comprises an SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one by one, wherein the cycles of the N charge selection signals comprise delay times, and there are time delays between the N charge selection signals, and the delay times in the cycles of the N charge selection signals are superimposed to be equal to the total delay time of the register selection signal routing of the N register areas, wherein: The method comprises: Receive register address; Determine the register area to be read and written according to the register address; The charging selection signal corresponding to the register area to be read and written is set to be valid.

2. The method according to claim 1, characterized in that The step of determining the register area to be read or written according to the register address comprises: Determine the register area to be read and written according to the high K bits of the register address; wherein N= .

3. The method according to claim 1, characterized in that The falling edge of the charging selection signal corresponding to the register area to be read or written is after the falling edge of the register selection signal of the Mth register in the register area to be read or written; the Mth register is the register with the farthest register selection signal routing in the register area to be read or written.

4. The method according to claim 3, characterized in that The rising edge of the charging selection signal corresponding to the register area to be read or written is before the rising edge of the register selection signal of the first register in the register area to be read or written; the first register is the register closest to the register selection signal in the register area to be read or written.

5. A device for improving read and write speed, applied to NAND flash memory, the NAND flash memory includes SRAM, N register areas connected to the SRAM, and N charge selection signals corresponding to the N register areas one by one, the cycle of the N charge selection signals includes a delay time, there is a time delay between the N charge selection signals, the delay time in the cycle of the N charge selection signals is superimposed to be equal to the total delay time of the register selection signal routing of the N register areas, characterized in that: The device comprises: A receiving module, used for receiving a register address; A register area determination module, used to determine the register area to be read and written according to the register address; The setting module is used to set the charging selection signal corresponding to the register area to be read and written to be valid.

6. The device according to claim 5, characterized in that The register area determination module comprises: A register area determination unit, used to determine the register area to be read and written according to the high K bits of the register address; wherein N= .

7. The device according to claim 5, characterized in that The falling edge of the charging selection signal corresponding to the register area to be read or written is after the falling edge of the register selection signal of the Mth register in the register area to be read or written; the Mth register is the register with the farthest register selection signal routing in the register area to be read or written.

8. The device according to claim 7, characterized in that The rising edge of the charging selection signal corresponding to the register area to be read or written is before the rising edge of the register selection signal of the first register in the register area to be read or written; the first register is the register closest to the register selection signal in the register area to be read or written.

9. A NAND flash memory, characterized in that: The NAND flash memory includes an SRAM, N register areas connected to the SRAM, and N charging selection signals corresponding to the N register areas one by one. The cycles of the N charging selection signals include delay times. There is a time delay between the N charging selection signals. The delay times in the cycles of the N charging selection signals are superimposed to be equal to the total delay time of the register selection signal routing of the N register areas.

10. The NAND flash memory according to claim 9, wherein: The N register areas have the same size, and the delay time difference of the charging selection signals corresponding to two adjacent register areas is the total delay time of the register selection signal routing of the N register areas / the total delay time of the N routings.

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