Method for vertically wiring logic cells incorporating stacked transistors in a three-dimensional logic device

Abstract

A semiconductor device comprises: a substrate having a substantially flat surface; a first logic gate disposed on the substrate and comprising a first field effect transistor (FET) having a first channel and a first pair of source-drain regions; a second logic gate stacked above the first logic gate in a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel and a second pair of source-drain regions; and a contact electrically connecting the source-drain regions of the first FET to the source-drain regions of the second FET such that at least a portion of a current flowing between the first logic gate and the second logic gate will flow in the vertical direction.

Description

[0001] Incorporation by reference

[0002] This disclosure claims the benefit of U.S. Provisional Application No. 62 / 727096, filed on September 5, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method for significant area scaling of logic standard cells through vertical wiring of floating stacked transistors and source / drain electrodes. Background Art

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. To the extent that the work of the present inventors is described in this background section, as well as aspects of this description that may not be identified as prior art at the time of filing, no explicit or implicit admission is made that it is prior art against the present disclosure.

[0005] When manufacturing semiconductor devices (especially at a microscopic scale), various manufacturing processes are performed, such as film deposition, etch mask creation, patterning, material etching and removal, and doping treatment. These processes are repeated to form the desired semiconductor device elements on the substrate. Historically, microfabrication has been used to create transistors on a plane and to form wiring / metallization above the active device plane, and therefore, this is characterized as a two-dimensional (2D) circuit or 2D production. Although miniaturization has greatly increased the number of transistors per unit area in 2D circuits, as miniaturization enters nanoscale semiconductor device production nodes, miniaturization will also face greater challenges. Semiconductor device manufacturers have expressed expectations for three-dimensional (3D) semiconductor circuits in which transistors and devices are stacked on top of each other. Summary of the invention

[0006] The present disclosure relates to a semiconductor device, comprising: a substrate having a substantially flat surface; a first logic gate, which is disposed on the substrate and includes a first field effect transistor (FET) having a first channel and a first pair of source-drain regions; a second logic gate, which is stacked above the first logic gate in a vertical direction perpendicular to the surface of the substrate, the second logic gate including a second FET having a second channel and a second pair of source-drain regions; and a contact, which electrically connects the source-drain region of the first FET to the source-drain region of the second FET, so that at least a portion of the current flowing between the first logic gate and the second logic gate will flow along the vertical direction.

[0007] The present disclosure further relates to a combinational logic unit, comprising: a substrate having a substantially flat surface; a plurality of logic gates stacked relative to each other along a vertical direction perpendicular to the surface of the substrate; and a contact extending along the vertical direction and electrically connecting an output terminal of one of the plurality of logic gates to an input terminal of another of the plurality of logic gates, such that at least a portion of a current flowing between the plurality of logic gates will flow along the vertical direction.

[0008] The present disclosure further relates to a semiconductor device, comprising: a substrate; a first field effect transistor (FET), which is arranged on the substrate in a first level and includes a first channel, a first gate structure, a first source electrode and a first drain electrode; a second FET, which is vertically stacked above the top of the first FET perpendicular to the plane of the substrate in the second level and includes a first channel, a first gate structure, a first source electrode and a first drain electrode; and a current source, which is electrically connected to the first source electrode or the first drain electrode of the first FET, wherein the current provided by the current source flows through the first FET in the first level, and the current leaving the first source electrode of the first FET or the first drain electrode of the first FET flows vertically upward toward the second level into the first source electrode of the second FET or the first drain electrode of the second FET.

[0009] The present disclosure also relates to a semiconductor device, wherein a first layer is composed of more than one adjacent field effect transistor (FET) and corresponding source and drain electrodes; a second layer is composed of more than one adjacent field effect transistor (FET) and corresponding source and drain electrodes, wherein a current provided from a current source flows through multiple FETs in the first layer, and a current leaving the source electrode of the first layer flows vertically upward toward the second layer.

[0010] It should be noted that the Summary of the Invention section does not specify all embodiments and / or incremental novel aspects of the disclosed or claimed invention. Instead, the Summary of the Invention only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives of the present invention and embodiments, the reader should consult the Detailed Description section of the disclosure and corresponding drawings as further discussed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various embodiments of the present disclosure, presented as examples, will be described in detail with reference to the following drawings, in which like reference numerals refer to like elements, and in which:

[0012] FIG. 1 illustrates a layout of a logic standard cell incorporating a buried Vss power rail and a buried Vdd power rail according to an embodiment of the present disclosure.

[0013] FIG. 2 is a schematic diagram showing the flow of current through a logic standard cell according to an embodiment of the present disclosure.

[0014] 3 shows a layout of an AOI standard cell incorporating a complementary FET (CFET) architecture, wherein NMOS and PMOS are stacked on top of each other, according to an embodiment of the present disclosure.

[0015] FIG. 4 is a schematic diagram showing current flow through an AOI standard cell having stacked NMOS and PMOS according to an embodiment of the present disclosure.

[0016] Figure 5A A schematic diagram of a vertically stacked gate cell incorporating vertically stacked transistors in which the lateral span of a standard cell fits within a single contact gate pitch is shown according to an embodiment of the present disclosure.

[0017] Figure 5B The current flow through a vertically stacked gate cell is shown according to an embodiment of the present disclosure.

[0018] Figure 5C A circuit diagram of a vertically stacked gate cell according to an embodiment of the present disclosure is shown.

[0019] Figure 5D The current flow through parallel vertically stacked gate cells is shown according to an embodiment of the present disclosure.

[0020] Figure 5E Mixed horizontal and vertical current flow through parallel vertically stacked gate cells is shown according to an embodiment of the present disclosure.

[0021] Figure 6 A schematic diagram of a vertically stacked gate cell with CFET-based stacked NMOS and PMOS architecture is shown according to an embodiment of the present disclosure.

[0022] Figure 7 A Vss and Vdd input side view of a three-level vertically stacked gate cell according to an embodiment of the present disclosure is shown.

[0023] Figure 8 A transistor side view of a three-level vertically stacked gate cell according to an embodiment of the present disclosure is shown.

[0024] Fig. 9 The embodiment according to the present disclosure is shown Figure 7 Side view of the Vss and Vdd inputs and opposite views of the NMOS S / D electrodes and PMOS S / D electrodes. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse the reference numerals in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. Further, for ease of description, spatially related terms such as "top", "bottom", "under", "below", "lower", "above", "upper" and the like may be used herein to describe the relationship between an element or feature and one or more other elements or features as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially related terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted in the same manner accordingly.

[0026] For the sake of clarity, the discussion order of the different steps described herein has been proposed. Generally, these steps can be performed in any suitable order. In addition, although each different feature, technology, configuration, etc. in this article may be discussed in different places of this disclosure, it is intended that each concept can be performed independently of each other or in combination with each other. Therefore, the present invention can be implemented and viewed in many different ways.

[0027] Area scaling of CMOS devices is beginning to reach the following limits: for the 3nm node, almost all conventional methods for reducing the track height of standard cells will be exhausted. Currently, most standard cell designs are based on a height of 6 to 7 track cells, and active work on so-called scaling boosters has paved the way for an eventual reduction to a height of 4 track cells. To achieve this, many new integration solutions have been developed and adopted by the industry. Such solutions include: (a) buried power rails, (b) active gate contacts, (c) single diffusion fusion cuts, (d) the number of FINs in both PMOS and NMOS is reduced to two FINs, and if variability can be resolved, it is expected to be reduced to a single FIN for both NMOS and PMOS, and (e) complete self-alignment of metal layers with vias.

[0028] It is believed that even for CFET devices, further reductions in the track height direction may prove difficult, and any scaling beyond that must come from reductions in the contacted gate pitch (CPP). Conventional scaling of the CPP also has fundamental limitations: the physical gate size cannot be extended downward below 10nm, and the low-k spacers used to maintain dielectric isolation between the metal gate and the metal source and drain contacts must be kept to a finite width.

[0029] The technology herein relates to a method for significantly scaling the area of ​​a logic standard cell by vertically wiring the device with a series of floating gates and source and drain electrodes stacked vertically on top of each other. Each transistor can be considered a "layer" or "level" of the device, and the current flowing through the device extends from the lower "layer" or "level" that supplies power to the device through the upward buried power rails in the device to the upper layer that can be connected to the interconnect line. This means that CPP pitch scaling can be accomplished by stacking transistors on top of each other in a stacked level configuration in a common standard cell. Therefore, from an area scaling perspective, although multiple transistors are stacked vertically in the common CPP space, a single CPP is used. For more complex standard cell designs incorporating a greater number of transistors, multiple transistors may be placed on lower and upper levels such that a certain balance may be achieved between the overall height of the transistor stack (which is related to the initial monolithic fin height) and the ratio of CPP reduction; thus, a standard cell consisting of, for example, six NMOS transistors and six PMOS transistors may be combined into three levels, with each level consisting of two adjacent common gates including both NMOS and PMOS transistors.

[0030] FIG1 shows a layout for a logic standard cell 100 incorporating a buried Vss power rail 105 and a buried Vdd power rail 110 according to an embodiment of the present disclosure. The logic standard cell 100 (e.g., an AND-OR-NOT (AOI) cell) can be designed such that nFETs and pFETs pass through a sequential sequence of gate electrodes, source electrodes, and drain electrodes, with current substantially traveling from one end to the other, such as along an east / west direction or a lateral direction (as shown). Given a planar substrate on which the structure is disposed, the east / west direction or the lateral direction can be interpreted as a direction along a plane parallel to the substrate.

[0031] 2 shows a schematic diagram of current flow through a logic standard cell 100 according to an embodiment of the present disclosure. For CMOS devices, nFETs and pFETs are arranged laterally adjacent to each other throughout the logic standard cell 100, which can be laid out in a lateral direction relative to the general current flow (as shown). For simplicity, all connections to the actual gate electrode are removed to focus on the current supplied to the individual source and drain contacts.

[0032] FIG3 shows a layout of an AOI standard cell 300 incorporating a complementary FET (CFET) architecture in accordance with an embodiment of the present disclosure, wherein NMOS and PMOS are stacked on top of each other. Another approach includes a CFET-enabled approach in which the nFET channel and the pFET channel are stacked on top of each other, rather than laterally adjacent to each other, in an attempt to scale the north / south or vertical orientation of the standard cell by up to, for example, 50%. Conventional logic scaling boosters may also be used for the CFET, thereby reducing the track height of the AOI standard cell 300 to as few as 3 tracks, as shown in FIG3 .

[0033] 4 shows a schematic diagram of current flow through an AOI standard cell 300 with stacked NMOS and PMOS according to an embodiment of the present disclosure. Stacking the source and drain electrodes enables sharing between NMOS and PMOS on a common track. Combined with the channels stacked on top of each other, this enables the formation of a four track height AOI standard cell 300. As with conventional logic, CFET current flow is still typically in the east / west direction; the main difference compared to conventional logic is that in the case of CFETs, the currents of nFET and pFET are on top of each other. In another embodiment, a three track height AOI standard cell 300 can be achieved by using, for example, a mid-track handshake.

[0034] The CFET takes advantage of stacking an NMOS channel and a PMOS channel directly on top of each other. For the case of a nanosheet CFET device, the cell height is not affected by the need to accommodate multiple fin pitches, and because the source and drain electrodes and the gate electrodes can be "staggered" or "stair-stepped," connections can be made from either NMOS or PMOS to common metal tracks in the back-end of line (BEOL), alleviating the need to reserve multiple tracks specifically for routing between NMOS and PMOS. An example is shown in FIG3 , where the ZN line is connected to the source and drain contacts 305 of the PMOS and the source and drain contacts 310 of the NMOS.

[0035] Even for CFET devices, CFET devices still consist of a series of gate electrodes and source and drain electrodes arranged in a lateral direction. Considering the effective current flow through the device, this is similar to a standard CMOS FET design, where the current flowing through the nFET channel and the pFET channel generally flows in an east / west direction, except that both currents flow vertically above each other. Since CFETs are able to reduce the track height in a standard cell to, for example, 3 or 4 tracks, the focus of continued scaling must be on reducing the contacted gate pitch (CPP).

[0036] The technology herein includes methods for stacking gate structures so that current flow within a standard cell can be routed upward within a three-dimensional device rather than outward (e.g., in a fin field effect transistor (FINFET) device). That is, the device can be layered into multiple levels or layers so that each level or layer can be a separate transistor and source and drain pair (see Figure 5A ).

[0037] Figure 5A A schematic diagram of a vertically stacked gate cell 500 incorporating a vertically stacked transistor 505 in accordance with an embodiment of the present disclosure is shown, in which the lateral span of a standard cell fits within a single contact gate pitch. In an embodiment, Figure 5A Internal wiring within a vertically stacked gate cell 500 is shown, which may be formed by internal via connections made between stacked source electrodes and stacked drain electrodes, and internal vias connecting a portion of the stacked source electrodes and a portion of the stacked drain electrodes to a metallization layer 510, or each layer or level may consist of multiple transistors and source and drain contacts to scale the overall CPP of a more complex standard cell.

[0038] Power to the source and drain can be supplied by, for example, a buried power rail. The power rail can supply an input that enters the first transistor labeled B on the NMOS side and passes through both B and A1 on the PMOS side. Vdd can be fed into the two levels of the device by forming a through-hole connection between the source electrode and the drain electrode at the first level and the second level on the PMOS side. Alternatively, a given device can be created by simply merging or shorting the source and drain electrodes of the PMOS at the first level and the second level. In another example, power can alternatively be supplied from the power rail at the metallization layer 510. For example, current flow can be sent downward through a level consisting of vertically stacked transistors 505 and source and drain electrodes, and is vertically routed to an output line that connects the bottom level to the output track at the metallization layer 510.

[0039] The output of the first-level vertical stacked transistor 505 is then passed upward on the PMOS side to the metal line at the metallization layer 510, which can be used to combine the outputs in the entire vertical stacked gate unit 500, and then the output of the first-level transistor is passed upward on the NMOS side to the inputs on the second and third levels of the vertical stacked gate unit 500.

[0040] Figure 5B The flow of current through a vertically stacked gate cell 500 is shown according to an embodiment of the present disclosure. Figure 5C 1 shows a circuit diagram of a vertically stacked gate unit 500 according to an embodiment of the present disclosure. In an embodiment, Figure 5B It is shown that the current no longer flows through the entire cell in a lateral direction, such as the logic standard cell 100 of FIG. 2 ; instead, the current flows only in a lateral direction through each vertically stacked transistor 505. Notably, the general current is then directed vertically upward to the next level or layer, where the current passes through the next vertically stacked transistor 505, and in this manner continues in an upward direction through the vertically stacked gate cell 500. For example, the vertically stacked transistors 505 may include a first vertically stacked transistor 505a, a second vertically stacked transistor 505b, and a third vertically stacked transistor 505c, wherein the first vertically stacked transistor 505a may be disposed below (and substantially or partially vertically aligned with) the second vertically stacked transistor 505b, and the second vertically stacked transistor 505b may be disposed below (and substantially or partially vertically aligned with) the third vertically stacked transistor 505c. The vertically stacked transistor 505 may include six source electrodes and drain electrodes (two source electrodes and drain electrodes are arranged on each transistor) and six channels arranged between each pair of source electrodes and drain electrodes, all of which are staggered relative to each other so as to provide connections inside the vertically stacked gate unit 500 and from the source electrodes and drain electrodes to the wiring tracks in the BEOL. The current can, for example, flow horizontally from left to right through the first vertically stacked transistor 505a (as shown in the figure), and can be directed vertically upward to flow through the second vertically stacked transistor 505b (as shown in the figure) from right to left. Subsequently, the current can be directed vertically upward again to flow through the third vertically stacked transistor 505c (as shown in the figure) from left to right again. In general, this produces a current flow in a generally upward vertical direction. It can be understood that more or fewer vertically stacked transistors 505 can be envisioned in the vertically stacked gate unit 500, and these transistors can be connected in a manner electrically connected to all vertically stacked transistors 505.

[0041] It is noteworthy that the current travels upward within the vertical stacked gate cell 500 by ascending layers or levels, where each layer or level is a separate vertical stacked transistor 505 that is physically separated from the vertical stacked transistor 505 below by incorporating a dielectric film. In the vertical stacked gate cell 500, each metal gate in the vertical stacked transistor 505 has a separate path to obtain input from the upper metal layer, so that the gate electrodes are staggered or stepped in the following manner: there is a connection point for each vertical stacked transistor 505 to a separate metal track. In this way, a given vertical stacked gate cell 500 can reduce the CPP to a single pitch in the lateral direction. In order to accommodate the independent metal gate connection to the BEOL, the track height of the standard cell can be increased. Therefore, although the vertical stacked gate cell 500 may not provide a direct, for example, 50% area scaling improvement relative to a fully scaled CFET device, it can provide some additional area scaling compared to the CFET because a trade-off is made between how much CPP reduction is achieved and the impact of the track height. For example, a typical CPP for a 7nm node might be as high as 50nm, while the critical metal pitch for the same device will be about 32nm. Therefore, any reduction in a single CPP that trades off the need to extend the track height of the cell by 1 critical metal pitch can still save a significant amount of area.

[0042] In an embodiment, it is beneficial to electrically isolate each vertically stacked transistor 505 from each other, which can be achieved by: (1) selective deposition of high-k into the channel, (2) forming a gap oxide between the channel and the high-k by driving oxygen through the high-k film, and (3) selective deposition of metal liner, barrier, and work function materials directly onto the conductor material that was previously selectively deposited onto the channel, rather than onto the dielectric material within the open replacement high-k metal gate (HKMG).

[0043] In an embodiment, a combination of anisotropically etched metals such as ruthenium or tungsten is used as the metal fill within the HKMG structure, enabling cutouts to be formed directly in each gate "stack" of a "level", which enables the formation of a staggered gate pattern that provides independent paths to the gate from the metal layers in the BEOL.

[0044] In an embodiment, a metal may be incorporated into the HKMG stack that has the ability to support selective deposition of dielectric films directly onto the metal surface. This may be beneficial for forming a controlled amount of dielectric isolation between any two stacked vertically stacked transistors 505 in order to control the capacitance between the vertically stacked transistors 505.

[0045] Common CMOS logic standard cell designs have a range in lateral CPP or gate pitch. The range of lateral CPP may be as low as one for inverters, three to four for AOI cells, and more than twelve for multiplexers (MUX) and flip-flop cells. For example, stacking twelve transistors on top of each other puts a lot of pressure on the initial fin height (e.g., silicon / silicon germanium fins), which can be used for integration of single devices and nanosheet channels. Increasing this initial fin height may cause manufacturing problems associated with fin bending, or changes between the size of the upper intended channel and the lower channel within the fin superlattice, and the height of these fins can generally be contained within the desired aspect ratio range with respect to fin height and fin width.

[0046] In an embodiment, a device including more than three gates may use a stacking layout of two CPPs, wherein the stacking height of the device remains at two or three levels, but may be stacked across two different sets of vertically stacked transistors 505. This also provides a method for how to make the overall layout close to the same level height for the case of multiple standard cells with different gate counts.

[0047] In an embodiment, elements of east / west wiring and north / south wiring may be combined.Instead of stacking all transistors within a standard cell on top of each other, a predetermined number of transistors may be stacked vertically into a predetermined number of vertical stacks, wherein each of the predetermined number of vertical stacks may involve a predetermined CPP pitch. Figure 5D The current flow through the parallel vertical stacked gate cells 598 according to an embodiment of the present disclosure is shown. In an embodiment, the parallel vertical stacked gate cells 598 may include multiple vertical stacked gate cells 500, each of which is arranged adjacent to each other in the lateral direction. It is worth noting that the current in the parallel vertical stacked gate cells 598 still generally flows in the vertical direction, but can be routed laterally across multiple groups of vertical stacked gate cells 500. For example, a six-transistor logic cell (parallel vertical stacked gate cells 598) can be made by using two groups of vertical stacked gate cells 500, where each group of vertical stacked gate cells 500 can include three vertically stacked transistors 505. The standard cell will have a significant CPP reduction from an initial "cell length" of seven CPP (including six transistors with a single diffusion cutoff between adjacent standard cells on the left and right) to a cell length of three CPP (including two vertical stacked gate cells 500 each consisting of three vertically stacked transistors 505 with a single diffusion cutoff between adjacent cells on the left and right).

[0048] Advantages of having multiple groups of vertically stacked transistors 505 within a cell design include allowing easier connections in the event that a signal output from the gate side of the source / drain contact is to be used as an input to a transistor, and routing of such signals will be much easier in terms of signal routing and complexity. In this example, the output from the drain side source / drain on the lower level or layer can be pulled up to the metallization layer 510, where it can then be easily passed to any vertically stacked transistor 505 within any vertically stacked gate cell 500 through a via-gate structure that is connected to the transistor 505. Thus, each level of the device can be designed to have a predetermined function, which is then performed within the cell until the next level. It will be understood that more than two groups can be included in the parallel vertically stacked gate cells 598, and each vertically stacked gate cell 500 can include more or less than three vertically stacked transistors 505. For example, 3, 100, or 1000 groups of vertically stacked gate cells 500 can be arranged adjacent to each other. For example, 2, 10, or 100 vertically stacked transistors 505 may be included in the vertically stacked gate unit 500 .

[0049] CMOS logic incorporates a design where the output of a particular vertically stacked transistor 505 can be used as the input of several other transistors. In such a design, efficient signal routing from the source / drain output terminals to the input side of multiple source / drain contacts is desired. To eliminate inter-cell wiring congestion within parallel vertically stacked gate cells 598, some wiring congestion can be alleviated by incorporating wiring elements within the vertically stacked interconnect structures themselves, where the vias connecting multiple levels of parallel vertically stacked gate cells 598 can have similar functions as tracks from metallization layers 510 within other cell designs. Figure 5EA mixed horizontal and vertical current flow through the parallel vertical stacked gate cells 598 is shown. In an embodiment, the routing of output signals from the output of the vertically stacked transistors 505 to multiple inputs can be performed by the internal wiring of the interconnect structure within the device. The signal flow within each level of the device can travel in the east-to-west direction or in the west-to-east direction. For example, whenever the signal output needs to be routed to the output track at the metallization layer 510, the signal can be directly pulled up to the drain side of the source / drain contact of the metallization layer 510 track. For example, whenever the signal output needs to be the input of any vertically stacked transistor 505, the signal can also be pulled up to the metallization layer 510 track, and then passed down to any vertically stacked transistor 505 configured to be functionalized by the input. For example, whenever the signal output is configured to pass through multiple transistors, the signal output can be routed to a level where two transistors are provided, and the signal can be sent to these two transistors.

[0050] Advantageously, this allows for a variety of arrangements within the vertically stacked transistor design (i.e., parallel vertically stacked gate cells 598) for signal routing within a standard cell, and also provides some potential improvements in the number of degrees of freedom that future electronic design automation tools may have in three-dimensional cell layout.

[0051] It is worth noting that the vertically stacked gate cell 500 is different from a "vertical FET" (VFET) device. A VFET device incorporates a common channel that extends vertically upward and has a gate electrode, source electrode, and drain electrode arranged perpendicular to the vertical channel. In such a device, since all connections to the gate electrode and the source and drain electrodes need to be made laterally, it becomes problematic to incorporate internal wiring between the source and drain contacts. According to the structure and current flow of the vertically stacked gate cell 500 described above, connections between internal source and drain connections can be accessed vertically, which can provide significantly greater scalability compared to a VFET.

[0052] A limitation of VFET devices is that connecting to these gate electrodes and source and drain electrodes is challenging and typically requires the electrodes to be very large in order to provide multiple connection points all the way to the BEOL metal, reducing any area benefits. A benefit of the vertically stacked gate cell 500 is that the vertically stacked transistors 505 still function properly, wherein the nanosheet channel or nanoring channel extending laterally through the gate electrode and source and drain electrodes is internally wired so that the output of one of the vertically stacked transistors 505 on a lower layer or level can be easily passed to the input of a vertically stacked transistor 505 on an upper layer or level.

[0053] Figure 6A schematic diagram of a vertically stacked gate cell 600 with a CFET-based stacked NMOS and PMOS architecture is shown according to an embodiment of the present disclosure. In an embodiment, the vertically stacked gate cell 500 can combine all of the above elements and can also combine the nFET / pFET stacking concept from the CFET architecture to produce a vertically stacked gate cell 600 with a CFET-based stacked NMOS and PMOS architecture. The vertically stacked gate cell 600 may include a vertically stacked transistor 605, wherein the vertically stacked transistor 605 may include a first vertically stacked transistor 605a, a second vertically stacked transistor 605b, and a third vertically stacked transistor 605c, wherein the first vertically stacked transistor 605a may be disposed below (and substantially or partially vertically aligned with) the second vertically stacked transistor 605b, and the second vertically stacked transistor 605b may be disposed below (and substantially or partially vertically aligned with) the third vertically stacked transistor 605c. The vertically stacked transistor 605 may include six source and drain electrodes, all of which are staggered relative to each other to provide connections within the vertically stacked gate cell 600 and from the source and drain electrodes to wiring tracks in the BEOL. This is an example of a six-level design. The current flow of the vertically stacked gate cell 600 remains consistent with the multi-level layout of the vertically stacked gate cell 500, in which current passes through each vertically stacked transistor 505 and then rises to the level above the transistor through the internal via wiring between the source and drain electrodes.

[0054] The following figure illustrates the process simulation for better understanding.

[0055] Figure 7A side view of the Vss 720 and Vdd 725 inputs of a three-level vertically stacked gate cell 700 according to an embodiment of the present disclosure is shown. The Vss input 720 can be disposed on the left side of the vertically stacked gate cell 700 and can power a first NMOS source / drain (S / D) electrode 715a on a first level 705a, while the Vdd input 725 can be disposed on the right side of the vertically stacked gate cell 700 and can power a first PMOS S / D electrode 720a on the first level 705a and a second PMOS S / D electrode 720b on a second level 705b, wherein the second level 705b can be disposed above the top of the first level 705a, and the third level 705c can be disposed above the top of the second level 705b. The vertically stacked gate cell 700 can also include a second NMOS S / D electrode 715b, a third NMOS S / D electrode 715c, and a third PMOS S / D electrode 720c. In this figure, the layers 705 can be connected or internally wired by incorporating internal vias, but other methods can also be used to accomplish this, such as making a common S / D electrode that covers multiple layers 705. It is worth noting that some functions that are usually accomplished by metal wiring, such as nFET to pFET connection, can be easily accomplished by laterally shorting the S / D contacts of two adjacent NMOS and PMOS, such as the third NMOS S / D electrode 715c and the third PMOS S / D 720c (as shown), thereby providing a single output to the metal track 710 that can be set in the first metal layer 735a.

[0056] Figure 8 A gate side view of a three-layer vertical stacked gate cell 700 according to an embodiment of the present disclosure is shown. Vertically stacked transistors 730 (including a first vertical stacked transistor 730a, a second vertical stacked transistor 730b, and a third vertical stacked transistor 730c) can occupy each level 705 of the vertical stacked gate cell 700. As shown, the vertically stacked transistors 730 can be shared between NMOS and PMOS, but the work function metal 795 surrounding the channel 790 may be different between the physical NMOS gate and the PMOS gate. The vertically stacked transistors 730 can be powered by the second metal layer 735b, and each connection from the second metal layer 735b downward is fed into an independent vertical stacked transistor 730 through the staggering of the vertical stacked transistors 730 on each level 705 to provide a landing area for each input from the second metal layer 735b to the vertically stacked transistors 730.

[0057] Fig. 9 The embodiment according to the present disclosure is shown Figure 7720 and Vdd 725 input side view of the NMOS S / D electrode 715 and the PMOS S / D electrode 720. In this view, the vertically stacked gate unit 700 may include a first NMOS S / D electrode output terminal 715a2, a second NMOS S / D electrode output terminal 715b2, a third NMOS S / D electrode output terminal 715c2, a first PMOS S / D electrode output terminal 720a2, a second PMOS S / D electrode output terminal 720b2, and a third PMOS S / D electrode output terminal 720c2. As can be seen on the first level 705a, the first PMOS S / D electrode output terminal 720a2 in the first vertically stacked transistor 730a on the PMOS (right) side can be pulled up to the metal track 710, while the first NMOS S / D electrode output terminal 715a2 from the first vertically stacked transistor 730a on the NMOS (left) side can be pulled up to the second NMOS S / D electrode output terminal 715b2 of the second vertically stacked transistor 730b on the second level 705b and the third NMOS S / D electrode output terminal 715c2 of the third vertically stacked transistor 730c on the third level 705c. Therefore, the first NMOS S / D electrode output terminal 715a2 can be used as an input source for the second vertically stacked transistor 730b and the third vertically stacked transistor 730c.

[0058] In another embodiment, the vertically stacked gate cell 700 can be constructed in which the source and drain regions of NMOS and PMOS are also stacked on top of each other in a CFET manner. This configuration results in a device in which there are six levels 705 instead of three, where the levels 705 can be determined by the S / D electrodes and the common gate can occupy two adjacent levels 705.

[0059] Thus, the described technology can achieve area scaling by stacking multiple independent gates on top of each other to reduce the east / west area or lateral area of ​​a standard cell to a smaller number of CPPs (contacted gate pitches).

[0060] The advantages of the aforementioned embodiments are described as follows.

[0061] The number of CPPs required for a given device can be reduced by stacking gates vertically on top of each other, thereby shrinking the area of ​​the device in an east / west analysis or lateral direction. Thus, by stacking the gates, the number of transistors in the device remains constant, which achieves the size benefits of a standard cell.

[0062] Each gate electrode, as well as the source and drain electrodes, can function as a separate "layer" or "tier" of the overall device. Current flowing through the device can be routed upward through elevated "layers" or "tiers" of the device by (a) internal vias that can connect source and drain contacts across multiple tiers or (b) by physically merging source and drain electrodes from two separate tiers into a single merged electrode. Thus, actions that are typically accomplished by routing in the back end of the line (BEOL) through metal interconnects can be accomplished internally through the incorporation of vias or merged or disconnected source and drain contacts.

[0063] The gates can be sized and staggered relative to each other within the device so that a connection to each gate can be clearly made from any BEOL metal layer.

[0064] The source and drain electrodes may also be staggered relative to each other to provide access to pull up to any metal track within the device at any time, thereby bypassing internal wiring to rise to elevated levels of a given device.

[0065] The current flowing through the device is usually upward, where the power can come from a buried power rail or a power rail in the BEOL (where the power goes to the source and drain electrodes on the lower level of the device). From here the current will flow through the transistor and feed into the adjacent source and drain electrodes, where the output can be passed up to the metal wiring tracks, or up to the next "level" of the device, where the output from the lower level can be used as an input to the upper level. The current will flow through the transistor on that level, then into the next source and drain electrodes, and then pass up again to the metal wiring tracks or supply input power for the next plane / transistor.

[0066] In terms of area scaling of a standard cell in the east / west direction, embodiments herein may include a single CPP (contacted gate / poly pitch). Although multiple gates are used, the gates are stacked on top of each other to achieve a smaller area size.

[0067] To accommodate multiple stacking of gates, the cell height may be increased for either north / south or vertical orientations to allow staggered connections to the stacked gates. The CPP may be much larger than the critical metal pitch, so a change in one CPP is typically 25% to 50% larger in physical size than any change in track cell height. For example, a reduction in one CPP may be as much as, for example, 42nm, but to achieve this may require adding additional track pitch to the standard cell, which may be of the order of, for example, 24nm, so the actual benefit in this example case may be, for example, 18nm.

[0068] For devices containing more than three gates, a stacked layout of two CPPs can be used, where the stack height of the device remains at two levels or three levels, but this is done across two different sets of stacked gates. This also provides a method for how to keep the overall layout close to the same level height for multiple standard cells with different gate counts.

[0069] In this device, the NMOS channel and the PMOS channel can be arranged side by side relative to each other, which is common in CMOS, so the (previously mentioned) example AOI cell can include a three-layer device. Alternatively, in a complementary FET (CFET) device, the NMOS channel and the PMOS channel themselves can be stacked on top of each other, which would make the device approach a six-layer device.

[0070] This device concept can realize standard cell on standard cell or chip on chip three-dimensional devices, because the upward scaling path does not need to be limited in the vertical direction and some wiring between cells can still be created internally between the output terminals of two cells stacked vertically on top of each other.

[0071] In the described embodiment, all gates can be common gates, where NMOS channels and PMOS channels pass through the same gate structure within each level of the device, but within each common gate, the work function metal deposited on the channel is channel specific (NMOS metal is deposited on the NMOS channel and PMOS metal is deposited on the PMOS channel). Alternatively, separate gates can be combined so that only NMOS gates can be used for NMOS channels, while separate PMOS gates can be used for PMOS channels. In this embodiment, the NMOS gate electrode and the PMOS gate electrode can be physically and electrically isolated from each other by forming a dielectric film, which can be deposited directly on one or both gate electrodes, or deposited to the uncovered / covered gate electrodes by a selective deposition method.

[0072] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and the description of the various components and processes used therein. However, it should be understood that the technology herein can be practiced in other embodiments that are separated from these specific details, and such details are for the purpose of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials, and configurations have been proposed in order to provide a thorough understanding. However, the embodiments can be practiced without these specific details. Components having substantially the same functional structure are represented by similar reference numerals, and any redundant description can therefore be omitted.

[0073] Various techniques have been described as multiple independent operations to help understand various embodiments. The order of description should not be interpreted as meaning that these operations must be dependent on the order. In fact, these operations do not need to be performed in the order presented. The described operations can be performed in an order different from the described embodiments. In additional embodiments, various additional operations can be performed and / or the described operations can be omitted.

[0074] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor wafer, a mask), or a layer (such as a thin film) on or overlying a base substrate structure. Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to a specific type of substrate, but this is for illustrative purposes only.

[0075] Those skilled in the art will also appreciate that many changes may be made to the operation of the above-mentioned techniques while still achieving the same purpose of the present invention. The scope of this disclosure is intended to include these changes. Therefore, the foregoing description of the embodiments of the present invention is not intended to be restrictive. On the contrary, any limitation to the embodiments of the present invention is presented in the appended claims.

Claims

1. A semiconductor device, comprising: a substrate having a surface, the surface being flat; a first logic gate disposed on the substrate and comprising a first field effect transistor, i.e., a first FET, having a first channel and a first pair of source-drain regions; a second logic gate stacked above the first logic gate in a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel and a second pair of source-drain regions; a first contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of a current flowing between the first logic gate and the second logic gate will flow in the vertical direction, a third logic gate stacked above the second logic gate in the vertical direction, the third logic gate comprising a third FET having a third channel and a third pair of source-drain regions; as well as a second contact electrically connecting the source-drain region of the second FET to the source-drain region of the third FET so that at least a portion of the current flowing between the second logic gate and the third logic gate will flow in the vertical direction, The first contact comprises a common electrode extending from a first source-drain region of the first FET to a source-drain region of the second FET.

2. The semiconductor device according to claim 1, wherein: The first logic gate includes a first set of complementary FETs including the first FET; and The second logic gate includes a second set of complementary FETs including the second FET.

3. The semiconductor device according to claim 2, wherein: At least one of the first set of complementary FETs and the second set of complementary FETs comprises laterally arranged complementary FETs spaced apart from one another in a lateral direction along the surface of the substrate.

4. The semiconductor device according to claim 1, wherein: The first contact includes a conductive through hole extending along the vertical direction.

5. The semiconductor device of claim 1 , further comprising a power rail configured to provide current to the first logic gate and the second logic gate, wherein The power rail includes a back-end-of-line (BEOL) power rail located above the second logic gate along the vertical direction.

6. The semiconductor device of claim 1 , further comprising a power rail configured to provide current to the first logic gate and the second logic gate, wherein The power rail includes a buried power rail located below the first logic gate along the vertical direction.

7. A semiconductor device comprising: a substrate having a surface, the surface being flat; a first logic gate disposed on the substrate and comprising a first field effect transistor, i.e., a first FET, having a first channel and a first pair of source-drain regions; a second logic gate stacked above the first logic gate in a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel and a second pair of source-drain regions; a first contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of a current flowing between the first logic gate and the second logic gate will flow in the vertical direction, a third logic gate disposed on the substrate laterally adjacent to the first logic gate and comprising a third FET having a third channel and a third pair of source-drain regions; a fourth logic gate, the fourth logic gate being stacked above the third logic gate in the vertical direction perpendicular to the surface of the substrate, the fourth logic gate comprising a fourth FET having a fourth channel and a fourth pair of source-drain regions; a second contact electrically connecting the source-drain region of the third FET to the source-drain region of the fourth FET so that at least a portion of the current flowing between the third logic gate and the fourth logic gate will flow in the vertical direction; as well as a third contact electrically connecting the source-drain region of the first FET to the source-drain region of the third FET such that at least a portion of the current flowing between the first logic gate and the third logic gate will flow in a lateral direction, The first contact comprises a common electrode extending from a source-drain region of the first FET to a source-drain region of the second FET.

8. A combinational logic unit, comprising: a substrate having a surface, the surface being flat; a plurality of logic gates stacked relative to each other in a vertical direction perpendicular to a surface of the substrate; as well as a contact extending in the vertical direction and electrically connecting an output terminal of one of the plurality of logic gates to an input terminal of another of the plurality of logic gates so that at least a portion of a current flowing between the plurality of logic gates will flow in the vertical direction, wherein the plurality of logic gates occupy a single contact gate pitch in a first direction along the surface of the substrate, and wherein the plurality of logic gates include three logic gates stacked relative to each other along the vertical direction; and The contacts include a plurality of contacts configured to electrically interconnect the plurality of logic gates in an AND-OR-NOT AOI unit configuration.

9. The combinatorial logic unit according to claim 8, wherein: The plurality of logic gates occupy more than one critical metal pitch in a second direction along the surface of the substrate and non-parallel to the first direction.

10. A semiconductor device comprising: substrate; A first field effect transistor, i.e., a first FET, is disposed on the substrate in a first level and includes an NMOS channel, a gate structure, a source electrode, and a drain electrode; a second FET vertically stacked above the top of the first FET in a second level perpendicular to the plane of the substrate and comprising an NMOS channel, a gate structure, a source electrode, and a drain electrode; as well as a current source electrically connected to a source electrode or a drain electrode of the first FET, wherein The current provided by the current source flows through the first FET in the first layer, The current leaving the source electrode of the first FET or the drain electrode of the first FET flows vertically upward to the second layer into the source electrode of the second FET or the drain electrode of the second FET, The source electrode of the first FET and the source electrode of the second FET include a first common electrode extending from the source electrode of the first FET to the source electrode of the second FET, and The drain electrode of the first FET and the drain electrode of the second FET include a second common electrode extending from the drain electrode of the first FET to the drain electrode of the second FET, wherein the first FET is part of a first complementary FET and the second FET is part of a second complementary FET; Another portion of the first complementary FET includes a PMOS channel, a gate structure, a source electrode, and a drain electrode; Another portion of the second complementary FET includes a PMOS channel, a gate structure, a source electrode, and a drain electrode.

11. The semiconductor device of claim 10, further comprising additional FETs, each additional FET being stacked on top of each other in additional levels.

12. The semiconductor device according to claim 10, wherein: The PMOS channel of the first complementary FET is disposed laterally adjacent to the NMOS channel of the first complementary FET; and The PMOS channel of the second complementary FET is disposed laterally adjacent to the NMOS channel of the second complementary FET.

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