Successive Approximation Analog-to-Digital Converter

Abstract

The present invention provides a successive approximation analog-to-digital converter, which includes a first successive approximation channel, a second successive approximation channel, a fine comparator and a noise shaping circuit. The first successive approximation channel has a first group of successive approximation registers and a first coarse comparator for coarsely adjusting the first group of successive approximation registers. The second successive approximation channel has a second group of successive approximation registers and a second coarse comparator for coarsely adjusting the second group of successive approximation registers. The fine comparator is used to alternately fine-tune the first group of successive approximation registers and the second group of successive approximation registers. The noise shaping circuit samples the residue of the first successive approximation channel for the fine comparator to fine-tune the second group of successive approximation registers, and samples the residue of the second successive approximation channel for the fine comparator to fine-tune the first group of successive approximation registers.

Description

Technical Field

[0001] The present invention relates to analog-to-digital converters (ADCs), and more particularly to successive approximation analog-to-digital converters (SAR ADCs). Background Art

[0002] Recently, the number of smart devices and the amount of data transmission are growing at an unprecedented rate. In order to provide users with a high-quality experience, wireless local area network (WLAN) plays a key role in wireless standards. Wifi 6 can improve spectrum efficiency, increase data rates, and serve more users simultaneously in public areas. In order to support 1024 quadrature amplitude modulation (QAM) in a 160MHz radio frequency (RF) signal bandwidth while maintaining sufficient error vector magnitude (EVM), the ADC must achieve an in-band dynamic range (DR) of 63-70dB at an 80MHz baseband bandwidth. Successive-approximation analog-to-digital converter (SAR ADC) is widely used in Wifi applications due to its low power consumption and small footprint. For DR>60dB, quantization noise and comparator noise become the main noise sources. Recently, noise-shaping (NS) SAR ADCs can significantly reduce these two noise sources and thus become increasingly used to improve the signal-to-noise ratio (SNR).

[0003] The following describes the basic concept of SAR ADC. In the input sampling stage, the input voltage V Iis sampled onto a weighted capacitor array (capacitive digital-to-analog converter, abbreviated as CDAC). During the analog-to-digital conversion stage, a successive approximation scheme is performed. The CDAC is controlled to successfully approximate its positive and negative output terminals. The comparator compares the positive and negative output terminals of the CDAC and adjusts a set of successive approximation registers (e.g., SAR logic) accordingly. The values ​​of this set of successive approximation registers are fed back to the CDAC to control the successive-approximation between the positive and negative output terminals of the CDAC. Based on a series of comparator outputs generated during the successive approximation process, the capacitors in the CDAC are switched between several reference voltages to balance the voltage levels on the positive and negative output terminals of the CDAC, and the input voltage V is determined from the MSB (most significant bit) to the LSB (least significant bit) of the set of successive approximation registers. I digital representation.

[0004] However, after successive approximation, there may still be a residual voltage V between the positive and negative output terminals of the CDAC. R . The residual voltage V R The noise shaping signal is derived to cancel the noise. The comparator of the SAR ADC usually provides an additional differential input pair for subtracting the noise shaping signal. However, the additional differential input pair will generate additional thermal noise and kickback noise. In addition, the generation of the noise shaping signal involves active residue amplification (using an operational amplifier), which consumes a lot of power.

[0005] Therefore, a high-efficiency, low-power, small-area, high-speed, and wide-bandwidth NS-SAR ADC is needed. Summary of the invention

[0006] To this end, a fully passive, time-interleaved (TI) noise-shaping successive approximation analog-to-digital converter (NS-SAR ADC) is presented in the present invention, which uses a passive (no operational amplifier) ​​signal residual summation technique and 2-way time interleaving. Compared with a single-channel SAR ADC, its signal bandwidth is doubled while maintaining the same dynamic range (DR) and figure-of-merit (FoM). A shared fine comparator can reduce interleaving glitches.

[0007] According to an exemplary embodiment of the present invention, the TI NS-SAR ADC includes a first successive approximation channel, a second successive approximation channel, a fine comparator, and a noise shaping circuit. The first successive approximation channel has a first group of successive approximation registers (e.g., SAR logic) and a first coarse comparator, and the first coarse comparator is used to roughly adjust the first group of successive approximation registers. The second successive approximation channel has a second group of successive approximation registers (e.g., another SAR logic) and a second coarse comparator, and the second coarse comparator is used to roughly adjust the second group of successive approximation registers. The fine comparator is used to alternately finely adjust the first group of successive approximation registers and the second group of successive approximation registers. The noise shaping circuit samples the residue of the first successive approximation channel for the fine comparator to fine-tune the second group of successive approximation registers, and samples the residue of the second successive approximation channel for the fine comparator to fine-tune the first group of successive approximation registers.

[0008] In an exemplary embodiment, the noise shaping circuit performs residual sampling using back-to-back capacitors and integrates the residuals through charge sharing to perform signal residual summation at the input side of the fine comparator.

[0009] In an exemplary embodiment, a first coarse comparator sets a first set of successive approximation registers in a first stage, and a fine comparator sets a first set of successive approximation registers in a second stage. The first stage precedes the second stage.

[0010] In an exemplary embodiment, the second coarse comparator sets the second set of successive approximation registers in the second stage, and the fine comparator sets the second set of successive approximation registers in the third stage. The second stage precedes the third stage.

[0011] In an exemplary embodiment, the first coarse comparator sets the first set of successive approximation registers in the third stage, and the fine comparator sets the first set of successive approximation registers in the fourth stage. The third stage precedes the fourth stage.

[0012] The successive approximation analog-to-digital converter of the present invention can provide a wide bandwidth with sufficient DR and has excellent power efficiency.

[0013] In the following embodiments, a detailed description is given with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various embodiments of the present invention, presented as examples, will be described in detail with reference to the following drawings, in which like reference numerals represent like elements, and:

[0015] Figure 1 A time-interleaved noise shaping successive approximation analog-to-digital converter (TI NS-SAR ADC) according to an exemplary embodiment of the present invention is shown.

[0016] Figure 2 The timing scheme for operating the TI NS-SAR ADC is shown and how the noise shaping circuit operates.

[0017] Figure 3A , Figure 3B , Figure 3C and Figure 3D The detailed connections of the noise shaping circuit in four different phases Phase_1 to Phase_4 are shown. DETAILED DESCRIPTION

[0018] The following description shows an exemplary embodiment of implementing the present invention. These descriptions are intended to illustrate the general principles of the present invention and should not be considered as limiting. The scope of the present invention can be determined by reference to the attached claims.

[0019] In order to increase the bandwidth and SNR, a time-interleaved (TI) noise-shaping successive-approximation analog-to-digital converter (NS-SAR ADC) is proposed. In an exemplary embodiment, a completely passive time-interleaved noise shaping technique is introduced to realize a power-saving ADC for wideband and low-noise data conversion.

[0020] Note that if the two channels are interleaved without additional processing, the residue is not available at the beginning of each analog-to-digital conversion stage and noise shaping fails. In the proposed architecture, after the first few bit cycles of the SAR conversion of one channel, the residue from the other channel is available. Thus, each channel is able to complete the analog-to-digital conversion with the correct residue.

[0021] Figure 1 A time-interleaved noise-shaping successive approximation analog-to-digital converter (TI NS-SAR ADC) 100 according to an exemplary embodiment of the present invention is shown. The TI NS-SAR ADC 100 has a first successive approximation channel CH1, a second successive approximation channel CH2, a fine comparator Comp_F, a noise shaping circuit (including eight capacitors C1 to C8, a pair of integration capacitors C INTP and C INTN , and control capacitors C1~C8, C INTP and C INTN The input signal V I (Refer to the differential input V IPand V IN ) is alternately sampled into the first successive approximation channel CH1 and the second successive approximation channel CH2, and the decoder DEC outputs the input signal V I The number represents Dout. Note that the control capacitors C1 to C8, C INTP and C INTN Multiple switches, Figure 1 Only some switches and their wiring connections are shown in this example. Figure 1 In addition to the switches and connections shown in FIG. INTP and C INTN Multiple switches and their circuit connections for controlling, for example, to achieve the following Figure 3A to Figure 3D Capacitor connections and their corresponding functions are shown.

[0022] The first successive approximation channel CH1 includes a first capacitive digital-to-analog converter (CDAC) CDAC1, a first coarse comparator Comp_C1, and a first set of successive approximation registers (e.g., SAR logic) SAR_L1. The second successive approximation channel CH2 includes a second capacitive digital-to-analog converter CDAC2, a second coarse comparator Comp_C2, and a second set of successive approximation registers (e.g., another SAR logic) SAR_L2.

[0023] The first capacitive digital-to-analog converter CDAC1 has a first capacitor network CN1 and a second capacitor network CN2. The top plate INP1 of the first capacitor network CN1 is coupled to the positive input terminal of the first coarse comparator Comp_C1, and the top plate INN1 of the second capacitor network CN2 is coupled to the negative input terminal of the first coarse comparator Comp_C1. In the input sampling phase of the first successive approximation channel CH1, the input signal V of the TI NS-SAR ADC 100 is sampled between the top plate INP1 of the first capacitor network CN1 and the top plate INN1 of the second capacitor network CN2. I Sampling. The first coarse comparator Comp_C1 is used to roughly adjust (coarsely adjust) the first group of successive approximation registers SAR_L1. The noise shaping circuit and the fine comparator Comp_F are used to finely adjust (finely adjust) the first group of successive approximation registers SAR_L1. The value of the first group of successive approximation registers SAR_L1 is fed back to control the first capacitive digital-to-analog converter CDAC1. A circuit loop is formed for successive approximation in the first successive approximation channel CH1.

[0024] The second capacitive digital-to-analog converter CDAC2 has a third capacitor network CN3 and a fourth capacitor network CN4, the top plate INP2 of the third capacitor network CN3 is coupled to the positive input terminal of the second coarse comparator Comp_C2, and the top plate INN2 of the fourth capacitor network CN4 is coupled to the negative input terminal of the second coarse comparator Comp_C2. In the input sampling phase of the second successive approximation channel CH2, the input signal V of the TI NS-SAR ADC 100 is sampled between the top plate INP2 of the third capacitor network CN3 and the top plate INN2 of the fourth capacitor network CN4. I The second coarse comparator Comp_C2 is used to roughly adjust (coarsely adjust) the second group of successive approximation registers SAR_L2. The noise shaping circuit and the fine comparator Comp_F further finely adjust (finely adjust) the second group of successive approximation registers SAR_L2. The value of the second group of successive approximation registers SAR_L2 is fed back to control the second capacitive digital-to-analog converter CDAC2. A circuit loop is formed for successive approximation in the second successive approximation channel CH2.

[0025] The first successive approximation channel CH1 and the second successive approximation channel CH2 operate in an interleaved manner. Specifically, the fine comparator Comp_F is shared by the first successive approximation channel CH1 and the second successive approximation channel CH2 to finely adjust the first group of successive approximation registers SAR_L1 and the second group of successive approximation registers SAR_L2. Sharing the fine comparator Comp_F not only saves hardware, but also converts the total channel offset into an offset between the coarse comparator and the fine comparator (between Comp_C1 and Comp_F, or between Comp_C2 and Comp_F), thereby preventing overloading of the analog-to-digital conversion and alleviating errors caused by channel mismatch.

[0026] Note that the fine comparator Comp_F and the noise shaping circuit perfectly eliminate the residue. The coarse-fine structure further solves the non-causality of the residue exchange between channels. The noise shaping circuit samples the residue of the first successive approximation channel CH1 (between INP1 and INN1), and accordingly, the fine comparator Comp_F finely adjusts the second group of successive approximation registers SAR_L2. The noise shaping circuit further samples the residue of the second successive approximation channel CH2 (between INP2 and INN2), and accordingly, the fine comparator Comp_F finely adjusts the first group of successive approximation registers SAR_L1. When the fine comparator Comp_F is running, the residue is ready. The fine comparator Comp_F operates based on reliable residual information.

[0027] For each round of setting of the successive approximation register SAR_L1 / SAR_L2, the coarse comparator Comp_C1 / Comp_C2 resolves the initial bit at high speed, and then the low-noise fine comparator Comp_F resolves the lower bits and processes the signal-residue summation. Since the coarse comparators (Comp_C1 and Comp_C2) only work on input signals without residue (not ready), this arrangement allows the other channel to have more time to complete the conversion and generate the residue. Once the residue is available and the residue can be charge-shared for integration, the fine comparator Comp_f resolves the signal-residue summation to achieve noise shaping.

[0028] The noise shaping circuit can perform residual sampling through back-to-back capacitors and integrate the residual through charge sharing for signal-residual summation at the input side of the fine comparator Comp_F (referenced to VRP and VRN). The sampled residual is 2 times larger than the residual sampled through only one capacitor and does not require amplification. The residual is connected in series with the capacitive digital-to-analog converter CDAC1 / CDAC2 to achieve summation.

[0029] The noise shaping circuit can be a fully passive design. Figure 1 The noise shaping circuit has eight capacitors C1 to C8, a pair of integrating capacitors C INTP and C INTN , and control capacitors C1 to C8 and C INTP and C INTN As shown in the figure, the first integrating capacitor C INTPThe top plate has a positive input terminal VRP coupled to the fine comparator Comp_F, the second integrating capacitor C INTN The first integrating capacitor C has a top plate coupled to the negative input terminal VRN of the fine comparator Comp_F. INTP and the second integrating capacitor C INTN Used to integrate the residues sampled from the first successive approximation channel CH1 and the second successive approximation channel CH2.

[0030] Figure 2 The timing scheme for operating the TI NS-SAR ADC 100 is shown and shows how the noise shaping circuit operates.

[0031] Described below Figure 2 The waveform shown in Figure 2 is shown in Figure 2. CLKS1 is the sampling clock of the first successive approximation channel CH1. CLKC1 is the coarse comparison clock that controls the first coarse comparator Comp_C1. CH1,1 The signal controls the first capacitor C1 and the second capacitor C2 as a pair of back-to-back capacitors to perform residual sampling on the first successive approximation channel CH1. CH1,2 The signal controls the fifth capacitor C5 and the sixth capacitor C6 to function as a pair of back-to-back capacitors (ie, Φ CH1,2 Control the switches around the fifth capacitor C5 and the sixth capacitor C6 to act as a pair of back-to-back capacitors), with Φ CH1,1 The first successive approximation channel CH1 is residually sampled in an interleaved manner. CLKS2 is the sampling clock of the second successive approximation channel CH2. CLKC2 is the coarse comparison clock signal that controls the second coarse comparator Comp_C2. Φ CH2,1 The signal controls the seventh and eighth capacitors C7 and C8 as a pair of back-to-back capacitors to perform residual sampling on the second successive approximation channel CH2. CH2,2 Control the switches around the third and fourth capacitors C3 and C4 so that they act as a pair of back-to-back capacitors, with Φ CH2,1 The second successive approximation channel CH2 is staggered for residual sampling. CLKF is the fine comparison clock that controls the fine comparator Comp_F. Φ Fine,1 The first capacitive digital-to-analog converter CDAC1 is operable to connect the first integrating capacitor C INTP and the second integrating capacitor C INTN , to form a SAR loop for the first successive approximation channel CH1. Fine,2 The second capacitive digital-to-analog converter CDAC2 is operable to connect the first integrating capacitor C INTP and the second integrating capacitor C INTN, to form a SAR loop for the second successive approximation channel CH2. Through the switches around the fifth capacitor C5 and the sixth capacitor C6, Φ RES CH1,2 Control the first integrating capacitor C INTP and the charge sharing between the fifth capacitor C5, and controlling the second integrating capacitor C INTN and the charge sharing between the sixth capacitor C6. RES CH2,1 Control the first integrating capacitor C INTP and the seventh capacitor C7, and controls the charge sharing between the second integrating capacitor C INTN and the charge sharing between the eighth capacitor C8. RES CH1,1 Control the first integrating capacitor C INTP The charge sharing between the first capacitor C1 and the control of the second integrating capacitor C INTN The charge sharing between the second capacitor C2. RES CH2,2 Control the first integrating capacitor C INTP and the charge sharing between the third capacitor C3, and controlling the second integrating capacitor C INTN and the charge sharing between the fourth capacitor C4. RES CH1,2 , Φ RES CH2,1 , Φ RES CH1,1 and Φ RES CH2,2 Used to provide a reliable residual for the signal-residual sum.

[0032] The TI NS-SAR ADC 100 operates in four phases: Phase_1, Phase_2, Phase_3, and Phase_4. The first phase Phase_1 is before the second phase Phase_2, the second phase Phase_2 is before the third phase Phase_3, and the third phase Phase_3 is before the fourth phase Phase_4. The first coarse comparator Comp_C1 sets the first set of successive approximation registers SAR_L1 in the first phase Phase_1 (referenced to CLKC1) to coarsely adjust SAR_L1, and the fine comparator Comp_F sets the first set of successive approximation registers SAR_L1 in the second phase Phase_2 (referenced to CLKF and Φ Fine,1) is used to set the first set of successive approximation registers SAR_L1 for fine-tuning SAR_L1. The second coarse comparator Comp_C2 sets the second set of successive approximation registers SAR_L2 in the second phase Phase_2 (reference CLKC2) to coarsely adjust SAR_L2, and the fine comparator Comp_F sets the second set of successive approximation registers SAR_L2 in the third phase Phase_3 (reference CLKF and Φ Fine，2 ) to set the second group of successive approximation registers SAR_L2 phase for fine adjustment of SAR_L2. The first coarse comparator Comp_C1 also sets the first group of successive approximation registers SAR_L1 (referenced to CLKC1) in the third phase Phase_3 to coarsely adjust SAR_L1, and the fine comparator Comp_F sets the first group of successive approximation registers SAR_L1 (referenced to CLKC1) in the fourth phase Phase_4 (referenced to CLKF and Φ Fine，1 )Set the first set of successive approximation registers SAR_L1 for fine-tuning SAR_L1.

[0033] At the end of the second phase Phase_2, the residual of the first successive approximation channel CH1 is estimated (due to the coarse adjustment of SAR_L1 in the first phase Phase_1 and the fine adjustment of SAR_L1 in the second phase Phase_2) and is sampled by the first capacitor C1 and the second capacitor C2 (refer to Φ CH1,1 ). Therefore, the following is a detailed comparison of the second successive approximation channel CH2 in the third phase Phase_3 (refer to Φ Fine,2 ) is based on the reliable residual values ​​sampled in the first and second capacitors C1 and C2 (reference Φ RES CH1,1 At the end of the third phase Phase_3, the estimation of the residual of the second successive approximation channel CH2 is completed (due to the coarse adjustment of SAR_L2 in the second phase Phase_2 and the fine adjustment of SAR_L2 in the third phase Phase_3), and the residual of the second successive approximation channel CH2 is estimated by the third and fourth capacitors C3 and C4 (reference Φ CH2,2 ) is sampled. Therefore, the following is a detailed comparison of the first successive approximation channel CH1 in the fourth phase Phase_4 (reference Φ Fine,1 ) is based on the reliable residual values ​​sampled in the third and fourth capacitors C3 and C4 (reference Φ RES CH2,2 ). Reliable residual elimination is achieved.

[0034] Figure 2 It is also shown that the second coarse comparator Comp_C2 sets the second set of successive approximation registers SAR_L2 (referenced to CLKC2) in the fourth phase Phase_4, and the fine comparator Comp_F sets the second set of successive approximation registers SAR_L2 (referenced to CLK_F and Φ) in the first phase Phase_1.Fine,2 ). The time-staggered scheme is completed through four phases: Phase_1 to Phase_4.

[0035] Figure 3A , Figure 3B , Figure 3C and Figure 3D The detailed connections of the noise shaping circuit in four different phases Phase_1 to Phase_4 are shown.

[0036] Figure 3A Corresponding to the first phase Phase_1. The top plate INP1 of the first capacitor network CN1 is coupled to the top plate of the first capacitor C1 and the bottom plate of the second capacitor C2, and the top plate INN1 of the second capacitor network CN2 is coupled to the bottom plate of the first capacitor C1 and the top plate of the second capacitor C2. The fifth capacitor C5 and the first integral capacitor C INTP The sixth capacitor C6 and the second integrating capacitor C are coupled in parallel between the positive input terminal VRP of the fine comparator Comp_F and the top plate INP2 of the third capacitor network CN3. INTN The top plate INP2 of the third capacitor network CN3 is coupled to the top plate of the seventh capacitor C7 and the bottom plate of the eighth capacitor C8, and the top plate INN2 of the fourth capacitor network CN4 is coupled to the bottom plate of the seventh capacitor C7 and the top plate of the eighth capacitor C8.

[0037] In the first phase Phase_1 , the fine comparator Comp_F sets the second set of successive approximation registers SAR_L2 based on the reliable residue sampled from the first successive approximation channel CH1 , and the first coarse comparator Comp_C1 sets the first set of successive approximation registers SAR_L1 .

[0038] Figure 3B Corresponding to the second phase Phase_2. The top plate INP1 of the first capacitor network CN1 is coupled to the top plate of the first capacitor C1 and the bottom plate of the second capacitor C2, and the top plate INN1 of the second capacitor network CN2 is coupled to the bottom plate of the first capacitor C1 and the top plate of the second capacitor C2. The seventh capacitor C7 and the first integrating capacitor C INTP The eighth capacitor C8 and the second integrating capacitor C are coupled in parallel between the positive input terminal VRP of the fine comparator Comp_F and the top plate INP1 of the first capacitor network CN1. INTN is coupled in parallel between the negative input terminal VRN of the fine comparator Comp_F and the top plate INN1 of the second capacitor network CN2. Figure 3AIn the first phase Phase_1 shown, C7 and C8 are coupled to CH2 in a back-to-back manner to perform residual sampling on CH2. After C7 and C8 obtain the residual of CH2, Figure 3B In the second phase Phase_2 shown, C7 and C8 are coupled to CDAC1 in CH1 for fine comparison in CH1. The top plate INP2 of the third capacitor network CN3 is coupled to the top plate of the third capacitor C3 and the bottom plate of the fourth capacitor C4, and the top plate INN2 of the fourth capacitor network CN4 is coupled to the bottom plate of the third capacitor C3 and the top plate of the fourth capacitor C4.

[0039] In the second phase Phase_2 , the fine comparator Comp_F sets the first set of successive approximation registers SAR_L1 based on the reliable residue sampled from the second successive approximation channel CH2 , and the second coarse comparator Comp_C2 sets the second set of successive approximation registers SAR_L2 .

[0040] Figure 3C Corresponding to the third phase Phase_3. The top plate INP1 of the first capacitor network CN1 is coupled to the top plate of the fifth capacitor C5 and the bottom plate of the sixth capacitor C6, and the top plate INN1 of the second capacitor network CN2 is coupled to the bottom plate of the fifth capacitor C5 and the top plate of the sixth capacitor C6. The first capacitor C1 and the first integrating capacitor C INTP The second capacitor C2 and the second integrating capacitor C are coupled in parallel between the positive input terminal VRP of the fine comparator Comp_F and the top plate INP2 of the third capacitor network CN3. INTN is coupled in parallel between the negative input terminal VRN of the fine comparator Comp_F and the top plate INN2 of the fourth capacitor network CN4. Figure 3B In the second phase Phase_2 shown in FIG. 1 , C1 and C2 are coupled to CH1 in a back-to-back manner to perform residual sampling on CH1. After C1 and C2 obtain the residual of CH1, Figure 3C In the third phase Phase_3 shown, C1 and C2 are coupled to CDAC2 in CH2 for fine comparison in CH2. The top plate INP2 of the third capacitor network CN3 is coupled to the top plate of the third capacitor C3 and the bottom plate of the fourth capacitor C4, and the top plate INN2 of the fourth capacitor network CN4 is coupled to the bottom plate of the third capacitor C3 and the top plate of the fourth capacitor C4.

[0041] In the third phase Phase_3 , the fine comparator Comp_F sets the second group of successive approximation registers SAR_L2 based on the reliable residue sampled from the first successive approximation channel CH1 , and the first coarse comparator Comp_C1 sets the first group of successive approximation registers SAR_L1 .

[0042] Figure 3DCorresponding to the fourth phase Phase_4. The top plate INP1 of the first capacitor network CN1 is coupled to the top plate of the fifth capacitor C5 and the bottom plate of the sixth capacitor C6, and the top plate INN1 of the second capacitor network CN2 is coupled to the bottom plate of the fifth capacitor C5 and the top plate of the sixth capacitor C6. The third capacitor C3 and the first integrating capacitor C INTP The fourth capacitor C4 and the second integrating capacitor C are coupled in parallel between the positive input terminal VRP of the fine comparator Comp_F and the top plate INP1 of the first capacitor network CN1. INTN is coupled in parallel between the negative input terminal VRN of the fine comparator Comp_F and the top plate INN1 of the second capacitor network CN2. Figure 3C In the third phase Phase_3 shown in FIG. 1 , C3 and C4 are coupled to CH2 in a back-to-back manner to perform residual sampling on CH2. After C3 and C4 obtain the residual of CH2, Figure 3D In the fourth phase Phase_4 shown, C3 and C4 are coupled to CDAC1 in CH1 for fine comparison in CH1. The top plate INP2 of the third capacitor network CN3 is coupled to the top plate of the seventh capacitor C7 and the bottom plate of the eighth capacitor C8, and the top plate INN2 of the fourth capacitor network CN4 is coupled to the bottom plate of the seventh capacitor C7 and the top plate of the eighth capacitor C8.

[0043] In the fourth phase Phase_4 , the fine comparator Comp_F sets the first set of successive approximation registers SAR_L1 based on the reliable residue sampled from the second successive approximation channel CH2 , and the second coarse comparator Comp_C2 sets the second set of successive approximation registers SAR_L2 .

[0044] Compared with the conventional single-channel SAR ADC, the above TI NS-SAR ADC effectively improves the dynamic range (DR) and doubles the bandwidth. The layout size is improved due to the shared fine comparator. Specifically, multiple differential input pair comparators and amplifiers are not required. Therefore, the proposed structure is able to provide wide bandwidth with sufficient DR for Wifi 6 while having excellent power efficiency.

[0045] Although the present invention has been described by way of example and according to preferred embodiments, it should be understood that the present invention is not limited to the disclosed embodiments. On the contrary, the present invention is intended to cover various modifications and similar arrangements that are obvious to those skilled in the art. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A successive approximation analog-to-digital converter, comprising: a first successive approximation channel having a first set of successive approximation registers and a first coarse comparator, wherein the first coarse comparator is coupled to the first set of successive approximation registers to coarsely adjust the first set of successive approximation registers; a second successive approximation channel having a second set of successive approximation registers and a second coarse comparator, the second coarse comparator being coupled to the second set of successive approximation registers to coarsely adjust the second set of successive approximation registers; a fine comparator, coupled to the first group of successive approximation registers and the second group of successive approximation registers, for fine-tuning the first group of successive approximation registers and the second group of successive approximation registers; as well as a noise shaping circuit that samples a residual of the first successive approximation channel for the fine comparator to fine-tune the second set of successive approximation registers, and samples a residual of the second successive approximation channel for the fine comparator to fine-tune the first set of successive approximation registers; Wherein, in a first stage, the first coarse comparator sets the first group of successive approximation registers, the fine comparator sets the second group of successive approximation registers and the second coarse comparator is disabled; and, in a second stage, the second coarse comparator sets the second group of successive approximation registers, the fine comparator sets the first group of successive approximation registers and the first coarse comparator is disabled.

2. The successive approximation analog-to-digital converter according to claim 1, wherein: The noise shaping circuit performs residual sampling using back-to-back capacitors; as well as The noise shaping circuit integrates the residuals by charge sharing for signal residual summing at the input side of the fine comparator.

3. The successive approximation analog-to-digital converter of claim 1, wherein: The first coarse comparator sets the first set of successive approximation registers in the first stage; The fine comparator sets the first set of successive approximation registers in the second stage; and The first stage precedes the second stage.

4. The successive approximation analog-to-digital converter according to claim 3, wherein: The second coarse comparator sets the second set of successive approximation registers in the second stage; The fine comparator sets the second set of successive approximation registers in a third stage; and The second stage precedes the third stage.

5. The successive approximation analog-to-digital converter according to claim 4, wherein: The first coarse comparator sets the first set of successive approximation registers in the third stage; The fine comparator sets the first set of successive approximation registers in a fourth stage; and The third stage precedes the fourth stage.

6. The successive approximation analog-to-digital converter according to claim 5, wherein: The second coarse comparator sets the second set of successive approximation registers in the fourth stage.

7. The successive approximation analog-to-digital converter according to claim 1, wherein: The noise shaping circuit further comprises: a first integrating capacitor having a top plate coupled to the positive input terminal of the fine comparator; and a second integrating capacitor having its top plate coupled to the negative input terminal of the fine comparator, The first integrating capacitor and the second integrating capacitor are used to integrate the residues sampled from the first successive approximation channel and the second successive approximation channel.

8. The successive approximation analog-to-digital converter according to claim 7, wherein: The first successive approximation channel also has a first capacitive digital-to-analog converter operating according to the first set of successive approximation registers, wherein the first capacitive digital-to-analog converter has a first capacitor network and a second capacitor network, the top plate of the first capacitor network is coupled to the positive input terminal of the first coarse comparator, and the top plate of the second capacitor network is coupled to the negative input terminal of the first coarse comparator; The second successive approximation channel also has a second capacitive digital-to-analog converter operating according to the second set of successive approximation registers, wherein the second capacitive digital-to-analog converter has a third capacitor network and a fourth capacitor network, the top plate of the third capacitor network is coupled to the positive input terminal of the second coarse comparator, and the top plate of the fourth capacitor network is coupled to the negative input terminal of the second coarse comparator; sampling an input signal of a time-interleaved noise shaping successive approximation analog-to-digital converter between a top plate of the first capacitor network and a top plate of the second capacitor network during an input sampling phase of the first successive approximation channel; as well as The input signal of the time-interleaved noise shaping successive approximation analog-to-digital converter is sampled between a top plate of the third capacitor network and a top plate of the fourth capacitor network during an input sampling phase of the second successive approximation channel.

9. The successive approximation analog-to-digital converter according to claim 8, wherein: The noise shaping circuit further comprises a first capacitor and a second capacitor, wherein: In the first phase and the second phase, the top plate of the first capacitor network is coupled to the top plate of the first capacitor and the bottom plate of the second capacitor, and the top plate of the second capacitor network is coupled to the bottom plate of the first capacitor and the top plate of the second capacitor; In a third phase, the first capacitor and the first integrating capacitor are coupled in parallel between the positive input terminal of the fine comparator and the top plate of the third capacitor network, and the second capacitor and the second integrating capacitor are coupled in parallel between the negative input terminal of the fine comparator and the top plate of the fourth capacitor network; and The first stage is before the second stage, and the second stage is before the third stage.

10. The successive approximation analog-to-digital converter according to claim 9, wherein: The noise shaping circuit further comprises a third capacitor and a fourth capacitor, wherein: In the second phase and the third phase, the top plate of the third capacitor network is coupled to the top plate of the third capacitor and the bottom plate of the fourth capacitor, and the top plate of the fourth capacitor network is coupled to the bottom plate of the third capacitor and the top plate of the fourth capacitor; In a fourth phase, the third capacitor and the first integrating capacitor are coupled in parallel between the positive input terminal of the fine comparator and the top plate of the first capacitor network, and the fourth capacitor and the second integrating capacitor are coupled in parallel between the negative input terminal of the fine comparator and the top plate of the second capacitor network; and The third stage precedes the fourth stage.

11. The successive approximation analog-to-digital converter according to claim 10, wherein: The noise shaping circuit further comprises a fifth capacitor and a sixth capacitor, wherein: In the first stage, the fifth capacitor and the first integrating capacitor are coupled in parallel between the positive input terminal of the fine comparator and the top plate of the third capacitor network, and the sixth capacitor and the second integrating capacitor are coupled in parallel between the negative input terminal of the fine comparator and the top plate of the fourth capacitor network.

12. The successive approximation analog-to-digital converter according to claim 11, wherein: The noise shaping circuit further comprises a seventh capacitor and an eighth capacitor, wherein: In the second stage, the seventh capacitor and the first integrating capacitor are coupled in parallel between the positive input terminal of the fine comparator and the top plate of the first capacitor network, and the eighth capacitor and the second integrating capacitor are coupled in parallel between the negative input terminal of the fine comparator and the top plate of the second capacitor network.

13. The successive approximation analog-to-digital converter of claim 12, wherein: In the third stage and the fourth stage, the top plate of the first capacitor network is coupled to the top plate of the fifth capacitor and the bottom plate of the sixth capacitor, and the top plate of the second capacitor network is coupled to the bottom plate of the fifth capacitor and the top plate of the sixth capacitor.

14. The successive approximation analog-to-digital converter of claim 13, wherein: In the first and fourth stages, the top plate of the third capacitor network is coupled to the top plate of the seventh capacitor and the bottom plate of the eighth capacitor, and the top plate of the fourth capacitor network is coupled to the bottom plate of the seventh capacitor and the top plate of the eighth capacitor.

15. The successive approximation analog-to-digital converter of claim 1, wherein the fine comparator alternately fine-tunes the first group of successive approximation registers and the second group of successive approximation registers.

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