Two-step solder mask defined design

Abstract

The present application relates to a two-step solder mask defined design. An apparatus for BGA packaging includes a pad mounted on a substrate. The apparatus also includes a solder mask layer disposed on the substrate and a buffer layer disposed on the solder mask layer. The solder mask layer may have a first hole and the buffer layer may have a second hole. The first hole and the second hole are aligned so that at least a portion of the pad is exposed to produce a solder mask defined mounting pad. The diameter of the second hole is greater than the diameter of the first hole.

Description

Technical Field

[0001] The present invention relates generally to mounting and connecting electronic devices, and more particularly to apparatus and methods for providing solder ball pad structures on an interposer or semiconductor die using a two-step solder mask defined design. Background Art

[0002] The ever-increasing demand for smaller, lighter and more compact electronic equipment has led to a concomitant demand for semiconductor packages with smaller profiles and mounting areas or "footprints". One response to this demand has been the development of so-called "flip-chip" methods of attaching and connecting semiconductor chips to substrates. Sometimes referred to as "controlled collapse chip attach" or "C4" methods, the technique involves forming balls of conductive metal (e.g., solder or gold) on input / output connection pads on the active surface of the chip, then inverting or "flipping" the chip, and "reflowing" the conductive balls, i.e., heating them to a melting point to fuse them to corresponding connection pads on the substrate.

[0003] Another response has been the development of so-called ball grid array (“BGA”) semiconductor packages, which are “surface mounted” and electrically connected to an associated carrier substrate, such as a printed circuit board (“PCB”) structure, with a plurality of solder balls in a method sometimes referred to as the “C5” method, which is similar to the flip chip method described above for mounting and connecting the bare die.

[0004] In both the C4 die and C5 package mounting and connection methods, multiple solder balls are attached to corresponding solder ball mounting solder pads or pads, which are defined on the surface of the interposer substrate or semiconductor die. The solder ball mounting pads can be defined by openings in an insulating layer or mask, which is called a "passivation layer" in the case of a semiconductor die, or a "solder mask" in the case of an interposer substrate of a BGA package. The passivation layer and the solder mask are collectively referred to as "solder resist" in this article. The interposer substrate in a BGA package can include a rigid or flexible sheet.

[0005] For some applications, the combined BGA package and carrier substrate (also referred to herein as an "electronic device assembly") is expected to be subjected to extreme temperature cycles. For example, in some automotive and server applications, the electronic device assembly may need to withstand a large temperature range and remain fully functional for a long life. The electronic device assembly may need to withstand large temperature fluctuations (e.g., -40°C to 125°C) of 1000-2000 cycles per 40 minutes as a measure of its ability to withstand field conditions. Because the carrier substrate (e.g., PCB board) and the BGA package can be made of different materials, there may be a difference in the coefficient of thermal expansion (CTE) between the BGA package and the carrier substrate. The difference in CTE may cause the BGA package and the carrier substrate to expand at different rates, which may cause stress in the solder joints that electrically connect the BGA package and the carrier substrate. The stress in the solder joints may cause premature failure due to, for example, the formation and propagation of cracks in the solder joints. Summary of the invention

[0006] According to one aspect of the present application, a method is provided. The method comprises: forming a pad on a substrate; applying a solder resist layer on the pad and the substrate; applying a buffer layer on the solder resist layer; etching the buffer layer and the solder resist layer to produce a first hole in the solder resist layer, wherein the first hole exposes at least a portion of the pad to produce a mounting pad; and further etching the buffer layer to produce a second hole in the buffer layer, wherein the interface diameter of the second hole is greater than the interface diameter of the first hole.

[0007] According to another aspect of the present application, a device is provided. The device comprises: a pad mounted on a substrate; a solder resist layer disposed on the substrate, the solder resist layer having a first hole; and a buffer layer disposed on the solder resist layer, the buffer layer having a second hole, wherein the first and second holes are aligned so that at least a portion of the pad is exposed, and wherein an interface diameter of the second hole is greater than an interface diameter of the first hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of an electronic device assembly according to the prior art.

[0009] Figure 2A is a top view of a portion of a BGA package according to an embodiment of the present technology.

[0010] Figure 2B yes Figure 2A Cross-sectional view of a BGA package.

[0011] Figure 3 is a flow chart illustrating a method of forming a BGA package according to an embodiment of the present technology. DETAILED DESCRIPTION

[0012] Embodiments of the present technology are directed to devices and methods for providing solder mask defined ("SMD") BGA packages of the present invention. In some embodiments, the SMD BGA package is formed using a two-step solder mask defined design. The two-step SMD design includes applying a solder mask and a buffer layer on top of an interposer substrate of the SMD BGA package. The solder mask may cover at least a portion of the surface of the surrounding interposer substrate, and the buffer layer may cover at least a portion of the solder mask. The SMD BGA package may also include metal terminal pads disposed on the interposer substrate, and the metal terminal pads may be at least partially exposed due to holes in the solder mask and the buffer layer. In some embodiments, the application of the solder mask and the buffer layer may be a continuous process (e.g., when the solder mask and the buffer layer have the same composition). The two-step SMD design may include generating a buffer layer opening and generating a solder mask opening. The holes in the buffer layer may be larger than the holes in the solder mask.

[0013] Figure 1 A cross-sectional view of a conventional electronic device assembly 10 is depicted. For clarity, only a single solder ball mounting pad and solder ball are shown. However, it should be understood by those skilled in the art that the electronic device assembly may include multiple solder balls attached to multiple mounting pads, respectively. The electronic device assembly 10 includes an interposer substrate 12 and a metal pad 14 disposed on the interposer substrate 12. A solder resist layer 15 may be formed on top of the interposer substrate 12. The solder resist layer 15 may include an opening or hole aligned with the metal pad 14 to expose the metal pad 14. The electronic device assembly 10 may also include a metal trace 22 disposed on a carrier substrate 20 (e.g., a PCB board). Solder joints 16 are formed by depositing solder balls between the interposer substrate 12 and the carrier substrate 20. Solder joints 16 may form electrical connections between the metal pad 14 and the metal trace 22. Solder joints 16 are connected to the metal pads through holes in the solder resist layer 15. The solder balls are typically made of a material different from the metal pads 14. Therefore, when solder joint 16 is formed on metal pad 14, different materials of solder ball and metal pad 14 are mixed with each other to form intermetallic compound ("IMC") layer 30 at the interface between solder joint 16 and metal pad 14. For example, solder ball can be made of tin-lead alloy, and metal pad can be made of copper. When solder joint 16 is formed, the composition of IMC layer 30 can include Cu6Sn5, Cu3Sn and / or other alloys.

[0014] However, the formation of the IMC layer 30 can create reliability issues for the solder joint 16. For example, interfacial delamination or cracks may initiate at the neck 35 of the solder joint 16 where the IMC layer 30 is formed. While the solder resist layer 15 can help mitigate the formation of cracks, the proximity of the IMC layer 30 to the exterior of the solder joint 16 may allow cracks to initiate and propagate through the solder joint 16, which shortens the life of the electronic device assembly 10. Cracks may initiate due to, for example, CTE differences between the interposer substrate 12 and the carrier substrate 20. Once initiated, the crack will propagate along the IMC layer 30 or in the bulk solder near the IMC layer 30 until an open circuit exists between the metal pad 14 and the metal trace 22. In applications that experience extreme temperature fluctuations, such as automotive and server applications, crack propagation and subsequent failure of electronic device assemblies may be accelerated.

[0015] In an exemplary embodiment of the present technology, one or more buffer layers can be formed on top of the solder mask to further block and / or reduce the area in the IMC layer that may cause potential cracks. For example, by adding at least one buffer layer made of organic material on top of the solder mask, the distance between the IMC layer and the outside of the solder joint can be increased. By increasing this distance, the solder joint can withstand higher stresses and withstand longer times, which can increase the life of the electronic device assembly. Because organic materials can be used for the buffer layer in some embodiments, there is no chemical reaction, and no additional IMC layer is formed between the buffer layer and the solder joint matrix.

[0016] Figure 2A A top view of a portion of a BGA package 100 is depicted. Again, for clarity, only a single solder ball mounting pad design is shown. However, it should be understood by those skilled in the art that a BGA package may include multiple mounting pads that may each accommodate multiple solder balls. The BGA package 100 may include a substrate 110 having mounting pads 128 defined by a solder mask formed thereon. The SMD mounting pads 128 are formed using a two-step SMD process, wherein a first SMD region is formed in the solder resist layer 120 (see Figure 2B ) and form a second SMD region in the buffer layer 122. Figure 2B is a cross-sectional view of the BGA package 100, which includes Figure 2A2B-2B of the substrate 110 and the terminal pads 114. The substrate 110 may comprise an insulating material, such as bismaleimide triazine, a flexible polyimide film or tape, fiberglass, polyimide tape, ceramic, or silicon, or it may alternatively comprise a semiconductor chip or die. Typically, a metal layer, such as copper, aluminum, gold, silver, nickel, tin, platinum, or a combination of the foregoing, may be laminated and / or plated on the surface of the substrate 110. The metal layer may then be patterned into a terminal pad 114 using known photolithography techniques, which may include one or more circuit traces 116 (shown by dashed lines) extending therefrom. In addition to the circuit traces 116, plated through holes, referred to as "through holes" (not shown), may connect the terminal pads 114 to the opposite surface of the substrate 110, as is known in the art.

[0017] An insulating layer in the form of a solder mask 120 is formed on the metal layer including the terminal pads 114. One or more additional insulating layers, such as a buffer layer 122, are formed on the solder mask 120. The buffer layer 122 helps mitigate the initiation of cracks in the IMC layer 130 by driving potential crack initiation locations away from the outer surface of the solder balls 124. Thus, if a crack develops, the crack grows inward and has a longer time to grow before failure occurs. Once formed, the BGA package 100 can be used with a similar Figure 1 The carrier substrates shown (eg, PCB boards) are joined to form an electronic device assembly (not shown).

[0018] Go to Figure 2B , the solder mask 120 may include an acrylic or polyimide plastic or epoxy resin screen-printed or spin-coated on the substrate sheet 112. The composition of the solder mask 120 is not limited to the materials discussed above, and other materials (e.g., photosensitive polymers that can be defined by light) that can act as solder resists without affecting the operation of the electronic device components can be used. In some embodiments, a dry film solder mask can be used. The composition of the buffer layer 122 can be composed of non-metallic organic materials. For example, in some embodiments, similar to the solder mask 120, the buffer layer 122 may include an acrylic or polyimide plastic or epoxy resin screen-printed or spin-coated on the solder mask 120. In some embodiments, the application of the buffer layer 122 after applying the solder mask 120 can be a continuous process. For example, when the buffer layer 122 and the solder mask 120 are composed of the same material, the layers 120 and 122 (e.g., a thick layer) can be applied simultaneously. The composition of the buffer layer 122 is not limited to those discussed above, and other organic materials (e.g., photosensitive polymers that can be defined by light) can be used. In some embodiments, the BGA package 100 may include more than one buffer layer.

[0019] An opening or hole 119 is formed in the buffer layer 122, and an opening or hole 121 is formed in the solder resist layer 120. In an exemplary embodiment of the present technology, in order to form the SMD mounting pad 128, the holes 119 and 121 are aligned to expose at least a portion of the terminal pad 114. Solder balls 124 are attached or formed on the mounting pad 128 through the holes 119 and 121. The solder resist layer 120 and the buffer layer 122 prevent the solder of the solder balls 124 from attaching to any portion of the terminal pad 114 other than the SMD mounting pad 128.

[0020] In some embodiments, one or both of the holes 119 and 121 are circular, and in some embodiments, they may be aligned to form concentric circles. In some embodiments, one or both of the holes 119 and 121 may have a non-circular shape. The sidewalls of the two holes 119, 121 may be straight or inclined or one straight and one inclined. For example, the sidewall of the buffer hole 121 may have an outward bevel (e.g., a larger opening away from the solder mask 120), while the sidewall of the hole 119 is straight, or vice versa. Of course, any combination of straight sidewalls and inclined sidewalls may be used. In some embodiments, the diameter of the hole 119 is greater than the diameter of the hole 121. In some embodiments, the diameter of the hole 121 at the interface between the buffer layer 122 and the solder mask 120 (also referred to herein as the "interface diameter") is greater than the interface diameter of the hole 119. For example, the interface diameter of the hole 121 may be 0.5% or more larger than the interface diameter of the hole 119. In some embodiments, the interface diameter of hole 121 can be greater than the interface diameter of hole 119 by a value in the range of 0.5% to 5%. The interface diameters of holes 119 and 121 can depend on the configuration and / or application of the electronic device assembly. In some embodiments, one or both holes 119 and 121 can have an interface diameter in the range of 0.2 mm to 0.4 mm.

[0021] In some embodiments, a two-step hole etching process can be used to produce holes 121 and 119. In some embodiments, hole 119 can be formed by etching both solder mask 120 and buffer layer 122. After hole 119 is formed, hole 121 (which may have a larger diameter) can be formed only by etching buffer layer 122. In other embodiments, hole 121 in buffer layer 122 is first formed by etching only buffer layer 122, and then hole 119 (which may have a smaller diameter) is formed by etching solder mask 120. Etching can be completed by photolithography and / or laser drilling process and / or another process. The etching process can be carefully controlled to ensure that over-etching and / or under-etching of layers 120, 122 is eliminated or maintained at an acceptable amount. For example, in the etching process, over-etching and / or under-etching can be controlled by the timing of laser drilling process and / or photolithography process. In some cases, selective masking of appropriate areas with a protective layer can be performed on a step-by-step basis to ensure that there is no over-etching and / or under-etching of layers 120, 122 (or at least the over-etching and / or under-etching is kept to an acceptable amount). Because those skilled in the art will understand how to perform the etching process, a detailed description of the etching process is omitted for brevity.

[0022] In some embodiments, the inner and outer solder resist layers 120 and the buffer layer 122 may have the same thickness. In other embodiments, the layers 120 and 122 may have different thicknesses. The thickness of the solder resist layer 120 and / or the buffer layer 122 may be greater than 5 microns. In some embodiments, the thickness of each layer 120, 122 may be in the range of 5 microns to 50 microns, and the combined thickness of the layers 120, 122 may be in the range of 10 microns to 100 microns. In some embodiments, the thickness of the solder resist layer 120 is greater than the thickness of the IMC layer 130. As described above, when the solder ball 124 is formed on the SMD mounting pad 128, the IMC layer 130 may be formed. In embodiments where the solder resist layer 120 is thicker than the IMC layer 130, the buffer layer 122 only contacts the solder joint matrix of the solder ball 124 without contacting the IMC mixture, which helps to mitigate crack formation. The IMC layer is not formed between the buffer layer 122 and the solder ball 124 because the buffer layer 122 is not metallic.

[0023] Figure 3 is a flow chart illustrating an example method 300 for forming a BGA package according to an embodiment of the present technology. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise indicated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0024] At frame 310, method 300 includes forming a pad on a substrate. For example, a pad 114 (e.g., a copper pad) may be formed on substrate 110. At frame 320, method 300 further includes applying a solder mask on the pad and substrate. For example, a solder mask 120 may be applied on substrate 110 and pad 114. At frame 330, method 300 also includes applying a buffer layer on the solder mask. For example, a buffer layer 122 may be applied on solder mask 120. At frame 340, method 300 includes etching the buffer layer and the solder mask to produce a first hole in the solder mask, the first hole exposing at least a portion of the pad to produce a mounting pad. For example, an opening may be formed in buffer layer 122 and solder mask 120 to expose at least a portion of pad 114 to produce hole 119 by photolithography and / or laser drilling process and / or another process. Appropriate timing and / or masking and / or other stop etching processes can be used to ensure that over-etching and / or under-etching in layers 120, 122 are eliminated or maintained at an acceptable amount. The exposed portion of pad 114 corresponds to SMD mounting pad 128. At box 350, the method further includes further etching the buffer layer to produce a second hole in the buffer layer, the interface diameter of the second hole being greater than the interface diameter of the first hole. For example, hole 121 can be produced by photolithography and / or laser drilling process and / or another process. Similarly, appropriate timing and / or masking and / or other stop etching processes can be used to ensure that over-etching and / or under-etching in layers 120, 122 are eliminated or maintained at an acceptable amount.

[0025] In some embodiments, the steps of applying solder mask and buffer layer (steps 320 and 330) can be a single continuous process. For example, if solder mask 120 and buffer layer 122 are made of the same material, a single layer with the thickness of solder mask and buffer layer can be formed. In some embodiments, in step 340, the hole in the buffer layer is first formed, and then in step 350, the hole in the solder mask can be formed. Of course, appropriate timing and / or mask and / or other stop etching processes can be used to ensure that over-etching and / or under-etching in layers 120, 122 are eliminated or maintained at an acceptable amount. In some embodiments, the method may include creating an additional buffer layer.

[0026] By using a two-step SMD design process, in which at least one buffer layer is applied on the solder mask layer, a robust electronic device assembly can be formed for high thermal stress applications. Because crack formation in the solder joints can be mitigated, exemplary embodiments of the electronic package assembly can have a high yield and low initial failure rate. In addition, those skilled in the art will recognize that the two-step SMD process of the present invention is economical and easy to implement because it only adds one additional step to the manufacture of the BGA package.

[0027] It should be noted that the above methods describe possible implementations, and that their operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, embodiments from two or more methods may be combined.

[0028] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") represents an inclusive list, so that, for example, a list of at least one of A, B, or C represents A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0029] It will be appreciated from the foregoing that, for purposes of illustration, specific embodiments of the present invention are described herein, but various modifications may be made without departing from the scope of the present invention. Of course, in the foregoing description, many specific details are discussed to provide a thorough and effective description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more specific details. In other examples, known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obfuscating other aspects of the technology. Generally, it will be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may be within the scope of the present technology.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a pad on a substrate; applying a solder resist layer on the pad and the substrate; applying a buffer layer on the solder resist layer; etching the buffer layer and the solder resist layer to produce a first hole in the solder resist layer, the first hole exposing at least a portion of the pad to produce a mounting pad; further etching the buffer layer to generate a second hole in the buffer layer, the second hole having an interface diameter greater than the interface diameter of the first hole; and A solder ball is formed on the mounting pad by applying a conductive material in the first hole and the second hole. 2 . The method according to claim 1 , wherein a thickness of the solder resist layer is greater than a thickness of an intermetallic compound layer formed at an interface of the mounting pad and the solder ball. The method of claim 1 , wherein the buffer layer comprises a non-metallic organic material.

4. The method of claim 3, wherein the non-metallic organic material comprises at least one of acrylic, polyimide plastic, or epoxy resin. 5 . The method of claim 1 , wherein the interface diameter of the second hole is 0.5% or more larger than the interface diameter of the first hole. 6 . The method of claim 5 , wherein the interface diameter of the second hole is greater than the interface diameter of the first hole by a value in the range of 0.5% to 5%. 7 . The method according to claim 1 , wherein a thickness of the solder resist layer is 5 micrometers or more and a thickness of the buffer layer is 5 micrometers or more. 8 . The method of claim 7 , wherein a combined thickness of the solder resist layer and the buffer layer is in a range of 10 microns to 100 microns.

9. The method of claim 1, wherein the mounting pad is a solder mask defined mounting pad.

10. A semiconductor device comprising: A pad mounted on the substrate; A solder resist layer, the solder resist layer being disposed on the substrate, the solder resist layer having a first hole; a buffer layer disposed on the solder resist layer, the buffer layer having a second hole, wherein the first hole and the second hole are aligned so that at least a portion of the pad is exposed, and wherein an interface diameter of the second hole is greater than an interface diameter of the first hole; and A solder ball is disposed on the exposed portion of the pad, wherein the solder ball contacts a portion of the buffer layer exposed by the second hole and further contacts a portion of the solder resist layer exposed by the first hole. 11 . The semiconductor device according to claim 10 , wherein a thickness of the solder resist layer is greater than a thickness of an intermetallic compound layer formed at an interface between the pad and the solder ball. The semiconductor device according to claim 10 , wherein the buffer layer comprises a non-metallic organic material.

13. The semiconductor device of claim 12, wherein the non-metallic organic material comprises at least one of acrylic, polyimide plastic, or epoxy resin. 14 . The semiconductor device according to claim 10 , wherein the interface diameter of the second hole is larger than the interface diameter of the first hole by 0.5% or more. 15 . The semiconductor device according to claim 14 , wherein the interface diameter of the second hole is larger than the interface diameter of the first hole by a value in a range of 0.5% to 5%. 16 . The semiconductor device according to claim 10 , wherein a thickness of the solder resist layer is 5 micrometers or more and a thickness of the buffer layer is 5 micrometers or more. 17 . The semiconductor device of claim 16 , wherein a combined thickness of the solder resist layer and the buffer layer is in a range of 10 micrometers to 100 micrometers.

18. The semiconductor device of claim 10, wherein the exposed portion of the pad is a solder mask defined mounting pad.

Images