Composite Pin Driver

Abstract

The present disclosure relates to a composite pin driver. A test system may use first and second different driver stages to provide a test signal to a device under test (DUT). The composite stage may receive a signal from the driver stage and provide a voltage output signal to the DUT through a gain circuit. The composite stage may include a buffer circuit configured to provide a first portion of the voltage output signal based on a first output signal from the first driver stage, and the composite stage may include a transimpedance circuit configured to provide a second portion of the voltage output signal based on a second output signal from the second driver stage. In one example, the gain circuit may receive a superimposed signal including the first portion and the second portion of the voltage output signal, and in response, provide a test signal to the DUT.

Description

Background Art

[0001] A test system for electronic device testing may include a pin driver circuit that provides a voltage test pulse to a device under test (DUT). In response, the test system may be configured to measure a response from the DUT, such as determining whether the DUT meets one or more specified operating parameters. The test system may optionally include multiple driver circuits, such as a Class AB driver circuit and a Class A driver circuit, to provide circuit test signals with different amplitudes or timing characteristics. In one example, the test system is configured to sense a jump on a DUT pin using an active load and a comparator circuit to measure a response from the DUT.

[0002] A system for testing digital integrated circuits (ICs) may include a driver circuit configured to provide multiple voltage levels (e.g., Vhigh, Vlow, and Vterm) to the DUT. The DUT may exhibit bidirectional (I / O) functionality in that it can both source and receive signals. The Vhigh and Vlow levels of the driver circuit are used to stimulate the DUT when in the "input" state, while Vterm acts as a terminal for the DUT in the "output" state. The switching process between Vhigh, Vlow, and Vterm can be conceptualized as a set of three switches, each with one terminal connected to Vhigh, Vlow, or Vterm and the other terminal connected to a common 50 ohm resistor, which in turn is connected to the DUT node. In this way, transitions between the three levels can be achieved by opening and closing the appropriate switches, such that only one switch is closed at any given time.

[0003] One function of an ATE test system is the ability to deliver precisely timed Vhigh, Vlow, and Vterm signals or transition signals to the DUT. It can be critical for a test system to provide essentially constant propagation delays and predictable signal edge locations independent of variables such as temperature, frequency, duty cycle, pulse width, or test vector history that can compromise the efficacy of the test system. Summary of the invention

[0004] The inventors have recognized that problems to be solved include providing a test signal generator system that is relatively small, inexpensive to produce, consumes less power than conventional systems, or provides higher fidelity relative to conventional systems. For example, the problem may include providing a test signal generator with improved pulse edge placement accuracy or improved bandwidth characteristics.

[0005] In an example, a solution to these and other problems may include a driver system having a composite stage. The composite stage may accommodate a wide range of voltage and current input and output signals and may support high bandwidth signals with greater accuracy. In an example, the composite stage may include a first input that may receive a voltage signal and may include a second input that may receive a current signal, and may provide a composite output signal based on a combination of the received voltage and current signals. In one example, a test system including the composite stage may have power handling characteristics similar to a class AB driver and may have bandwidth characteristics similar to a class A driver.

[0006] In one example, the compound stage provides a high impedance environment so that the devices used in the front-end switch or driver circuit can be many times smaller than those used in a conventional class A switch circuit. Additionally, because the switching operation can be performed in the high impedance environment of the compound stage, the front-end switch current signal can be many times smaller than the current signal used in a conventional class A switch circuit.

[0007] In one example, the composite stage can also help isolate the front-end driver or switch stage from the DUT. By improving isolation, parasitic loading effects can be reduced and bandwidth can be improved compared to traditional driver arrangements. As a result, smaller or fewer capacitive elimination devices can be used, or can be omitted entirely.

[0008] This summary is intended to provide an overview of the subject matter of this patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide more information about this patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the drawing number in which the element is first introduced.

[0010] Figure 1 An example of a test system topology including multiple driver circuits is generally shown.

[0011] Figure 2 An example of a test system topology including a composite stage and multiple driver circuits is generally shown.

[0012] Figure 3 An example of a block diagram of a composite level for a test system is generally shown.

[0013] Figure 4 An example of a schematic diagram of a portion of a composite station for a testing system is generally shown.

[0014] Figure 5An example of a method is generally shown that can include using a composite stage in a test system to provide a test signal to a DUT. DETAILED DESCRIPTION

[0015] The pin driver circuits of the test system can provide voltage pulse excitation to the device under test (DUT) at a specified time, and can optionally measure the response from the DUT. The test system can be configured to provide high-fidelity output signal pulses over a relatively large output signal amplitude range to accommodate different types of devices under test. In some examples, the test system includes a physically large current switching stage to facilitate large voltage swings. However, such a large current switching stage may have the liability of producing a smaller voltage swing because parasitic signals (e.g., stray signals caused by parasitic effects associated with the physically large switching stage) can reduce the fidelity of the test signal waveform and the test signal bandwidth.

[0016] The test systems and methods described herein provide, among other things, a pin driver architecture that can improve pulse edge placement accuracy and signal bandwidth at high power or low power operating levels. In one example, the system described herein can include a composite stage to receive and combine signals from multiple different driver circuits before providing the signals to the DUT. In one example, the composite stage can include: a voltage signal amplifier circuit, such as configured to receive and process signals from a class AB driver stage; and a transimpedance circuit, such as configured to receive and process signals from a class A driver stage. Additional driver stages, or multiple instances of one or more types of driver stages, can optionally be used with the composite stages discussed herein.

[0017] In one example, multiple drivers or driver stages may be used to provide a test system that is configurable to test a variety of semiconductor devices with varying voltage and speed requirements. Additionally, multiple drivers may be used to enhance or enable multiple signal level testing or "multiplexing" for physical layer testing. During physical layer testing, multiple drivers may be switched simultaneously to provide a variety of different stimulus or drive signals to the DUT.

[0018] In an example, a Class AB driver can be configured to pass a wide range of different voltage amplitude signals and can be configured to consume a minimal amount of power. The Class AB driver can have moderate bandwidth and timing accuracy. The Class AB driver can include or use a diode bridge, a transistor differential pair, or other switching elements. In an example, the Class AB driver can be configured to perform moderate speed testing of a system-on-chip circuit or other circuit or device.

[0019] In one example, a Class A driver can be configured to pass a relatively low amplitude current signal and can be configured to have high bandwidth and timing accuracy. In an example, a Class A driver can be configured to switch a larger current signal directly at the output node of the driver or at the input of the DUT. In one example, a Class A driver can be configured to perform high-speed testing of storage circuits or other devices. In one example, for example, due to the large component devices used to switch large current signals on the DUT, the Class A driver may be parasitic on the DUT, thereby reducing the overall bandwidth of the test system. In one example, certain test systems may include capacitive cancellation elements to offset the loading effects of the Class A driver, however, the physical size of such elements may be large and may result in increased part size and increased chip cost. In one example, as discussed herein, a composite stage can be used with a smaller Class A driver to reduce or eliminate the need for such a cancellation element.

[0020] Figure 1 A first example 100 of a test system topology including a plurality of driver circuits is generally shown. The first example 100 includes a first DriverAB 108 that may include a class AB driver circuit and a first DriverA 116 that may include a class A driver circuit. The first example 100 may further include an output element, such as a first resistor 104, which may be configured to provide a specified output or load impedance. In an example, the first example 100 may include a first load circuit 122, which may include, for example, a comparator circuit, an active load, or other load device. In one example, the test system is configured to provide a first output current 106i_OUT at a DUT pin 102.

[0021] In an example, the first DriverAB 108 may be configured to generate a voltage excitation signal by selecting between parallel-connected diode bridges, where each bridge is driven by a unique dedicated DC voltage level. Figure 1 In the first example 100, DC voltages Vih 110 and Vil 112 drive a diode bridge in a first DriverAB 108. The switching stage may be followed by a voltage buffer stage that may provide power gain, such as may be used to generate high current to service a 50 ohm DUT environment.

[0022] In contrast to the first driver AB 108, the first driver A 116 may be configured to generate transitions on the DUT pin 102 using a relatively large current switching stage that may be directly coupled to the DUT pin 102. The current switching stage in the first driver A 116 may be responsive to a control signal Swing 120 (e.g., which may be a voltage control signal) to alternately switch current to and from the DUT pin 102. The first driver A 116 may provide high-speed operation, for example, because it is not burdened by a Class AB voltage buffer stage with its attendant bandwidth limitations and other performance limitations.

[0023] In one example, the first driver A 116 can be configured to provide a relatively low amplitude signal at the DUT pin 102. For example, the first driver A 116 can provide a signal having a swing of approximately 2 volts. The first DriverAB 108 can be configured to provide a relatively high amplitude signal at the DUT pin 102, for example, -1.5 volts to +7 volts. The first driver A 116 typically operates at a higher switching speed or bandwidth than the first driver AB 108. In one example, the first driver AB 108 can be configured to sink the switching current from the first driver A 116. That is, the first DriverAB 108 can act as a buffer into which the first DriverA 116 can provide current, for example, through the first resistor 104.

[0024] A specific one or both of the first DriverAB 108 and the first DriverA 116 may be selected to meet completely different DUT test requirements that may not otherwise be met by a single driver. For example, while both driver circuits may provide a DUT waveform, the first DriverAB 108 may be configured to provide a large amplitude, low bandwidth stimulus signal, and the first DriverA 116 may be configured to provide a low amplitude, high bandwidth stimulus signal.

[0025] In the example, the first DriverAB 108 and the first DriverA 116 do not share an enable pin. Instead, each driver circuit includes independent enable control through pins EnAB 114 and EnA 118. The independent enable control helps the first DriverAB 108 act as a low-speed high-voltage excitation source and act as a static non-transition buffer to absorb the switching current from the first DriverA 116.

[0026] Figure 2A second example 200 of a test system topology is generally shown including a composite stage 202 and a plurality of driver circuits. The second example 200 may include a second DriverAB 208 and a second DriverA 216. In the example, the second DriverAB 208 may be a device that is the same or similar to the first DriverAB 108, and the second DriverA 216 may be a device that is similar to the first DriverAB 108. Figure 1 The first driver A 116 in the example is the same or a similar device.

[0027] In one example, the second driver A 216 can be a physically smaller device than the first driver A 116. For example, the second driver A 216 can be at least one, and optionally multiple, orders of magnitude smaller than the first driver A 116. The second driver A 216 can be configured to provide a signal having similar timing characteristics as the first driver A 116, but having different amplitude characteristics. In one example, the second driver A 216 can be manufactured more expensively than the first driver A 116 because it can occupy less chip area or can include or use components with more relaxed performance requirements.

[0028] The second example 200 may further include a first resistor 104, a DUT pin 102, and a first load circuit 122, which may be similar to the above. Figure 1 That is, the DriverAB 208 and the second DriverA 216 of the second example 200 may be the same as or similar to the items described in the discussion of FIG. Figure 1 The exemplary drivers are used interchangeably to provide a signal to the DUT via the DUT pin 102, or as in Figure 1 In the example of FIG. 1 , the second DriverAB 208 and the second DriverA 216 may be terminated with the same first resistor 104 or first load circuit 122 .

[0029] The second example 200 may further include a composite stage 202 and a first amplifier circuit 204. The composite stage 202 may be configured to receive the test signal from the second driver AB 208 and the second driver A 216 and, in response, provide the signal to the DUT pin 102 through the first amplifier circuit 204. The first amplifier circuit 204 may be configured to buffer or amplify the signal from the composite stage 202 for transmission to the DUT pin 102. In an example, the composite stage 202 may receive and respond to the signal from the second driver AB 208 or the second driver A 216 concurrently or sequentially.

[0030] The composite stage 202 may provide a relatively high input impedance environment for signals received from the second driver AB 208 or the second driver A 216. Thus, the switching signal provided by one or both of the second driver AB 208 or the second driver A 216 may be relatively smaller than, for example, the switching signal provided by the second driver AB 208 or the second driver A 216. Figure 1 The first example 100 of the embodiment of the present invention may be a signal provided by the first driver AB 108 or the first driver A 116. For example, the switch current signal from the second DriverA 216 may be one or more orders of magnitude smaller than the signal from the first DriverA 116. The composite stage 202 may receive the smaller signals, convert them to voltage signals, and then pass the signals to the DUT pin 102 through the first amplifier circuit 204. In the case where the second stage driver 216 is isolated from the DUT pin 102 by the composite stage 202 and the first amplifier circuit 204, the parasitic loading of the second stage driver 216 may be reduced or eliminated, and thus a compensation component or other mitigation circuit may be omitted from the signal path.

[0031] Figure 3 Generally, an example of a block diagram of the composite stage 202 is shown. The composite stage 202 may include a composite stage gain circuit 308 and a transimpedance circuit 310, wherein the composite stage gain circuit 308 may be configured to receive a first input signal from a voltage input node 302 and the transimpedance circuit 310 may be configured to receive a second input signal from a current input node 304. That is, the composite stage 202 may be configured to receive a voltage input signal at the voltage input node 302 and the composite stage 202 may be configured to receive a current input signal at the current input node 304.

[0032] In an example, the composite stage gain circuit 308 may include a buffer circuit or an amplifier circuit configured to receive one or more signals from the second DriverAB 208 using the voltage input node 302. In response to the signal at the voltage input node 302, the composite stage gain circuit 308 may provide a first portion of the output signal at the summing node 312. In an example, the composite stage gain circuit 308 may include a voltage buffer that provides a signal that is substantially the same as the signal received from the second DriverAB 208 at the voltage input node 302 in amplitude, duration, frequency, phase, or other characteristics.

[0033] In an example, the transimpedance circuit 310 may include a circuit configured to receive one or more signals from the second driver A216 using the current input node 304. In response to the current signal received at the current input node 304, the transimpedance circuit 310 may provide a second portion of the output signal at the summing node 312. That is, the transimpedance circuit 310 may receive the current signal and provide a corresponding voltage signal in response. In an example, the transimpedance circuit 310 may be configured to receive the current signal at the current input node 304 and then provide a voltage signal having an amplitude, duration, frequency, phase, or other signal characteristic that corresponds to or depends on the characteristics of the received current signal.

[0034] In one example, the summing node 312 receives a first portion of the output signal from the composite stage gain circuit 308 and receives a second portion of the output signal from the transimpedance circuit 310. The summing node 312 may include a node or circuit configured to combine or sum the signal portions together to provide an output signal that is a superposition of the first and second portions of the output signal. Other signals may similarly be superimposed or combined at the summing node 312. The composite stage 202 may provide an output signal of the summing node 312 from the composite stage output node 306 to, for example, the first amplifier circuit 204. For example, the first amplifier circuit 204 may receive a superposition signal including the first and second portions of the voltage output signal from the composite stage output node 306 and, in response, provide a test signal to the first resistor 104 or the DUT pin 102.

[0035] Figure 4 An example of a schematic diagram of a composite level 202 is generally shown. In one example, the schematic diagram of the composite level 202 may include or represent Figure 3 The block diagram illustrates components that may be used in the composite stage gain circuit 308 or the transimpedance circuit 310 .

[0036] exist Figure 4 In an example of the composite stage 202, the composite stage 202 includes a composite stage amplifier circuit 402 configured to receive a voltage signal from the voltage input node 302. The composite stage amplifier circuit 402, in response to the signal at the voltage input node 302, can provide a corresponding voltage signal to a feedback network 406 coupled between the composite stage amplifier circuit 402 and the composite stage output node 306. In an example, the composite stage amplifier circuit 402 and / or the feedback network 406 can be configured to provide a signal at the composite stage output node 306 that can include a substantially 1:1 representation of the signal received at the voltage input node 302. Various components of the feedback network 406 are shown as examples, and other configurations or components can be used, for example, to similarly enhance the bandwidth characteristics of the composite stage 202.

[0037] exist Figure 4 In an example, the composite stage 202 includes a transimpedance resistor 404. The transimpedance resistor 404 can be coupled to the current input node 304 and can be configured to receive a current input signal from, for example, the second driver A216. For example, the transimpedance resistor 404 can have a fixed resistance characteristic, such as 1 kOhm. In an example, the transimpedance resistor 404 can have a variable or selectable resistance characteristic, which can be determined based on, for example, the magnitude or other characteristics of the signal received from the current input node 304. The transimpedance resistor 404 can be used to receive the current input signal and convert it into a voltage signal that can be combined with other voltage signals from the composite stage amplifier circuit 402 or the voltage input node 302, such as using a feedback network 406 or using another circuit configured to combine signals. In an example, the feedback network 406 can be configured to reduce the apparent input impedance characteristic of the composite stage 202 at the current input node 304, for example, to be less than the impedance characteristic of the transimpedance resistor 404.

[0038] Figure 5 Generally, an example of a method 500 is shown, which can include using a composite stage in a test system to provide a test signal to a DUT. In an example, the method 500 can include or use a Figure 2 , Figure 3 or Figure 4 The composite stage 202 of the example of method 500 can be configured to receive corresponding voltage and current excitation signals, convert the current excitation signal to a voltage, and combine the voltage signals to provide a voltage output signal to the DUT.

[0039] At block 502, the method 500 may include providing a control signal to a voltage driver. Block 502 may include or use a timing controller or other control circuit to issue a control signal to a voltage driver (e.g., a second DriverAB 208). In an example, block 502 may include using a timing controller to provide the Vih 110 and Vil 112 signals to the second DriverAB 208 at different corresponding times and non-overlapping times. In response to the control signal provided at block 502, the method 500 may continue at block 504 and use the voltage driver to provide a voltage test signal to the composite stage. For example, block 504 may include using the second DriverAB 208 to provide a voltage test signal or multiple voltage test signals to the composite stage 202.

[0040] At block 506, the method 500 may include providing a control signal to a current driver. Block 506 may include or use the same or different timing controller or other control circuit to issue a control signal to a current driver (e.g., second driver A 216). In an example, block 506 may include providing the control signal Swing 120 to the second driver 216 using the timing controller. In response to the control signal provided at block 506, the method 500 may continue at block 508 and use the current driver to provide a current test signal to the composite stage. For example, block 508 may include providing a current test signal or multiple current test signals to the composite stage 202 using the second driver A 216. In an example, the control signals provided in blocks 502 and 506 may be provided substantially simultaneously, so that the voltage test signal provided in block 504 and the current test signal provided in block 508 may be provided substantially sequentially or may be provided substantially simultaneously. In other words, the voltage test signal may be provided to the composite stage at different times or simultaneously with the current test signal being provided to the composite stage.

[0041] At block 510, the composite stage may receive one or more voltage test signals from block 504, and the composite stage may receive one or more current test signals from block 508. The various voltage and current signals may have different non-overlapping arrival times and durations, or the signals may overlap or may be received simultaneously. The one or more voltage test signals may be received at the voltage input node 302 of the composite stage 202, and the one or more current test signals may be received at the current input node 304 of the composite stage 202.

[0042] Block 512 and block 514 may be performed substantially simultaneously, or may be performed sequentially or at different times. At block 512, method 500 may include buffering the voltage test signal received at the composite stage at block 510, and in response, providing a first voltage signal portion of the composite stage output signal. Buffering the voltage test signal at block 512 may include using one or more of the composite stage gain circuit 308, the composite stage amplifier circuit 402, or the feedback network 406 of the composite stage 202.

[0043] At block 514, method 500 may include processing the current test signal received at the composite stage at block 510 and, in response, providing a second voltage signal portion of the composite stage output signal. Processing the current test signal at block 514 may include using a transimpedance device or circuit, such as using the transimpedance circuit 310 or the transimpedance resistor 404 of the composite stage 202.

[0044] At block 516, method 500 may include combining the first and second voltage signal portions from blocks 512 and 514 to provide a composite level output signal. In an example, the first and second voltage signal portions may be summed or superimposed, for example, at summing node 312, to provide the composite level output signal. At block 518, the composite level output signal may be buffered or amplified, for example, using first amplifier circuit 204, and provided to the DUT, for example, DUT pin 102.

[0045] In one example, as previously described, the problem to be solved includes providing a test signal generator system that is relatively small, inexpensive to produce, consumes less power than conventional systems, or provides higher fidelity relative to conventional systems. For example, the problem may include providing a test signal generator with improved pulse edge placement accuracy or improved bandwidth characteristics. Various aspects of the present disclosure can help provide solutions to these and other problems associated with test systems.

[0046] In one example, aspect 1 may include or use a subject matter (e.g., an apparatus, system, device, method, device, or device-readable medium for performing an action, including an apparatus or product that includes instructions that can be caused by the device when executed to perform an action), for example, may include or use a composite stage circuit used as a driver system, the composite stage circuit is responsive to input signals of at least a first driver and a second driver, and the composite stage circuit is configured to provide an output voltage signal to an output gain stage at a composite stage output node. In aspect 1, the composite stage circuit may include: a voltage input node configured to receive an input voltage signal from the first driver, a current input node configured to receive an input current signal from the second driver, a first gain circuit configured to receive the input voltage signal at the voltage input node and provide a first portion of the output voltage signal at the composite stage output node based on the input voltage signal, and a transimpedance circuit configured to receive the input current signal at the current input node and provide a second portion of the output voltage signal at the composite stage output node based on the input current signal. In aspect 1, the first and second portions of the output voltage signal may be superimposed at the composite stage output node to provide the output voltage signal.

[0047] Aspect 2 may include or use the subject matter of Aspect 1, or may be combined with the subject matter of Aspect 1 to optionally include: a transimpedance circuit including a resistor connected in series between the current input node and the composite stage output node.

[0048] Aspect 3 may include or use the subject matter of Aspect 2, or may be combined with the subject matter of Aspect 2 to optionally include: the first gain circuit includes a feedback network configured to reduce an apparent input impedance of the current input node to less than an impedance characteristic of a resistor.

[0049] Aspect 4 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 1 to 3 to optionally include or use: an output gain stage configured to provide a test signal to a device under test (DUT) via an output resistor, wherein the test signal is based on an output voltage signal at an output node of the composite stage.

[0050] Aspect 5 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 1 to 4 to optionally include or use: the first gain circuit includes a feedback network configured to enhance the bandwidth characteristics of the composite stage circuit.

[0051] Aspect 6 may include or use the subject matter of aspect 5, or may be combined with the subject matter of aspect 5 to optionally include: the first gain circuit is configured to provide a first portion of the output voltage signal with substantially the same amplitude and phase as the input voltage signal from the first driver.

[0052] Aspect 7 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 1 to 6 to optionally include or use: the first driver includes a Class AB driver configured to provide a voltage test signal at a first speed, and the second driver includes a Class A driver configured to provide a current test signal at a second speed less than the first speed.

[0053] Aspect 8 may include or use, or may optionally be combined with the subject matter of one or any combination of aspects 1 to 7 to optionally include: the voltage input node is configured to receive the input voltage signal from the first driver in response to a first control signal from a control circuit, and the current input node is configured to receive the input current signal from the second driver in response to a second control signal from the control circuit. In aspect 8, the control circuit may assert the first and second control signals simultaneously.

[0054] Aspect 9 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 1 to 8 to optionally include: the first and second portions of the output voltage signal are superimposed or combined at the composite stage output node using a summing circuit.

[0055] Aspect 10 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 1 to 9 to optionally include: a first gain circuit coupled to the transimpedance circuit at the composite stage output node.

[0056] Aspect 11 may include or use a subject matter (e.g., an apparatus, system, device, method, device, or device-readable medium for performing an action, including an apparatus or product that includes instructions that can be caused by the device when executed to perform an action), for example, may include or use a driver circuit for providing a test signal to a device under test (DUT). In aspect 11, the driver circuit includes: a voltage buffer circuit configured to provide a first voltage output signal at an intermediate output node in response to an input voltage signal from a first driver stage, and a transimpedance circuit configured to provide a second voltage output signal at the intermediate output node in response to an input current signal from a different second driver stage, and an amplifier circuit configured to receive a combined signal including a superposition of the first voltage output signal and the second voltage output signal from the intermediate output node, and provide an output signal to the DUT in response to the combined signal.

[0057] Aspect 12 may include or use the subject matter of Aspect 11, or may be combined with the subject matter of Aspect 11 to optionally include or use: a first driver stage providing an input voltage signal, and including or using a second driver stage providing an input current signal.

[0058] Aspect 13 may include or use the subject matter of Aspect 12, or may be combined with the subject matter of Aspect 12 to optionally include: the first driver stage is configured to provide an input voltage signal at two or more discrete and non-zero signal levels, and includes a second driver stage providing an input current signal at two or more discrete non-zero signal levels.

[0059] Aspect 14 may include or use, or may optionally be combined with the subject matter of one or any combination of aspects 12 to 13 to optionally include or use: a control circuit configured to provide signal amplitude and signal timing instructions to each of the first and second driver stages.

[0060] Aspect 15 may include or use, or may optionally be combined with the subject matter of one or any combination of aspects 12 to 14 to optionally include or use: the first driver stage provides a relatively low speed signal as an input voltage signal. In aspect 15, the second driver stage may be configured to provide a relatively high speed signal as an input current signal.

[0061] Aspect 16 may include or use subject matter (e.g., an apparatus, system, device, method, device, or device-readable medium for performing an action, including an apparatus or product that can cause instructions to perform an action when executed by the device), for example, may include or use a method for providing a digital test signal to a device under test (DUT). In aspect 16, the method may include: providing a voltage test signal to a voltage input node, providing a current test signal to a current input node, buffering the voltage test signal to provide a first voltage signal portion of a composite output signal, processing the current test signal to provide a second voltage signal portion of the composite output signal, wherein the composite output signal includes a combination of the first and second voltage signal portions, and buffering the composite output signal to provide the digital test signal to the DUT.

[0062] Aspect 17 may include or use the subject matter of aspect 16 or may be combined with the subject matter of aspect 16 to optionally include: processing the current test signal including using a transimpedance circuit to receive the current test signal and in response providing a first voltage signal portion of the composite output signal.

[0063] Aspect 18 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 16 or 17 to optionally include: buffering the composite output signal using an amplifier circuit.

[0064] Aspect 19 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 16 to 18 to optionally include: using a first driver circuit belonging to a first class of signal drivers to provide a voltage test signal, and using a second driver circuit belonging to a different second class of signal drivers to provide a current test signal.

[0065] Aspect 20 may include or use, or may optionally be combined with the subject matter of one or any combination of Aspects 16 to 19 to optionally include: providing timing and / or amplitude control signals to the first and second driver circuits, and in response, using the first and second driver circuits to provide a voltage test signal and a current test signal, respectively.

[0066] Each of these non-limiting aspects may stand alone or may be combined in various permutations or combinations with one or more of the other aspects, examples or features discussed elsewhere herein.

[0067] This detailed description includes references to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show specific embodiments in which the present invention can be practiced by way of illustration. These embodiments are also referred to as "examples" in this article. In addition to those elements shown or described, such examples may include elements. However, the inventors also contemplate examples in which only those elements shown or described are provided. The inventors contemplate examples using any combination or arrangement of those elements shown or described (or one or more aspects thereof), with respect to the specific examples (or one or more aspects thereof) shown or described herein, or other examples (or one or more aspects thereof).

[0068] In this document, the terms "a" or "an" are used in patent documents to include one or more, independent of any other instances or uses of "at least one" or "one or more". In this document, unless otherwise stated, the term "or" is used to indicate a non-exclusive or "A or B" includes "A but not B", "B but not A", and "A and B". In this document, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein".

[0069] In the following claims, the terms "including" and "comprising" are open-ended, that is, systems, apparatus, articles, compositions, preparations, or methods that include elements in addition to the elements listed after the term in a claim are still considered to be within the scope of the claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0070] The method examples described herein may be at least partially machine or computer-implemented. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions, which may be operable to configure an electronic device to perform the method as described in the above examples. The implementation of such a method may include codes such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may constitute a part of a computer program product. In addition, in an example, the code may be tangibly stored on one or more volatile, non-temporary or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable disks (such as optical disks and digital video disks), cassettes, memory cards or memory sticks, random access memories (RAM), read-only memories (ROM), etc.

[0071] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, other embodiments may be used, for example, by a person of ordinary skill in the art. An abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. The premise of submitting this document is that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the present disclosure. This should not be interpreted as intending to make undeclared public features essential to any claim. Instead, the subject matter of the invention may be less than all the features of a specific disclosed embodiment. Therefore, the following claims are thus incorporated into the detailed description as examples or embodiments, each claim existing independently as an independent embodiment, and it is expected that such embodiments may be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents given by these claims.

Claims

1. A composite stage circuit for a pin driver system, the composite stage circuit being responsive to respective input signals from at least a first driver and a second driver and configured to provide an output voltage signal to an output gain stage at a composite stage output node, the composite stage circuit comprising: a voltage input node configured to receive an input voltage signal from the first driver; a current input node configured to receive an input current signal from the second driver; a first gain circuit configured to receive the input voltage signal at the voltage input node and provide a first portion of the output voltage signal at the composite stage output node based on the input voltage signal; and a transimpedance circuit configured to receive the input current signal at the current input node and provide a second portion of the output voltage signal at the composite stage output node based on the input current signal; Wherein a first portion and a second portion of the output voltage signal are combined at the composite stage output node to provide the output voltage signal.

2. The composite stage circuit of claim 1, wherein the transimpedance circuit comprises a resistor or resistance connected in series between the current input node and the composite stage output node.

3. The composite stage circuit of claim 2, wherein the first gain circuit includes a feedback network configured to provide an apparent input impedance of the current input node that is less than an impedance characteristic of the resistor or resistors.

4. The composite stage circuit of claim 1, further comprising an output gain stage configured to provide a test signal to a device under test (DUT) via an output resistor, wherein the test signal is based on an output voltage signal at an output node of the composite stage.

5. The composite stage circuit of claim 1, wherein the first gain circuit comprises a feedback network configured to establish a bandwidth characteristic of the composite stage circuit.

6. The composite stage circuit of claim 5, wherein the first gain circuit is configured to provide a first portion of the output voltage signal with amplitude and phase characteristics that correspond to amplitude and phase characteristics of an input voltage signal from the first driver.

7. The composite stage circuit of claim 1, wherein the first driver comprises a class AB driver configured to provide a voltage test signal at a first speed, and wherein the second driver comprises a class A driver configured to provide a current test signal at a second speed less than the first speed.

8. The composite stage circuit of claim 1, wherein the voltage input node is configured to receive the input voltage signal from the first driver in response to a first control signal from a control circuit, and wherein the current input node is configured to receive the input current signal from the second driver in response to a second control signal from the control circuit, wherein the control circuit asserts the first control signal and the second control signal at least partially simultaneously.

9. The composite stage circuit of claim 1, wherein the first and second portions of the output voltage signal are summed at the composite stage output node using a summing circuit.

10. The composite stage circuit of claim 1, wherein the first gain circuit is coupled to the transimpedance circuit at the composite stage output node.

11. A driver circuit for providing a test signal to a device under test (DUT), the driver circuit comprising: a voltage buffer circuit configured to provide a first voltage output signal at an intermediate output node in response to an input voltage signal from the first driver stage; a transimpedance circuit configured to provide a second voltage output signal at the intermediate output node in response to an input current signal from a different second driver stage; and The amplifier circuit is configured to receive a combined signal including a superposition of the first voltage output signal and the second voltage output signal from the intermediate output node, and provide an output signal to a device under test DUT in response to the combined signal.

12. The driver circuit of claim 11, further comprising a first driver stage configured to provide an input voltage signal, and a second driver stage configured to provide an input current signal.

13. The driver circuit of claim 12, wherein the first driver stage is configured to provide the input voltage signal at two or more discrete and non-zero signal levels, and wherein the second driver stage is configured to provide the input current signal at two or more discrete and non-zero signal levels.

14. The driver circuit of claim 12, further comprising a control circuit configured to provide signal amplitude instructions and signal timing instructions to each of the first and second driver stages.

15. The driver circuit of claim 12, wherein the first driver stage is configured to provide a relatively low speed signal as the input voltage signal, and The second driver stage is configured to provide a relatively high speed signal as the input current signal.

16. A method for providing a digital test signal to a device under test (DUT) using a driver circuit, wherein the driver circuit is a driver circuit according to any one of claims 11-15, The driver circuit further comprises: a voltage input node configured to receive the input voltage signal from the first driver stage; a current input node configured to receive the input current signal from the second driver stage; The method includes: providing a voltage test signal to the voltage input node; providing a current test signal to the current input node; buffering the voltage test signal by the voltage buffer circuit to provide a first voltage signal portion of a composite output signal; processing the current test signal through the transimpedance circuit to provide a second voltage signal portion of the composite output signal, wherein the composite output signal comprises a combination of the first voltage signal portion and the second voltage signal portion; and The composite output signal is buffered by the amplifier circuit to provide a digital test signal to a device under test (DUT).

17. The method of claim 16, wherein buffering the composite output signal comprises amplifying the composite output signal.

18. The method of claim 16, wherein providing the voltage test signal comprises using a first class AB driver circuit, and wherein providing the current test signal comprises using a second, different class A driver circuit.

19. The method of claim 18, further comprising providing at least one of a timing control signal or an amplitude control signal to the first driver circuit and the second driver circuit, respectively, and in response, providing a voltage test signal and a current test signal using the first driver circuit and the second driver circuit, respectively.

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