Memory subsystem with internal logic to perform machine learning operations

Abstract

The present application relates to a memory subsystem having internal logic for performing machine learning operations. A memory component may include a memory cell, wherein a first region of the memory cell will store a machine learning model and a second region of the memory cell will store input data and output data of the machine learning operation. A controller may be coupled to the memory component via one or more internal buses to perform the machine learning operation by applying the machine learning model to the input data to generate the output data.

Description

Technical Field

[0001] The present invention relates generally to memory components, and more particularly to memory subsystems having internal logic for performing machine learning operations. Background Art

[0002] The memory subsystem may be a storage device, a memory module, and a mixture of a storage device and a memory module. The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] In one aspect, the present application relates to a system comprising: a memory component comprising a plurality of memory cells, wherein a first region of the memory cells will store a machine learning model and a second region of the memory cells will store input data and output data of a machine learning operation related to the machine learning model; and a controller coupled to the memory component via one or more internal buses to perform the machine learning operation by applying the machine learning model to the input data to generate output data.

[0004] In another aspect, the present application relates to a method comprising: receiving a request to perform a machine learning operation at a memory subsystem; configuring a memory component of the memory subsystem to perform a portion of the machine learning operation; receiving a result of the execution of the portion of the machine learning operation from the memory component; and executing the remaining portion of the machine learning operation at a controller of the memory subsystem through a processing device based on the result of the execution of the portion of the machine learning operation received from the memory component.

[0005] In another aspect, the present application relates to a system comprising: a memory component; and a processing device operatively coupled to the memory component to perform the following operations: receiving a request to perform a machine learning operation; configuring the memory component of a memory subsystem to perform a portion of the machine learning operation; receiving a result of the execution of the portion of the machine learning operation from the memory component; and executing the remaining portion of the machine learning operation at a controller of the memory subsystem based on the result of the execution of the portion of the machine learning operation received from the memory component. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the invention.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the invention is described.

[0008] Figure 2 An example computing environment including one or more memory components including a machine learning component according to some embodiments of the invention is described.

[0009] Figure 3 An example memory component having an internal machine learning operation component according to some embodiments of the present invention is described.

[0010] Figure 4 is a flow chart of an example method for performing machine learning operations and for storing host data at a memory component according to some embodiments.

[0011] Figure 5 An example memory component having an internal machine learning operation component based on a memory cell of the memory component according to some embodiments of the present invention is illustrated.

[0012] Figure 6 is a flow chart of an example method of allocating portions of a memory component to machine learning operations and storing host data in accordance with some embodiments.

[0013] Figure 7 is a flow chart of an example method for providing an indication of a capacity of a memory component to a host system based on a machine learning model in accordance with some embodiments.

[0014] Figure 8 Machine learning operation components implemented in a memory subsystem controller of a memory subsystem according to some embodiments of the present invention are described.

[0015] Fig. 9 Machine learning operation components implemented in one or more memory components of a memory subsystem according to some embodiments of the present invention are described.

[0016] Fig.10 is a flow chart of an example method of performing a portion of a machine learning operation at one or more memory components of a memory subsystem in accordance with some embodiments.

[0017] Fig.11 An example memory component and memory subsystem having a single bus for transmitting data for a memory space and a machine learning space according to some embodiments of the present invention are described.

[0018] Fig.12 is a flow chart of an example method for transmitting a requested operation to a memory space or a machine learning space based on the type of operation according to some embodiments.

[0019] Fig.13is a flow chart of an example method for providing a requested operation to a memory space or a machine learning space based on a memory address according to some embodiments.

[0020] Fig.14 Example memory components and memory subsystems having separate buses for transmitting data for a memory space and a machine learning space according to some embodiments of the present invention are described.

[0021] Fig.15 is a flow chart of an example method of performing operations in an order based on the priority of machine learning operations according to some embodiments of the present invention.

[0022] Fig.16A A series of operations are described in which a memory space and a machine learning space for a memory component or memory subsystem have been received according to some embodiments of the present invention.

[0023] Fig. 16B A series of operations that have been sorted based on priorities for machine learning operations according to some embodiments of the present invention are described.

[0024] Fig.17 is a flow chart of an example method for changing the performance of a machine learning operation based on a performance metric associated with a memory space in accordance with some embodiments.

[0025] Fig.18 is a block diagram of an example computer system in which embodiments of the invention may operate. DETAILED DESCRIPTION

[0026] Aspects of the present invention relate to a memory subsystem having internal logic for performing machine learning operations. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system can utilize a memory subsystem that includes one or more memory components. The host system can provide data for storage at the memory subsystem and can request retrieval of data from the memory subsystem.

[0027] A conventional memory subsystem may utilize conventional memory components to store and retrieve data for a host system. The host system may perform machine learning operations that utilize a machine learning model to process data. For example, a machine learning model may be used to classify data or make other inferences or decisions based on processing of the data by the machine learning model. A machine learning model refers to a model artifact that is created by a training process and may be composed of a single level of linear or nonlinear operations (e.g., a support vector machine [SVM]) or multiple levels of nonlinear operations such as a neural network (e.g., a deep neural network, a spiking neural network, a recursive neural network, etc.). As an example, a deep neural network model may have one or more hidden layers and may be trained by adjusting the weights of the neural network according to a back-propagation learning algorithm or the like.

[0028] Conventionally, the memory subsystem may store data to be processed (e.g., input data to be applied to a machine learning model) and a machine learning model. The host system may further utilize a machine learning processor (e.g., a neural network processor or a neural network accelerator) that performs machine learning operations based on data and machine learning models stored at a memory component of the memory subsystem. For example, the data and the machine learning model may be retrieved from the memory component and provided to the machine learning processor. For certain machine learning operations, there may be repeated transmissions of intermediate data of the machine learning operation (e.g., intermediate data generated by different layers of the machine learning model) between the machine learning processor and the memory component of the memory subsystem. For example, during the execution of the machine learning operation, data may be transmitted via an external bus or interface between the memory component and the machine learning processor. The transmission of data, machine learning models, any intermediate data, and output data between the memory component (and / or memory subsystem) and a separate machine learning processor may acquire additional time or latency to transmit various data on a separate external bus or interface coupling the memory component or memory subsystem with a separate machine learning processor.

[0029] Aspects of the present invention solve the above and other deficiencies by enabling a memory component to have internal logic for performing machine learning operations. For example, the functionality of a machine learning processor can be implemented within the internal logic of a memory component, so that a separate and external bus or interface is not used to transmit data, machine learning models, and any intermediate data between the memory component and / or memory subsystem and an external machine learning processor. For example, the machine learning processor can be implemented by internal logic based on memory cells of a memory component, or the machine learning processor can be implemented by internal logic based on digital logic or resistor arrays implemented inside the memory component. In some embodiments, the machine learning processor can be implemented within a memory subsystem. For example, the machine learning processor can be implemented inside a memory component included in a memory subsystem, and / or the machine learning processor can be implemented inside a controller of the memory subsystem (also referred to as a memory subsystem controller), or as a separate component of the memory subsystem (e.g., a separate machine learning processor circuit).

[0030] Thus, a memory component (or memory subsystem) can be used to perform machine learning operations without using an external machine learning processor. In addition, the same memory component or memory subsystem can also be used to store and retrieve data for a host system. Thus, a host system can utilize the same memory component or memory subsystem to store and retrieve host data while also performing machine learning operations for the host system.

[0031] Advantages of the present invention include, but are not limited to, improved performance of machine learning operations. For example, because no or less information (e.g., input data, intermediate data for machine learning operations, or machine learning models) is transmitted from a memory component or memory subsystem to an external machine learning processor via an external bus or interface, the latency in providing such information to be used in a machine learning operation can be reduced. As a result, the internal machine learning processor can receive input data and machine learning models in less time while also storing and retrieving intermediate data and output results of machine learning operations in less time. As a result, the performance of a memory component or memory subsystem to perform machine learning operations can be improved because less time is used to perform a single machine learning operation, thereby facilitating the memory component or memory subsystem to perform additional machine learning operations.

[0032] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the invention is illustrated. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0033] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage devices (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0034] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. The host system 120 uses, for example, the memory subsystem 110 to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0035] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices including a memory and a processing device. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize an NVM express (NVMe) interface to access a memory component (e.g., a memory device 130). The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0036] The memory devices may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0037] Examples of non-volatile memory devices (e.g., memory devices 130) include NAND type flash memory. Each of the memory devices 130 may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. Each of the memory cells may store one or more data bits used by the host system 120. In addition, the memory cells of the memory devices 130 may be grouped into memory pages or memory blocks, which may refer to units of a memory component for storing data.

[0038] Although non-volatile memory components such as NAND-type flash memory are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), magnetic random access memory (MRAM), "NOR" (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells.

[0039] The memory subsystem controller 115 may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0041] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present invention, the memory subsystem 110 may not include the memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0043] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0044] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. In the same or alternative embodiments, local media controller 135 may include machine learning operation component 113 to perform machine learning operations, and / or machine learning operation component 113 may be implemented based on internal logic of memory devices 130 and / or 140.

[0045] The memory subsystem 110 includes a machine learning operation component 113 that can perform machine learning operations. In some embodiments, the memory subsystem controller 115 includes at least a portion of the machine learning operation component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the machine learning operation component 113 is part of the host system 110, an application, or an operating system.

[0046] The machine learning operation component 113 can be used to perform machine learning operations. For example, the machine learning operation component 113 can receive data from the memory component and can also receive a machine learning model from the memory component. The machine learning operation component 113 can perform machine learning operations based on the received data and the received machine learning model to produce output results. Other details about the operation of the machine learning operation component 113 are described below.

[0047] Figure 2 An example computing environment including one or more memory components including a machine learning component 225 is illustrated according to some embodiments of the present invention. In general, the memory component 220 may correspond to Figure 1 Memory device 130 or memory device 140. Memory component 220 may be a volatile memory component or a non-volatile memory component, for example.

[0048] like Figure 2As shown in , the memory component 220 may include a machine learning operation component 225 that can perform machine learning operations. In some embodiments, the machine learning operation may include, but is not limited to, the processing of data using a machine learning model 231 to classify the data, make predictions or decisions, or any other type of output results. The machine learning model 231 may be based on, but is not limited to, a neural network such as a spiking neural network, a deep neural network, or another type of machine learning model. As an example, the machine learning operation may correspond to the use of a machine learning model to process input image data to classify or identify an object or target of the input image data. In some embodiments, the machine learning model may be a neural network represented by a group of nodes (i.e., neurons) connected to other nodes. The connection between a pair of nodes may be referred to as an edge. For example, a node 232 and another node 233 may be connected to a third node 234 via edges 235 and 236. Each edge in the neural network may be assigned a weight that is identified as a digital value. Input data (e.g., data to be processed) may be provided to a node and may then be processed based on the weight of the connecting edge. For example, the value of the weight of the edge may be multiplied by the input data of the node and the node at the end of the edge may accumulate multiple values. As an example, node 232 may receive input data and node 233 may receive another input data (e.g., pixel bit values ​​associated with an image). A particular weight value assigned to edge 236 may be combined (e.g., multiplied or other such operations) with the input data provided to node 232 to produce an output value, and another weight value assigned to edge 235 may be combined (e.g., multiplied) with other input data provided to node 233 to produce another output value. The output values ​​may then be combined (e.g., accumulated) at node 234 to produce a combined output value. The combined output value from node 234 may be combined or multiplied with another weight assigned to the next edge and accumulated at the next node. For example, machine learning model 231 may include nodes grouped into multiple layers. Signals (e.g., input data and intermediate data) may propagate through the layers until the last layer (i.e., the final output layer), which produces the output result of the machine learning operation. As previously described, the input data and other such intermediate data from the node are multiplied by the weight of the edge and then accumulated at the end or destination of the edge at other nodes. Thus, a machine learning operation may contain multiple layers or a series of multiply and accumulate (MAC) sub-operations.

[0049] As shown, the machine learning model 231 can be implemented in the internal logic of the memory component 220. For example, in conjunction with Figure 3The described machine learning model 231 may be implemented as digital logic or a resistor array of the memory component 220. For example, the nodes, edges, and weights may be implemented in the digital logic or resistor array of the memory component. Figure 5 The described machine learning model 231 can be implemented in the memory unit of the memory component 220. For example, the nodes, edges, and weights can be implemented by using or configuring the memory unit of the memory component. In some embodiments, such as in combination Figure 8 The memory subsystem controller of the described memory subsystem can implement the machine learning model 231. In the same or alternative embodiments, as in combination with Fig. 9 The described machine learning model 231 may be implemented in one or more memory components 220 of the memory subsystem.

[0050] Figure 3 An example memory component 300 with an internal machine learning component according to some embodiments of the present invention is illustrated. In general, the memory component 300 may correspond to Figure 1 The memory device 130 or 140 or Figure 2 The memory component 220. The memory component 300 may be a volatile memory component or a non-volatile memory component.

[0051] like Figure 3 As shown in , the memory component 300 may include a memory unit 315 for storing data. For example, the memory component 300 may receive data from the host system 310 and may store the data at the memory unit 315 of the memory component 300. The host system may further specify a machine learning operation to be performed by the memory component 300. For example, the machine learning operation may be performed by a machine learning operation component 301, which is included in the package of the memory component 300 or inside the memory component 300. In some embodiments, the machine learning operation component 301 may correspond to digital logic for implementing machine learning operations. For example, the digital logic may be used to implement a machine learning model and receive input data for the machine learning model and to generate output data for the machine learning model. As previously described, the machine learning model may be the structure of a neural network and the associated weight values ​​of the nodes and edges between the nodes of the neural network. As described in conjunction with Figure 2 The described machine learning operations may then be performed by the digital logic of the machine learning operation component 301 configured based on the weights, edges, and nodes of the machine learning model. The digital logic may be implemented using digital logic gates or other such circuitry. In some embodiments, the multiplication and accumulation (MAC) sub-operation of the machine learning operation may be performed by the digital logic of the machine learning operation component 301.

[0052] In some embodiments, the machine learning operation component 301 may correspond to a resistor array. For example, the multiplication and accumulation sub-operations of the machine learning operation may be performed by the resistor array of the machine learning operation component 301. For example, the resistor array may represent a machine learning model. Each resistor may represent a node and the resistance value of the resistor may be programmed or tuned to correspond to the weight value of the edge between a pair of resistors representing a pair of nodes of a neural network. For example, a resistor may represent a node and the resistance of the resistor may be programmed to represent the weight value of the edge connected at the output of the resistor. The output of the resistor may be an analog value based on the programmed resistance of the resistor and the analog input to the resistor (e.g., a multiplication sub-operation). The analog value outputs of a pair of resistors may then be combined to produce a combined analog value (e.g., an accumulation sub-operation). In some embodiments, the output of the last layer of the resistors of the machine learning model may be coupled to an analog / digital (ADC) converter to convert one or more analog signals as the final value of the machine learning model into a digital signal that can be used to represent the output of the machine learning model.

[0053] In operation, the memory component 300 can store input data 303 for machine learning operations. For example, the input data 303 can be an image, audio, text, or any other data. The input data 303 can be stored at a specific area of ​​the memory unit of the memory component 300 that has been allocated to store input data for machine learning operations. The allocated area of ​​the memory unit can store multiple different input data that can be used separately during the machine learning operation. In some embodiments, the input data 303 can be provided by the host system 310. For example, the host system 310 can transmit the input data 303 to the memory component or the memory subsystem containing the memory component. In the same or alternative embodiments, the host system 310 can provide an indication that a machine learning operation will be performed on the input data 303. For example, the host system 310 can identify specific input data to be used for machine learning operations. The machine learning model 302 can store information specifying the structure (e.g., edges, nodes, and weight values) of one or more machine learning models. For example, another area of ​​the memory unit of the memory component 300 can be allocated for storing the machine learning model 302. In some embodiments, another area can store different machine learning models.

[0054] In operation, the host system 310 can specify specific input data and a specific machine learning model to be used with the machine learning operation. The machine learning operation component 301 can receive a machine learning model 302 corresponding to the specified machine learning model and can be configured or programmed to implement the machine learning operation based on the machine learning model 302. For example, the multiplication and accumulation sub-operations can be performed according to the machine learning model 302. In some embodiments, the digital logic or resistance value of the resistor array can be configured to perform the multiplication and accumulation sub-operations based on the machine learning model 302. The machine learning operation component 301 can then perform the machine learning operation by retrieving the specified input data 303 and processing the retrieved input data 303 based on the machine learning model 302 to generate output data 304. For example, the output data can be stored at another area of ​​the memory unit of the memory component 300 allocated to store the results of the machine learning operation component 301. In some embodiments, the output data 304 can be returned to the host system 310. In the same or alternative embodiments, machine learning operation component 301 can provide an indication or notification to host system 310 that the requested machine learning operation has been completed and the resulting output data 304 has been stored at a specific location at the memory subsystem. Host system 310 can later request the resulting output data 304 by specifying the specific location where the output data 304 has been stored.

[0055] In some embodiments, the machine learning model 302, input data 303, and output data 304 may be stored in a portion of the memory component that is near or closer to the machine learning operation component 301 than other memory cells of the memory component.

[0056] Thus, the memory component can be used to store data for a host system. The same memory component can contain internal logic to perform machine learning operations for the host system. The internal logic can be coupled to the memory cells of the memory component via one or more internal buses that are not external to the memory component.

[0057] Figure 4 4 is a flow chart of an example method 400 for performing machine learning operations and for storing host data at a memory component according to some embodiments. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0058] like Figure 4 As shown in , at operation 410, processing logic receives a request to perform a machine learning operation at a memory component. The machine learning operation may be specified by a host system. For example, the host system may provide input data to be processed and analyzed by the machine learning operation to produce output data, or the host data may specify input data currently stored at the memory component. In some embodiments, the machine learning operation may be performed by digital logic or a resistor array contained within the memory component. For example, the machine learning operation may be performed by internal logic of the memory component. In the same or alternative embodiments, the machine learning operation may be performed by a processor such as a processor or a processor. Figure 5 The host system may be configured to perform the machine learning operations by using a memory unit of a memory component as described above. The machine learning operations may be neural network processing of input data as previously described. In addition, the host system may specify a specific machine learning model to be used during the machine learning operations.

[0059] At operation 420, processing logic performs a machine learning operation at a memory component. For example, the machine learning operation may be performed by the internal logic of the memory component as previously described. In some embodiments, the machine learning operation component may be configured to perform the machine learning operation based on the machine learning model. At operation 430, processing logic receives host data from a host system. For example, the host system may provide data to be stored at a memory component or a memory subsystem including the memory component. The host data may be data that is not intended to be used by the machine learning operation. For example, the host data may be other data to be written to the memory component and to be retrieved from the memory component in response to a subsequent read operation from the host system. At operation 440, processing logic stores the host data from the host system at the same memory component where the machine learning operation has been performed. For example, the host data may be stored across memory cells of a memory component that also includes internal logic to perform the machine learning operation. In addition, the internal logic may be separate from the memory cells of the memory component. Thus, the same memory component may be used to store host data and perform machine learning operations for the host system.

[0060] Figure 5An example memory component 500 having an internal machine learning operation component based on a memory cell of the memory component according to some embodiments of the present invention is illustrated. In general, the memory component 500 may correspond to Figure 1 The memory device 130 or 140 or Figure 2 The memory component 500 may be a volatile memory or a non-volatile memory. In addition, the machine learning operation component 501 may correspond to Figure 1 The machine learning operation component 113.

[0061] like Figure 5 As shown in , the machine learning operation component 501 can be based on the memory cells of the memory component 500. For example, the memory cells of the memory component 500 can be used to implement the machine learning model 502 of the machine learning operation. In some embodiments, the conductivity of different memory cells can be used to implement the machine learning model. For example, each memory cell can correspond to a node of a neural network and the conductivity of the memory cell can be programmed to correspond to the weight value applied to the input of the memory cell. For example, the memory cell can be programmed to a specific conductivity, so when the input is applied to the memory cell, the change (e.g., multiplication) of the input signal applied by the memory cell can be based on the conductivity of the memory cell. In addition, the memory cell can receive multiple input signals from the outputs of other memory cells. Such input signals can be accumulated at the memory cell and then multiplied based on the conductivity of the memory cell. Thus, the multiplication and accumulation sub-operations as previously described can be performed by configuring or programming the memory cell to represent the nodes, edges, and weight values ​​of the machine learning model.

[0062] Input data 503 may be data to be processed by a machine learning operation as previously described. For example, input data 503 may be received from a host system 510 for machine learning operations for analysis and may be stored at a region of memory cells of the memory component 500. Machine learning operations may be performed by input data 503, and output data 504 may be generated based on input data 503 and a machine learning model 502 as previously described. For example, the machine learning operation component 501 may configure memory cells for machine learning operations (e.g., multiplication and accumulation sub-operations) based on the machine learning model 502. The configuration of the memory cells may correspond to programming of the conductivity of the memory cells based on the weight values ​​specified by the machine learning model 502. The machine learning operation component 501 may then process the input data 503 to generate output data 504 and store the output data 504 at another region of the memory cells of the memory component 500. In some embodiments, the output data 504 may be returned to the host system 510. In the same or alternative embodiments, the machine learning model 502, input data 503, and output data 504 can be stored at a memory unit that is near or closer to the machine learning operation component 501 than other memory units of the memory component used to store host data that is not used by the machine learning operation.

[0063] Thus, the memory cells of the same memory component can be used to store data from the host system 510 and to perform machine learning operations for the host system 510. For example, a region of a memory cell can be used to store host data and return host data in response to a read request from the host system 510. Another different region of the memory cell can be used to represent the nodes and weights of a neural network for a machine learning operation. In some embodiments, the region of the memory cell can be coupled to an internal bus of the memory cell.

[0064] Figure 6 6 is a flow chart of an example method 600 of allocating portions of a memory component to machine learning operations and storing host data according to some embodiments. The method 600 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by Figure 1The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0065] like Figure 6As shown in , at operation 610, processing logic receives a request to perform a machine learning operation at a memory component. For example, a host system may provide an indication that the memory component will perform a machine learning operation. As previously described, the machine learning operation may be a neural network operation. The host system may store data at the memory component and indicate that the input to the machine learning operation is data already stored at the memory component. For example, the host system may specify or identify specific data or the location of data stored at the memory component, which should be the input to the machine learning operation. At operation 620, processing logic allocates a portion of the memory component to the machine learning operation. For example, a region or portion of a memory cell of the memory component may be used to implement a machine learning operation based on a machine learning model. In some embodiments, the machine learning model may be received from the host system or may be received from another region of the memory component. As previously described, the allocation of a portion of the memory component may correspond to programming of the memory cell to implement a machine learning model, such as a neural network. At operation 630, processing logic determines the remaining portion of the memory component that is not allocated to the machine learning operation. For example, another region or portion of the memory cell that is not used to implement the machine learning operation may be identified. For example, the remaining memory cells of the memory component that may be used to store host data may be determined. In some embodiments, a data structure may store information identifying a region or memory cell (or data block or other such data unit) of a memory component for implementing a machine learning operation, and another region or memory cell (or other data block or data unit) may be used to store host data when a machine learning operation is implemented within the memory component. At operation 640, processing logic receives host data from a host system. For example, the host system may provide data to be stored at a memory component. In some embodiments, the host data may be data that is not operated on by a machine learning operation. In the same or alternative embodiments, the host data may be a combination of data that is not operated on by a machine learning operation and other data that will serve as input to the machine learning operation. At operation 650, processing logic stores the host data from the host system at the remainder of the memory component that is not allocated to the machine learning operation. For example, the host data may be stored at a memory component that also performs machine learning operations on other data. In some embodiments, the host system may specify whether particular data will be input for a machine learning operation or not input for a machine learning operation. If the data will be input for a machine learning operation, the received data may be stored at a region or portion of a memory component that will store input data for the machine learning operation. For example, as previously described with respect to Figure 5As described, the data may be stored at a region of a memory component that has been allocated to store input data for a machine learning operation. Otherwise, if the data is not input for a machine learning operation, the data may be stored elsewhere in the memory component.

[0066] Thus, the memory component may contain internal logic for performing machine learning operations. The internal logic may be implemented in the memory cells of the memory component. The same memory component may further store host data. The host data may include input data for the machine learning operation and other data that is not input data or used with the machine learning operation.

[0067] Figure 7 is a flow chart of an example method 700 for providing an indication of the capacity of a memory component to a host system based on a machine learning model in accordance with some embodiments. The method 700 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 700 is performed by Figure 1 The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0068] like Figure 7As shown in , at operation 710, processing logic allocates a portion of a memory component for machine learning operations based on a machine learning model. For example, the memory cells of the memory component may be configured or programmed based on the nodes, edges, and weights specified by the machine learning model. Thus, a portion of the memory cells of the memory component may be allocated to be programmed or configured for machine learning operations. At operation 720, processing logic provides an indication of the capacity of the remaining portion of the memory component to the host system based on the machine learning model. For example, the capacity of the memory component storing host data may be determined. The capacity for storing host data may be based on the difference between the capacity of the memory component when no machine learning operations are implemented in the memory component and the capacity of the memory component when the machine learning operations are implemented in the memory component. In some embodiments, the capacity may be based on the difference between the amount of data that can be stored at the total number of memory cells of the memory component when no machine learning operations are implemented at the memory cells and the amount of data that can be stored at the number of memory cells used to implement the machine learning operations. The indication may be provided by a memory component or a memory subsystem controller of a memory subsystem that includes the memory component. In some embodiments, the indication may specify the capacity of a memory component (or memory subsystem) to store host data not used by a machine learning operation, the capacity of a memory component to store input data for a machine learning operation, the capacity of a memory component to store output data of a machine learning operation, and a portion of a memory component used to perform a machine learning operation.

[0069] At operation 730, processing logic receives an indication to change the machine learning model for the machine learning operation. In some embodiments, the host system may specify that a different machine learning model is to be used during the machine learning operation. For example, a new neural network or other such new machine learning model may be implemented. In some embodiments, the host may indicate that a new machine learning model is to be used when a different analysis or processing of the input data or a different type or classification of the input data is to be used for the machine learning operation. Different numbers of memory cells may be programmed or configured based on the new machine learning model. For example, a portion of the memory cells of the memory component may be configured or programmed to perform a machine learning operation based on the machine learning model. The machine learning operation may subsequently be based on the new machine learning model. Another portion of the memory cells of the memory component may subsequently be configured to be programmed to perform a machine learning operation based on the new machine learning model.

[0070] In some embodiments, more memory cells or fewer memory cells may be configured or programmed to implement machine learning operations through a new machine learning model relative to a previous machine learning model. In the same or alternative embodiments, the memory cells used to implement machine learning operations through a new machine learning model may be different memory cells than the memory cells used to implement machine learning operations through a previous machine learning model. For example, if more memory cells are to be used for a new machine learning model, then the memory cells are used to configure the previous machine learning model and the additional memory cells may be used to implement machine learning operations through the new machine learning model. Thus, the memory cells used to implement machine learning operations through a new machine learning model may include the same memory cells or a subset of the memory cells used to implement machine learning operations through a previous machine learning model. In some embodiments, the memory cells configured or programmed to implement a new machine learning model may be different from the memory cells used to implement a previous machine learning model. For example, different groups of memory cells may be used to implement machine learning operations through a new machine learning model relative to the memory cells used for a previous machine learning model. In some embodiments, different groups of memory cells may be memory cells allocated to store host data. Thus, the group of memory cells used to store host data and the group of memory cells used to implement the machine learning model can be changed between the groups of memory cells so that the machine learning operations are not continuously implemented by the same group of memory cells.

[0071] At operation 740, in response to receiving the indication, another portion of the memory component is allocated for machine learning operations based on the changed machine learning model processing logic. For example, a different number of memory cells can be programmed or configured to implement machine learning operations through the changed machine learning model. In some embodiments, the memory cells that implement the previous machine learning model can be configured or programmed to no longer implement the previous machine learning model. For example, the memory cells that implement the previous machine learning model can be configured or programmed to no longer implement the previous machine learning model and then the memory cells can be configured or programmed to implement the new machine learning model. Thus, because a different number of memory cells can be used to implement the new machine learning model, the capacity of the memory component to store host data can also change. For example, if the new machine learning model specifies more nodes than the previous machine learning model, more memory cells can be used to implement the new machine learning model. At operation 750, another indication of the capacity of the remaining portion of the memory component is provided to the host system based on the changed machine learning model processing logic. For example, the indication can specify the remaining capacity of the memory component that can be used to store host data when the internal logic of the memory component (e.g., other memory cells) is configured or programmed to implement the new machine learning model. The remaining capacity of the memory component may be different than a previous remaining capacity of the memory component when a previous machine learning model was implemented.

[0072] Figure 8 Machine learning operation components implemented in a memory subsystem controller of the memory subsystem 800 according to some embodiments of the present invention are illustrated.

[0073] like Figure 8 As shown in , the machine learning operation component 113 can be implemented by a memory subsystem controller 815 corresponding to the memory subsystem controller 115. For example, a processor or other circuit system of the memory subsystem controller 815 can implement the operation of the machine learning operation component 113 as described herein. Thus, the memory subsystem can include internal logic to perform machine learning operations. The internal logic can correspond to the memory subsystem controller. For example, the memory subsystem controller can include functionality to perform machine learning operations or a neural network processor. Examples of such machine learning or neural network processors include, but are not limited to, multiplication and accumulation sub-operations as described herein.

[0074] In operation, input data for machine learning operations may be stored at memory component 830 and / or memory component 840. In some embodiments, memory components 830 and 840 are non-volatile memory components, volatile memory components, or a mixture of one or more non-volatile memory components and one or more volatile memory components. Machine learning operation component 113 may receive an instruction from a host system to perform a machine learning operation. In response to receiving the instruction, machine learning operation component 113 may retrieve input data from one of memory components 830 and 840. For example, machine learning operation component 113 may identify specific input data stored at one of the memory components and may retrieve data from the corresponding memory component. Subsequently, machine learning operation component 113 at memory subsystem controller 815 may perform machine learning operations. For example, multiplication and accumulation sub-operations and any other machine learning sub-operations may be performed by machine learning operation component 113 inside memory subsystem controller 815. In some embodiments, a machine learning model for machine learning operations may be stored at memory subsystem controller 815 or retrieved from one of memory components 830 and 840. The internal logic of the memory subsystem controller 815 can be configured based on the machine learning model. In addition, the output of the machine learning operation can be returned to the host system that has requested the machine learning operation and / or the output can be stored at one of the memory components 830 and 840. For example, the output can be stored at the same memory component from which the input data was retrieved. In some embodiments, the output can be stored at a specific location of a specific memory component used to store the output data of the machine learning operation.

[0075] Although not shown, in some embodiments, the machine learning operation component 113 may be implemented by another integrated circuit separate from the memory subsystem controller 815. For example, another integrated circuit coupled to the memory subsystem controller and the memory components 830 and 840 via an internal bus or interface of the memory subsystem controller may perform the functionality of the machine learning operation component 113.

[0076] Fig. 9 Machine learning operation components implemented in one or more memory components of memory subsystem 900 according to some embodiments of the present invention are illustrated.

[0077] like Fig. 9As shown in , the machine learning operation component 113 can be implemented by one or more memory components 930 and 940. For example, the machine learning operation or neural network accelerator can be executed inside the memory component. In some embodiments, the memory component can be a volatile memory component and / or a non-volatile memory component. In the same or alternative embodiments, the internal logic that performs the machine learning operation or the neural network accelerator can be executed by any number or combination of volatile memory components and non-volatile memory components.

[0078] In operation, the memory subsystem controller 915 may receive a request from the host system to perform a machine learning operation on input data. For example, the host system may specify a specific machine learning model to be used with specific input data. The memory subsystem controller 915 may identify a specific memory component that currently stores specific input data. In addition, the memory subsystem controller 915 may transmit a request to the machine learning operation component 113 at the identified memory component to perform a machine learning operation. For example, the request may specify the input data and machine learning model to be used for the machine learning operation. The machine learning operation component 113 may then configure the internal logic of the memory component to perform a machine learning operation on the input data to generate output data. The output data may be stored at the memory component and / or provided back to the memory subsystem controller 915 to be returned to the host system.

[0079] In some embodiments, the machine learning operations performed by the internal logic of the memory component may be certain sub-operations of the machine learning operation component. For example, in some embodiments, the internal logic of the memory component may have limited processing power and may perform a subset of the sub-operations of the machine learning operation. In some embodiments, the internal logic may perform multiplication and accumulation sub-operations. As previously described, the machine learning operation may correspond to multiple layers of nodes associated with the multiplication and accumulation sub-operations. The internal logic of the memory component may perform sub-operations of a subset of the layers of the machine learning operation to produce an intermediate result, which is then returned to the memory subsystem controller 915 (or a separate integrated circuit), and the memory subsystem controller may perform further machine learning operations on the intermediate data based on the final layer of the machine learning model to produce output data. In some embodiments, the intermediate results may be returned to the host system, so the host system may perform further machine learning operations on the intermediate data based on the final layer of the machine learning model to produce output data.

[0080] In some embodiments, different portions of the machine learning operation may be implemented in the internal logic of different memory components. For example, if the machine learning model includes a larger number of nodes or layers, then the internal logic of more memory components may be configured to implement different portions of the machine learning operation relative to if the machine learning model includes a smaller number of nodes or layers.

[0081] Fig.10 1000 is a flowchart of an example method for performing a portion of a machine learning operation at one or more memory components of a memory subsystem according to some embodiments. The method 1000 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 1000 is performed by Figure 1 The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0082] like Fig.10As shown in , at operation 1010, processing logic receives an instruction to perform a machine learning operation at a memory subsystem. For example, a host system may provide a request to a neural network accelerator inside a memory subsystem to process input data stored at the same memory subsystem. At operation 1020, processing logic configures one or more memory components of the memory subsystem to perform a portion of the machine learning operation. For example, as previously described, the internal logic of the memory component may perform a sub-operation of the machine learning operation. The memory cells, digital logic, or resistor arrays of one or more memory components may be configured to perform multiplication and accumulation sub-operations based on a machine learning model specified by the host system. In some embodiments, the memory component that also stores the input data may be a memory component configured to implement the machine learning operation. At operation 1030, processing logic receives the result of a portion of the machine learning operation from one or more memory components. For example, the result of a sub-operation of the machine learning operation performed by the internal logic of one or more memory components may be received. The result may be the output of the multiplication and accumulation sub-operation. In some embodiments, the sub-operation performed by the internal logic may be a portion of a layer of a machine learning model corresponding to the machine learning operation. For example, the result of a portion of the machine learning operation may be intermediate data for a portion of a layer of a machine learning model. The intermediate data may be input data for a next portion of a layer of a machine learning model that has not yet been executed by the internal logic of the memory component. At operation 1040, the processing logic performs the remaining portion of the machine learning operation based on the received results from the one or more memory components. For example, the remaining sub-operations of the remaining layers may be performed by the internal logic of the memory subsystem controller or a separate integrated circuit to generate output data for the machine learning operation. In some embodiments, the intermediate data may be returned to the host system and the host system may perform the remaining portion of the machine learning operation.

[0083] Thus, the memory component of the memory subsystem can perform a portion of the machine learning operation. The results of the portion of the machine learning operation can be returned to the memory subsystem controller (or a host system or a separate integrated circuit within the memory subsystem) to complete the machine learning operation through the data returned from the memory component.

[0084] Aspects of the present invention further relate to utilizing a bus to transmit data between a host system and a memory component or memory subsystem. A conventional memory subsystem may include or may be coupled to a bus for transmitting data between the host system and the conventional memory subsystem. For example, a bus may be used to transmit requests from the host system (e.g., read operations, write operations, etc.) to the memory subsystem and transmit data from the memory subsystem to the host system. Another bus may be used to transmit data between the host system and a machine learning processor (e.g., a neural network processor). For example, the host system may transmit data through the machine learning processor on the bus while the host system transmits data through the conventional memory subsystem using another bus.

[0085] As previously described, a memory component or memory subsystem may contain internal logic that performs functionality for machine learning operations. The same memory component or memory subsystem may contain functionality for storing data for a host system separate from the machine learning operations. In some embodiments, the functionality for machine learning operations implemented by the internal logic of a memory component or memory subsystem may be referred to as a machine learning space, while the memory cells of a memory component or memory subsystem that store host data separate from the machine learning operations may be referred to as a memory space. Thus, a single memory component or memory subsystem may contain functionality for both the machine learning space and the memory space. Therefore, a single bus may not be used to transmit data only for the memory space of a memory component or memory subsystem.

[0086] Aspects of the present invention address the above and other deficiencies by transmitting data for a machine learning space and a memory space of a memory component or memory subsystem on a single bus, or by transmitting data for a machine learning space and a memory space of a memory component or memory subsystem on multiple buses. For example, a single bus can be virtualized to transmit data between a host system and a memory component or memory subsystem. In some embodiments, the host system can transmit operations (e.g., read requests, write requests, etc.) to a memory component or memory subsystem on a bus. Based on the type of operation or the memory address location of the operation, the operation from the host system can be transmitted to be executed at the machine learning space or the memory space of the memory component or memory subsystem. Thus, operations transmitted from the host system on a single bus can be provided to the memory space or the machine learning space.

[0087] In some embodiments, multiple buses can be used to transmit data between a memory component or memory subsystem that includes a memory space and a machine learning space. For example, a bus can be used to transmit data between a host system and the memory space and another bus can be used to transmit data between the host system and the machine learning space. Thus, a memory component or memory subsystem can include multiple buses that are each used to transmit data separately between the memory space and the machine learning space.

[0088] Advantages of the present invention include, but are not limited to, reducing the complexity of the design of a memory component or memory subsystem when a single bus is used to transmit data for a machine learning space and a memory space of the memory component or memory subsystem. For example, a single bus can result in fewer connections and less wiring than multiple buses coupling a host system with a memory component or memory subsystem. In addition, management of data or operations transmitted on a bus for the memory space and the machine learning space can result in improved performance of the memory space and the machine learning space. The use of separate buses for the memory space and the machine learning space can result in faster transmission of data for each of the memory space and the machine learning space, resulting in improved performance of the functionality of the memory space and the machine learning space.

[0089] Fig.11 An example memory component 1110 and a memory subsystem 1120 are described according to some embodiments of the present invention, which have a single bus for transmitting data for a memory space and a machine learning space. The machine learning operation component 113 can be used to transmit and receive data for the memory space and the machine learning space of each of the memory component 1110 and the memory subsystem 1120.

[0090] like Fig.11 As shown in , the memory component 1110 may include a machine learning operation component 113 to manage the reception and transmission of data on a single bus 1113 for a memory space 1111 and a machine learning space 1112 of the memory component 1110. As previously described, the memory space 1111 may be a memory cell or any other storage unit of the memory component 1110 that may be used to store host data from a host system. In some embodiments, the host data may be data that is not used by the machine learning operation of the machine learning space 1112. The machine learning space 1112 may be the internal logic of the memory component 1110. For example, as previously described, the internal logic may correspond to other memory cells (or any other type of storage cells) of the memory component 1110, which are configured or programmed based on the definition of the machine learning model so that a machine learning operation can be performed at the memory cell.

[0091] In addition, the memory subsystem 1120 may include a machine learning operation component 113 to manage the reception and transmission of data on a single bus 1123 for the memory space 1121 and the machine learning space 1122. For example, the memory space 1121 may be a memory cell of one or more memory components for storing host data as previously described, and the machine learning space 1122 may be the internal logic of one or more memory components for performing one or more machine learning operations. In some embodiments, the internal logic of the machine learning space 1122 may be included in a controller of the memory subsystem 1120 as previously described. In some embodiments, the memory component 1110 and the memory subsystem 1120 may include a decoder that may be used to receive data from the corresponding bus and decode the received data before transmitting the decoded data to the memory space and / or the machine learning space. For example, the decoder may decode a logical address specified by an operation, which is provided via a bus to a physical address located at one of the memory space or the machine learning space. In some embodiments, each of the memory space and the machine learning space may include a separate decoder.

[0092] In addition, the internal bus can be used to couple the machine learning space with the memory space. For example, input data and a machine learning model can be transmitted from the memory space to the machine learning space via the internal bus, and output data from the machine learning space can be transmitted to the memory space via the internal bus. Thus, the memory component or memory subsystem can include a bus for transmitting data between the host system and the memory component or memory subsystem and an internal bus for transmitting data between the memory space and the machine learning space of the memory component or memory subsystem.

[0093] In operation, data may be transmitted between a host system and a memory component or memory subsystem on a single bus. In some embodiments, a bus may refer to an interface of one or more signals for transmitting data between at least two devices (e.g., a host system and a memory component or memory subsystem). A memory component or memory subsystem may receive a request for an operation via a single bus for a memory space and a machine learning space. Examples of operations for a memory space include, but are not limited to, read operations, write operations, and erase operations associated with host data. Examples of operations for a machine learning space include, but are not limited to, provision of input data for a machine learning operation, provision of a definition of a machine learning model, commands to initiate or execute a machine learning operation based on a specific definition of a machine learning model with specific input data, requests to receive output data or results of a machine learning operation, and the like. In some embodiments, an operation or machine learning space may be any operation that interacts with a machine learning operation. Thus, different operations for different functionalities (e.g., a memory space or a machine learning space) within a memory component or a memory subsystem may be received on the same virtualized bus. As described in further detail below, an operation or data may be transmitted or provided to a memory space or a machine learning space based on the type of operation received or another characteristic or attribute of the operation or data.

[0094] Fig.12 1 is a flow chart of an example method 1200 for transmitting a requested operation to a memory space or a machine learning space based on the type of operation according to some embodiments. The method 1200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 1200 is performed by Figure 1 The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0095] like Fig.12As shown in , at operation 1210, the processing logic receives a request to access a memory component or a memory subsystem. The request may be provided by a host system. For example, the request may be an operation to access a memory space or a machine learning space of a memory component or a memory subsystem. The request may be received via a bus or other such interface for transmitting data between a host system and a memory component and / or a memory subsystem. At operation 1220, the processing logic determines the type of operation specified by the request. For example, the request may specify an operation to be performed in a memory space or a machine learning space of a memory component or a memory subsystem. For example, the request may be an operation to write data to a memory component or a memory subsystem or to read data from a memory component or a memory subsystem. The request may specify any operation that may be used to access or modify host data stored at a memory space of a memory component or a memory subsystem. In addition, the request may be an operation to access input data, output data, or a machine learning definition, to update input data, output data, or a machine learning definition, to interact with input data, output data, or a machine learning definition, and / or to implement or perform a machine learning operation at the internal logic of a memory component or a memory subsystem. Thus, the operation may be a first type of operation corresponding to an operation for a memory space or a second type of operation corresponding to an operation for a machine learning space.The operation may specify a type of action to be performed at a memory component or memory subsystem.

[0096] At operation 1230, the processing logic transmits the request to a memory space or a machine learning space of a memory component or a memory subsystem based on the type of operation specified by the request. For example, an operation provided by a host system may be provided to a machine learning space or a memory space based on whether the operation is typically used to access a memory space or a machine learning space. For example, a memory component or a memory subsystem may include a data structure that identifies different types of operations that can be performed by a memory component or a memory subsystem and can be received from a host system. Each type of operation can be assigned to a memory space or a machine learning space. When a request for an operation assigned to a memory space is received via a bus, the operation can be transmitted to the memory space or performed at the memory space. In some embodiments, the operation can be transmitted to a decoder or another component for decoding an operation for a memory space. Otherwise, when a request for an operation assigned to a machine learning space is received via a bus, the operation can be transmitted to the machine learning space or performed at the machine learning space. In some embodiments, the operation can be transmitted to a decoder or another component for decoding an operation for a machine learning space.

[0097] Thus, different types of operations can be transmitted to a memory component or memory subsystem via a single bus. Operations can be transmitted to a memory space or a machine learning space based on the type of operation.

[0098] Fig.13 1 is a flow chart of an example method 1300 for providing a requested operation to a memory space or a machine learning space based on a memory address according to some embodiments. The method 1300 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 1300 is performed by Figure 1 The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0099] like Fig.13 As shown in , at operation 1310, processing logic receives a request to perform an operation at a memory component or memory subsystem. As previously described, the operation can be an operation for a memory space (e.g., a read operation, a write operation, an erase operation, etc.) or an operation for a machine learning space (e.g., an operation associated with a machine learning operation). At operation 1320, processing logic determines a memory address specified by the operation. For example, the operation can specify a memory address or other such location of a data block or other such logical or physical data unit of a memory component or memory subsystem. In some embodiments, the memory address can be a physical data block of a memory component or a location of a memory component in a memory subsystem.

[0100] At operation 1330, processing logic determines whether the memory address corresponds to a memory space or a machine learning space. For example, a range of memory addresses can be assigned to a memory space and another range of memory addresses can be assigned to a machine learning space. Each range of memory addresses can contain a unique set of memory addresses so that the memory address is assigned to only one of the memory space or the machine learning space. At operation 1340, processing logic provides an operation for execution at the determined memory space or machine learning space. For example, the operation can be forwarded to a decoder or other such component of a memory component or memory subsystem for decoding an operation for a corresponding memory space or a corresponding machine learning space. If the memory address of the operation is contained in the range of memory addresses assigned to the memory space, then the operation can be provided to the memory space. Otherwise, if the memory address of the operation is contained in the range of memory addresses assigned to the machine learning space, then the operation can be provided to the machine learning space.

[0101] Fig.14 An example memory component 1410 and a memory subsystem 1420 are illustrated according to some embodiments of the present invention, which have separate buses for transmitting data for the memory space and the machine learning space. Each of the memory component 1410 and the memory subsystem 1420 can include a machine learning operation component 113 to transmit and receive data for the memory space and the machine learning space on separate buses.

[0102] like Fig.14As shown in , the memory component 1410 may include a machine learning operation component 113, a memory space 1411, and a machine learning space 1412. The memory component 1410 may be coupled to buses or interfaces 1413 and 1414. Each bus 1413 and 1414 may be used to transmit data for the corresponding memory space 1411 and machine learning space 1412. For example, the bus 1413 may be used to transmit data between the host system and the memory space 1411 and the bus 1414 may be used to transmit data between the host system and the machine learning space 1412. Thus, each bus may be used to transmit data between the host system and one of the memory space 1411 and the machine learning space 1412 without transmitting data for the other of the memory space 1411 and the machine learning space 1412. Similarly, the memory subsystem 1412 may include a machine learning operation component 113, which may forward or provide data received via buses 1423 and 1425 to the memory space 1421 or the machine learning space 1422. For example, bus 1423 can be used to transmit data between the host system and the memory space 1421 and bus 1425 can be used to transmit data between the host system and the machine learning space 1422.

[0103] In addition, an internal bus may be used to couple the machine learning space with the memory space of the memory component 1410 or the memory subsystem 1420. Thus, the memory component or the memory subsystem may include a separate bus for transmitting data between the host system and the machine learning space and the memory space of the memory component or the memory subsystem and an internal bus for transmitting data between the memory space and the machine learning space of the memory component or the memory subsystem.

[0104] In operation, data can be transmitted between the host system and the memory component or memory subsystem on two buses, where each bus is dedicated to one of the memory space or machine learning space within the memory component or memory subsystem. For example, data received via bus 1423 can be forwarded or provided to memory space 1421, while data received via bus 1425 can be forwarded or provided to machine learning space 1422.

[0105] Fig.15 is a flow chart of an example method for performing operations in an order based on the priority of machine learning operations according to some embodiments of the present invention. Method 1500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 1500 is performed by Figure 1The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0106] like Fig.15 As shown in , at operation 1510, the processing logic determines a set of operations for the memory space. The set of operations may be operations that have been received by a memory component or a memory subsystem. In some embodiments, the set of operations may be stored at a buffer memory of a memory component or a memory subsystem. For example, the set of operations may be operations that have been provided by a host system and are to be performed at a memory component or a memory subsystem. The set of operations may be received via a virtualized bus or a separate bus as previously described. In addition, the set of operations may include, but is not limited to, read operations of host data, write operations of host data, and erase operations of host data, wherein the host data is stored at a memory component or a memory subsystem and is separate from or not used by a machine learning operation. Each of the operations may be an operation to be performed at a memory space of a memory component or a memory subsystem. In some embodiments, a memory subsystem controller of a memory subsystem or a local controller of a memory component may receive a set of operations. In the same or alternative embodiments, the set of operations may be stored at a buffer of a memory subsystem or a memory component.

[0107] At operation 1520, processing logic determines another set of operations for the machine learning space. For example, another set of operations may be received from a host system, which will be performed for machine learning operations as previously described. Another set of operations may be received via a virtualized bus or another bus that is separate from the bus that provides a set of operations for the memory space. Thus, operations for the memory space and the machine learning space may be received by a memory component or a memory subsystem. At operation 1530, processing logic receives an indication of a priority for a machine learning operation associated with the machine learning space. The priority may be received from the host system. For example, the host system may transmit a message indicating a priority level for a machine learning operation that is being performed at the machine learning space or will be performed at the machine learning space. In some embodiments, the priority may be a number or other such value that specifies the importance or performance requirements of the machine learning operation. For example, the priority may have a high value to indicate a high priority level or a low value to indicate a low priority level for the machine learning operation. The performance requirements may specify the maximum amount of time that the machine learning operation will be executed to process the input data, the rate at which the input data will be processed by the machine learning operation, the amount of time that can pass before the output data of the machine learning operation will be provided to the host system, and the like. In some embodiments, the priority for the machine learning operation can be based on the input data provided to the machine learning operation. For example, if the input data has a high priority level, then the machine learning operation may also have a high priority level when applying the machine learning model to the input data. Otherwise, if the input data does not have a high priority level, then the machine learning operation does not have a high priority level when applying the machine learning model to the input data.

[0108] At operation 1540, processing logic determines the order of operations from the set of memory spaces and the machine learning space based on the priority for the machine learning operations. For example, operations from the set of memory spaces and another set of machine learning spaces may be initially ordered as different operations are received at a memory component or memory subsystem. Thus, the operations may be in an initial order based on when each corresponding operation has been received at a memory component or memory subsystem. For example, an operation received before another operation may be designated in an order before the other operation. The order may subsequently change based on the priority of the machine learning operation. For example, if the host system indicates that the machine learning operation has a high priority or other such designation, then the operations for the machine learning space may be reordered to be before the operations for the memory space.

[0109] At operation 1550, the processing logic performs operations in the determined order to access the memory space and the machine learning space. For example, operations can be performed or emitted to the memory space and the machine learning space based on the reordering of the operations so that earlier specified operations are performed or emitted before later specified operations.

[0110] Thus, the order of operations for the memory space and the machine learning space can be changed based on the priority of the machine learning operations to be performed at the machine learning space. If the priority of the machine learning operation is higher, then one or more operations for the machine learning operation can be placed earlier in the order than other operations for the memory space. For example, the operation for the machine learning operation can be executed earlier because the machine learning operation is associated with a higher priority or importance. Otherwise, if the priority of the machine learning operation is lower, then the operations for the memory space and the operations for the memory space can be ordered as the corresponding operations are received at the memory component or memory subsystem.

[0111] Fig.16A Description According to some embodiments of the present invention, a series of operations for a memory space and a machine learning space of a memory component or a memory subsystem has been received. In some embodiments, a machine learning operation component 113 of a memory component or a memory subsystem can receive a series of operations for a memory space and a machine learning space. The series of operations can be ordered in sequence as each operation is received by the memory component or the memory subsystem.

[0112] like Fig.16A As shown in , operations 1600 can be initially ordered as operations are received from a host system. For example, operation A 1610 can be initially received from a host system, followed by operation B 1620, operation C 1630, operation D 1640, and operation X 1650. Operations A through D can specify a memory space while operation X 1650 can specify a machine learning space. In some embodiments, the host system can provide an indication of whether the corresponding operation is to be performed at a memory space or a machine learning space. In the same or alternative embodiments, the type of operation or the memory address of the operation can be used to determine whether the operation is to be performed at a memory space or a machine learning space, as previously described.

[0113] Fig. 16B Illustrate a series of operations that have been sorted based on priorities for machine learning operations according to some embodiments of the present invention. In some embodiments, a memory component or a machine learning operation component 113 of a memory subsystem may sort a series of operations for a memory space and a machine learning space based on priorities for machine learning operations.

[0114] like Fig. 16BAs shown in , operations 1600 can be reordered based on the priority of the machine learning operations. For example, the host system can indicate that the priority for machine learning operations is higher or higher than the priority for operations for memory space. Thus, operation X 1650 received later can be reordered so that operation X 1650 can be executed before other operations A to D and / or can be transmitted to the machine learning space before other operations A to D are transmitted to the memory space.

[0115] Fig.17 is a flow chart of an example method for changing the performance of a machine learning operation based on a performance metric associated with a memory space in accordance with some embodiments. The method 1700 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 1700 may be performed by Figure 1 The machine learning operation component 113 is performed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0116] like Fig.17As shown in , at operation 1710, processing logic receives host data at a memory component or memory subsystem that performs a machine learning operation. For example, the host system may provide a read operation, a write operation, or an erase operation to be performed at the memory component or memory subsystem, while the internal logic of the memory component or memory subsystem performs the machine learning operation. At operation 1720, processing logic determines a performance metric associated with a memory space of the memory component or memory subsystem. The performance metric may be based on the rate at which the read, write, or erase operation is performed at the memory space when the internal logic of the machine learning space performs the machine learning operation. For example, in some embodiments, the internal logic of the machine learning space may affect the performance of the memory space. In some embodiments, the type of machine learning model used for the machine learning operation at the machine learning space, the amount of input data, etc. may change the rate at which the operation is performed at the memory space. Since a larger machine learning model or more operations are performed for the machine learning space, fewer resources of the memory component or memory subsystem may be used for the memory space. At operation 1730, processing logic determines whether the performance metric associated with the memory space has met the threshold performance metric. For example, a performance metric may be deemed to satisfy a threshold performance metric when the performance metric is equal to or less than a threshold performance metric. A performance metric may be deemed to not satisfy a threshold performance metric when the performance metric is greater than a threshold performance metric. As previously described, a performance metric may correspond to a rate of execution of operations for a memory space. For example, a performance metric may be a latency of a write operation, a read operation, or a combination of a write operation and a read operation performed on the memory space. A performance metric may be determined to not satisfy a performance metric threshold when the latency of the operation exceeds a threshold latency, and a performance metric may be determined to satisfy a performance metric threshold when the latency of the operation is equal to or less than a threshold latency.

[0117] At operation 1740, in response to determining that the performance metric does not meet the threshold performance metric, the processing logic changes the performance of the machine learning operation performed at the memory component or memory subsystem. For example, if the latency of the operation exceeds the threshold latency metric, then the machine learning operation can be changed so that the latency of the operation for the memory space can be below the threshold latency metric. In some embodiments, the performance of the machine learning operation can be changed by reducing the rate at which the machine learning operation is performed, reducing the rate at which input data can be provided to the machine learning operation, utilizing a different machine learning model, such as a machine learning model that utilizes fewer sub-operations, etc. Otherwise, if the performance of the machine learning operation is performed at the memory component or memory subsystem in response to determining that the performance metric meets the threshold performance metric, then the machine learning operation is not changed.

[0118] Fig.18An example machine of a computer system 1800 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 1800 may correspond to a host system (e.g., Figure 1 A host system 120 including a memory subsystem (e.g., Figure 1 110), coupled to or utilizing a memory subsystem, or may be used to perform operations of the controller (e.g., to execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network connection) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0119] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, a digital or non-digital circuit system, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be performed by the machine. In addition, while a single machine is described, the term "machine" shall also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0120] The example computer system 1800 includes a processing device 1802, a main memory 1804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1818, which communicate with each other via a bus 1830.

[0121] The processing device 1802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1802 is configured to execute instructions 1826 for performing the operations and steps discussed herein. The computer system 1800 may further include a network interface device 1808 to communicate over a network 1820.

[0122] The data storage system 1818 may include a machine-readable storage medium 1824 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 1826 or software embodying any one or more of the methods or functions described herein. The instructions 1826 may also reside, completely or at least partially, within the main memory 1804 and / or within the processing device 1802 during execution thereof by the computer system 1800, the main memory 1804 and the processing device 1802 also constituting machine-readable storage media. The machine-readable storage medium 1824, the data storage system 1818, and / or the main memory 1804 may correspond to Figure 1 Memory subsystem 110.

[0123] In one embodiment, instructions 1826 include implementing a component corresponding to a machine learning operation (e.g., Figure 1 The machine-readable storage medium 1824 is a computer program product that is used to store or encode the functional instructions of the machine learning operation component 113 of the present invention. Although the machine-readable storage medium 1824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for machine execution and causes the machine to perform any one or more of the methods of the present invention. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0124] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations that leads to a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0125] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within a computer system's memories or registers or other such information storage systems.

[0126] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0127] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used together with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices for performing the methods. The structures of various these systems will be presented as set forth in the following description. In addition, the present invention is described without reference to any particular programming language. It will be appreciated that the teachings of the present invention as described herein may be implemented using various programming languages.

[0128] The present invention may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0129] In the foregoing description, embodiments of the present invention have been described with reference to specific example embodiments of the present invention. It will be apparent that various modifications may be made to the present invention without departing from the broader spirit and scope of embodiments of the present invention as set forth in the appended claims. Accordingly, the description and drawings should be viewed in an illustrative rather than a restrictive sense.

Claims

1. A memory system, comprising: a memory component comprising a plurality of memory cells, wherein a first region of the memory cells is to store a machine learning model and a second region of the memory cells is to store input data and output data of a machine learning operation related to the machine learning model; as well as a controller coupled to the memory component via one or more internal buses to perform a portion of the machine learning operation by applying the machine learning model to the input data to generate the output data, Wherein the controller further programs a portion of the memory cells of the memory component based on the machine learning model to cause the portion of the memory cells to perform a remaining portion of the machine learning operation.

2. The memory system of claim 1, wherein the machine learning model is a neural network machine learning model.

3. The memory system of claim 1 , wherein the controller is further configured to: configuring the memory component to perform a portion of the machine learning operation; receiving a result of the portion of the machine learning operation from the memory component; as well as A remainder of the machine learning operation is performed based on the received results from the memory component.

4. The memory system of claim 3, wherein the portion of the machine learning operation performed by the memory component corresponds to a multiply and accumulate sub-operation of the machine learning operation.

5. The memory system of claim 1 , wherein the controller is further configured to: receiving host data from a host system; and The received host data is stored at the memory component, the memory component storing the machine learning model and the input data and output data of the machine learning operation.

6. The memory system of claim 1, wherein programming a portion of the memory cells of the memory component based on the machine learning model comprises programming resistances of resistors of a resistor array of the memory component based on the machine learning model.

7. A method for performing a memory operation, comprising: receiving a request to perform a machine learning operation at a memory subsystem; programming a portion of memory cells of a memory component of the memory subsystem based on a machine learning model to cause the portion of the memory cells to perform a portion of the machine learning operation; receiving, from the memory component, a result of the execution of the portion of the machine learning operation; as well as Based on the results of the execution of the portion of the machine learning operation received from the memory component, a remaining portion of the machine learning operation is executed at a controller of the memory subsystem by a processing device.

8. The method of claim 7, wherein the performing of the portion of the machine learning operation associated with the memory component corresponds to a multiply and accumulate sub-operation of the machine learning operation.

9. The method of claim 7, wherein the machine learning operation corresponds to a plurality of layers of multiplication and accumulation sub-operations, and wherein the portion of the machine learning operation is a first subset of the plurality of layers, and wherein the remaining portion of the machine learning operation is a second subset of the plurality of layers.

10. The method according to claim 7, further comprising: receiving host data, wherein the host data is not used for the machine learning operation; as well as The host data is stored at the memory component, the memory component configured to perform the portion of the machine learning operation.

11. The method according to claim 7, further comprising: receiving host data, wherein the host data is not used for the machine learning operation; determining a particular memory component of a plurality of memory components that is not configured to perform the portion of the machine learning operation; as well as The host data is stored at the particular memory component that is not configured to perform the portion of the machine learning operation.

12. The method of claim 7, wherein programming a portion of the memory cells of the memory component based on a machine learning model comprises programming resistance values ​​of resistors of a resistor array of the memory component based on the machine learning model of the machine learning operation.

13. A memory system comprising: Memory components; as well as A processing device operatively coupled to the memory component to perform the following operations: receiving a request to perform a machine learning operation; programming a portion of memory cells of the memory component of the memory system based on a machine learning model to cause the portion of the memory cells to perform a portion of the machine learning operation; receiving, from the memory component, a result of the execution of the portion of the machine learning operation; as well as A remaining portion of the machine learning operation is performed at a controller of the memory system based on the results of the execution of the portion of the machine learning operation received from the memory component.

14. The memory system of claim 13, wherein the execution of the portion of the machine learning operation associated with the memory component corresponds to a multiply and accumulate sub-operation of the machine learning operation.

15. The memory system of claim 13, wherein the machine learning operation corresponds to multiple layers of multiplication and accumulation sub-operations, and wherein the portion of the machine learning operation is a first subset of the multiple layers, and wherein the remaining portion of the machine learning operation is a second subset of the multiple layers.

16. The memory system of claim 13, wherein the processing device is further configured to: receiving host data, wherein the host data is not used for the machine learning operation; and The host data is stored at the memory component, the memory component configured to perform the portion of the machine learning operation.

17. The memory system of claim 13, wherein the processing device is further configured to: receiving host data, wherein the host data is not used for the machine learning operation; determining a particular memory component of a plurality of memory components that is not configured to perform the portion of the machine learning operation; and The host data is stored at the particular memory component that is not configured to perform the portion of the machine learning operation.

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