Adsorption method, mounting platform and plasma treatment device

Abstract

An adsorption method, a stage, and a plasma processing apparatus are provided to suppress the reduction of adsorption force. The adsorption method is used to adsorb an adsorbate on a stage having an electrostatic chuck, the adsorbate being at least one of a substrate or an edge ring. The adsorption method includes: placing the adsorbate on the electrostatic chuck; and applying an alternating voltage of two or more phases (n phases) with different phases to the electrodes of the electrostatic chuck, wherein the n-phase alternating voltage is applied based on a self-biasing voltage.

Description

Technical Field

[0001] This disclosure relates to an adsorption method, a mounting stage, and a plasma processing apparatus. Background Technology

[0002] A mounting stage is known to adsorb a substrate in a processing apparatus that performs necessary processes such as etching on a substrate.

[0003] Patent document 1 discloses an electrostatic chuck device for applying an alternating voltage, wherein the alternating voltage is an n-phase alternating voltage, where n is 2 or more. The electrostatic chuck device is characterized by having: electrodes for applying the n-phase alternating voltage; a sample stage made of an insulator that insulates the electrodes from each other; and a circuit for applying the n-phase alternating voltage.

[0004] <Prior art documents>

[0005] <Patent Documents>

[0006] Patent Document 1: Japanese Patent Application Publication No. 2003-332412 Summary of the Invention

[0007] <Problem to be solved by this invention>

[0008] In one aspect, this disclosure provides an adsorption method, a stage, and a plasma processing apparatus for suppressing the reduction of adsorption force.

[0009] <Methods for solving problems>

[0010] To address the aforementioned problems, according to one embodiment, an adsorption method is provided for adsorbing an object on a stage having an electrostatic chuck, the object being adsorbed being at least one of a substrate or an edge ring, the adsorption method comprising: placing the object being adsorbed on the electrostatic chuck; and applying an alternating voltage of two or more phases (n phases) with different phases to the electrodes of the electrostatic chuck, wherein the n-phase alternating voltage is applied based on a self-biasing voltage.

[0011] <The Effects of the Invention>

[0012] According to one aspect, an adsorption method, a mounting stage, and a plasma processing apparatus for suppressing the reduction of adsorption force can be provided. Attached Figure Description

[0013] Figure 1 This is a schematic cross-sectional view showing an example of a plasma processing apparatus according to one embodiment.

[0014] Figure 2 This is a plan view showing an example of the arrangement of electrodes in an electrostatic chuck.

[0015] Figure 3 (a) is a graph showing an example of a three-phase AC voltage applied to the electrodes. Figure 3 (b) is a graph showing an example of the sum of adsorption forces when a three-phase AC voltage is applied.

[0016] Figure 4 (a) is a graph showing an example of a two-phase AC voltage applied to the electrodes. Figure 4 (b) is a graph showing an example of the sum of adsorption forces when a two-phase AC voltage is applied.

[0017] Figure 5 This is a graph showing an example of the applied voltage and the flow rate of the heat transfer gas. Detailed Implementation

[0018] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and repeated descriptions are sometimes omitted.

[0019] [Plasma Processing Device]

[0020] Reference Figure 1 A plasma processing apparatus 1 according to one embodiment will be described. Figure 1 This is a schematic cross-sectional view showing an example of a plasma processing apparatus 1 according to one embodiment. The plasma processing apparatus 1 according to this embodiment is a capacitively coupled parallel plate substrate processing apparatus and has a chamber 10. The chamber 10 is, for example, a cylindrical container made of aluminum with an anodized surface and is grounded.

[0021] At the bottom of chamber 10, a cylindrical support stage 14 is arranged via an insulating plate 12 made of ceramic or the like, and a mounting stage 16 is provided on the support stage 14, for example. The mounting stage 16 has an electrostatic chuck 20 and a base 16a, and a wafer W is placed on the upper surface of the electrostatic chuck 20. Around the wafer W, an annular edge ring 24 made of, for example, silicon is arranged. The edge ring 24 is also called a focusing ring. The edge ring 24 is an example of an outer peripheral component arranged around the mounting stage 16. Around the base 16a and the support stage 14, an annular insulating ring 26 made of, for example, quartz is provided. Inside the central side of the electrostatic chuck 20, a first electrode 20a made of a conductive film is held by an insulating layer 20b. The first electrode 20a is connected to a power supply 22. A voltage applied from power source 22 to the first electrode 20a creates a potential difference between the front surface of the electrostatic chuck 20 and the wafer W, which is the object to be adsorbed, thus adsorbing the wafer W onto the wafer mounting surface of the electrostatic chuck 20. Additionally, a second electrode 20c, made of a conductive film, is held between an insulating layer 20b on the inner periphery of the electrostatic chuck 20. The second electrode 20c is connected to power source 23. A voltage applied from power source 23 to the second electrode 20c creates a potential difference between the front surface of the electrostatic chuck 20 and the edge ring 24, which is the object to be adsorbed, thus adsorbing the edge ring 24 onto the edge ring mounting surface of the electrostatic chuck 20. It should be noted that the electrostatic chuck 20 may include a heater to control the temperature.

[0022] Inside the support platform 14, for example, a refrigerant chamber 28 is formed in an annular or spiral shape. Refrigerant at a predetermined temperature, such as cooling water, supplied from the cooler unit (not shown), passes through pipe 30a, the refrigerant chamber 28, and pipe 30b, and returns to the cooler unit. By circulating the refrigerant in this path, the temperature of the wafer W can be controlled using the temperature of the refrigerant. Furthermore, a heat transfer gas, such as He gas, supplied from a heat transfer gas supply mechanism (not shown), is supplied via gas supply line 32 to the gap between the front side of the electrostatic chuck 20 and the back side of the wafer W. This heat transfer gas increases the heat transfer coefficient between the front side of the electrostatic chuck 20 and the back side of the wafer W, thereby more effectively controlling the temperature of the wafer W using the temperature of the refrigerant. Additionally, if the electrostatic chuck 20 has a heater, by utilizing heating with the heater and cooling with the refrigerant, the temperature of the wafer W can be controlled with high responsiveness and high precision. Alternatively, the heat transfer gas, such as He gas, supplied from the heat transfer gas supply mechanism (not shown), can also be supplied to the gap between the front side of the electrostatic chuck 20 and the back side of the edge ring 24 via a gas supply line (not shown). Furthermore, the heat transfer characteristics between the electrostatic chuck 20 and the adsorbed material (wafer W, edge ring 24) can be controlled by controlling the pressure of the He gas supplied to the gap between the front side of the electrostatic chuck 20 and the back side of the adsorbed material (wafer W, edge ring 24), and the temperature of the adsorbed material (wafer W, edge ring 24).

[0023] An upper electrode 34 is disposed on the top of the chamber 10 opposite to the stage 16. A plasma processing space is formed between the upper electrode 34 and the stage 16. The upper electrode 34 seals the opening at the top of the chamber 10 via an insulating shielding member 42. The upper electrode 34 has an electrode plate 36 and an electrode support 38. The electrode plate 36 has a plurality of gas exhaust holes 37 formed on the opposing surface opposite to the stage 16 and is formed of silicon or a silicon-containing material such as SiC. The electrode support 38 supports the electrode plate 36 in a removable manner and is formed of a conductive material, such as aluminum with an anodized surface. Inside the electrode support 38, a plurality of gas flow holes 41a, 41b extend downward from the gas diffusion chambers 40a, 40b and communicate with the gas exhaust holes 37.

[0024] The gas inlet 62 is connected to the processing gas supply source 66 via a gas supply pipe 64. A mass flow controller (MFC) 68 and an on / off valve 70 are sequentially installed on the gas supply pipe 64, upstream of the processing gas supply source 66. The processing gas is supplied from the processing gas supply source 66, and its flow rate and on / off state are controlled by the mass flow controller 68 and the on / off valve 70. The gas is then discharged in a spray pattern through the gas supply pipe 64, gas diffusion chambers 40a and 40b, gas flow holes 41a and 41b, and finally through the gas outlet 37.

[0025] The plasma processing apparatus 1 includes a first high-frequency power supply 90 and a second high-frequency power supply 48. The first high-frequency power supply 90 is a power source that generates first high-frequency power (hereinafter also referred to as "HF power"). The first high-frequency power has a frequency suitable for generating plasma. The frequency of the first high-frequency power is, for example, a frequency in the range of 27 MHz to 100 MHz. The first high-frequency power supply 90 is connected to the base 16a via a matching device 88 and a power supply line 89. The matching device 88 has circuitry for matching the output impedance of the first high-frequency power supply 90 with the impedance of the load side (base 16a side). It should be noted that the first high-frequency power supply 90 can be connected to the upper electrode 34 via the matching device 88.

[0026] The second high-frequency power supply 48 is a power source that generates a second high-frequency power (hereinafter also referred to as "LF power"). The second high-frequency power has a frequency lower than that of the first high-frequency power. When the second high-frequency power is used in conjunction with the first high-frequency power, the second high-frequency power is used as a high-frequency power for biasing ions to attract them to the wafer W. The frequency of the second high-frequency power is, for example, a frequency in the range of 400 kHz to 13.56 MHz. The second high-frequency power supply 48 is connected to the base station 16a via a matching unit 46 and a power supply line 47. The matching unit 46 has a circuit for matching the output impedance of the second high-frequency power supply 48 with the impedance of the load side (base station 16a side). It should be noted that a DC pulse can be used as the bias power for attracting ions to the wafer W. In this case, the plasma processing apparatus 1 has a DC pulse power supply (not shown) instead of the second high-frequency power supply 48. The DC pulse power supply is connected to the base station 16a via the power supply line 47. Alternatively, a synthesized wave obtained by combining multiple input voltages such as a DC pulse (rectangular wave) or a triangular wave can be used as the bias power for attracting ions to the wafer W. In this case, the plasma processing apparatus 1 has a power supply (not shown) for outputting the synthesized wave instead of the second high-frequency power supply 48. The power supply for outputting the synthesized wave is connected to the base 16a via a power supply line 47.

[0027] It should be noted that a second high-frequency power source can be used without the first high-frequency power source; that is, only a single high-frequency power source can be used to generate plasma. In this case, the frequency of the second high-frequency power source can be greater than 13.56 MHz, for example, 40 MHz. The plasma processing apparatus 1 may also exclude the first high-frequency power source 90 and the matching device 88. With this structure, the stage 16 also functions as the lower electrode. In addition, the upper electrode 34 also functions as a nozzle for supplying gas.

[0028] The second variable power supply 50 is connected to the upper electrode 34 and applies a DC voltage to the upper electrode 34. The first variable power supply 55 is connected to the edge ring 24 and applies a DC voltage to the edge ring 24. By applying a predetermined DC voltage corresponding to the consumption of the edge ring 24 from the first variable power supply to the edge ring 24, the thickness of the sheath on the edge ring 24 is controlled. This eliminates the step difference between the sheath on the edge ring 24 and the sheath on the wafer W, prevents the ion irradiation angle from becoming tilted at the edge of the wafer W, and avoids the occurrence of tilting, where the shape of the recess formed on the wafer W becomes tilted.

[0029] Furthermore, a DC voltage detector 57 for measuring the voltage of the edge ring 24 is installed at a branch point in the wiring used to apply voltage to the edge ring 24 from the first variable power supply 55. A switch 56 is also provided at the branch point. The switch 56 is configured to switch between a first state for connecting the edge ring 24 to the first variable power supply 55 and a second state for connecting the edge ring 24 to the DC voltage detector 57. By setting the switch 56 to the first state, a voltage can be applied to the edge ring 24. Furthermore, by setting the switch 56 to the second state, the self-bias voltage Vdc of the edge ring 24, which is the voltage applied to the edge ring 24 (which serves as a cathode) during plasma processing due to the difference in the migration velocities of electrons and ions, can be detected.

[0030] An exhaust device 84 is connected to an exhaust pipe 82. The exhaust device 84 includes a vacuum pump such as a turbomolecular pump, and exhausts air through the exhaust pipe 82 from an exhaust port 80 formed at the bottom of the chamber 10, thereby reducing the pressure inside the chamber 10 to the required vacuum level. Furthermore, the exhaust device 84 uses the value of a pressure gauge (not shown) for measuring the pressure inside the chamber 10 to maintain a constant pressure. An inlet / outlet 85 is provided on the side wall of the chamber 10. The wafer W is moved in or out of the inlet / outlet 85 by opening and closing a gate valve 86.

[0031] A baffle 83 is arranged in a ring between the insulator ring 26 and the side wall of the chamber 10. The baffle 83 has multiple through holes, is made of aluminum, and its surface is covered with ceramic such as Y2O3.

[0032] When performing predetermined plasma processing such as plasma etching in the plasma processing apparatus 1 of this structure, the gate valve 86 is opened, and the wafer W is moved into the chamber 10 via the loading / unloading outlet 85, placed on the wafer mounting surface of the electrostatic chuck 20, and then the gate valve 86 is closed. Additionally, the edge ring 24 is placed on the edge ring mounting surface of the electrostatic chuck 20. Processing gas is supplied to the interior of the chamber 10, and the interior of the chamber 10 is vented using the exhaust device 84.

[0033] A first high-frequency power and a second high-frequency power are applied to the mounting stage 16. Furthermore, a voltage is applied to the first electrode 20a of the electrostatic chuck 20 using power supply 22, thereby attracting the wafer W to the wafer mounting surface of the electrostatic chuck 20. Additionally, a voltage is applied to the second electrode 20c of the electrostatic chuck 20 using power supply 23, thereby attracting the edge ring 24 to the edge ring mounting surface of the electrostatic chuck 20. It should be noted that a DC voltage can be applied to the upper electrode 34 from the second variable power supply 50.

[0034] Plasma treatments, such as etching, are performed on the surface of wafer W by using free radicals and ions in the plasma generated in the plasma processing space.

[0035] The plasma processing apparatus 1 includes a control unit 200 for controlling the operation of the entire apparatus. A CPU within the control unit 200 executes plasma processing procedures, such as etching, based on a recipe stored in a memory such as ROM or RAM. This recipe allows setting control information for the apparatus, including processing time, pressure (gas exhaust), first and second high-frequency power or voltage, and various gas flow rates. Furthermore, the recipe allows setting the temperatures within the chamber (upper electrode temperature, chamber sidewall temperature, wafer W temperature, electrostatic chuck temperature, etc.) and the temperature of the refrigerant output from the cooler. It should be noted that these recipes representing the program or processing conditions can be stored in a hard disk or semiconductor memory. Alternatively, the recipe can be set to a predetermined location and retrieved by storing it in a portable computer-readable storage medium such as a CD-ROM or DVD.

[0036] Next, use Figure 2 The arrangement of the electrodes of the electrostatic chuck 20 in the stage 16 will be further explained. Figure 2 (a) is a plan view showing an example arrangement of the first electrode 20a on the wafer mounting surface of the electrostatic chuck 20. Figure 2 (b) is a plan view showing an example arrangement of the second electrode 20c on the edge ring mounting surface of the electrostatic chuck 20.

[0037] like Figure 2As shown in (a), the first electrode 20a on the wafer mounting surface has electrodes 20a1, 20a2, and 20a3. Electrodes 20a1, 20a2, and 20a3 have a generally fan-shaped planar shape and are arranged circumferentially relative to the central axis of the electrostatic chuck 20. A power supply 22 is connected to electrodes 20a1, 20a2, and 20a3, respectively. The power supply 22 generates an alternating current voltage.

[0038] like Figure 2 As shown in (b), the second electrode 20c on the edge ring mounting surface has electrodes 20c1, 20c2, and 20c3. Electrodes 20c1, 20c2, and 20c3 have a generally arc-shaped planar shape and are arranged circumferentially relative to the central axis of the electrostatic chuck 20. A power supply 23 is connected to electrodes 20c1, 20c2, and 20c3, respectively. The power supply 23 generates an alternating current voltage.

[0039] It should be noted that although the structure of the electrodes (electrodes 20a1, 20a2, 20a3) of the first electrode 20a has been described with the electrodes arranged circumferentially, it is not limited to this and the electrodes may also be arranged radially. Similarly, although the structure of the electrodes (electrodes 20c1, 20c2, 20c3) of the second electrode 20c has been described with the electrodes arranged circumferentially, it is not limited to this and the electrodes may also be arranged radially.

[0040] Next, use Figure 3 (a) The three-phase AC voltage applied to the second electrode 20c (electrodes 20c1, 20c2, 20c3) is described. Figure 3 (a) is a graph illustrating an example of a three-phase AC voltage applied to electrodes 20c1, 20c2, and 20c3. The vertical axis represents the applied voltage, and the horizontal axis represents time. A solid line represents an example of an AC voltage applied to electrode 20c1, a dotted line represents an example of an AC voltage applied to electrode 20c2, and a dashed line represents an example of an AC voltage applied to electrode 20c3. It should be noted that the applied voltage amplitude is normalized to 1.

[0041] In one embodiment, the AC voltages applied by the power supply 23 to electrodes 20c1, 20c2, and 20c3 have the same maximum amplitude, the same frequency, and different phases. For example, the phase difference of the AC voltages applied to electrodes 20c1, 20c2, and 20c3 is set to 120°.

[0042] Furthermore, the AC voltage applied to electrodes 20c1, 20c2, and 20c3 using power supply 23 is applied based on the self-biasing voltage Vdc of edge ring 24. For example, the AC voltage applied to electrodes 20c1, 20c2, and 20c3 using power supply 23 is applied with reference to the self-biasing voltage Vdc of edge ring 24. In other words, the average voltage of the AC voltage applied to electrodes 20c1, 20c2, and 20c3 using power supply 23 is offset according to the self-biasing voltage Vdc of edge ring 24. In other words, regarding the AC voltage applied to electrodes 20c1, 20c2, and 20c3 using power supply 23, a negative DC voltage (deviating from) the self-biasing voltage Vdc based on edge ring 24 is superimposed (on the AC component). It should be noted that in Figure 3 In one example of (a), the self-bias voltage Vdc of edge ring 24 is illustrated as -0.2.

[0043] It should be noted that the self-bias voltage Vdc of the edge ring 24 is detected, for example, by a DC voltage detector 57. It should also be noted that the method for detecting the self-bias voltage Vdc is not limited to this, and other methods can be used. Alternatively, a preset value can be used as the self-bias voltage Vdc. This preset value can be determined in advance, for example, through experimentation or simulation, and stored in the memory of the control unit 200. Furthermore, the relationship between the self-bias voltage Vdc and plasma generation conditions (e.g., the LF power used for bias) can be determined in advance, and the self-bias voltage Vdc can be estimated based on the plasma generation conditions.

[0044] use Figure 3 (b) Applying an electric field to the second electrode 20c (electrodes 20c1, 20c2, 20c3) Figure 3 (a) illustrates the adsorption force of the edge ring 24 under the 3-phase AC voltage. Figure 3 (b) is an example graph showing the sum of the adsorption forces of the edge ring 24 when a three-phase AC voltage is applied to electrodes 20c1, 20c2, and 20c3. The vertical axis represents the sum of the adsorption forces, and the horizontal axis represents time. Figure 3 As shown in (b), the adsorption force that enables the stage 16 to adsorb the edge ring 24 is constant.

[0045] Furthermore, the three-phase AC voltage applied to the first electrode 20a (electrodes 20a1, 20a2, 20a3) is also applied in the same manner as the three-phase AC voltage applied to the second electrode 20c (electrodes 20c1, 20c2, 20c3), by applying... Figure 3 The three-phase AC voltage shown in (a) thus, as Figure 3 (b) shows that the adsorption force that enables the stage 16 to adsorb the wafer W is constant.

[0046] It should be noted that the AC voltage applied to electrodes 20a1, 20a2, and 20a3 using power supply 22 is based on the self-biasing voltage Vdc of wafer W. For example, the AC voltage applied to electrodes 20a1, 20a2, and 20a3 using power supply 22 is applied with reference to the self-biasing voltage Vdc of wafer W. In other words, the average voltage of the AC voltage applied to electrodes 20a1, 20a2, and 20a3 using power supply 22 is offset according to the self-biasing voltage Vdc of wafer W. In other words, with respect to the AC voltage applied to electrodes 20a1, 20a2, and 20a3 using power supply 22, a negative DC voltage (deviating from) the self-biasing voltage Vdc of wafer W is superimposed (on the AC component).

[0047] It should be noted that a DC voltage detector (not shown) for detecting the self-bias voltage Vdc of wafer W can be included. Alternatively, a preset value can be used as the self-bias voltage Vdc. This preset value can be determined in advance, for example, through experimentation or simulation, and stored in the memory of the control unit 200. Furthermore, the relationship between the self-bias voltage Vdc and plasma generation conditions (e.g., HF power) can be predetermined, and the self-bias voltage Vdc can be estimated based on these conditions. Additionally, the relationship between the self-bias voltage Vdc of the edge ring 24 and the self-bias voltage Vdc of wafer W can be predetermined, and the self-bias voltage Vdc of wafer W can be estimated based on the self-bias voltage Vdc of the edge ring 24 detected by the DC voltage detector 57.

[0048] In addition, Figure 2 and Figure 3 Although the example described uses a case where the first electrode 20a and the second electrode 20c have three poles, it is not limited to this; they can also have two poles or four poles. Furthermore, the number of poles of the first electrode 20a and the second electrode 20c can be the same or different.

[0049] use Figure 4 The case where the second electrode 20c has two poles will be further explained. Figure 4 (a) is a graph showing an example of the two-phase AC voltage applied to each electrode when the second electrode 20c has two poles. The vertical axis represents the applied voltage, and the horizontal axis represents time. A solid line curve represents an example of the AC voltage applied to one electrode of the second electrode 20c, and a dotted-dash line curve represents an example of the AC voltage applied to the other electrode of the second electrode 20c. It should be noted that the applied voltage amplitude is normalized to 1.

[0050] The AC voltages applied to each electrode of the second electrode 20c by power supply 23 have the same maximum amplitude, the same frequency, and different phases. For example, the phase difference of the AC voltages applied to each electrode of the second electrode 20c is set to 90°. Furthermore, the AC voltages applied to each electrode by power supply 23 are applied based on the self-biasing voltage Vdc of edge ring 24. For example, the AC voltages applied to each electrode by power supply 23 are applied with reference to the self-biasing voltage Vdc of edge ring 24. In other words, the average voltage of the AC voltages applied to each electrode by power supply 23 is offset according to the self-biasing voltage Vdc of edge ring 24. In other words, with respect to the AC voltages applied to each electrode by power supply 23, a negative DC voltage (deviating from) the self-biasing voltage Vdc of edge ring 24 is superimposed (on) the AC component. It should be noted that... Figure 4 In one example of (a), the self-bias voltage Vdc of edge ring 24 is illustrated as -0.2.

[0051] use Figure 4 (b) Applying pressure to each electrode of the second electrode 20c Figure 4 (a) illustrates the adsorption force of the edge ring 24 under two-phase AC voltage. Figure 4 (b) is an example graph showing the sum of the adsorption forces of the edge ring 24 when a two-phase AC voltage is applied to each electrode of the second electrode 20c. The vertical axis represents the sum of the adsorption forces, and the horizontal axis represents time. Figure 4 As shown in (b), even if the second electrode 20c has two poles, the adsorption force of the stage 16 on the edge ring 24 can be kept constant.

[0052] While comparing with a reference example, the adsorption method of the stage 16 (electrostatic chuck 20) ​​of the plasma processing apparatus 1 according to one embodiment will be described.

[0053] According to the first reference example, a DC voltage is applied to the first electrode 20a and the second electrode 20c of the electrostatic chuck 20 on the stage 16 to attract the wafer W or edge ring 24 to the stage 16. In the structure where the DC voltage is applied, if the time for attracting the wafer W or edge ring 24 to the stage 16 is prolonged, the charge on the wafer W or edge ring 24 moves towards the insulating layer 20b of the electrostatic chuck 20. Therefore, the effectively applied DC voltage decreases, and the electrostatic attraction force decreases. It should be noted that in plasma processing, the heat of the plasma is thermally input to the stage 16. As the temperature of the stage 16 rises, the charge moves more easily, the effectively applied DC voltage decreases further, and the electrostatic attraction force decreases further.

[0054] In contrast, in the adsorption method of the mounting stage 16 of the plasma processing apparatus 1 according to one embodiment, an alternating voltage is applied to the first electrode 20a and the second electrode 20c of the electrostatic chuck 20 to adsorb the wafer W or edge ring 24 onto the mounting stage 16. Therefore, even if the wafer W or edge ring 24 is adsorbed for a long time, the reduction of electrostatic adsorption force due to charge movement can be prevented.

[0055] According to the second reference example, a DC voltage is applied to the first electrode 20a and the second electrode 20c of the electrostatic chuck 20 on the stage 16 to attract the wafer W or edge ring 24 to the stage 16. In the second reference example, the average voltage of the applied AC voltage is applied with GND as a reference. In other words, the average voltage of the applied AC voltage is set to 0V.

[0056] Figure 5 This is a graph showing an example of the applied voltage and the flow rate of the heat transfer gas (He gas). Figure 5 (a) illustrates one implementation method. Figure 5 (b) shows the second reference example. The first vertical axis represents the applied voltage, the second vertical axis represents the flow rate of He gas, which is supplied as heat transfer gas to the gap between the front side of the electrostatic chuck 20 and the back side of the edge ring 24, and the horizontal axis represents time. A solid line curve represents an example of an AC voltage applied to one electrode of the second electrode 20c, and a dotted line curve represents an example of an AC voltage applied to the other electrode of the second electrode 20c. It should be noted that the applied voltage amplitude is normalized to 1. In addition, the He gas flow rate is represented by a dashed line. Here, a two-phase AC voltage is used as an example for explanation.

[0057] Here, in the plasma processing, a negative self-bias voltage Vdc is generated in the edge ring 24. Therefore, in Figure 5 In example (b), judging from the potential (self-bias voltage Vdc) of the edge ring 24, the time for applying a positive voltage is longer than the time for applying a negative voltage. Furthermore, the maximum absolute value of the applied positive voltage is greater than the maximum absolute value of the applied negative voltage. Therefore, similar to the case of applying a DC voltage as shown in the first reference example, if the time for the edge ring 24 to be attracted to the stage 16 is prolonged, the charge on the edge ring 24 moves towards the insulating layer 20b of the electrostatic chuck 20. Therefore, if the time for the edge ring 24 to be attracted to the stage 16 is prolonged, the effectively applied voltage decreases, and the attraction force of the edge ring 24 decreases. Additionally, due to the difference between the average voltage of the applied AC voltage and the potential (self-bias voltage Vdc) of the edge ring 24, the sum of the attraction forces of the edge ring 24 vibrates, making it impossible to obtain a stable attraction force.

[0058] Here, if the adsorption force of the mounting stage 16 on the edge ring 24 decreases, the gap between the front side of the electrostatic chuck 20 and the back side of the edge ring 24 widens, and the flow rate of He gas supplied to the gap increases. Figure 5 As indicated by arrow 502 in (b), it shows that when the average applied voltage is set to 0V, the flow rate of He gas gradually increases, and the adsorption force of the edge ring 24 decreases. Furthermore, the variation in the He gas flow rate is also more pronounced than described later. Figure 5 (a) big.

[0059] In contrast, in the adsorption method of the stage 16 of the plasma processing apparatus 1 according to one embodiment, such as Figure 5 As shown in (a), the applied AC voltage is referenced to the self-bias voltage Vdc of the edge ring 24. In other words, the average voltage of the applied AC voltage is offset according to the self-bias voltage Vdc of the edge ring 24.

[0060] Therefore, in Figure 5 In example (a), considering the potential (self-bias voltage Vdc) of the edge ring 24, the time for applying a positive voltage can be equal to the time for applying a negative voltage. Furthermore, the maximum absolute value of the applied positive voltage can be equal to the maximum absolute value of the applied negative voltage. Therefore, even if the time for the edge ring 24 to be attracted to the stage 16 is prolonged, the movement of charge from the edge ring 24 towards the insulating layer 20b of the electrostatic chuck 20 can be suppressed. Figure 5 Arrow 501 in (a) shows that the increase in He gas flow rate was suppressed and the decrease in the adsorption force of edge ring 24 was prevented. Furthermore, the variation in He gas flow rate was also less than... Figure 5 (b) Small.

[0061] As described above, according to the adsorption method of the stage 16 of the plasma processing apparatus 1 in one embodiment, even if the adsorption time of the electrostatic chuck 20 on the adsorbed material (wafer W, edge ring 24) is relatively long, the reduction of adsorption force can be suppressed. Thus, for example, even in the process of adsorbing the adsorbed material (wafer W, edge ring 24) of 3D NAND with a high layer stack for a long time, the reduction of adsorption force can be suppressed.

[0062] It should be noted that, although the self-biasing voltage Vdc, which is superimposed as a negative DC voltage on the AC voltage (in... Figure 3 The example given is -0.2, but it is not limited to this. For example, a negative DC voltage based on the self-bias voltage Vdc (e.g., 50% of Vdc, -0.1) can be superimposed on the AC voltage. In this case, since charge movement can also be reduced compared to the structure of Reference Example 2, the reduction in the adsorption force of the electrostatic chuck 20 on the adsorbed object can be suppressed to a certain extent.

[0063] Although the embodiments of plasma processing apparatus 1 have been described above, this disclosure is not limited to the above embodiments, and various modifications and improvements can be made within the scope of the spirit of this disclosure as set forth in the claims.

Claims

1. A stage comprising: a base; an electrostatic chuck provided on the base and having an n-pole electrode of 2 poles or more inside; and a power source that applies n-phase alternating voltages of 2 phases or more, whose phases are different from each other, to the n-pole electrode, wherein the power source includes an alternating current power source that is directly connected to the n-pole electrode and applies an alternating voltage for adsorbing an adsorbed object; and a direct current power source that applies a negative direct current voltage based on a self-bias voltage to the alternating voltage in such a manner that the average voltage of the alternating voltage is offset by the negative direct current voltage so that the time during which a positive voltage of the alternating voltage is applied is equal to the time during which a negative voltage of the alternating voltage is applied.

2. A plasma processing apparatus comprising the stage according to claim 1.

3. The plasma processing apparatus according to claim 2, further comprising: a gas supply portion that supplies a heat transfer gas between the back surface of the adsorbed object, which is at least one of a substrate or a ring, and the front surface of the stage, to the adsorbed object placed and adsorbed on the stage.

4. The plasma processing apparatus according to claim 2, wherein the self-bias voltage to be superimposed is calculated in accordance with the conditions of plasma processing.

5. The plasma processing apparatus according to claim 2, wherein the self-bias voltage to be superimposed is a detection value of a voltage detection portion that detects the voltage of the adsorbed object, which is at least one of a substrate or a ring, placed and adsorbed on the stage. ​

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