DAC control logic for controlling the DAC

Abstract

The present disclosure relates to a DAC control logic for controlling a DAC. The DAC control logic (45) is used to control a DAC (2) to supply a target voltage V to a switching converter (1; FIG. 4 ). TARGET The DAC logic includes control logic (54) configured to decrement a DAC input code (47) supplied to the DAC in a series of steps in response to the DAC ramping down. For at least some of the steps during the ramping down, the DAC control logic is configured to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.

Description

Technical Field

[0001] The present invention relates to controlling the output voltage of a DAC, in particular for being supplied as a target voltage to a switching converter. Background Art

[0002] A switching regulator can be used to convert one DC voltage to another DC voltage. For example, a buck converter can be used to step a voltage down, a boost converter can be used to step a voltage up, and a buck-boost can be used to step a voltage down or up.

[0003] Switching regulators typically use pulse width modulation (PWM) to control switches in the power stage to vary the current through an inductor. The duty cycle of the PWM signal is controlled based on the inductor current, and varying the duty cycle is used to regulate the output voltage.

[0004] The output DC voltage of the switching regulator is set using a target voltage. The target voltage may be fixed, or may be controllably adjusted using a digital-to-analog converter (DAC). Summary of the invention

[0005] According to a first aspect of the present invention, there is provided a device or DAC control logic for controlling a DAC for supplying a target voltage V to a switching converter. TARGET The device or DAC logic includes control logic configured to decrement a DAC input code supplied to the DAC in a series of steps in response to the DAC ramping down. For at least some of the steps during the ramping down, the device or DAC logic is configured to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.

[0006] This can help reduce undershoot of the DAC's output voltage.

[0007] The device or DAC logic may also include a ramp-down detector configured to identify a DAC ramp-down by determining whether a new DAC input code is less than a current DAC input code.

[0008] The device or DAC logic may also include a calculator configured to calculate a difference Δ between the new DAC input code and the current DAC input code. The difference Δ is a current cycle counter indicating the current cycle counter at which the target voltage V is reached. TARGET The number of switching cycles remaining before.

[0009] The control logic can be configured to determine a condition including whether the difference Δ is less than or equal to a predetermined value N, and based on a positive determination, wait until at least one switching cycle has occurred before decrementing the DAC input code, and based on a negative determination, decrement the DAC input code from the current value to the new value regardless of whether at least one switching cycle has occurred.

[0010] The predetermined value N indicates that when the target voltage V is reached TARGET The number of previous switching cycles during which the DAC input code should be waited before the switching cycle(s) have occurred. The predetermined value N may be selected from a range between 5 and 30 or between 10 and 20. The predetermined value N may be between 0 and 0.2Δ (i.e., at most 20% of the difference Δ), or may be between 0 and 0.1Δ (i.e., at most 10% of the difference Δ). The predetermined value N may be determined based on an expected value of Δ, which may be determined based on the number of DAC levels.

[0011] In response to a DAC clock edge (eg, a rising DAC clock rate), decrementing the DAC input code may occur.

[0012] The conditions may also include whether the switching regulator is applying an audio band suppression that suppresses switching below a given frequency. The audio band suppression may be achieved by introducing additional switching cycles in order to maintain a minimum switching frequency.

[0013] Based on a positive determination, the control logic may be configured to reduce the DAC clock rate.

[0014] According to a second aspect of the present invention, a DAC logic comprising the device or DAC control logic of the first aspect is provided. The DAC logic may also include a DAC clock generator for generating a DAC update clock signal. The DAC logic may also include a first data latch for receiving and storing a new DAC input code. The DAC logic may also include a second data latch for receiving and storing a current DAC input code for providing to the DAC.

[0015] The DAC logic may also include, for example, a register to store a predetermined value N. The predetermined value N may be programmable, for example, by an external processor-based controller.

[0016] The DAC logic may also include logic for Boolean combination of signals from the switching converters. The DAC may be an n-bit DAC, where 5≤n≤16, such as 8≤n≤12. For example, the DAC may be a 10-bit DAC.

[0017] According to a third aspect of the invention there is provided a system comprising a DAC and DAC logic comprising the device or DAC control logic of the first aspect, the DAC logic being arranged to provide a DAC input code to the DAC.

[0018] The DAC logic may also provide a DAC update clock signal.

[0019] According to a fourth aspect of the present invention, there is provided a monolithic integrated circuit comprising the system of the third aspect. Thus, the monolithic integrated circuit may be a DAC IC. The monolithic integrated circuit may include more than one DAC, and each DAC may have corresponding DAC control logic.

[0020] The monolithic integrated circuit may include a switching converter, and the DAC may be configured to provide a target voltage to the switching converter. Thus, the monolithic integrated circuit may be a switching converter IC. The switching converter IC may include a power stage (e.g., including two or more power transistors for switching current through an energy storage element such as an inductor coil).

[0021] The switching converter may be, for example, a hysteretic switching converter employing a synthetic current ramp. The switching converter may be a current mode switching converter. The switching converter may be a voltage mode switching converter. The switching converter may be a non-isolated switching converter. The switching converter may include an inductor coil as an energy storage element. The switching converter may be a buck converter, a boost converter, a buck-boost converter, or an inverting converter.

[0022] According to a fifth aspect of the present invention, there is provided a method for controlling a DAC, the DAC supplying a target voltage V to a switching regulator. TARGET The method includes decrementing a DAC input code supplied to a DAC in a series of steps in response to a DAC ramp-down. For at least some of the steps (e.g., for all steps or only for the last N steps, where N is a positive, non-zero integer), decrementing the DAC input code includes waiting until at least one switching cycle has occurred in a switching converter before decrementing the DAC input code from a current value to a new value.

[0023] The method may also include identifying a DAC ramp down by determining whether a new DAC input code is less than a current DAC input code.

[0024] The method may further include calculating a difference Δ between the new DAC input code and the current DAC input code. The difference Δ is the current cycle counter, which indicates that the target voltage V is reached. TARGET The number of switching cycles remaining before.

[0025] The method may further include determining a condition including whether the difference Δ is less than or equal to a predetermined value N, and upon a positive determination, waiting until at least one switching cycle has occurred before decrementing the DAC input code, or upon a negative determination, decrementing the DAC input code from the current value to the new value regardless of whether at least one switching cycle has occurred. The predetermined value N represents the value of the DAC input code that is set to the new value after reaching the target voltage V TARGET The number of previous switching cycles during which a decreasing DAC input code should wait before a switching cycle has occurred.

[0026] The predetermined value N may be selected from a range between 5 and 30 or between 10 and 20. The range depends on the switching converter (eg, control loop bandwidth and the number of bits in the DAC).

[0027] In response to a DAC clock edge (eg, a rising DAC clock rate), decrementing the DAC input code may occur.

[0028] The conditions may also include whether the switching regulator is applying an audio band suppression that suppresses switching below a given frequency.

[0029] The method may also include, based on a positive determination, reducing the DAC clock rate.

[0030] The given number is preferably selected from the range between 5 and 30, and more preferably selected from the range between 10 and 20.

[0031] According to a sixth aspect of the present invention, there is provided a computer program comprising instructions for executing the method of the fifth aspect.

[0032] According to a seventh aspect of the present invention, there is provided a computer program product comprising a computer readable medium storing a computer program (the computer readable medium may be non-transitory).

[0033] According to an eighth aspect of the present invention, there is provided an electronic system comprising a power supply, a device, a switching regulator, a monolithic integrated circuit of the previous aspect, and a load. The electronic system may be a portable (e.g., handheld or laptop) electronic device, such as a mobile phone, a tablet computing device, or a laptop computer, and the load may be an electronic circuit system within the portable electronic device. The electronic system may be a lighting system, and the load may be (multiple) lighting elements, such as (multiple) LEDs. The electronic system may be an automotive system, and the load may be, for example, an electronic control unit. The power supply may be a battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Certain embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0035] Figure 1is a schematic block diagram of a power converter and a DAC for providing a target voltage to the power converter;

[0036] Figure 2 is a schematic block diagram of a power converter in the form of a buck-boost regulator;

[0037] Figure 3 The diagram shows Figure 1 DAC output voltage and target voltage and compensated output voltage and inductor current simulated by the power converter and DAC shown in;

[0038] Figure 4 is a schematic block diagram of a power converter and a DAC providing a target voltage to the power converter and DAC logic including a DAC update control logic for controlling an output voltage of the DAC;

[0039] Figure 5 is a schematic block diagram of DAC logic including DAC update control logic;

[0040] Figure 6 It is a process flow chart of DAC update control;

[0041] Fig. 7A is a timing diagram showing the variation of inductor current and PWM over time under low load conditions and illustrating the switching frequency;

[0042] Figure 7B is a timing diagram showing the variation of inductor current and PWM over time under low load conditions such that the switching frequency is at a threshold for audio band rejection;

[0043] Figure 7C is a table illustrating the relationship between the signal ABS switching frequency;

[0044] Figure 8 is a schematic block diagram of a power converter taking into account audio band rejection and a DAC providing a target voltage to the power converter and a DAC control including a modified DAC update control for controlling an output voltage of the DAC;

[0045] Fig. 9 The diagram shows the first light load condition. Figure 4 DAC output voltage and target voltage and compensated output voltage and inductor current simulated by the power converter and DAC shown in;

[0046] Fig.10 The figure shows the second medium load condition. Figure 1 DAC output voltage and target voltage and compensated output voltage and inductor current simulated by the power converter and DAC shown in;

[0047] Fig.11 The figure shows the second medium load condition. Figure 4 DAC output voltage and target voltage and compensated output voltage and inductor current simulated by the power converter and DAC shown in;

[0048] Fig.12 The figure shows the third highest load condition. Figure 1 DAC output voltage and target voltage and compensated output voltage and inductor current simulated by the power converter and DAC shown in;

[0049] Fig.13 The figure shows the third highest load condition. Figure 4 DAC output voltage and target voltage and compensated output voltage and inductor current simulated by the power converter and DAC shown in;

[0050] Fig.14 A illustrates the first light load condition. Figure 1 The DAC output voltage and target voltage simulated by the power converter and DAC shown in FIG. 1 and the compensated output voltage and high-side FET gate voltage;

[0051] Fig.14 B to 14D respectively illustrate the first light load condition. Figure 4 The power converter and DAC shown in , the DAC output voltage and target voltage simulated for N exceeding the number of DAC levels (N=10 and N=20) and the compensated output voltage and high-side FET gate voltage;

[0052] Fig.15 A shows the light load condition for the fourth pole. Figure 1 The DAC output voltage and target voltage simulated by the power converter and DAC shown in FIG. 1 and the compensated output voltage and high-side FET gate voltage;

[0053] Fig.15 B to 15D respectively illustrate the fourth pole under light load conditions Figure 4 The power converter and DAC shown in , the DAC output voltage and target voltage simulated for N exceeding the number of DAC levels (N=10 and N=20) and the compensated output voltage and high-side FET gate voltage;

[0054] Fig.16 A and 16B are for Figure 1 The DAC shown in Figure 4 DAC shown in , simulated undershoot voltage versus current load for buck, boost, extreme boost, and buck-boost converters;

[0055] Fig.17A and 17B Respectively for Figure 1 The DAC shown in Figure 4 Table of simulated undershoot voltage versus current load for buck, boost, extreme boost, and buck-boost converters for the DAC shown in;

[0056] Fig.18 Illustration of the use Figure 1 The DAC shown in FIG. 1 shows the simulated AC output voltage and load current variation with respect to time for an ABS cycle;

[0057] Fig.19 illustrates simulated DAC output voltage and load current variations with respect to time for an ABS cycle using the DAC shown in FIG. 7 ; and Fig. 20 is a schematic block diagram of a voltage source, switching regulator, load, and controller. DETAILED DESCRIPTION

[0058] In the following, like parts are denoted by like reference numerals.

[0059] DAC and DAC Control Logic

[0060] Reference Figure 1 , shows a power converter 1 (or "DC to DC converter" or "switching regulator"), a digital-to-analog converter (DAC) 2, and DAC control logic 3. The power converter 1 may take the form of a buck converter, a boost converter, a buck-boost converter, or other similar type of converter.

[0061] The DAC 2 comprises an input for receiving an n-bit DAC code 4 (eg, an 8-bit DAC) and an output for providing a corresponding analog output voltage, which is used as a target voltage V of the power converter 1. TARGET .

[0062] In an arrangement referred to herein as a "simple DAC arrangement" or "simple DAC", the DAC 2 is controlled by DAC control logic 3. As will be described in more detail below, the simple DAC arrangement is useful for understanding the present invention.

[0063] DAC control logic 3 receives an n-bit digital code and a clock signal CLK, and supplies an n-bit digital code and a DAC clock signal DAC CLK based on the clock signal CLK to DAC 2. If the clock rate of the clock signal CLK is too high, DAC control logic 3 may divide the clock signal CLK down to a suitable rate for DAC 2.

[0064] The power converter 1 generates a voltage according to the target voltage VTARGET The voltage signal V IN Converted to output voltage V SYS The power converter 1 includes an error amplifier 5 which directly or indirectly receives a target voltage V TARGET and the converter output voltage V SYS As first and second inputs, the converter outputs a voltage V SYS is sensed and used as feedback voltage V FB The error amplifier 5 has an output, which outputs an error signal V via a stability compensation node (or “control node”) COMP. C (or “control signal”), the error signal is V TARGET With V SYS The error measurement between .

[0065] The power converter 1 is arranged to reduce the control signal V C magnitude, and in doing so, makes the output voltage V SYS Converge and track the target voltage V TARGET .

[0066] Reference Figure 2 , an example of a power converter 1 in the form of a buck-boost converter is shown.

[0067] The power converter 1 has a voltage input node 6 and a voltage output node 7, and employs an energy storage element in the form of an inductor 8 having first and second nodes (or "phase nodes") LX1, LX2. First and second pairs of switches Q1, Q3, Q2, Q4 are used to control the voltage across the inductor 8, the first and second pairs of switches being driven by first and second drivers 9, 10, respectively.

[0068] In the first pair of switches, the first and third switches Q1, Q3 are arranged in a totem pole configuration between the voltage input node 6 and the ground GND. In the second pair of switches, the second and fourth switches Q2, Q4 are arranged in a totem pole configuration between the voltage output node 7 and the ground GND. The switches Q1, Q2, Q3, Q4 take the form of suitable power transistors, such as power MOSFETs.

[0069] The first gate driver 9 supplies upper and lower gate drive signals UG1, LG1 to the first (high side) and third (low side) switches Q1, Q3, respectively. The second gate driver 10 supplies upper and lower gate drive signals UG2, LG2 to the second (high side) and fourth (low side) switches Q2, Q4, respectively. The gate drivers 9, 10 are controlled by a loop selector 11, which is controlled by a pulse width modulation (PWM) signal PWM and outputs the first and second PWM signals PWM_BUCK, PWM_BOOST to the first and second gate drivers 9, 10, respectively.

[0070] Output current i OUT and optionally an input current i IN The sensed currents are sensed and the sensed currents are fed into the loop selector 11. The loop selector 11 comprises a zero crossing detector (not shown) which generates a zero crossing detector signal ZCD (not shown) which can be used to control the gate drivers 9, 10. The output voltage V SYS and optionally an input voltage V IN is sensed and fed back to the loop selector 11.

[0071] The power converter 1 includes a synthetic ramp generator circuit 14, which includes a transconductance (or "g m ”) amplifier 15 and modulator capacitor C R The inductor current information is obtained by sensing the voltage across the inductor using a transconductance amplifier 15 and by generating a signal that is proportional to the inductor current I L A sawtooth voltage ramp proportional to V R and are synthesized.

[0072] The hysteresis control circuit 16 includes an error amplifier 5 which receives an error voltage V from the loop selector 11. ERR , where V ERR =V TARGET -V FB The error amplifier 5 outputs an error signal V via the stability compensation node COMP. C , the stability compensation node is supplied to the first and second voltage level generators 17, 18 for generating the upper and lower window levels V W+ 、V W- , upper and lower window levels V W+ 、V W- The voltage ramp VR is supplied to the non-inverting input of the first comparator 18 and the inverting input of the second comparator 19, respectively.

[0073] The outputs of the first and second comparators 19, 20 are provided to reset the R input of the SR latch 21 and to set the S input of the SR latch 21, respectively. The Q output of the latch 21 is supplied to the loop selector 11 as a PWM signal ("PWM").

[0074] Regulator undershoot during ramp-down

[0075] Dynamically change the target output voltage V TARGET can present significant challenges, especially during ramp-down, when trying to achieve an output voltage V across the full range of operating conditions and modes. SYS The minimum undershoot.

[0076] Regulator 1 attempts to increase the output voltage V SYS Controlled relative to the target voltage V TARGET As previously mentioned, the power switches Q1, Q2, Q3, Q4 are driven by PWM signals PWM_BUCK, PWM_BOOST, and the regulator 1 adjusts the PWM duty cycle and frequency to regulate the output. The stability compensation node COMP is the main loop stability compensation node.

[0077] Figure 3 The diagram shows Figure 1 In the simple DAC arrangement shown in Figure 1, the IN =5.4V and V IN = 13.5V target voltage V TARGET Undershoot problem during ramp down.

[0078] Reference Figure 1 and 3 DAC control logic 3 makes the target voltage V TARGET The voltage is continuously ramped down to the final voltage level at a specified ramp-down rate. The undershoot may exceed the specification significantly, especially at light load conditions. In this article, light load is defined as approximately 10mA. However, the definition of light load and heavy load depends on the application. For light load, V TARGET drops more than the converter output voltage V SYS fast, and therefore, the converter output voltage V SYS Close to V TARGET When the control voltage V at the stability compensation node COMP is C is clamped at its minimum level. The control voltage V C It takes time to return to its operating range. During this period, the converter output voltage V SYS Will go down. Figure 3 In the case shown in , the undershoot is 43mV.

[0079] In many cases, undershoot can have detrimental effects, such as when the load is a digital system with HIGH and LOW binary states (such as an IC), an electronic component with an ON threshold voltage (such as an LED), or other system that relies on voltage levels, in which case there is a minimum critical voltage for reliable operation.

[0080] One way to reduce power consumption is to reduce the supply voltage. This reduces the voltage headroom between the minimum critical voltage (e.g., the voltage level at which a state changes) and the signal voltage (which depends on the supply voltage). If the power is reduced to a level where the signal voltage is just above the minimum critical voltage, any undershoot may cause the signal voltage to drop below the minimum critical voltage and thus generate errors in the case of digital systems and noise (such as LED flicker) in the case of electronic components.

[0081] Controlling the converter output voltage V during ramp-down SYS

[0082] Reference Figure 4 , shows a power converter 1 and a DAC 2, and a DAC logic 43 (referred to herein as a "delayed DAC arrangement" or "delayed DAC") that adjusts or controls a target voltage V TARGET The reduction in output voltage V SYS The undershoot.

[0083] DAC logic 43 is similar to Figure 1 , except that the DAC logic 43 includes a DAC update control block 51, which controls the reduction of the DAC code based on the update request signal. In some examples, a PWM signal can be used as the update request signal. In other examples, two or more signals (such as a PWM signal and an ABS signal in the case where an audio band suppression (ABS) is used, the ABS signal indicating that the power converter 1 is in the ABS state) can be used to generate the update request signal.

[0084] During ramp down, if a switching cycle has not occurred since the last step down, the DAC update control 51 delays (or "wait") the step down in the DAC code until a PWM switching cycle has occurred. This situation can help ensure that DAC 2 is not updated until the converter output voltage V SYS The target voltage V corresponding to the previous DAC code has been reached TARGET Therefore, control V C is kept within the correct operating range and therefore there is no settling time while the DAC reaches its final target.

[0085] DAC 2 and DAC control logic 45

[0086] Reference Figure 5 , showing the DAC 2 and DAC logic 43 in more detail.

[0087] DAC logic 43 includes: a first data latch 44 for receiving and storing a new DAC code (e.g., from a microcontroller); a DAC control logic 45; and a second data latch 46 for receiving and storing a DAC code 47 ("current DAC code") before the DAC code 47 is sent to DAC 2.

[0088] The DAC control logic 45 includes a DAC clock generator 50 that generates a DAC clock signal DAC CLK based on the clock signal CLK and a DAC update control 51 .

[0089] The DAC update control 51 includes a ramp-down detector 52 , a difference calculator 53 , a control logic 54 , a register 55 and optionally an update request signal generator 56 .

[0090] The ramp down detector 52 is arranged to identify the occurrence of a ramp down from the new DAC code and the current DAC.When a ramp down is identified, the DAC update control 51 enters a mode or state in which it controls (or "delays") step decreases in the DAC code 47 .

[0091] In response to a ramp down being detected, the difference calculator 53 is arranged to calculate an initial value of the difference Δ between the new DAC code and the current DAC code 47. As will be explained later, the DAC update control 51 decreases the difference Δ each time the DAC code 47 decreases. The difference Δ is used to indicate whether the DAC 2 is in correspondence with supplying the target voltage V corresponding to the new DAC code. TARGET How close is it? In this article, the target voltage V corresponding to the new DAC code TARGET The point at which the slope drops is called the "end of the ramp down".

[0092] The register 52 stores, among other things, a cycle number N. The cycle number N is programmable or can be hard-coded. The cycle number N is used to define the time at which the DAC control logic 45 starts controlling the target voltage V TARGET Point of ramp down (measured cycle number from the end of ramp down).

[0093] The DAC update control 51 may include an update request signal generator 56. The update request signal generator 56 includes an AND gate receiving two inputs of PWM and nABS and a NOT gate 57 for inverting ABS to generate an ABS bar (or "nABS").

[0094] Reference Figure 5 and 6, the operation of the DAC update control block 51 will now be described.

[0095] When a new DAC code is received, the DAC update control 51 determines the target voltage V TARGET Is it ramping down (step S1). If the new DAC code is the same or higher (corrected) than the current DAC code 47, it waits for the next new DAC code.

[0096] If a ramp down is identified, the DAC update control 51 calculates an initial value of the difference Δ between the new DAC code and the current DAC code 47 (step S2 ). This value Δ is stored in the register 55 .

[0097] The DAC update control 51 determines whether to start controlling the target voltage V by comparing the current value Δ with the number of cycles N. TARGET of reduction (step S3).

[0098] If the target voltage V TARGET To be controlled, the DAC update control 51 waits for the next PWM cycle to start indicated by the rising edge of the PWM or update request (step S4). Once the PWM cycle starts, the DAC update control 51 waits for the next DAC clock cycle indicated by the rising edge of the DAC CLK (step S5).

[0099] The DAC update control 51 then decreases the DAC code 47 stored in the latch 46 by the step size (in this case, 1) (step S6), and also decreases the value Δ by the same step size (step S7).

[0100] At step S3, if DAC update control 51 determines that the target voltage does not need to be controlled, it proceeds to step down the DAC code 47 stored in latch 46 and decrease the value Δ at the next available DAC clock cycle (steps S5, S6 and S7).

[0101] DAC update control 51 continues this process until the DAC output (ie, DAC code 47 stored in latch 46) is equal to the new DAC code (step S8).

[0102] Once this process is completed, the process starts from step S1 where the DAC update control 51 waits for the next new DAC code.

[0103] Reduce ramp-down time

[0104] As previously explained, still refer to Figure 4 , 5One way to minimize undershoot is often to delay the DAC update until the next PWM switching cycle. For example, this can be achieved by omitting step S3 or setting N to a larger number, such as for a 10-bit DAC 1024, preferably, N exceeds the number of DAC levels.

[0105] One disadvantage of this method is that the ramp-down time may be increased, especially in very light I LOAD under the circumstances.

[0106] An alternative approach is to delay the DAC update to the next PWM switching cycle for only the last N cycles, where N is chosen so that the undershoot remains within specification (i.e., does not exceed the specified value). Therefore, this scenario helps reduce undershoot while also limiting the increase in ramp-down time to a small amount.

[0107] This method allows the output voltage V SYS Ramp down at the fastest speed allowed by the load until the output voltage reaches the last N cycles. During these final delayed updates, the update clock rate DAC CLK can also be reduced (via control signal CNTL) to its slowest rate to further reduce undershoot.

[0108] The combined effect is to allow the control voltage V C The DAC 2 settles into the correct range before continuing to reach its final target level, thereby minimizing undershoot with only a slight increase in settling time (<10%) over the simple DAC arrangement under all load conditions.

[0109] Audio band suppression

[0110] Reference Fig. 7A , in discontinuous conduction mode (DCM), the switching period (1 / F SW ) to control the load current I LOAD , where F SW is the switching frequency.

[0111] Reference Figure 7B , although a 30,000Hz threshold can be used, when the switching frequency F SW As it decreases, the switching frequency may begin to approach and even enter the audio band frequency range, typically between 20 and 20,000 Hz. This situation may cause audio interference.

[0112] If it is equal to 1 / F AUDIO ABS can be achieved by introducing switching cycles during the period of . During an ABS switching cycle, no net energy is transferred to the output. If DAC 2 is stepped down during an ABS switching cycle, DAC 2 will output voltage VSYS The problem is that for light loads with ABS, V TARGET drops more than the output voltage V SYS fast, and therefore when the output voltage V SYS Close to V TARGET , control voltage V C may be clamped at its minimum level. The control voltage V C takes time to return to the operating range, and during this period, the output voltage V SYS It will rush down.

[0113] Reference Figure 8 , the power converter 1 , DAC 2 and DAC logic 43 are shown again.

[0114] The update request is not only based on PWM, but also on ABS. During the ABS cycle, ie, when ABS is HIGH, the stepping down of the DAC code 47 is prohibited.

[0115] Also refer to Figure 7C , the power converter 1 can signal when the ABS is not being used (eg, ABS=0; LOW) and when it is being used (eg, ABS=1; HIGH).

[0116] simulation

[0117] The output voltage V is plotted using Cadence Virtuoso (RTM) for a buck-boost converter using a simple DAC and delayed DAC arrangement under various load conditions. SYS , control voltage VC and inductor current IL are simulated.

[0118] In some cases, the gate voltage Gate Q2 is also simulated, where the gate voltage Gate Q2 is an externally available gate drive signal used to monitor the PWM switching cycle. However, it should be noted that the inductor terminal voltages LX1, LX2 will also provide the same information.

[0119] The simulation settings are as follows: (1) the buck-boost regulator is configured for boost mode operation; (2) the DAC ramp-down rate is set faster than the load current allows, except for high load currents; and (3) load current = light, medium, and high current loads. In this case, very light loads are defined as approximately 1 mA, light loads are defined as approximately 10 mA, medium loads are defined as approximately 200 mA, and high loads are defined as approximately >500 mA. However, these definitions can change depending on the application.

[0120] The simulations compared a simple DAC arrangement and a delayed DAC arrangement in which only the last 10 PWM cycles were delayed (unless otherwise stated).The undershoot region is shown in more detail to the right of each graph.

[0121] The simulation is performed for two values ​​of the comparator input voltage, namely, V IN =5.4V and V IN =13.5.

[0122] Fig. 9 The diagram shows the first light load condition. Figure 4 The DAC output voltage and target voltage as well as the compensated output voltage and inductor current simulated by the power converter and DAC shown in .

[0123] Fig.10 The figure shows the second medium load condition. Figure 1 The power converter and DAC shown in FIG. 4 simulate the DAC output voltage and target voltage as well as the compensated output voltage and inductor current.

[0124] Fig.11 The figure shows the second medium load condition. Figure 4 The DAC output voltage and target voltage as well as the compensated output voltage and inductor current simulated by the power converter and DAC shown in .

[0125] Fig.12 The figure shows the third highest load condition. Figure 1 The DAC output voltage and target voltage as well as the compensated output voltage and inductor current simulated by the power converter and DAC shown in .

[0126] Fig.13 The figure shows the third highest load condition. Figure 4 The DAC output voltage and target voltage as well as the compensated output voltage and inductor current simulated by the power converter and DAC shown in .

[0127] Fig.14 A illustrates the first light load condition. Figure 1 The DAC output voltage and target voltage simulated by the power converter and DAC shown in FIG. , as well as the compensated output voltage and high-side FET gate voltage.

[0128] Fig.14 B to 14D respectively illustrate the first light load condition. Figure 4 The power converter and DAC shown in , the DAC output voltage and target voltage simulated for N exceeding the number of DAC levels (N=10 and N=20) and the compensated output voltage and high-side FET gate voltage.

[0129] Fig.15 A shows the light load condition for the fourth pole. Figure 1 The DAC output voltage and target voltage simulated by the power converter and DAC shown in FIG. , as well as the compensated output voltage and high-side FET gate voltage.

[0130] Fig.15 B to 15D respectively illustrate the fourth pole under light load conditions Figure 4 The power converter and DAC shown in , the DAC output voltage and target voltage simulated for N exceeding the number of DAC levels (N=10 and N=20) and the compensated output voltage and high-side FET gate voltage.

[0131] Fig.16 A and 16B are for Figure 1 The DAC shown in Figure 4 Figure 2. The DAC shown in Figure 2 shows simulated undershoot voltage versus current load for buck, boost, extreme boost, and buck-boost converters.

[0132] Fig.17A and 17B Respectively for Figure 1 The DAC shown in Figure 4 Table of simulated undershoot voltage versus current load for the buck, boost, extreme boost, and buck-boost converters for the DAC shown in FIG.

[0133] Fig.18 Illustration of the use Figure 1 For the DAC shown in FIG. 1 , the simulated DAC output voltage and load current are plotted versus time for an ABS cycle.

[0134] Fig.19 Illustration of the use Figure 8 For the DAC shown in FIG. 1 , the simulated DAC output voltage and load current are plotted versus time for an ABS cycle.

[0135] system

[0136] Reference Fig. 20 , a power management system 100 is shown.

[0137] The power management system 100 includes a switching regulator IC 101 having an off-chip inductor 8. The power management system 100 includes a power source 102 (eg, a battery) and a load 103 (eg, a digital system or lighting assembly(s).

[0138] Switching regulator IC 101 includes a power converter 1 (e.g., a buck-boost converter) and a digital core 105. Power converter 1 includes a power stage (not shown) that includes a power switch. In some cases, the power stage can be off-chip, that is, the switching regulator can include a control stage (not shown).

[0139] The digital core 105 includes a DAC control 43. The digital core 105 including the DAC control 43 may be controlled by a host 106, for example in the form of a microcontroller or a system on chip (SoC), via I2C and SMPI bus interfaces. The host 106 may also provide a clock signal CLK.

[0140] Revise

[0141] It will be appreciated that various modifications may be made to the embodiments described above. Such modifications may include equivalent and other features known in the design, manufacture and use of power management and its components, and equivalent and other features may be used instead of or in addition to the features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0142] Although a hardware-implemented method of controlling the DAC is described (using DAC logic implemented in hardware logic / circuitry), the method may be performed in software (eg, by an MCU / SoC).

[0143] Although the ramp-down is detected digitally, the ramp-down may be detected using analog detection (eg, using a differentiator).

[0144] The DAC resolution can be higher, such as up to 16 bits, or lower, such as down to 5 bits or even lower.

[0145] There is no need to use a hysteretic switching converter. The switching converter can be any form of switching converter that uses a DAC to set the output target and has a closed loop control system.

[0146] The inductor (which may take the form of a coil) does not have to be off-chip.

[0147] Although the claims have been expressed as specific combinations of features in this application, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein explicitly or implicitly, or any generalization thereof, whether or not it relates to the same invention as currently claimed in any claim and whether or not it alleviates any or all of the same technical problems as the present invention. The applicant hereby notifies that during the examination of this application or any other application derived therefrom, new claims may be expressed as such features and / or such combinations of features.

Claims

1. A DAC control logic (45) for controlling a DAC (2) to supply a target voltage V to a switching converter (1) TARGET , the DAC control logic includes logic for performing the following operations: decrementing a DAC input code during one or more steps in the DAC ramp down prior to a last number of one or more steps in the DAC ramp down; determining a condition including whether a difference Δ between a new value of the DAC input code and a current value of the DAC input code is less than or equal to a predetermined value N corresponding to the last number of steps; Upon a positive determination, waiting until at least one switching cycle has occurred before decrementing the DAC input code; upon a negative determination, decrementing the DAC input code from the current value to the new value regardless of whether the at least one switching cycle has occurred; decrementing the DAC input code during the last number of steps during the DAC ramp-down and by deferring to a next switching cycle; and reducing a clock rate corresponding to the DAC during the last number of steps during the DAC ramp-down, The ramp-down detector is configured to identify the DAC ramp-down by determining whether a new DAC input code is less than a current DAC input code, and the calculator is configured to calculate the difference Δ.

2. The DAC control logic (45) of claim 1, wherein the conditions further include whether the switching regulator (1) is applying audio band rejection that suppresses switching below a given frequency.

3. The DAC control logic (45) of claim 1 or 2, further comprising control logic (54), wherein the control logic (54) is configured to reduce the DAC clock rate based on the positive determination.

4. An electronic system comprising: DAC(2); as well as DAC logic (43) comprising the DAC control logic (45) of any one of claims 1 to 3, the DAC logic being arranged to supply the DAC input code (47) to the DAC.

5. A monolithic integrated circuit comprising the electronic system according to claim 4.

6. The monolithic integrated circuit of claim 5, further comprising: Switching converter (1); The DAC is configured to provide a target voltage to the switching converter.

7. A method for controlling a DAC (2) that supplies a target voltage V to a switching regulator (1) TARGET , the method comprising: decrementing a DAC input code (47) during one or more steps in the DAC ramp down prior to a last number of one or more steps in the DAC ramp down; identifying the DAC ramp down by determining whether a new DAC input code (4) is less than a current DAC input code (47); calculating a difference Δ between a new value of the DAC input code and a current value of the DAC input code; determining a condition, the condition comprising whether the difference Δ is less than or equal to a predetermined value N corresponding to the last number of steps; Upon a positive determination, waiting until at least one switching cycle has occurred before decrementing the DAC input code; upon a negative determination, decrementing the DAC input code from the current value to the new value regardless of whether the at least one switching cycle has occurred; decrementing the DAC input code during the last number of steps during the DAC ramp-down and by deferring to a next switching cycle; and During the final number of steps during the DAC ramp-down, a clock rate corresponding to the DAC is reduced.

8. The method of claim 7, wherein the conditions further comprise whether the switching regulator (1) is applying an audio band suppression which suppresses switching below a given frequency.

9. The method according to claim 7 or 8, further comprising: Based on the affirmative determination, the DAC clock rate is reduced.

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