Method of manufacturing a gate terminal of a hemt device and hemt device

Abstract

Embodiments of the present disclosure relate to methods of manufacturing a gate terminal of a HEMT device and a HEMT device. A method for manufacturing a HEMT device includes forming a dielectric layer on a heterostructure; forming a through-opening through the dielectric layer; and forming a gate electrode in the through-opening. Forming the gate electrode includes forming a sacrificial structure; depositing a first gate metal layer by evaporation; performing lift-off of the sacrificial structure; depositing a second gate metal layer by sputtering; and depositing a third gate metal layer. The second gate metal layer forms a barrier against diffusion of metal atoms from the second gate metal layer to the heterostructure.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a high electron mobility transistor (HEMT) device and the HEMT device itself. Background Technology

[0002] High electron mobility transistors (HEMTs) are known, and they are based on the formation of a high-mobility two-dimensional electron gas (2DEG) layer at a heterojunction (i.e., at the interface between semiconductor materials with different band gaps). For example, HEMT transistors based on a heterojunction between aluminum gallium nitride (AlGaN) and gallium nitride (GaN) layers are known.

[0003] HEMT transistors based on heterojunctions or AlGaN / GaN heterostructures offer several advantages, making them particularly suitable for and widely used in various applications. For example, the high breakdown threshold of HEMT transistors is used for high-performance power switching; the high electron mobility in the conductive channels allows for the formation of high-frequency amplifiers; and the high electron concentration in the 2DEG allows for low resistance (“on-state resistance” R) in the on-state. ON ).

[0004] Furthermore, GaN-based devices used in radio frequency (RF) applications typically have better RF performance than similar silicon LDMOS devices.

[0005] One of the key aspects of GaN-based HEMT devices, especially in RF applications, is related to gate current. This is the primary reason why current leakage can be detected at the drain electrode when the device is off. High leakage current can significantly degrade the device's RF performance. Summary of the Invention

[0006] The applicant has analyzed the different causes of leakage current in HEMT devices and identified three possible paths: (a) through the surface of the heterostructure, due to surface traps introduced during the surface passivation or cleaning steps of the heterostructure; (b) between the gate electrode and the source electrode, due to the lateral expansion of the gate electrode and the source electrode being close to each other; and (c) through the Schottky barrier, due to the decrease in barrier potential.

[0007] The applicant found that the aforementioned possible causes (a) and (b) played a negligible role in the generation of gate leakage current, while cause (c) was the primary cause.

[0008] One approach to address the barrier potential reduction was to use nickel (Ni) as the contact metal between the gate electrode and the AlGaN barrier layer of the heterostructure. Nickel is chosen due to its high work function. However, nickel has relatively high resistance, making it unsuitable for complete gate electrode formation. For this purpose, a layer of gold (Au) was used to cover the nickel and reduce its resistance. However, this approach is unsuitable for CMOS production lines due to contamination from the machinery used in CMOS processes caused by gold. A possible nickel alternative for forming the gate electrode is aluminum (Al), which can be utilized without gold coverage due to its good conductivity. However, aluminum has a lower work function and is not the optimal choice, as this solution does not allow for effective reduction of gate leakage current. Furthermore, aluminum diffuses within the heterostructure, creating conductive paths that favor leakage current in the off-state.

[0009] In various embodiments, this disclosure provides a method for manufacturing a HEMT device and a HEMT device thereof, which is adapted to overcome the disadvantages of the prior art.

[0010] According to this disclosure, a method for manufacturing a HEMT device and a HEMT device are provided.

[0011] In one or more embodiments, a method for manufacturing a HEMT device is provided, the method comprising: forming a dielectric layer on a heterostructure of a semiconductor body; forming a through-hole extending through the dielectric layer to a surface region of the heterostructure; and forming a gate electrode in the through-hole. Forming the gate electrode comprises: forming a sacrificial structure on the dielectric layer, the sacrificial layer extending laterally on the dielectric layer to the through-hole; depositing a first gate metal layer in the through-hole and onto the sacrificial structure by a vapor deposition process, the first gate metal layer being configured to form a Schottky contact with the heterostructure; removing the sacrificial structure and portions of the first gate metal layer on the sacrificial structure; depositing a second gate metal layer on and in direct contact with the first metal layer and the dielectric layer by a sputtering process; and depositing a third gate metal layer on the second gate metal layer, the third gate metal layer comprising aluminum. The second gate metal layer forms a barrier against the diffusion of aluminum atoms from the third metal layer into the heterostructure.

[0012] In one or more embodiments, a HEMT device is provided, comprising: a heterostructure, a dielectric layer on the heterostructure, and a gate electrode extending entirely through the dielectric layer. The gate electrode includes: a first gate metal layer configured to form a Schottky contact with the heterostructure; a second gate metal layer on the first gate metal layer; and a third gate metal layer on the second gate metal layer. The third gate metal layer comprises aluminum, and the second gate metal layer forms a barrier against the diffusion of aluminum atoms from the third metal layer into the heterostructure.

[0013] In one or more embodiments, a HEMT device is provided, comprising: a heterostructure, a dielectric layer on the heterostructure, and a gate electrode extending through the dielectric layer and contacting the heterostructure. The gate electrode includes a first gate metal layer covering the heterostructure and includes a protective layer between the heterostructure and the first gate metal layer. The protective layer is configured to prevent metal atoms from diffusing from the first metal layer into the heterostructure. Attached Figure Description

[0014] To better understand this disclosure, preferred embodiments of the disclosure will now be described by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0015] Figure 1 A side cross-sectional view shows a HEMT device according to an embodiment of the present disclosure;

[0016] Figure 2 The side view section is shown. Figure 1 Magnified details of the gate electrode of a HEMT device; and

[0017] Figures 3A to 3H The diagram shows... Figure 1 The manufacturing steps of HEMT devices. Detailed Implementation

[0018] Figure 1 A gallium nitride-based normally-on HEMT device 1 is illustrated in a triaxial system of orthogonal X, Y, and Z axes. HEMT device 1 is particularly suitable for use in RF applications, such as 4G and 5G base stations (including technological improvements and variations), mobile phones, RF cooking appliances, drying and heating equipment, aerospace equipment and systems, L-band and S-band radars, etc.

[0019] HEMT device 1 includes: a substrate 2, such as silicon or silicon carbide (SiC) or sapphire (Al2O3); a channel layer 4, intrinsic gallium nitride (GaN), extending over the substrate 2; and a barrier layer 6, intrinsic aluminum gallium nitride (AlGaN) or more generally a compound based on ternary or quaternary gallium nitride alloys (such as Al...). x Ga 1-x N, AlInGaN, In x Ga 1-x N, Al x In 1-x Al), extending above the channel layer 4; passivation layer or insulating layer 7, a dielectric material such as silicon nitride (Si3N4) or silicon oxide (SiO2), extending on the upper side 6a of the barrier layer 6; and gate region (or gate electrode) 8, extending into the semiconductor body 3 between the source region 10 and the drain region 12.

[0020] The channel layer 4 and the barrier layer 6 form a heterostructure 3. The heterostructure 3 thus extends between the lower side 4a of the channel layer 4 and the upper side 6a of the barrier layer 6, the lower side 4a being part of the interface with the underlying substrate 2.

[0021] The substrate 2, the channel layer 4, and the barrier layer 6 are collectively defined below using the term semiconductor body 5. Semiconductor body 5 houses the active region 3a, which in use houses the conductive channel of the HEMT device 1.

[0022] Through corresponding portions of insulating layer 7, gate region 8 is laterally separated from source region 10 and drain region 12 (i.e., along the X direction). Gate region 8 is recessed, meaning it extends relatively deep through insulating layer 7 until it reaches the upper side 6a of barrier layer 6. In other words, gate region 8 is formed in opening 9, which extends along Z through the entire thickness of insulating layer 7; alternatively, opening 9 extends through a portion of barrier layer 6 (e.g., to a depth of 1 nm–10 nm). Gate region 8 extends at active region 3a.

[0023] According to another embodiment (not shown), depending on need or design considerations, the semiconductor body 5 and the active region 3a contained therein may consist of only one or more layers of GaN or GaN alloy (appropriately doped or of intrinsic type).

[0024] The source region 10 and drain region 12 (e.g., conductive material of metal) extend deep into the semiconductor body 5, extending completely through the barrier layer 6 and terminating at the interface between the barrier layer 6 and the channel layer 4.

[0025] According to another embodiment not shown, the source region 10 and the drain region 12 also extend partially through the channel layer 4, without terminating in the channel layer 4.

[0026] According to another embodiment not shown, the source region 10 and the drain region 12 extend along Z to a portion of the thickness of the barrier layer 6 and terminate inside the barrier layer 6.

[0027] According to another embodiment not shown, the source region 10 and the drain region 12 extend only through the insulating layer 7 until they reach the surface 6a of the barrier layer 6, without sinking into the barrier layer 6.

[0028] According to one aspect of this disclosure, such as Figure 2 As shown, it represents Figure 1Enlarged details of gate region 8, which is formed by a stack comprising: a first metal layer 20 adapted to facilitate the formation of a Schottky contact with the heterostructure 3 (here, particularly with the barrier layer 6); a protective layer (or diffusion barrier layer) 22 adapted to prevent the diffusion of metal atoms into the heterostructure 3, extending entirely over the first metal layer 20; a second metal layer 24 adapted to form a gate contact with reduced resistivity, extending over the protective layer 22 and isolated from the semiconductor body 5 by the protective layer 22; and a cap layer 26 adapted to protect the second metal layer 24 from external agents (e.g., to prevent corrosion, oxidation, etc.).

[0029] If the protective layer 22 is adapted to facilitate the formation of Schottky contact with the heterostructure 3, the first metal layer can be omitted.

[0030] Furthermore, if the second metal layer 24 is made of a material that does not undergo degradation, or if degradation can be ignored, the cap layer 26 can be omitted.

[0031] More specifically, in embodiments of this disclosure, the first metal layer 20 is a nickel (Ni) layer in contact with the barrier layer 6; the protective layer 22 is a tungsten nitride (WN) layer extending over the Ni layer 20; the second metal layer 24 is an aluminum (Al) layer extending over the WN layer 22; and the cap layer 26 is a titanium nitride (TiN) layer extending over the Al layer 24.

[0032] For example, the Ni layer 20, which facilitates the formation of a Schottky contact with the underlying barrier layer 6, can be replaced by a Pt or Pd layer (typically a material difficult to etch). Exemplarily, the Ni layer 20 has a thickness selected between 30 nm and 200 nm. The Ni layer 20 can be omitted if tungsten nitride is used as the protective layer 22, as the latter is suitable for forming a good Schottky contact with the AlGaN of the barrier layer 6. In this case, the WN layer 22 is in direct contact with the barrier layer 6.

[0033] In the presence of Ni layer 20, WN layer 22 can be replaced by a different metal nitride layer with barrier properties, such as tantalum nitride (TaN) or titanium-titanium-titanium-oxynitride (TiTiONTi), to prevent the diffusion of metal atoms from the overlying metal layer 24. Exemplarily, WN layer 22 has a thickness selected between 20 nm and 100 nm.

[0034] The Al layer 24 improves the conductivity of the gate region 8, eliminating the conductivity reduction problem of the Ni layer 20. The Al layer 24 is completely separated or isolated from the heterostructure 3 by the WN layer 22. Therefore, the WN layer 22 forms a barrier against aluminum diffusion from the Al layer 24 into the heterostructure 3. Exemplarily, the Al layer 24 has a thickness selected between 400 nm and 800 nm. Exemplarily, the Al layer 24 can be replaced by another metal layer compatible with CMOS processes.

[0035] The TiN layer 26 serves as an additional protective layer, suitable for preventing aluminum degradation phenomena such as corrosion and oxidation. Exemplarily, the TiN layer 26 has a thickness selected between 10 nm and 50 nm. Exemplarily, the TiN layer 26 can be replaced by a material with similar properties and / or functions. Alternatively, the TiN layer 26 can be omitted, particularly when an organic material is used as an antireflective agent under the resist (however, for large geometries, this antireflective material can be omitted, where the lithography is unaffected by the substrate's reflectivity).

[0036] The following is for reference. Figures 3A to 3F describe Figure 1 The manufacturing steps of the gate region 8 of the HEMT device 1. Figures 3A-3F Limited by the fabrication of gate region 8, and not illustrated the (contextual, preceding and / or subsequent) steps for forming source and drain terminals, electrical contact metallization, general electrical connections, and any other elements known, useful or necessary for the operation of HEMT device 1.

[0037] According to one embodiment of this disclosure, Figure 3A exist Figure 1 In the same reference system, a portion of wafer 30 is shown in a side cross-sectional view during the fabrication steps of the HEMT device. Wafer 30 is compared with the previously referenced... Figure 1 Description and in Figure 1 Common elements shown are indicated using the same reference numerals and will not be described in detail again.

[0038] Specifically, refer to again Figure 3A The wafer 30 is arranged to include: a substrate 2, such as silicon (Si), silicon carbide (SiC), or aluminum oxide (Al2O3), having a front side 2a and a back side 2b opposite to each other in the Z direction; a gallium nitride (GaN) channel layer 4, having a lower side 4a that extends adjacent to and overlaps with the front side 2a of the substrate 2; and an aluminum gallium nitride (AlGaN) barrier layer 6 extending over the channel layer 4. As described above, the barrier layer 6 and the channel layer 4 form a heterostructure 3.

[0039] On the front side of the barrier layer 6, a passivation layer or dielectric layer 32 of a dielectric or insulating material (such as silicon nitride (SiN), silicon oxide (SiO2), or other materials) is formed. The insulating layer 32 has a thickness between 5 nm and 300 nm (e.g., equal to 100 nm) and is formed by means of deposition CVD or atomic layer deposition ALD, and will form at the end of the manufacturing step. Figure 1 Insulation layer 7.

[0040] Then, Figure 3B For example, by means of photolithography and etching steps, the insulating layer 32 is selectively removed so as to remove a selective portion of the insulating layer 32 in a region of the wafer 30 in which the gate region of the HEMT device is expected to be formed in a subsequent step (i.e., at a portion of the active region 3a).

[0041] According to a corresponding embodiment, the etching step may stop at the underlying barrier layer 6 or continue partially within the barrier layer 6. In both cases, the surface portion 6' of the underlying barrier layer 6 is exposed. The etching of the barrier layer 6 is carried out, for example, by means of dry etching. The removed portion of the barrier layer 6 creates a cavity along Z with a depth, for example, between 0 nm and 5 nm.

[0042] Therefore, an opening 9 is formed extending over the entire thickness of the insulating layer 32. The patterned insulating layer 32 thus corresponds to... Figure 1 Insulation layer 7.

[0043] Then, Figure 3C A stack 34 of sacrificial layers is formed on wafer 30. Specifically, the following is formed:

[0044] - The first sacrificial layer 34' is a non-photosensitive (or non-photodeterminable) organic polymer solution, specifically, commercially known as "PMGI" or "SF11" (which is a resist comprising a polydimethylglutarimide polymer); having a thickness between 0.6 μm and 1.3 μm (depending on the thickness of the subsequent metal to be deposited); and

[0045] - The second sacrificial layer 34” is a photosensitive or photodeterminable material (e.g., a photoresist) that extends over the first sacrificial layer 34’ and has a thickness between 0.6 μm and 4 μm.

[0046] Both the first and second sacrificial layers 34' and 34" can be formed using spin coating technology.

[0047] Stack 34 is on insulating layer 7 and extends inside opening 9.

[0048] Subsequently, Figure 3DThe second sacrificial layer 34” is patterned using photolithography and development steps to remove selective portions of the sacrificial layer 34” located at the opening 9, i.e., in the region of the wafer 30 where the gate 8 is to be formed. Since the first sacrificial layer 34” is not photosensitive, the photolithography step of the second sacrificial layer 34” has no effect on the first sacrificial layer 34”. At the end of development of the second sacrificial layer 34” (e.g., by means of TMAH), the first sacrificial layer 34” is partially exposed at the removed area of ​​the second sacrificial layer 34”. During this step, isotropic etching of the first sacrificial layer 34” also occurs to uniformly remove the exposed area of ​​the first sacrificial layer 34”. Because the etching is of the isotropic type, removal of the first sacrificial layer 34’ is also observed below the second sacrificial layer 34” (i.e., “under-etching” or “undercutting” phenomenon), extending towards the source and drain regions without reaching them. Figure 3D In the cross-sectional view, the undercut region 35 extends along the direction X.

[0049] The removal of the first sacrificial layer 34' continues until the barrier layer 6 is reached.

[0050] After this step, except for region 30a in which the gate region 8 is to be formed, the stack 34 remains on the wafer 30, covering the wafer 30.

[0051] Then, Figure 3E The step of forming the first metal layer 20 for the gate region 8 is performed.

[0052] Therefore, the following process steps are implemented.

[0053] After the wafer 30 is introduced into the deposition chamber, nickel target deposition is performed using any suitable type of evaporation, such as a evaporation process that uses an "electron gun" as the source. The evaporation process is performed for the time required or suitable for depositing a nickel layer of the desired thickness. As an example, the pressure in the evaporation chamber is maintained at approximately 10... -6 The value of mbar is set, and the deposition rate is between approximately 0.1 nm / s and 1 nm / s. This forms the first metal layer 20.

[0054] The first metal layer 20 extends partially into the opening 9, contacting the barrier layer 6 and above the second sacrificial layer 34”. The applicant has found that the type of deposition method (evaporation) chosen for the first metal layer 20, together with the construction of the stack 34 of the sacrificial layers, allows for the avoidance of deposition of the first metal layer 20 along the vertical wall of the first sacrificial layer 34” (i.e., extending along the Z). In other words, in a plan view, the metal layer 20 has an extension substantially defined by the opening through the second sacrificial layer 34”. It is evident that during deposition, even though the metal layer 20 has a defined extension of the first sacrificial layer 34’, a portion of the nickel typically also extends outside the opening 9. In practice, given current techniques and processes, the vapor-deposited metal material is typically also deposited laterally over the opening 9 above the insulating layer, primarily due to the fact that the opening 34” is typically slightly larger than the opening 9 (in this case, the metal does not completely cover region 9 due to possible mask misalignment and is also used to form the field plate).

[0055] Then, Figure 3F The first and second sacrificial layers 34', 34'' are removed by means of any suitable type of stripping process, and the portion of the first metal layer 20 extending above the second sacrificial layer 34'' (i.e., outside the region 30a of the wafer 30 in which the gate region 8 is to be formed) is also removed along with them.

[0056] The presence of the undercut region 35 is advantageous during this stripping step because the absence of a nickel layer along the vertical wall of the first sacrificial layer 34' does not impair the stripping process.

[0057] Next, Figure 3G The step of forming the protective layer 22 of WN is then performed. For this purpose, the sputtering process is carried out in any suitable manner.

[0058] The applicant has discovered that the WN layer deposited by sputtering meets the barrier layer requirements, or is suitable for resisting the diffusion of atoms from the aluminum metal layer 24.

[0059] Then, the Al layer 24 and the TiN layer 26 are formed by any suitable means or method, such as sputtering.

[0060] refer to Figure 3H By means of a masking etching step, using a mask 38 such as a photoresist, a portion of the WN and Al metal layers thus formed is removed, extending beyond the area where the gate 8 is to be formed. Etching is performed using a dry process utilizing chlorine (Cl2), boron trichloride (BCl3), and argon (Ar)-based chemicals (typically used for metal etching) to remove the Al layer 24 and the WN layer 22.

[0061] It should be noted that, considering the high selectivity of the etching used to remove aluminum and tungsten nitride relative to nickel, the first metal layer 20 will not be... Figure 3H Etching damage or over-etching. Obviously, this advantage can also be achieved by using other materials besides nickel but with the same selective properties as etching (e.g., Pt or Pd).

[0062] Then remove mask 38 to form Figure 2 Device 1, the device is provided with Figure 2 The gate region 8 is shown in detail in the diagram.

[0063] From the above description, the advantages of this disclosure are clear.

[0064] Specifically, for RF applications, a method for fabricating GaN-based HEMT devices is proposed that is compatible with CMOS production lines and does not have the gate leakage current-related drawbacks observed in known types of devices.

[0065] Finally, it is clear that modifications and changes may be made to the description and illustrations herein without departing from the scope of this disclosure as defined in the appended claims.

[0066] For example, there may be a stack of overlapping layers extending between the substrate 2 and the heterostructure 3, such as a buffer layer and a hole supply layer.

[0067] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents to these claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A method for manufacturing a high electron mobility transistor (HEMT) device, comprising: forming a dielectric layer on a heterostructure of a semiconductor body; forming a through-opening extending through the dielectric layer to a surface layer region of the heterostructure; and forming a gate electrode in the through-opening, the forming of the gate electrode comprising: forming a sacrificial structure on the dielectric layer, the sacrificial structure laterally extending on the dielectric layer to the through-opening; depositing, by an evaporation process, a first gate metal layer in the through-opening and onto the sacrificial structure, the first gate metal layer being configured to form a Schottky contact with the heterostructure; performing a lift-off step comprising removing a portion of the first gate metal layer on the sacrificial structure and the sacrificial structure; depositing, by a sputtering process, a second gate metal layer on and in direct contact with the first gate metal layer and the dielectric layer, the second gate metal layer consisting of tungsten nitride; and depositing a third gate metal layer on the second gate metal layer, the third gate metal layer comprising aluminum, the second gate metal layer forming a barrier against diffusion of aluminum atoms from the third gate metal layer towards the heterostructure, wherein the dielectric layer comprises silicon nitride, wherein the forming of the sacrificial structure comprises: forming a first sacrificial layer of a non-photodefinable material on the dielectric layer; forming a second sacrificial layer of a photodefinable material on the first sacrificial layer; performing a lithography process to remove a selective portion of the second sacrificial layer corresponding at least partially to the through-opening until reaching the first sacrificial layer; and forming an undercut region under the second sacrificial layer by isotropically etching the first sacrificial layer, wherein the depositing of the second gate metal layer comprises depositing tungsten nitride in direct contact with the dielectric layer and with the first gate metal layer, wherein the depositing of the third gate metal layer comprises performing a sputtering process of aluminum in direct contact with the second gate metal layer, wherein the method further comprises: removing, during a respective masked etching step, a selective portion of the second gate metal layer and of the third gate metal layer laterally extending to the through-opening; and forming a three-layer stack comprising the first gate metal layer, the second gate metal layer and the third gate metal layer overlapping and aligned with each other at the through-opening. completely covering a bottom of the through-opening.

2. The method of claim 1, wherein depositing the first gate metal layer comprises: forming a cap layer on the first gate metal layer, the cap layer being configured to protect the first gate metal layer from environmental agents.

3. The method of claim 1 or 2, wherein forming the gate electrode further comprises:

4. The method according to claim 3, wherein the cap layer comprises titanium nitride.

5. A high electron mobility transistor (HEMT) device, comprising: a heterostructure; a dielectric layer comprising silicon nitride on the heterostructure; and a gate electrode extending completely through the dielectric layer, the gate electrode comprising: a first gate metal layer configured to form a Schottky contact with the heterostructure; ​ ​ a second gate metal layer on the first gate metal layer, the second gate metal layer consisting of a metal nitride layer comprising tungsten nitride; and a third gate metal layer on the second gate metal layer, the third gate metal layer comprising aluminum, wherein the second gate metal layer forms a barrier against diffusion of aluminum atoms from the third gate metal layer towards the heterostructure, wherein the gate electrode further comprises a three-layer stack comprising the first gate metal layer, the second gate metal layer and third gate metal layer overlapping and aligned with each other at a through-opening in the dielectric layer.

6. The HEMT device of claim 5, wherein the gate electrode further comprises a cap layer on the first gate metal layer and configured to protect the first gate metal layer from environmental agents.

7. The HEMT device of claim 6, wherein the cap layer comprises titanium nitride.

8. The HEMT device of claim 5, wherein the heterostructure comprises a channel layer and a barrier layer on the channel layer, the channel layer and the barrier layer comprising respective compound materials comprising group III-V elements.

9. The HEMT device of claim 5, further comprising: a source electrode extending into the heterostructure, the source electrode terminating in the heterostructure; and a drain electrode extending into the heterostructure at a distance from the source electrode, the drain electrode terminating in the heterostructure, wherein the gate electrode is in direct electrical contact with the heterostructure.

10. A device, comprising: a heterostructure; a dielectric layer comprising silicon nitride on the heterostructure; a gate electrode extending through the dielectric layer and contacting the heterostructure, the gate electrode comprising: a first gate metal layer covering the heterostructure; and a protective layer between the heterostructure and the first gate metal layer, the protective layer configured to block diffusion of metal atoms from the first gate metal layer towards the heterostructure; a source electrode or a drain electrode extending into the heterostructure to a greater depth than the gate electrode, a second gate metal layer consisting of a metal nitride layer comprising tungsten nitride, in direct contact with the heterostructure, wherein the gate electrode further comprises a three-layer stack comprising the first gate metal layer, the second gate metal layer and third gate metal layer overlapping and aligned with each other at a through-opening in the dielectric layer.

11. The device of claim 10, wherein the protective layer is configured to form a Schottky contact with the heterostructure.

12. The device of claim 10, wherein the second gate metal layer extends between the heterostructure and the protective layer.

13. The device of claim 12, wherein the first gate metal layer comprises aluminum, the second gate metal layer comprises nickel, and the protective layer comprises tungsten nitride. ​

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