Semiconductor chip and semiconductor package including the semiconductor chip

Abstract

The disclosed embodiments include a semiconductor chip and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate and a protective insulating layer, the semiconductor substrate having a top surface, a top connection pad disposed in the top surface, an opening included in the protective insulating layer, and the protective insulating layer does not cover at least a portion of the top connection pad on the semiconductor substrate. The protective insulating layer may include: a bottom protective insulating layer; a covering insulating layer including a side covering portion covering at least a portion of a side surface of the bottom protective insulating layer and a top covering portion disposed separately from the side covering portion to cover at least a portion of a top surface of the bottom protective insulating layer. The protective insulating layer may also include a top protective insulating layer located on the top covering portion.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0136943 filed on October 30, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The disclosed inventive concept relates to a semiconductor chip and a semiconductor package including the semiconductor chip, and more particularly, to a semiconductor chip including a connection pad (also referred to as a “bonding pad”) and a semiconductor package including the semiconductor chip. Background Art

[0003] In order to meet the demand for miniaturized, multifunctional and high-performance electronic products, semiconductor packages are required to be thin and lightweight and have high speed and high performance. Therefore, the demand for semiconductor chips for realizing systems with high memory bandwidth and semiconductor packages including semiconductor chips is increasing. Since the memory bandwidth is proportional to the data transmission speed and the number of data transmission lines, the memory bandwidth can be increased by increasing the memory operating speed or the number of data transmission lines. Therefore, the number and density of connection bumps attached to the connection pads of the semiconductor chip are increasing. Summary of the invention

[0004] The inventive concept provides a semiconductor chip including a connection pad for enhancing attachment reliability on a connection bump and a semiconductor package including the semiconductor chip.

[0005] The inventive concept provides a semiconductor chip and a semiconductor package including the semiconductor chip as described below.

[0006] According to one aspect of the inventive concept, a semiconductor chip is provided, the semiconductor chip comprising: a semiconductor substrate having a top surface, a top connection pad being arranged in the top surface; and a protective insulating layer, the protective insulating layer comprising an opening, the protective insulating layer not covering at least a portion of the top connection pad on the semiconductor substrate. The protective insulating layer may include: a bottom protective insulating layer; a covering insulating layer, including a side covering portion covering at least a portion of a side surface of the bottom protective insulating layer and a top covering portion provided separately from the side covering portion to cover at least a portion of a top surface of the bottom protective insulating layer. The protective insulating layer may also include a top protective insulating layer located on the top covering portion.

[0007] According to another aspect of the inventive concept, a semiconductor package is provided, the semiconductor package comprising a first semiconductor chip, the first semiconductor chip having: a first top connection pad and a first bottom connection pad, respectively disposed on the top surface and the bottom surface of a first semiconductor substrate; a first protective insulating layer, the first protective insulating layer including a first opening, the first protective insulating layer not covering at least a portion of the first top connection pad on the first semiconductor substrate. The first semiconductor chip may also include a first through electrode electrically connecting the first top connection pad to the first bottom connection pad, and the semiconductor package may also include at least one second semiconductor chip. The second semiconductor chip may include: a second top connection pad, disposed on the top surface of the second semiconductor substrate; a second protective insulating layer, the second protective insulating layer including a second opening, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate; and an internal connection terminal, disposed on the second top connection pad and electrically connecting the first semiconductor chip to the at least one second semiconductor chip through the first bottom connection pad of the first semiconductor chip, the internal connection terminal contacting the side surface of the second protective insulating layer in the second opening. In some embodiments, the at least one second semiconductor chip is stacked on the bottom surface of the first semiconductor chip. In addition, in some embodiments, the first protective insulating layer may include: a bottom protective insulating layer; a covering insulating layer, including a side covering portion covering at least a portion of a side surface of the bottom protective insulating layer and a top covering portion separately provided from the side covering portion to cover at least a portion of a top surface of the bottom protective insulating layer; and a top protective insulating layer located on the top covering portion.

[0008] According to another aspect of the inventive concept, a semiconductor package is provided, the semiconductor package comprising a first semiconductor chip, the first semiconductor chip having a first top connection pad and a first bottom connection pad respectively arranged on the top surface and the bottom surface of a first semiconductor substrate. The first semiconductor chip may include: a first barrier layer, covering a portion of the top surface of the first top connection pad; a first protective insulating layer, the first protective insulating layer having a first opening, the first protective insulating layer not covering at least a portion of the first top connection pad on the first semiconductor substrate. The first semiconductor chip may also include a first through electrode electrically connecting the first top connection pad to the first bottom connection pad, and the semiconductor package may also include a plurality of second semiconductor chips. The second semiconductor chip may include: a second top connection pad and a second bottom connection pad, respectively arranged on the top surface and the bottom surface of the second semiconductor substrate; a second protective insulating layer, the second protective insulating layer including a second opening, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate, and the plurality of second semiconductor chips are stacked on the bottom surface of the first semiconductor chip. The second semiconductor chip may also include an internal connection terminal, the internal connection terminal electrically connecting the second top connection pad to the first bottom connection pad, or electrically connecting the second top connection pad and the second bottom connection pad of different second semiconductor chips in the plurality of second semiconductor chips. In some embodiments, the first protective insulating layer includes: a bottom protective insulating layer including a protrusion and a step, the step defining an upper portion of the protrusion adjacent to the opening. The first protective insulating layer may also include: a covering insulating layer having a side covering portion covering at least a portion of a side surface of the bottom protective insulating layer and a top covering portion provided separately from the side covering portion to cover at least a portion of a top surface of the bottom protective insulating layer; and a top protective insulating layer located on the top covering portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1A is a cross-sectional view showing a semiconductor chip according to an embodiment of the disclosure, Figure 1B is a cross-sectional view showing a top connection pad of a semiconductor chip according to a disclosed embodiment;

[0011] FIG. 2A to FIG. 2D are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor chip including a top connection pad according to a disclosed embodiment;

[0012] Figure 3 is a cross-sectional view showing a semiconductor package according to a disclosed embodiment;

[0013] FIG. 4A to FIG. 4Dis a cross-sectional view showing a connection pad of a semiconductor package according to a disclosed embodiment;

[0014] Figure 5 is a cross-sectional view showing a system including a semiconductor package according to a disclosed embodiment, Fig. 6A and Figure 6B is an enlarged cross-sectional view showing a first top connection pad and a second top connection pad each included in a semiconductor package of a system according to a disclosed embodiment;

[0015] FIG. 7A to FIG. 7D is an enlarged cross-sectional view showing a first top connection pad in a semiconductor package included in a system according to a disclosed embodiment; and

[0016] FIG. 8A to FIG. 8D is an enlarged cross-sectional view illustrating a second top connection pad in a semiconductor package included in a system according to a disclosed embodiment. DETAILED DESCRIPTION

[0017] Figure 1A is a cross-sectional view showing a semiconductor chip 100 according to an embodiment of the disclosure, Figure 1B is a cross-sectional view showing the top connection pads of the semiconductor chip 100 according to the disclosed embodiment. In detail, Figure 1B It is shown Figure 1A A cross-sectional view of an enlarged area B.

[0018] Reference Figure 1A and Figure 1B The semiconductor chip 100 may include a semiconductor substrate 110 and a top connection pad 122 disposed on an active surface, which is a top surface of the semiconductor substrate 110 .

[0019] The semiconductor substrate 110 may include a base substrate, and various conductive layers and insulating layers are formed and patterned on the base substrate. The base substrate may be cut from a portion of a wafer and may be, for example, a crystalline semiconductor material, such as silicon (Si). Alternatively, the base substrate of the semiconductor substrate 110 may be formed of another crystalline semiconductor material such as germanium (Ge), and / or may include a compound crystalline semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide (InP). The semiconductor substrate 110 may include an effective surface and an ineffective surface opposite to the effective surface, for example, the bottom surface of the semiconductor substrate 110. For example, the base substrate of the semiconductor substrate 110 may include one or more conductive regions (e.g., impurity-doped wells) and various isolation structures such as shallow trench isolation (STI) structures for separating / isolating the various conductive regions from each other.

[0020] In the specification, the top surface and the bottom surface of the semiconductor substrate may represent the effective surface and the ineffective surface of the semiconductor substrate, respectively. That is, even when the effective surface of the semiconductor substrate is disposed under the ineffective surface in the final product (i.e., the effective surface is oriented to face downward in the real world), the effective surface of the semiconductor substrate is considered to be the top surface of the semiconductor substrate, and the ineffective surface of the semiconductor substrate is also considered to be the bottom surface of the semiconductor substrate. In addition, the terms "top surface" and "bottom surface" may be applied to an element disposed on the effective surface and an element disposed on the ineffective surface, respectively.

[0021] The semiconductor device 112 may be formed on and within the active surface of the semiconductor substrate 110, and the semiconductor device 112 may be formed as an integrated circuit and as a combination of a plurality of individual electronic components (such as transistors, logic gates, etc.). The semiconductor device 112 may be referred to as a first semiconductor device. The plurality of individual electronic components may include various microelectronic devices (e.g., metal-oxide-semiconductor field effect transistors such as complementary metal-insulator-semiconductor (CMOS) transistors, image sensors such as system large-scale integration (LSI) and CMOS imaging sensors (CIS), micro-electromechanical systems (MEMS), active devices, and passive devices). The plurality of individual electronic components may be electrically connected to and / or formed together with portions of the conductive regions of the semiconductor substrate 110. The semiconductor device 112 may be formed as a combination of a plurality of individual electronic components connected together using conductive wiring (the conductive wiring may include (a plurality of) conductive plugs). In addition, each electronic component may be electrically isolated from other individual electronic components adjacent thereto by an insulating layer.

[0022] The semiconductor chip 100 may be, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable and programmable read-only memory (EEPROM) chip, a phase change random access memory (PRAM) chip, a magnetic random access memory (MRAM) chip, or a resistive random access memory (RRAM) chip. The semiconductor chip 100 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0023] In some embodiments, the semiconductor chip 100 may be a high bandwidth memory (HBM) DRAM semiconductor chip. In some embodiments, the semiconductor chip 100 may be a buffer chip including a serial-parallel conversion circuit. In some embodiments, the semiconductor chip 100 may be a buffer chip for controlling an HBM DRAM semiconductor chip. When the semiconductor chip 100 is a buffer chip for controlling an HBM DRAM semiconductor chip, the semiconductor chip 100 may be referred to as a master chip, and the HBM DRAM semiconductor chip may be referred to as a slave chip. Alternatively, the semiconductor chip 100 may be referred to as a first semiconductor chip.

[0024] exist Figure 1A and Figure 1B In the embodiment, the top connection pad 122 is shown as being buried in the semiconductor substrate 110, but is not limited thereto. In some embodiments, the top connection pad 122 may protrude from the top surface of the semiconductor substrate 110.

[0025] In the specification, the semiconductor substrate 110 may include a base substrate formed of a crystalline semiconductor material (e.g., bulk Si, silicon on insulator, etc.) and various conductive material layers and insulating material layers formed on the base substrate for forming the semiconductor device 112. That is, the semiconductor substrate 110 may only mean that its main component includes a semiconductor material (such as including a base semiconductor substrate as described herein) without requiring that the semiconductor substrate 110 is formed only of a semiconductor material.

[0026] A protective insulating layer 150 exposing the top connection pad 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150 may include a bottom protective insulating layer 152, a cover insulating layer 154, and a top protective insulating layer 156. For ease of illustration and convenience of description, the cover insulating layer 154 is not shown. Figure 1A In the Figure 1B Detailed description is shown in FIG. For example, the bottom protective insulating layer 152 may include an inorganic material such as an oxide or a nitride. For example, the bottom protective insulating layer 152 may include at least one of silicon oxide and silicon nitride. In some embodiments, the bottom protective insulating layer 152 may include silicon nitride. For example, the capping insulating layer 154 may include silicon nitride. For example, the top protective insulating layer 156 may be a photosensitive polyimide (PSPI) and / or include a photosensitive polyimide (PSPI). The protective insulating layer 150 may be referred to as a first protective insulating layer.

[0027] The semiconductor chip 100 may include a through electrode 130 disposed on an inactive surface, the through electrode 130 electrically connecting the top connection pad 122 to the bottom connection pad 124 and passing through at least a portion of the semiconductor substrate 110 between the top surface and the bottom surface of the semiconductor substrate 110, and the inactive surface may be the bottom surface of the semiconductor substrate 110. The through electrode 130 may be referred to as a first through electrode. The top connection pad 122 may be referred to as a first top connection pad. The bottom connection pad 124 may be referred to as a first bottom connection pad.

[0028] The through electrode 130 may include a conductive plug passing through the semiconductor substrate 110 and a conductive barrier layer surrounding the conductive plug. The conductive plug may have a circular column shape, and the conductive barrier layer may have a cylindrical shape surrounding the sidewall of the conductive plug. A via insulating layer may be disposed between the semiconductor substrate 110 and the through electrode 130 and may surround the sidewall of the through electrode 130.

[0029] exist Figure 1A , the through-electrode 130 is shown to directly connect the top connection pad 122 to the bottom connection pad 124, but is not limited thereto, and the through-electrode 130 may be formed to have one of a via-first structure, a via-middle structure, and a via-last structure.

[0030] In some embodiments, the barrier layer 123 may be formed at a portion of the top connection pad 122. The barrier layer 123 may be disposed between the top connection pad 122 and the bottom protective insulating layer 152. The barrier layer 123 may include, for example, at least one material selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), but is not limited thereto. Figure 1B , it is shown that the top connection pad 122 is buried in the semiconductor substrate 110 and the barrier layer 123 protrudes from the top surface of the semiconductor substrate 110, but exemplary embodiments are not limited thereto. In some embodiments, the top connection pad 122 and the barrier layer 123 may both be buried in the semiconductor substrate 110. In some other embodiments, the top connection pad 122 and the barrier layer 123 may protrude from the top surface of the semiconductor substrate 110. The barrier layer 123 may be referred to as a first barrier layer. In some embodiments, the barrier layer 123 may be omitted.

[0031] The protective insulating layer 150 may include a bottom protective insulating layer 152, a capping insulating layer 154, and a top protective insulating layer 156. The bottom protective insulating layer 152 may include an opening OP1 that exposes at least a portion of the top connection pad 122. In some embodiments, the sidewall of the opening OP1 may extend in a vertical (perpendicular) direction relative to the main surface of the semiconductor substrate 110. For example, the sidewall of the opening OP1 may extend in a vertical direction (vertically) relative to the upper surface of the substrate 110. The bottom protective insulating layer 152 may include a step ST, which is disposed at a portion of the bottom protective insulating layer 152 adjacent to the opening OP1 and includes a relatively low top surface. The portion of the bottom protective insulating layer 152 having a level higher than the level of the relatively low top surface of the bottom protective insulating layer 152 (i.e., the bottom surface of the step ST) may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152 may refer to the bottom surface of the step ST and the top surface of the protrusion PRT, respectively. That is, the step ST may be disposed at the upper portion of the opening OP1 to limit the protrusion PRT. The top protective insulating layer 156 may be disposed on the protrusion PRT. For example, in the step ST region, the bottom protective insulating layer 152 may have a top surface that is relatively lower in elevation / height than the top surface of the bottom protective insulating layer 152 in the protrusion PRT region. Similarly, in the step ST region, the bottom protective insulating layer 152 may have a bottom surface that is relatively higher in elevation / height than the bottom surface of the bottom protective insulating layer 152 in the protrusion PRT region.

[0032] In some embodiments, when the semiconductor chip 100 includes the barrier layer 123, the opening OP1 may pass through the bottom protective insulating layer 152 and the barrier layer 123 to expose a portion of the top surface of the top connection pad 122. The opening OP1 may be referred to as a first opening. At least a portion of the barrier layer 123 may be disposed between the top connection pad 122 and the bottom protective insulating layer 152.

[0033] The capping insulating layer 154 may cover a portion of the bottom protective insulating layer 152. In some embodiments, the capping insulating layer 154 may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152. The capping insulating layer 154 may include a side capping portion 154S covering a portion of the side surface of the bottom protective insulating layer 152 and a top capping portion 154T covering a portion of the top surface of the bottom protective insulating layer 152 (i.e., the top surface of the protrusion PRT).

[0034] The side covering portion 154S may cover at least a portion of the side surface of the barrier layer 123 and at least a portion of the side surface of the bottom protective insulating layer 152 in the opening OP1. In some embodiments, the side covering portion 154S may cover a portion of the side surface of the barrier layer 123 and a portion of the side surface of the bottom protective insulating layer 152 in the opening OP1 (i.e., between the step ST and the top surface of the top connection pad 122). In some embodiments, the bottom surface of the side covering portion 154S may contact a portion of the top surface of the top connection pad 122. The uppermost end of the side covering portion 154S may be disposed at the same level (elevation / height) as the bottom surface of the step ST or may be disposed at a level lower than the bottom surface of the step ST.

[0035] The top covering portion 154T may be disposed between the bottom protective insulating layer 152 and the top protective insulating layer 156. The top covering portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152 and the bottom surface of the top protective insulating layer 156. The top covering portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152 (e.g., the top surface of the protrusion PRT of the bottom protective insulating layer 152 (i.e., a relatively high top surface)). In addition, the top covering portion 154T may not cover the top surface of the bottom protective insulating layer 152 in the step ST region. The top covering portion 154T may cover the entire bottom surface of the top protective insulating layer 156. As will be described below with reference to FIG. 2A to FIG. 2D As described, the cover insulating layer 154 may be first formed to cover all of the top surface and side surfaces of the bottom protective insulating layer 152 and a portion of the top surface of the top connection pad 122 exposed by the bottom surface of the opening OP1, and then may be formed by removing a portion of the cover insulating layer 154 covering at least a portion of the top surface of the top connection pad 122 and a portion of the cover insulating layer 154 covering a portion of the top surface of the bottom protective insulating layer 152. In the process of removing the portion of the cover insulating layer 154 covering a portion of the top surface of the bottom protective insulating layer 152, a portion of the upper portion of the bottom protective insulating layer 152 may also be removed together, and thus, the step ST and the protrusion PRT may be formed at the bottom protective insulating layer 152. Therefore, the cover insulating layer 154 may not cover the surface of the bottom protective insulating layer 152 in the region corresponding to the step ST.

[0036] FIG. 2A to FIG. 2D 1 is a cross-sectional view sequentially illustrating a method of manufacturing a semiconductor chip including a top connection pad according to an exemplary embodiment of the disclosure. In detail, FIG. 2A to FIG. 2D is shown with Figure 1A Region B is a cross-sectional view of an enlarged region corresponding to the region.

[0037] Reference Figure 2A, a top connection pad 122 may be formed in the top surface of the semiconductor substrate 110. The top connection pad 122 may include a conductive material. In some embodiments, the top connection pad 122 may include aluminum (Al). A barrier layer 123 may be formed on the top connection pad 122. The barrier layer 123 may include, for example, at least one material selected from Ti, TiN, Ta, and TaN. In some embodiments, the barrier layer 123 may include TiN. In some other embodiments, the barrier layer 123 may be omitted.

[0038] The through electrode 130 may be formed in the semiconductor substrate 110, and the through electrode 130 may be electrically connected to the top connection pad 122. The through electrode 130 may contact the bottom surface of the top connection pad 122, but is not limited thereto. In some embodiments, a wiring pattern and a wiring via may be provided between the through electrode 130 and the top connection pad 122, and the wiring pattern and the wiring via may electrically connect the through electrode 130 to the top connection pad 122.

[0039] A bottom protective insulating layer 152 may be formed on the semiconductor substrate 110 and the top connection pad 122. The bottom protective insulating layer 152 may be formed, for example, by a plasma enhanced chemical vapor deposition (PECVD) process. The bottom protective insulating layer 152 may cover the semiconductor substrate 110 and the top connection pad 122. In an embodiment where the barrier layer 123 is formed on the top connection pad 122, the bottom protective insulating layer 152 may cover the semiconductor substrate 110 and the barrier layer 123. For example, the bottom protective insulating layer 152 may include an inorganic material such as an oxide or a nitride. In some embodiments, the bottom protective insulating layer 152 may include silicon nitride.

[0040] Reference Figure 2B , an opening OP1 exposing at least a portion of the top connection pad 122 may be formed by removing a portion of the bottom protection insulating layer 152 above the top connection pad 122. In the case where the barrier layer 123 is formed on the top connection pad 122, the opening OP1 may pass through the bottom protection insulating layer 152 and the barrier layer 123, and thus, a portion of the top surface of the top connection pad 122 may be exposed at the bottom surface of the opening OP1. In some embodiments, the opening OP1 may be formed such that a sidewall of the opening OP1 extends in a vertical direction relative to the main surface of the semiconductor substrate 110. For example, the opening OP1 may be formed by removing a portion of the bottom protection insulating layer 152 or removing a portion of each of the bottom protection insulating layer 152 and the barrier layer 123 based on a high density plasma (HDP) etching process.

[0041] Reference Figure 2C, a capping insulating layer 154 may be formed on the resulting material formed with the opening OP1. The capping insulating layer 154 may be formed to conformally cover the sidewall and bottom surface of the opening OP1, i.e., a portion of the side surface of each of the bottom protective insulating layer 152 and the barrier layer 123, a portion of the top surface of the top connection pad 122, and the top surface of the bottom protective insulating layer 152, with a substantially certain thickness. The capping insulating layer 154 may include the same material as that of the bottom protective insulating layer 152. For example, the capping insulating layer 154 may include silicon nitride.

[0042] Reference Figure 2D , a top protective insulating layer 156 may be formed to cover a portion of the capping insulating layer 154. The top protective insulating layer 156 may include a polymer. For example, the top protective insulating layer 156 may include photosensitive polyimide (PSPI).

[0043] The top protective insulating layer 156 may be formed to be separated from the opening OP1. For example, the edge of the top protective insulating layer 156 may be separated from the edge of the opening OP1. The top protective insulating layer 156 may be formed to not cover the inner portion of the opening OP1 and the portion of the cover insulating layer 154 adjacent to the opening OP1. The top protective insulating layer 156 may be formed so that the width of the portion of the cover insulating layer 154 not provided with the top protective insulating layer 156 has a value greater than the value of the width of the opening OP1.

[0044] Reference Figure 1A , Figure 1B and Figure 2D , a portion of the capping insulating layer 154 and a portion of the upper portion of the bottom protective insulating layer 152 may be removed by using the top protective insulating layer 156 as an etching mask. A portion of the capping insulating layer 154 and a portion of the upper portion of the bottom protective insulating layer 152 may be removed by an anisotropic etching process. A portion of the capping insulating layer 154 may be removed, and thus the capping insulating layer 154 may include a side covering portion 154S and a top covering portion 154T separated from each other. A portion of the bottom protective insulating layer 152 may be removed, and thus the bottom protective insulating layer 152 may include a step ST and a protrusion PRT.

[0045] A portion of the covering insulating layer 154 that covers the top surface of the bottom protective insulating layer 152 and is not covered by the top protective insulating layer 156 and a portion of the covering insulating layer 154 on the top connecting pad 122 may be removed, a portion of the covering insulating layer 154 that is disposed between the top protective insulating layer 156 and the bottom protective insulating layer 152 may be retained as a top covering portion 154T, and a portion of the covering insulating layer 154 on the side surface of the bottom protective insulating layer 152 and the side surface of the barrier layer 123 in the opening OP1 may be retained as a side covering portion 154S, which is, for example, a spacer type.

[0046] In the process of removing a portion of the capping insulating layer 154, over-etching may be performed to expose a portion of the top surface of the top connection pad 122. Therefore, a portion of the upper portion of the bottom protective insulating layer 152 not covered by the top protective insulating layer 156 may be removed, so that a step ST may be formed. In addition, a portion of the upper portion of the bottom protective insulating layer 152 covered by the top protective insulating layer 156 may not be removed, so that a protrusion PRT may be formed.

[0047] Reference Figures 1A to 2D ,like Figure 2D As shown in FIG. 1 , in the process of forming the top protective insulating layer 156 , the top connection pad 122 may be covered by the capping insulating layer 154 and may remain in an unexposed state.

[0048] For example, by developing PSPI for forming the top protective insulating layer 156 in a state where the top surface of the top connection pad 122 is exposed, the top surface of the top connection pad 122 may be discolored by the developer. Such discoloration may be a problem in some conventional processes.

[0049] In the semiconductor chip 100 according to the disclosed embodiment, the top protective insulating layer 156 can be formed in a state where the top connection pad 122 is covered by the cover insulating layer 154 and is not exposed, so the top surface of the top connection pad 122 does not change color. Fig. 6A In the process of the top connection pad 122, the connection terminal 140 can be accurately attached to the top surface of the top connection pad 122, and thus, the connection reliability between the connection terminal 140 and the top connection pad 122 can be enhanced.

[0050] Figure 3 is a cross-sectional view showing a semiconductor package 1000 according to a disclosed embodiment.

[0051] Reference Figure 3 , the semiconductor package 1000 may include a first semiconductor chip 100 and a plurality of second semiconductor chips 200. Figure 3, the semiconductor package 1000 is shown as including four second semiconductor chips 200, but is not limited thereto. For example, the semiconductor package 1000 may include two or more second semiconductor chips 200. In some embodiments, the semiconductor package 1000 may include a multiple of four (4x) second semiconductor chips 200, for example, eight, twelve, sixteen, etc. The semiconductor package 1000 may be referred to as a sub-semiconductor package. A plurality of second semiconductor chips 200 may be sequentially stacked on the first semiconductor chip 100 in a vertical direction. Each of the first semiconductor chip 100 and the plurality of second semiconductor chips 200 may be sequentially stacked so that its effective surface faces its lower portion.

[0052] The first semiconductor chip 100 may include a first semiconductor substrate 110 having a first semiconductor device 112 formed on its effective surface, a first top connection pad 122 and a first bottom connection pad 124 respectively arranged on the effective surface and the ineffective surface of the first semiconductor substrate 110, a first through-electrode 130 that passes through at least a portion of the first semiconductor substrate 110 to electrically connect the first top connection pad 122 to the first bottom connection pad 124, and a first protective insulating layer 150 that exposes at least a portion of the first top connection pad 122 and covers the effective surface of the first semiconductor substrate 110.

[0053] In some embodiments, the first semiconductor chip 100 may be an HBMDRAM semiconductor chip. In some embodiments, the first semiconductor chip 100 may be a buffer chip including a serial-parallel conversion circuit. In some embodiments, the first semiconductor chip 100 may be a buffer chip for controlling an HBMDRAM semiconductor chip.

[0054] In addition to the active surface being provided at the lower portion and the inactive surface being provided at the upper portion, Figure 3 The first semiconductor chip 100 shown in FIG. Figure 1A The semiconductor chip 100 shown in FIG. 1 is the same as that shown in FIG. 1 , and therefore, the semiconductor chip 100 shown in FIG. 1 may be omitted. Figures 1A to 2D That is, the first semiconductor chip 100 included in the semiconductor package 1000 may be Figure 1A The semiconductor chip 100 shown in FIG. 1 is a semiconductor chip with an upper portion and a lower portion thereof being inverted therebetween.

[0055] The second semiconductor chip 200 may include a second semiconductor substrate 210 having a second semiconductor device 212 formed on its effective surface, a second top connection pad 222 and a second bottom connection pad 224 respectively disposed on the effective surface and the ineffective surface of the second semiconductor substrate 210, a second through electrode 230 passing through at least a portion of the second semiconductor substrate 210 to electrically connect the second top connection pad 222 to the second bottom connection pad 224, and a second protective insulating layer 250 exposing at least a portion of the second top connection pad 222 and covering the effective surface of the second semiconductor substrate 210. The second protective insulating layer 250 may include an inorganic material such as an oxide or a nitride. For example, the second protective insulating layer 250 may include at least one of silicon oxide and silicon nitride. In some embodiments, the second protective insulating layer 250 may include silicon nitride.

[0056] The second semiconductor substrate 210, the second top connection pad 222, the second bottom connection pad 224 and the second through-electrode 230 may be respectively the same as, substantially the same as, or similar to the first semiconductor substrate 110, the first top connection pad 122, the first bottom connection pad 124 and the first through-electrode 130, and therefore, their repeated detailed description is omitted.

[0057] The second semiconductor chip 200 may be, for example, a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip. In some embodiments, the second semiconductor chip 200 may be an HBM DRAM semiconductor chip. The first semiconductor chip 100 may be referred to as a master chip, and the second semiconductor chip 200 may be referred to as a slave chip.

[0058] The internal connection terminal 240 may be attached on the second top connection pad 222 of each of the plurality of second semiconductor chips 200. The internal connection terminal 240 may electrically connect the first bottom connection pad 124 of the first semiconductor chip 100 to the second top connection pad 222 of the plurality of second semiconductor chips 200 and may electrically connect the second bottom connection pad 224 and the second top connection pad 222 of each of the plurality of second semiconductor chips 200.

[0059] The internal connection terminal 240 may include a base column 242 (conductive column) under the second top connection pad 222 and a conductive cap 246 on the base column 242. In some embodiments, the cover column ( Figure 6B The inner connection terminal 240 may be disposed between the base column 242 and the conductive cap 246. The inner connection terminal 240 may be referred to as a second connection terminal, and the base column 242, the cover column 244, and the conductive cap 246 may be referred to as a second conductive column, a second cover column, and a third conductive cap, respectively. Figure 6BThe internal connection terminal 240 and the second protective insulating layer 250 are described in detail. Fig. 6A The connection terminal 140 shown in FIG. 1 may be referred to as a first connection terminal, and the internal connection terminal 240 may be referred to as a second connection terminal.

[0060] The insulating adhesive layer 350 may be disposed between the first semiconductor chip 100 and each of the plurality of second semiconductor chips 200. For example, the insulating adhesive layer 350 may include a non-conductive film (NFC), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin. The insulating adhesive layer 350 may surround the internal connection terminal 240 and may fill the area between the first semiconductor chip 100 and each of the plurality of second semiconductor chips 200.

[0061] In some embodiments, the second semiconductor chip 200 disposed at the uppermost end farthest from the first semiconductor chip 100 among the plurality of second semiconductor chips 200 may not include the second bottom connection pad 224 and the second through-electrode 230. In some embodiments, the thickness of the second semiconductor chip 200 disposed at the uppermost end farthest from the first semiconductor chip 100 among the plurality of second semiconductor chips 200 may have a value smaller than a value of the thickness of each of the other second semiconductor chips 200.

[0062] The width and area of ​​the first semiconductor chip 100 may each have a corresponding value greater than the corresponding width and corresponding area of ​​each of the plurality of second semiconductor chips 200. The semiconductor package 1000 may further include a mold layer 300 surrounding the side surfaces of the plurality of second semiconductor chips 200 and the side surface of the insulating adhesive layer 350 on the first semiconductor chip 100. The mold layer 300 may include, for example, an epoxy mold compound (EMC).

[0063] FIG. 4A to FIG. 4D is a cross-sectional view showing a connection pad of a semiconductor package according to an embodiment of the disclosure. In detail, FIG. 4A to FIG. 4D is shown with Figure 1A The cross-sectional view of the enlarged area corresponding to area B is Figure 1A and Figure 1B The same reference numerals refer to the same elements, and repeated descriptions thereof may be omitted.

[0064] Reference Figure 4A, a protective insulating layer 150a exposing the connection pad 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150a may include a bottom protective insulating layer 152a, a capping insulating layer 154a, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152a may include an inorganic material such as an oxide or a nitride. For example, the bottom protective insulating layer 152a may include at least one of silicon oxide and silicon nitride. In some embodiments, the bottom protective insulating layer 152a may include silicon nitride. For example, the capping insulating layer 154a may include silicon nitride. For example, the top protective insulating layer 156 may include PSPI. The protective insulating layer 150a may be referred to as a first protective insulating layer.

[0065] In some embodiments, the barrier layer 123a may be formed on a portion of the connection pad 122. For example, the barrier layer 123a may be formed only at an edge portion of the connection pad 122, thus exposing a central portion of the connection pad 122. The barrier layer 123a may be disposed between the connection pad 122 and the bottom protective insulating layer 152a. In some embodiments, the barrier layer 123a may be omitted.

[0066] The protective insulating layer 150a may include a bottom protective insulating layer 152a, a cover insulating layer 154a, and a top protective insulating layer 156. The bottom protective insulating layer 152a may include an opening OP1a that exposes at least a portion of the connection pad 122. The opening OP1a may have a horizontal width that increases in a direction away from (vertical direction) from the bottom surface of the opening OP1a to the upper portion of the opening OP1a. For example, the opening OP1a may have a relatively small width in the horizontal direction at the lowest elevation corresponding to the elevation of the upper surface of the connection pad 122 and an increased and relatively large width in the horizontal direction at various elevations above the lowest elevation. The bottom protective insulating layer 152a and the barrier layer 123a may have a combined horizontal width that decreases from the bottom surface of the opening OP1a to the upper portion of the opening OP1a. That is, the side surface of the bottom protective insulating layer 152a that is adjacent to the opening OP1a and the side surface of the barrier layer 123a that is adjacent to the opening OP1a may be inclined away from the bottom of the opening OP1a and may extend upward.

[0067] The bottom protective insulating layer 152a may include a step STa including a relatively low top surface at a portion of the bottom protective insulating layer 152a adjacent to the opening OP1a. A portion of the bottom protective insulating layer 152a having a level higher than that of the relatively low top surface of the bottom protective insulating layer 152a (i.e., the bottom surface of the step STa) may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152a may refer to the bottom surface of the step STa and the top surface of the protrusion PRT, respectively.

[0068] The opening OP1a may pass through the bottom protective insulating layer 152a and the barrier layer 123a to expose a portion of a top surface of the connection pad 122. The opening OP1a may be referred to as a first opening.

[0069] The capping insulating layer 154a may cover a portion of the bottom protective insulating layer 152a. In some embodiments, the capping insulating layer 154a may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152a. The capping insulating layer 154a may include a side covering portion 154Sa covering a portion of the side surface of the bottom protective insulating layer 152a and a portion of the side surface of the barrier layer 123a, and a top covering portion 154T covering a portion of the top surface of the bottom protective insulating layer 152a (i.e., the top surface of the protrusion PRT).

[0070] The side covering portion 154Sa may cover at least a portion of the side surface of the barrier layer 123a and at least a portion of the side surface of the bottom protective insulating layer 152a in the opening OP1a. In some embodiments, the side covering portion 154Sa may cover all side surfaces of the barrier layer 123a and all side surfaces of the bottom protective insulating layer 152a in the opening OP1a. In some embodiments, the side covering portion 154Sa may cover a portion of the side surface of the barrier layer 123a and a portion of the side surface of the bottom protective insulating layer 152a in the opening OP1a (i.e., between the step STa and the top surface of the top connection pad 122). In some embodiments, the bottom surface of the side covering portion 154Sa may contact a portion of the top surface of the connection pad 122. The uppermost end of the side covering portion 154Sa may be set at the same level (elevation / height) as the bottom surface of the step STa or may be set at a level (elevation / height) lower than the bottom surface of the step STa.

[0071] The top covering portion 154T may be disposed between the bottom protective insulating layer 152a and the top protective insulating layer 156. The top covering portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152a and the bottom surface of the top protective insulating layer 156. The top covering portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152a (e.g., the top surface of the protrusion PRT of the bottom protective insulating layer 152a (i.e., a relatively high top surface)). In addition, the top covering portion 154T may not cover the top surface of the bottom protective insulating layer 152a in the step STa region. The top covering portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

[0072] Reference Figure 4B , a protective insulating layer 150b exposing the connection pad 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150b may include a bottom protective insulating layer 152b, a capping insulating layer 154b, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152b may include silicon nitride. For example, the capping insulating layer 154b may include silicon nitride. The protective insulating layer 150b may be referred to as a first protective insulating layer.

[0073] The barrier layer 123b may be formed on a portion of the connection pad 122. For example, the barrier layer 123b may expose a central portion of the connection pad 122 and cover at least a portion of the remaining unexposed region of the connection pad 122. The barrier layer 123b may be disposed between the connection pad 122 and the bottom protective insulating layer 152b.

[0074] The protective insulating layer 150b may include a bottom protective insulating layer 152b, a cover insulating layer 154b, and a top protective insulating layer 156. The bottom protective insulating layer 152b may include an opening OP1b that exposes at least a portion of the connection pad 122. The opening OP1b may have a horizontal width that increases from the bottom surface of the opening OP1b to the upper portion of the opening OP1b in a direction away from (vertical direction). For example, the opening OP1b may have a relatively small width in the horizontal direction at the lowest elevation corresponding to the elevation of the upper surface of the connection pad 122 and an increased and relatively large width in the horizontal direction at various elevations above the lowest elevation. The bottom protective insulating layer 152b and the barrier layer 123b may have a horizontal width that decreases from the bottom surface of the opening OP1b to the upper portion of the opening OP1b in a direction away from (vertical direction). That is, a side surface of the bottom protective insulating layer 152 b in the opening OP1 b and a side surface of the barrier layer 123 b in the opening OP1 b may be inclined away from the bottom of the opening OP1 b and may extend upward.

[0075] The bottom protective insulating layer 152b may include a step STb including a relatively low top surface at a portion of the bottom protective insulating layer 152b adjacent to the opening OP1b. A portion of the bottom protective insulating layer 152b having a level higher than that of the relatively low top surface of the bottom protective insulating layer 152b (i.e., the bottom surface of the step STb) may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152b may refer to the bottom surface of the step STb and the top surface of the protrusion PRT, respectively.

[0076] The opening OP1b may pass through the bottom protective insulating layer 152b and the barrier layer 123b to expose a portion of the top surface of the connection pad 122. The opening OP1b may be referred to as a first opening.

[0077] In the process of forming the opening OP1b, due to the difference in etching characteristics between the bottom protective insulating layer 152b and the barrier layer 123b, a sub-step STsb may be formed between the bottom protective insulating layer 152b and the barrier layer 123b in the opening OP1b. The sub-step STsb may be defined by the side surface of the bottom protective insulating layer 152b and the exposed top surface of the barrier layer 123b. The width of the portion of the opening OP1b at the level where the barrier layer 123b is disposed may have a value smaller than the value of the width of the portion of the opening OP1b at the level where the bottom protective insulating layer 152b is disposed.

[0078] The capping insulating layer 154b may cover a portion of the bottom protective insulating layer 152b. In some embodiments, the capping insulating layer 154b may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152b. The capping insulating layer 154b may include a side covering portion 154Sb covering a portion of the side surface of the bottom protective insulating layer 152b and a portion of the side surface of the barrier layer 123b, and a top covering portion 154T covering a portion of the top surface of the bottom protective insulating layer 152b (i.e., the top surface of the protrusion PRT).

[0079] The side covering portion 154Sb may cover each of at least a portion of the side surface of the barrier layer 123b and at least a portion of the side surface of the bottom protective insulating layer 152b in the opening OP1b. In some embodiments, the side covering portion 154Sb may include a first side portion 154Sb1 covering a portion of the side surface of the barrier layer 123b and a second side portion 154Sb2 covering a portion of the side surface of the bottom protective insulating layer 152b in the opening OP1b. The first side portion 154Sb1 and the second side portion 154Sb2 may be spaced apart from each other with an exposed portion of the top surface of the barrier layer 123b located therebetween. In some embodiments, the bottom surface of the first side portion 154Sb1 may contact a portion of the top surface of the connection pad 122. In some embodiments, the bottom surface of the second side portion 154Sb2 may contact a portion of the top surface of the barrier layer 123b. The uppermost ends of the first side portion 154Sb1 and the second side portion 154Sb2 may be disposed at the same level as or lower than bottom surfaces of the sub-step STsb and the step STb, respectively.

[0080] The top covering portion 154T may be disposed between the bottom protective insulating layer 152b and the top protective insulating layer 156. The top covering portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152b and the bottom surface of the top protective insulating layer 156. The top covering portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152b (e.g., the top surface of the protrusion PRT of the bottom protective insulating layer 152b (i.e., a relatively high top surface)). In addition, the top covering portion 154T may not cover the top surface of the bottom protective insulating layer 152b in the step STb region. The top covering portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

[0081] Reference Figure 4C , a protective insulating layer 150c exposing the connection pad 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150c may include a bottom protective insulating layer 152c, a capping insulating layer 154c, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152c may include silicon nitride. For example, the capping insulating layer 154c may include silicon nitride. The protective insulating layer 150c may be referred to as a first protective insulating layer.

[0082] The barrier layer 123c may be formed on a portion of the connection pad 122. For example, the barrier layer 123c may be formed only at an edge portion of the connection pad 122, thus exposing a central portion of the connection pad 122. The barrier layer 123c may be disposed between the connection pad 122 and the bottom protective insulating layer 152c.

[0083] The protective insulating layer 150c may include a bottom protective insulating layer 152c, a cover insulating layer 154c, and a top protective insulating layer 156. The bottom protective insulating layer 152c may include an opening OP1c that exposes at least a portion of the connection pad 122. The opening OP1c may have a horizontal width that increases from the bottom surface of the opening OP1c to the upper portion of the opening OP1c in a direction away from (vertical direction). The bottom protective insulating layer 152c and the barrier layer 123c may have a horizontal width that decreases from the bottom surface of the opening OP1c to the upper portion of the opening OP1c in a direction away from (vertical direction). That is, the side surface of the bottom protective insulating layer 152c that is adjacent to the opening OP1c and the side surface of the barrier layer 123c that is adjacent to the opening OP1c may be inclined away from the bottom of the opening OP1c and may extend upward.

[0084] The bottom protective insulating layer 152c may include a step STc including a relatively low top surface at a portion of the bottom protective insulating layer 152c adjacent to the opening OP1c. A portion of the bottom protective insulating layer 152c having a level higher than that of the relatively low top surface of the bottom protective insulating layer 152c (i.e., the bottom surface of the step STc) may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152c may refer to the bottom surface of the step STc and the top surface of the protrusion PRT, respectively.

[0085] The opening OP1c may pass through the bottom protective insulating layer 152c and the barrier layer 123c to expose a portion of the top surface of the connection pad 122. The opening OP1c may be referred to as a first opening.

[0086] In the process of forming the opening OP1c, due to the difference in etching characteristics between the bottom protective insulating layer 152c and the barrier layer 123c, a sub-step STsc may be formed between the bottom protective insulating layer 152c and the barrier layer 123c in the opening OP1c. The sub-step STsc may be defined by the side surface of the bottom protective insulating layer 152c and the top surface of the barrier layer 123c. The width of a portion of the opening OP1c at a level at which the barrier layer 123c is disposed may have a value smaller than the width of a portion of the opening OP1c at a level at which the bottom protective insulating layer 152c is disposed.

[0087] The side surface of the barrier layer 123c facing the barrier layer 123c in the opening OP1c may be more inclined than the side surface of the bottom protective insulating layer 152c facing the bottom protective insulating layer 152c. That is, the acute angle between the top surface of the barrier layer 123c and the side surface of the bottom protective insulating layer 152c may be greater than the acute angle between the bottom surface of the barrier layer 123c and the side surface of the barrier layer 123c.

[0088] The capping insulating layer 154c may cover a portion of the bottom protective insulating layer 152c. In some embodiments, the capping insulating layer 154c may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152c. The capping insulating layer 154c may include a side covering portion 154Sc covering a portion of the side surface of the bottom protective insulating layer 152c and a top covering portion 154T covering a portion of the top surface of the bottom protective insulating layer 152c (i.e., the top surface of the protrusion PRT).

[0089] The side covering portion 154Sc may cover at least a portion of a side surface of the bottom protective insulating layer 152c in the opening OP1c. In some embodiments, the side covering portion 154Sc may cover at least a portion of a side surface of the bottom protective insulating layer 152c in the opening OP1c, but may not cover a side surface of the barrier layer 123c.

[0090] In an embodiment where the acute angle between the top surface of the blocking layer 123c and the side surface of the bottom protective insulating layer 152c is greater than the acute angle between the bottom surface of the blocking layer 123c and the side surface of the blocking layer 123c, a portion of the covering insulating layer 154c on the side surface of the bottom protective insulating layer 152c may be retained as a side covering portion 154Sc, which may be a spacer type, but may not be retained on the side surface of the blocking layer 123c.

[0091] The side covering portion 154Sc may be spaced apart from the connection pad 122. In some embodiments, the bottom surface of the side covering portion 154Sc may contact a portion of the top surface of the barrier layer 123c. The uppermost end of the side covering portion 154Sc may be disposed at the same level as the bottom surface of the step STc or may be disposed at a level lower than the bottom surface of the step STc.

[0092] The top covering portion 154T may be disposed between the bottom protective insulating layer 152c and the top protective insulating layer 156. The top covering portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152c and the bottom surface of the top protective insulating layer 156. The top covering portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152c (e.g., the top surface of the protrusion PRT of the bottom protective insulating layer 152c (i.e., a relatively high top surface)). In addition, the top covering portion 154T may not cover the top surface of the bottom protective insulating layer 152c in the step STc region. The top covering portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

[0093] Reference Figure 4D, a protective insulating layer 150d exposing the connection pad 122 and covering the top surface of the semiconductor substrate 110 may be disposed on the top surface of the semiconductor substrate 110. The protective insulating layer 150d may include a bottom protective insulating layer 152d, a capping insulating layer 154d, and a top protective insulating layer 156. For example, the bottom protective insulating layer 152d may include silicon nitride. For example, the capping insulating layer 154d may include silicon nitride. The protective insulating layer 150d may be referred to as a first protective insulating layer.

[0094] The barrier layer 123d may be formed on a portion of the connection pad 122. For example, the barrier layer 123d may be formed only at an edge portion of the connection pad 122, thus exposing a central portion of the connection pad 122. The barrier layer 123d may be disposed between the connection pad 122 and the bottom protective insulating layer 152d.

[0095] The protective insulating layer 150d may include a bottom protective insulating layer 152d, a cover insulating layer 154d, and a top protective insulating layer 156. The bottom protective insulating layer 152d may include OP1d that exposes at least a portion of the connection pad 122. The opening OP1d may have a horizontal width that increases from the bottom surface of the opening OP1d to the upper portion of the opening OP1d in a direction away from (vertical direction). The bottom protective insulating layer 152d and the barrier layer 123d may have a horizontal width that decreases from the bottom surface of the opening OP1d to the upper portion of the opening OP1d in a direction away from (vertical direction). That is, the side surface of the bottom protective insulating layer 152d in the opening OP1d and the side surface of the barrier layer 123d in the opening OP1d may be inclined away from the bottom of the opening OP1d and may extend upward.

[0096] The bottom protective insulating layer 152d may include a step STd including a relatively low top surface at a portion of the bottom protective insulating layer 152d adjacent to the opening OP1d. A portion of the bottom protective insulating layer 152d having a level higher than that of the relatively low top surface of the bottom protective insulating layer 152d (i.e., the bottom surface of the step STc) may be referred to as a protrusion PRT. The relatively low top surface and the relatively high top surface of the bottom protective insulating layer 152d may refer to the bottom surface of the step STd and the top surface of the protrusion PRT, respectively.

[0097] The opening OP1d may pass through the bottom protective insulating layer 152d and the barrier layer 123d to expose a portion of the top surface of the connection pad 122. The opening OP1d may be referred to as a first opening.

[0098] In the process of forming the opening OP1d, due to the difference in etching characteristics between the bottom protective insulating layer 152d and the barrier layer 123d, a sub-step STsd may be formed between the bottom protective insulating layer 152d and the barrier layer 123d in the opening OP1d. The sub-step STsd may be defined by the side surface of the bottom protective insulating layer 152d and the top surface of the barrier layer 123d. The width of the portion of the opening OP1d at the level where the barrier layer 123d is disposed may have a value smaller than the value of the width of the portion of the opening OP1d at the level where the bottom protective insulating layer 152d is disposed.

[0099] The capping insulating layer 154d may cover a portion of the bottom protective insulating layer 152d. In some embodiments, the capping insulating layer 154d may cover a portion of each of the side surface and the top surface of the bottom protective insulating layer 152d. The capping insulating layer 154d may include a side covering portion 154Sd covering a portion of the side surface of the bottom protective insulating layer 152d and a portion of the side surface of the barrier layer 123d, and a top covering portion 154T covering a portion of the top surface of the bottom protective insulating layer 152d (i.e., the top surface of the protrusion PRT).

[0100] The side covering portion 154Sd may cover each of at least a portion of the side surface of the barrier layer 123d and at least a portion of the side surface of the bottom protective insulating layer 152d in the opening OP1d. In some embodiments, the side covering portion 154Sd may include a first side portion 154Sd1 covering a portion of the side surface of the barrier layer 123d and a second side portion 154Sd2 covering a portion of the side surface of the bottom protective insulating layer 152d in the opening OP1d. The first side portion 154Sd1 and the second side portion 154Sd2 may be spaced apart from each other with a portion of the top surface of the barrier layer 123d located therebetween.

[0101] In some embodiments, the first side portion 154Sd1 may be spaced apart from the connection pad 122. In some embodiments, a bottom surface of the second side portion 154Sd2 may contact a portion of the top surface of the barrier layer 123d. The uppermost end of the first side portion 154Sd1 and the uppermost end of the second side portion 154Sd2 may be disposed at the same level as the bottom surface of the sub-step STsd and the bottom surface of the step STd, respectively, or may be disposed at a level lower than the bottom surface of the sub-step STsd and the bottom surface of the step STd, respectively.

[0102] In the side surface of the barrier layer 123d in the opening OP1d, the lower portion may have a slope that is gentler than that of the upper portion. For example, the slope of the lower portion of the barrier layer 123d may be smaller than that of the upper portion of the barrier layer 123d. In addition, for example, the inclined surface of the barrier layer 123d may be recessed upward away from the connection pad 122. The barrier layer 123d may include a tail portion 123TA adjacent to the bottom surface of the opening OP1d. The tail portion 123TA may be a portion of the lower portion of the barrier layer 123d adjacent to the bottom surface of the opening OP1d, and the lower portion of the barrier layer 123d includes a side surface having a slope that is gentler than that of the side surface of the upper portion of the barrier layer 123d.

[0103] The first side portion 154Sd1 may be disposed on a side surface of an upper portion of the barrier layer 123d and may not be disposed at the tail portion 123TA of the barrier layer 123d (ie, a side surface of a lower portion of the barrier layer 123d).

[0104] The top covering portion 154T may be disposed between the bottom protective insulating layer 152d and the top protective insulating layer 156. The top covering portion 154T may be disposed between the top surface of the protrusion PRT of the bottom protective insulating layer 152d and the bottom surface of the top protective insulating layer 156. The top covering portion 154T may cover only a portion of the top surface of the bottom protective insulating layer 152d (e.g., the top surface of the protrusion PRT of the bottom protective insulating layer 152d (i.e., a relatively high top surface)). In addition, the top covering portion 154T may not cover the top surface of the bottom protective insulating layer 152d in the step STd region. The top covering portion 154T may cover the entire bottom surface of the top protective insulating layer 156.

[0105] Figure 5 is a cross-sectional view showing a system 1 including a semiconductor package according to an embodiment of the disclosure, Fig. 6A and Figure 6B is an enlarged cross-sectional view showing a first top connection pad and a second top connection pad each included in a semiconductor package of the system 1 according to a disclosed embodiment.

[0106] Reference Figure 5 , the system 1 may include a main board 600 on which an interposer 500 is mounted, a semiconductor package 1000 including a first semiconductor chip 100 and a plurality of second semiconductor chips 200 each attached to the interposer 500, and a third semiconductor chip 400. Figure 3 The semiconductor package 1000 is described in detail, and thus, a repeated description thereof is omitted.

[0107] The third semiconductor chip 400 may include a third semiconductor substrate 410, a third top connection pad 420, a third protective insulating layer 450, and a third connection terminal 440. The third connection terminal 440 may include a third conductive column 442 on the third top connection pad 420 and a third conductive cap 446 on the third conductive column 442. Figure 6B A third covering column that is the same as or similar to the covering column 244 shown in FIG. 4 may be disposed between the third conductive column 442 and the third conductive cap 446. The third semiconductor substrate 410, the third top connection pad 420, the third protective insulating layer 450, and the third connection terminal 440 are respectively Figure 3 The first semiconductor substrate 110, the first top connection pad 122, the first protective insulating layer 150 and the first connection terminal 140 shown in each of the drawings are substantially similar (or identical) to each other, or are respectively Figure 3 The second semiconductor substrate 120, the second top connection pad 222, the second protective insulating layer 250, and the second internal connection terminal 240 respectively shown in FIG. 1 are substantially similar (or identical) elements, and therefore, their detailed descriptions are omitted.

[0108] The third semiconductor chip 400 may be, for example, a CPU chip, a GPU chip, or an AP chip.

[0109] The interposer 500 may include a base layer 510 , a first top pad 522 disposed on a top surface of the base layer 510 , and a first bottom pad 524 disposed on a bottom surface of the base layer 510 .

[0110] The base layer 510 may include semiconductor, glass, ceramic or plastic. For example, the base layer 510 may include silicon. A wiring layer connected to the first top pad 522 and / or the first bottom pad 524 may be provided on the top surface and / or the bottom surface of the base layer 510, and an internal through electrode electrically connecting the first top pad 522 to the first bottom pad 524 may be formed in the base layer 510. The first connection terminal 140 electrically connecting the semiconductor package 1000 to the interposer 500 and the third connection terminal 440 electrically connecting the third semiconductor chip 400 to the interposer 500 may be connected to the first top pad 522.

[0111] The first underfill layer 380 may be disposed between the semiconductor package 1000 and the interposer 500, and the second underfill layer 480 may be disposed between the third semiconductor chip 400 and the interposer 500. The first underfill layer 380 and the second underfill layer 480 may surround the first connection terminal 140 and the third connection terminal 440, respectively. The system 1 may further include an encapsulation molding layer 900, which surrounds the side surface of the semiconductor package 1000 and the side surface of the third semiconductor chip 400 on the interposer 500. The encapsulation molding layer 900 may include, for example, EMC.

[0112] The system connection terminal 540 may be attached on the first bottom pad 524. The system connection terminal 540 may electrically connect the interposer 500 to the main board 600.

[0113] The main board 600 may include a base board layer 610, a second top pad 622 disposed on the top surface of the base board layer 610, and a second bottom pad 624 disposed on the bottom surface of the base board layer 610. In some embodiments, the main board 600 may be a printed circuit board (PCB). For example, the main board 600 may be a multi-layer PCB. The base board layer 610 may include at least one material selected from phenolic resin, epoxy resin, and polyimide.

[0114] A solder resist layer (not shown) exposing the second top pad 622 and the second bottom pad 624 may be formed on each of the top surface and the bottom surface of the base board layer 610. The system connection terminal 540 may be connected to the second top pad 622, and the external connection terminal 640 may be connected to the second bottom pad 624. The system connection terminal 540 may electrically connect the first bottom pad 524 to the second top pad 622. The external connection terminal 640 connected to the second bottom pad 624 may connect the system 1 to the outside.

[0115] In some embodiments, the system 1 may not include the mainboard 600 (and the external connection terminals 640 of the mainboard 600 ), and the system connection terminals 540 of the interposer 500 may perform a function similar to that of the external connection terminals 640 in the absence of the external connection terminals 640 .

[0116] In some embodiments, where the system 1 is used as a part of a larger system, the system 1 may be referred to as a main semiconductor package and the semiconductor package 1000 may be referred to as a sub-semiconductor package.

[0117] Reference Fig. 6A, the first connection terminal 140 can electrically connect the first top connection pad 122 to the first top pad 522. The first connection terminal 140 can include a first base column 142 (first conductive column) on the first top connection pad 122 and a first conductive cap 146 on the first base column 142. In some embodiments, the first cover column 144 can be disposed between the first base column 142 and the first conductive cap 146.

[0118] The first base column 142 may include, for example, copper, and the first cover column 144 may include, for example, at least one of nickel, copper, palladium, platinum, and gold. In some embodiments, the first cover column 144 may include nickel. In some other embodiments, the first cover column 144 may have a multilayer structure including a first layer including nickel and a second layer covering the first layer and including copper.

[0119] The first conductive cap 146 may contact the first top pad 522 of the interposer 500 to electrically connect the first semiconductor chip 100 to the interposer 500. The first conductive cap 146 may include, for example, at least one of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), gold (Au), zinc (Zn), and lead (Pb).

[0120] The first base pillar 142 may be formed to fill the first opening OP1 and protrude relative to the top surface of the bottom protection insulating layer 152 and the top surface of the capping insulating layer 154. Fig. 6A , the top surface of the first base pillar 142 is shown to be disposed at a level higher than the top surface of the capping insulating layer 154 and lower than the top surface of the top protective insulating layer 156, but is not limited thereto. In some embodiments, the top surface of the first base pillar 142 may be disposed at a level higher than the top surface of the top protective insulating layer 156.

[0121] The first base column 142 may be formed to be separated from the protrusion PRT of the bottom protective insulating layer 152. The side surface of the lower portion of the first base column 142 may contact the side covering portion 154S. The side covering portion 154S may be disposed between the first base column 142 and each of the bottom protective insulating layer 152 and the first barrier layer 123. The first base column 142 may be separated from the top covering portion 154T. For example, there may be a gap or opening between the first base column 142 and the top covering portion 154T.

[0122] Reference Figure 6B, the second internal connection terminal 240 can electrically connect the second top connection pad 222 to the first bottom connection pad 124 or can electrically connect the second top connection pad 222 to the second bottom connection pad 224. The second internal connection terminal 240 can include a second base column 242 on the second top connection pad 222 and a second conductive cap 246 on the second base column 242. In some embodiments, the second cover column 244 can be disposed between the second base column 242 and the second conductive cap 246.

[0123] The second conductive cap 246 can contact the first bottom connection pad 124 of the first semiconductor chip 100 or the second bottom connection pad 224 of another second semiconductor chip 200 (a different second semiconductor chip 200 among multiple second semiconductor chips 200) to electrically connect the second semiconductor chip 200 to the first semiconductor chip 100 or to electrically connect different second semiconductor chips 200 among multiple second semiconductor chips 200.

[0124] The second base pillar 242 may be formed to fill the second opening OP2 and protrude relative to the top surface of the second protective insulating layer 250. For example, the second base pillar 242 may be formed to completely fill the second opening OP2. Fig. 6A The side surface of the lower portion of the second base pillar 242 may contact the second protective insulating layer 250 .

[0125] Can be done by using Figure 2A and Figure 2B The method for manufacturing the bottom protective insulating layer 152 is shown in Figure 2B The second protective insulating layer 250 is formed by forming the bottom protective insulating layer 152 in a shape similar to the shape of the intermediate material obtained in FIG. Fig. 6A Unlike the first protective insulating layer 150 shown in FIG. 1 , the second protective insulating layer 250 may not include elements corresponding to the capping insulating layer 154 and the top protective insulating layer 156 and may not include the step ST and the protrusion PRT both included in the bottom protective insulating layer 152 .

[0126] FIG. 7A to FIG. 7D is an enlarged cross-sectional view showing a first top connection pad in a semiconductor package included in a system according to an embodiment of the disclosure. FIG. 4A to FIG. 4D The protective insulating layers 150a to 150d and the barrier layers 123a to 123d shown in FIG. Fig. 6A In addition to the first protective insulating layer 150 and the first barrier layer 123, FIG. 7A to FIG. 7D Respectively FIG. 4A to FIG. 4D Basically the same, so you can omit FIG. 4A to FIG. 4D as well as Fig. 6A The same or similar description.

[0127] Reference Fig. 7A , the first base column 142 may be formed to be separated from the protrusion PRT of the bottom protection insulating layer 152a. The side surface of the lower portion of the first base column 142 may contact the side covering portion 154Sa. The side covering portion 154Sa may be disposed between the first base column 142 and each of the bottom protection insulating layer 152a and the barrier layer 123a.

[0128] Reference Figure 7B , the first base column 142 may be formed to be separated from the protrusion PRT of the bottom protection insulating layer 152b. For example, there may be a gap between the first base column 142 and the bottom protection insulating layer 152b. The side surface of the lower portion of the first base column 142 may contact the first side portion 154Sb1 and the second side portion 154Sb2 that are separately disposed from each other. The first side portion 154Sb1 may be disposed between the barrier layer 123b and the first base column 142, and the second side portion 154Sb2 may be disposed between the bottom protection insulating layer 152b and the first base column 142.

[0129] Reference Figure 7C , the first base column 142 may be formed to be separated from the protrusion PRT of the bottom protection insulating layer 152c. For example, there may be a gap between the first base column 142 and the bottom protection insulating layer 152c. The lowermost side surface of the first base column 142 may contact the barrier layer 123c, and the lower side surface of the first base column 142 that does not contact the barrier layer 123c (i.e., the upper side surface instead of the lowermost side surface) may contact the side covering portion 154Sc. The side covering portion 154Sc may be disposed between the bottom protection insulating layer 152c and the first base column 142.

[0130] Reference Fig.7D , the first base column 142 may be formed to be separated from the protrusion PRT of the bottom protection insulating layer 152d. The side surface of the lower portion of the first base column 142 may contact the first side portion 154Sd1 and the second side portion 154Sd2 which are separately provided from each other. The first side portion 154Sd1 may be provided between the barrier layer 123d and the first base column 142, and the second side portion 154Sd2 may be provided between the bottom protection insulating layer 152d and the first base column 142.

[0131] The side surface of the lower portion of the first base pillar 142 may sequentially contact the tail portion 123TA of the barrier layer 123 d , the first side portion 154Sd1 , a portion of the top surface of the barrier layer 123 d , and the second side portion 154Sd2 from the lowermost portion of the first base pillar 142 .

[0132] FIG. 8A to FIG. 8Dis an enlarged cross-sectional view showing a second top connection pad in a semiconductor package included in a system according to an embodiment of the disclosure. Figure 6B In addition to the second protective insulating layer 250 and the second barrier layer 223, FIG. 8A to FIG. 8D Each of Figure 6B Basically the same, so you can omit Figure 6B The same or similar description.

[0133] Reference Fig. 8A , the second protective insulating layer 250a may include a second opening OP2a exposing at least a portion of the second top connection pad 222. The second base column 242 may be formed to fill the second opening OP2a and protrude relative to the top surface of the second protective insulating layer 250a. The second opening OP2a may have a horizontal width that increases from the bottom surface of the second opening OP2a to the upper portion of the second opening OP2a in a direction away from (vertical direction). The second protective insulating layer 250a and the second barrier layer 223a may have a horizontal width that decreases from the bottom surface of the second opening OP2a to the upper portion of the second opening OP2a in a direction away from (vertical direction). That is, the side surface of the second protective insulating layer 250a in the second opening OP2a and the side surface of the second barrier layer 223a in the second opening OP2a may be inclined away from the opening OP2a and may extend upward. The side surface of the lower portion of the second base column 242 may contact the side surface of the second protective insulating layer 250a and the side surface of the second barrier layer 223a.

[0134] Reference Figure 8B , the second protective insulating layer 250b may include a second opening OP2b exposing at least a portion of the second top connection pad 222. The second base column 242 may be formed to fill the second opening OP2b and protrude relative to the top surface of the second protective insulating layer 250b. The second opening OP2b may have a horizontal width that increases from the bottom surface of the second opening OP2b to the upper portion of the second opening OP2b in a direction away from (vertical direction). The second protective insulating layer 250b and the second barrier layer 223b may have a horizontal width that decreases from the bottom surface of the second opening OP2b to the upper portion of the second opening OP2b in a direction away from (vertical direction). That is, the side surface of the second protective insulating layer 250b in the second opening OP2b and the side surface of the second barrier layer 223b in the second opening OP2b may be inclined away from the second opening OP2b and may extend upward. The side surface of the lower portion of the second base column 242 may contact the side surface of the second protective insulating layer 250b and the side surface of the second barrier layer 223b.

[0135] An intermediate step STmb may be formed between the second protective insulating layer 250b and the second barrier layer 223b in the second opening OP2b. The intermediate step STmb may be defined by the side surface of the second protective insulating layer 250b and the top surface of the second barrier layer 223b in the second opening OP2b. The width of a portion of the second opening OP2b at a level where the second barrier layer 223b is disposed may have a value smaller than a value of a width of a portion of the second opening OP2b at a level where the second protective insulating layer 250b is disposed.

[0136] Reference Figure 8C , the second protective insulating layer 250c may include a second opening OP2c exposing at least a portion of the second top connection pad 222. The second base column 242 may be formed to fill the second opening OP2c and protrude relative to the top surface of the second protective insulating layer 250c. The second opening OP2c may have a horizontal width that increases from the bottom surface of the second opening OP2c to the upper portion of the second opening OP2c in a distance direction (vertical direction). The second protective insulating layer 250c and the second barrier layer 223c may have a horizontal width that decreases from the bottom surface of the second opening OP2c to the upper portion of the second opening OP2c in a distance direction. That is, the side surface of the second protective insulating layer 250c in the second opening OP2c and the side surface of the second barrier layer 223c in the second opening OP2c may be inclined away from the second opening OP2c and may extend upward.

[0137] The side surface of the second barrier layer 223c adjacent to the second opening OP2c may be less inclined than the side surface of the second protective insulating layer 250c facing the second protective insulating layer 250c. That is, the acute angle between the top surface of the second barrier layer 223c and the side surface of the second protective insulating layer 250c may be greater than the acute angle between the bottom surface of the second barrier layer 223c and the side surface of the second barrier layer 223c. The side surface of the lower portion of the second base pillar 242 may contact the side surface of the second protective insulating layer 250c and the side surface of the second barrier layer 223c.

[0138] An intermediate step STmc may be formed between the second protective insulating layer 250c and the second barrier layer 223c in the second opening OP2c. The intermediate step STmc may be defined by the side surface of the second protective insulating layer 250c and the top surface of the second barrier layer 223c. The width of a portion of the second opening OP2c at a level where the second barrier layer 223c is disposed may have a value smaller than a value of a width of a portion of the second opening OP2c at a level above the level where the second barrier layer 223c is disposed.

[0139] Reference Fig.8D, the second protective insulating layer 250d may include a second opening OP2d exposing at least a portion of the second top connection pad 222. The second base column 242 may be formed to fill the second opening OP2d and protrude relative to the top surface of the second protective insulating layer 250d. The second opening OP2d may have a horizontal width that increases from the bottom surface of the second opening OP2d to the upper portion of the second opening OP2d in a direction away from (vertical direction). The second protective insulating layer 250d and the second barrier layer 223d may have a horizontal width that decreases from the bottom surface of the second opening OP2d to the upper portion of the second opening OP2d in a direction away from (vertical direction). That is, the side surface of the second protective insulating layer 250d in the second opening OP2d and the side surface of the second barrier layer 223d in the second opening OP2d may be inclined away from the opening and may extend upward.

[0140] The side surface of the second barrier layer 223d adjacent to the second opening OP2d may be adjacent to the second protective insulating layer 250d and tilted differently from the side surface of the second protective insulating layer 250d. That is, the slope of the side surface of the second barrier layer 223d may vary. For example, the slope of the side surface of the second barrier layer 223d at the lower portion closest to the second top connection pad 222 may be smaller than the slope of the side surface of the second barrier layer 223d at the upper portion farther from the second top connection pad 222. The inclination angle of the side surface of the second barrier layer 223d at the upper portion farther from the second top connection pad 222 may be smaller than the inclination angle between the bottom surface of the second barrier layer 223d and the side surface of the second barrier layer 223d. The side surface of the lower portion of the second base column 242 may contact the side surface of the second protective insulating layer 250d and the side surface of the second barrier layer 223d.

[0141] The side surface of the second barrier layer 223d adjacent to the lower portion of the second opening OP2d may have a slope gentler than that of the side surface of the upper portion. The second barrier layer 223d may include a tail portion 223TA adjacent to the bottom surface of the second opening OP2d. The tail portion 223TA may be a portion adjacent to the lower portion of the second barrier layer 223d near the second top connection pad 222 and may include a side surface having a slope gentler than that of the side surface of the upper portion of the second barrier layer 223d.

[0142] While the inventive concept has been particularly shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor chip, comprising: a semiconductor substrate including a top surface, a top connection pad disposed in the top surface; as well as a protective insulating layer, the protective insulating layer comprising an opening, the protective insulating layer not covering at least a portion of the top connection pad on the semiconductor substrate, The protective insulating layer comprises: a bottom protective insulating layer; a covering insulating layer comprising a side covering portion covering at least a portion of a side surface of the bottom protective insulating layer and a top covering portion provided separately from the side covering portion to cover at least a portion of a top surface of the bottom protective insulating layer; and a top protective insulating layer located on the top covering portion. Wherein, the semiconductor chip further comprises a barrier layer, wherein at least a portion of the barrier layer is disposed between the top connection pad and the bottom protective insulating layer, The opening passes through the bottom protective insulating layer and the barrier layer.

2. The semiconductor chip according to claim 1, wherein: The bottom protective insulating layer also includes protrusions and steps. The step defines an upper portion of the protrusion adjacent to the opening.

3. The semiconductor chip according to claim 2, wherein: The top covering portion covers a top surface of the protrusion, and a top protective insulating layer is disposed on the protrusion.

4. The semiconductor chip according to claim 2, wherein: The side covering portion covers at least a portion of a side surface of the bottom protective insulating layer, the portion of the side surface of the bottom protective insulating layer being lower in level than a bottom surface of the step.

5. The semiconductor chip according to any one of claims 2 to 4, wherein: The side covering portion is configured to cover at least a portion of a side surface of the bottom protection insulating layer and all side surfaces of the barrier layer between the step and a top surface of the top connection pad.

6. The semiconductor chip according to claim 1, wherein: The side covers include: a first side portion covering a portion of a side surface of the barrier layer; and a second side portion covering a portion of a side surface of the bottom protective insulating layer, The first side portion and the second side portion are separated from each other.

7. The semiconductor chip according to claim 6, wherein: The first side portion is spaced apart from the top connection pad. 8 . The semiconductor chip according to claim 1 , further comprising a sub-step defined in the opening by a side surface of the bottom protection insulating layer and a top surface of the barrier layer.

9. The semiconductor chip according to claim 1, wherein: The side cover portions are separated from the top connection pads.

10. The semiconductor chip according to claim 1, wherein The side covering portion covers at least a portion of a side surface of the bottom protection insulating layer and does not cover a side surface of the barrier layer.

11. A semiconductor package, comprising: The first semiconductor chip comprises: a first top connection pad and a first bottom connection pad, which are respectively disposed on the top surface and the bottom surface of the first semiconductor substrate; a first protective insulating layer, the first protective insulating layer comprises a first opening, and the first protective insulating layer does not cover at least a portion of the first top connection pad on the first semiconductor substrate; and a first through electrode, which electrically connects the first top connection pad to the first bottom connection pad; and at least one second semiconductor chip, comprising: a second top connection pad disposed on the top surface of the second semiconductor substrate; a second protective insulating layer, the second protective insulating layer comprising a second opening, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate; and an internal connection terminal disposed on the second top connection pad and electrically connecting the first semiconductor chip to the at least one second semiconductor chip through the first bottom connection pad of the first semiconductor chip, the internal connection terminal contacting a side surface of the second protective insulating layer in the second opening, wherein the at least one second semiconductor chip is stacked on the bottom surface of the first semiconductor chip, Among them, the first protective insulating layer includes: a bottom protective insulating layer; a covering insulating layer, including a side covering portion covering at least a portion of the side surface of the bottom protective insulating layer and a top covering portion separately arranged from the side covering portion to cover at least a portion of the top surface of the bottom protective insulating layer; and a top protective insulating layer, located on the top covering portion.

12. The semiconductor package according to claim 11, wherein The bottom protective insulating layer and the second protective insulating layer include the same material.

13. The semiconductor package according to claim 11, wherein: The bottom protective insulating layer also includes protrusions and steps. wherein the step defines an upper portion of the protrusion adjacent to the first opening, Wherein, no step is provided in the second protective insulating layer.

14. The semiconductor package according to claim 13, wherein: A top protective insulating layer is disposed on the protrusion, and The top covering portion is disposed between the protrusion and the top protective insulating layer.

15. The semiconductor package according to claim 13, wherein: The uppermost end of the side cover portion is disposed at the same level as or lower than the bottom surface of the step.

16. The semiconductor package according to any one of claims 13 to 15, further comprising a barrier layer, at least a portion of the barrier layer being disposed between the first top connection pad and the bottom protection insulating layer, in, The first opening passes through the bottom protective insulating layer and the barrier layer, The side covering portion covers a portion of a side surface of the bottom protection insulating layer between the step and a top surface of the first top connection pad and all side surfaces of the barrier layer.

17. A semiconductor package, comprising: The first semiconductor chip comprises: a first top connection pad and a first bottom connection pad, which are respectively arranged on the top surface and the bottom surface of the first semiconductor substrate; a first barrier layer, which covers a portion of the top surface of the first top connection pad; a first protective insulating layer, which comprises a first opening, and the first protective insulating layer does not cover at least a portion of the first top connection pad on the first semiconductor substrate; and a first through electrode, which electrically connects the first top connection pad to the first bottom connection pad; and A plurality of second semiconductor chips, comprising: a second top connection pad and a second bottom connection pad, respectively disposed on the top surface and the bottom surface of the second semiconductor substrate; a second protective insulating layer, the second protective insulating layer comprising a second opening, the second protective insulating layer not covering at least a portion of the second top connection pad on the second semiconductor substrate, the plurality of second semiconductor chips being stacked on the bottom surface of the first semiconductor chip; and an internal connection terminal, electrically connecting the second top connection pad to the first bottom connection pad, or electrically connecting the second top connection pad and the second bottom connection pad of different second semiconductor chips among the plurality of second semiconductor chips, Among them, the first protective insulating layer includes: a bottom protective insulating layer, including a protrusion and a step, wherein the step defines an upper portion of the protrusion adjacent to the opening; a covering insulating layer, including a side covering portion covering at least a portion of a side surface of the bottom protective insulating layer and a top covering portion separately arranged from the side covering portion to cover at least a portion of a top surface of the bottom protective insulating layer; and a top protective insulating layer, located on the top covering portion.

18. The semiconductor package according to claim 17, wherein: The bottom protective insulating layer, the cover insulating layer and the second protective insulating layer all include inorganic materials, and The top protective insulating layer includes a polymer.

19. The semiconductor package according to claim 17 or 18, wherein: The top protective insulating layer covers the top surface of the protrusion of the bottom protective insulating layer, and The uppermost end of the side cover portion is disposed at the same level as or lower than the bottom surface of the step.

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