Noise cancellation technique for sine-to-square wave converter

Abstract

A sine-to-square converter circuit receives a sine wave signal and provides a first square wave signal having a first frequency. A 2X clock multiplier circuit multiplies the first square wave signal and provides a second square wave signal at a second frequency that is twice the first frequency. A first storage element clocked by the second square wave signal stores a delayed version of the first square wave signal and provides an even-odd signal. A second storage element clocked by the second square wave signal receives the even-odd signal and provides an odd-even signal. A duty cycle correction circuit adjusts a threshold of the sine-to-square converter based on a difference in duty cycle pulse width between the even-odd signal and the odd-even signal.

Description

TECHNICAL FIELD

[0001] The present invention relates to noise cancellation, and more particularly to noise cancellation for a sine-to-square wave converter. BACKGROUND

[0002] Sine waves are very common in electronic communication systems because oscillators naturally output sine waves. In wireless, wireline, and optical communication links, an oscillator sets the time reference for the system. Frequency synthesizers following the oscillator generate a clock or local oscillator signal at a particular or different frequency for use in the communication link. Frequency synthesizers preferably have a square wave with sharp edges as their reference input to be free from other noise sources in the synthesizer circuit. Therefore, a sine-to-square wave converter is used between the oscillator circuit and the synthesizer. However, the output of the oscillator can be corrupted by low frequency additive noise, which can be the result of biasing circuits used in the oscillator or the sine-to-square wave converter. This very low frequency additive noise is converted to phase noise as the edges of the square wave are modulated by the additive noise through the sine-to-square wave converter. This noise also appears at the output of the frequency synthesizer and affects the phase noise performance of the clock or local oscillator signal, ultimately affecting the performance of the data communication link. The effect of this additive noise is shown as a "hump" 101 in the phase noise curve of an exemplary frequency synthesizer. Therefore, a better method of noise cancellation is needed to improve the performance of the frequency synthesizer and ultimately the performance of the data communication link. SUMMARY

[0003] Therefore, in one embodiment, an apparatus includes a sine-to-square wave converter circuit coupled to receive a sine wave signal and provide a first square wave signal having a first frequency. A clock multiplier circuit coupled to receive the first square wave signal and provide a second square wave signal having a second frequency that is twice the first frequency. A duty cycle correction circuit coupled to provide a voltage to an input of the sine-to-square wave converter to adjust a threshold of the sine-to-square wave converter based on a pulse width difference between a first signal having the first frequency and a second signal having the first frequency.

[0004] In another embodiment, a method includes converting a sine wave signal to a first square wave signal having a first frequency in a sine-to-square wave converter circuit. The method also includes multiplying the first square wave signal in a clock multiplier circuit and providing a second square wave signal having a second frequency that is twice the first frequency. A first signal having the first frequency and a second signal having the first frequency are generated using the second square wave signal and a threshold of the sine-to-square wave converter is adjusted based on a pulse width difference between the first signal and the second signal.

[0005] In one embodiment, a sine-to-square converter circuit is coupled to receive a sine wave signal and provide a first square wave signal having a first frequency. A clock multiplier circuit is coupled to receive the first square wave signal and provide a second square wave signal having a second frequency that is twice the first frequency. A first storage element having an input coupled to a delayed version of the first square wave signal, the first storage element clocked by the second square wave signal provided by the clock multiplier circuit, and providing an even-odd signal. A second storage element having an input coupled to the even-odd signal, clocked by the second square wave signal and providing an odd-even signal. A duty cycle correction circuit coupled to provide a voltage to an input of the sine-to-square converter to adjust a threshold of the sine-to-square converter based on a pulse width difference between the even-odd signal and the odd-even signal. BRIEF DESCRIPTION OF DRAWINGS

[0006] The application can be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0007] Figure 1 Phase noise curves of an example frequency synthesizer are shown, as well as the impact of this additional noise.

[0008] Figure 2 A block diagram of an embodiment of a system to reduce noise is shown.

[0009] Figure 3 Other details of a system to reduce noise are shown, including a sine-to-square converter followed by a 2X clock multiplier and a feedback loop providing duty cycle correction.

[0010] Figure 4A A timing diagram of signals generated by the circuit in Figure 3 is shown.

[0011] Figure 4B A timing diagram of signals generated by the circuit in Figure 3 is shown, where the duty cycle of the flx signal is 50%.

[0012] Figure 5 Sources of noise in the system of Figure 3 are shown.

[0013] Figure 6 How noise appears in waveform form before and after the clock multiplier is shown.

[0014] Figure 7 How the 2X multiplier shapes the noise is illustrated.

[0015] Figure 8 A differential embodiment of the duty cycle adjustment circuit is shown.

[0016] Figure 9A A single-ended embodiment of the duty cycle adjustment circuit is shown.

[0017] Figure 9B Mismatch effects in the current source in the single-ended embodiment are shown.

[0018] Figure 10 An enable circuit for keeping the duty cycle correction circuit loop open until the peak amplitude of the input sinusoidal signal reaches a threshold voltage value is shown.

[0019] The use of the same reference signs in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0020] The embodiments described herein reduce the low frequency additional noise caused by the biasing circuit used in the oscillator and / or the sinusoidal to square wave converter, which is otherwise converted into phase noise when the edges of the rectangular wave are modulated by this noise. The embodiments described herein improve the phase noise performance while consuming very small silicon area, are modular and can be used with any PLL architecture (analog / digital) after the sinusoidal to square wave. It also consumes very low power.

[0021] Figure 2 An exemplary block diagram of a system 200 that reduces noise is shown. An oscillator (OSC) 201 provides a sinusoidal wave 203 to a sinusoidal to square wave converter and noise canceller 205. The sinusoidal to square wave converter and noise canceller 205 provides a reference clock signal with reduced noise to a phase detector 207 of a phase locked loop 208, which includes a loop filter 209, a voltage controlled oscillator 211 that provides an output signal 215. The goal is to ensure that the output signal 215 does not have phase noise caused by additional noise of the oscillator or the sinusoidal to square wave converter. The PLL 208 also includes a feedback divider 217 and a delta sigma modulator 221 to control the division ratio of the feedback divider. The embodiments described herein are equally applicable to other PLL architectures, such as Integer-N, where the division value of the feedback divider is not modulated by a DSM.

[0022] Figure 3 Various aspects of the system are shown in more detail. In Figure 3In an embodiment, the oscillator 301 is a crystal oscillator and provides a sinusoidal wave signal 302 to a sinusoidal-to-square wave converter circuit 303. A key idea is to add a 2X clock multiplier 305 behind the sinusoidal-to-square wave converter circuit 303 and then adjust the threshold of the sinusoidal-to-square wave converter through a feedback loop that includes a duty cycle correction circuit 307. The 2X clock multiplier 305 doubles the frequency of the f 1x signal 306 provided by the sinusoidal-to-square wave converter 303 and provides a f 2x signal 310.

[0023] Figure 4A A timing diagram of signals generated by the circuit of Figure 3 is shown. Referring to Figure 3 and FIG. 4, the f 1x signal 306 and the delayed f 1x signal 308 are provided to an XOR gate to produce the f 2x signal 310. A storage element (e.g., a D flip-flop) 311 receives the delayed f 1x signal 308, is clocked by the f 2x signal, and provides an even-odd signal 315 having a first frequency to the duty cycle correction circuit 307 and a storage element (e.g., a D flip-flop) 317. The storage element 317 provides an odd-even signal 319 also having the first frequency to the duty cycle correction circuit 307. Note that the even-odd and odd-even signals have nominally equal pulse widths but opposite polarities. The f 2x signal 310 is provided to a phase and frequency detector of a clock synthesizer circuit (not shown in Figure 3 ) as a reference clock signal. Figure 4B A timing diagram of signals generated by the circuit of Figure 3 is shown, where the duty cycle of the f 1x signal 306 is 50%.

[0024] Figure 5 A sinusoidal wave 302 provided by a crystal oscillator and 1 / f noise 502 present in the input to the sinusoidal-to-square wave converter circuit 303 as well as thermal noise 504 of a DC bias resistor used as additional noise are shown. The sinusoidal-to-square wave converter 303 provides the f 1x signal 306 to the 2X multiplier 305. Figure 6 How the noise affects the sinusoidal-to-square wave converter is shown. The sinusoidal-to-square wave converter acts as an inverter and triggers from low to high as well as from high to low depending on the threshold setting of the sinusoidal-to-square wave converter. Referring to Figure 6A sine wave 601, along with additional and 1 / f noise 603, is provided to the sine-to-square wave converter. Ideally, assuming no noise, the sine-to-square wave converter should set its threshold to switch at the zero-crossing points of the sine wave, i.e., low to high at 605, high to low at 607, and low to high at 609. The additional and 1 / f noise 603 raises the voltage of the nominal input waveform, causing the sine-to-square wave converter to switch from low to high before 605, then from high to low after 607, and finally from low to high before 609. The additional noise at the input of the sine-to-square wave converter modulates the rising and falling edges with opposite polarities. In other words, if the additional noise causes the rising edge to advance, as shown in 621 and 625, then it also causes the falling edge to delay, as shown in 623. The rise edge advance or fall edge delay is based on... Where S is the slope of the sine wave at the zero crossing point, and v n This is the magnitude of the added 1 / f noise. Conversely, using a 2X multiplier after a sine-to-square wave converter shifts the adjacent edges of the 2X multiplier output (f2x) in opposite directions, by the same amount as shown in 631 and 633. The phase detector of the frequency synthesizer sees an equal and opposite time error every other edge after the 2X multiplier, thus eliminating this added noise.

[0025] Figure 7 The noise resulting from using a 2X multiplier is shown. At 701, the generation of f by adding a noise-free sine wave 703 to the noise component 705 is shown. 2x Waveform 701. Noise component 705 is the frequency. place Where T ref It is the period of a sine wave. The frequency domain is shown at 715, which shows the period at f. ref 721 and at 3f ref The noise component at 723, but at 2f ref The location does not exist, where f ref It is f 1x Therefore, as shown in the time domain of 727 and the frequency domain of 729, 2X multiplication adds noise from 2f. ref Shift to odd harmonics.

[0026] However, due to the asymmetry of the devices in the sine-to-square wave generator, the spacing between odd and even edges may differ from the spacing between even and odd edges. This can result in a large 1X frequency component in the 2X output spectrum, limiting the performance of the frequency synthesizer. A feedback loop is used as a basic (1X) suppression circuit and adjusts the threshold of the sine / square converter so that the spacing between odd and even edges is the same as the spacing between even and odd edges of the 2X output.

[0027] Since the noise at the threshold input of the sine-to-square converter is "only" present around the even harmonics and DC to first order, any noise contribution from the feedback loop itself will also be suppressed. This allows for a wider bandwidth feedback loop to be designed. Since a wider bandwidth loop naturally implies a smaller time constant, a compact implementation can be achieved using smaller resistors and smaller capacitors. Furthermore, since a large noise resistor with a small capacitor is used, the current consumption and silicon area is further reduced (since the noise of this circuit is rejected).

[0028] Figure 8 An embodiment of a circuit implementation 800 of the duty cycle correction circuit 307 is shown that adjusts f 1x signal 306 to a 50% duty cycle. The duty cycle correction circuit 800 includes a differential charge pump 801, a filter 803, and an operational amplifier 805. The differential charge pump 801 receives the even-odd signal 315 and the odd-even signal 319 from the 2X multiplier. In contrast to a single-ended charge pump (see FIG. 9), the differential charge pump is not sensitive to device mismatches in the current sources 807 and 809. The output differential current is only a function of the pulse width difference of the even-odd and odd-even signals. Note that any pulse width difference is due to the difference in pulse width of the even-odd and odd-even signals of opposite polarity. The f 1x signal 306 (see Figure 4B ) is adjusted to a 50% duty cycle by the duty cycle correction circuit 800, the even-odd and odd-even signals also have a 50% duty cycle, and any changes in duty cycle due to noise are reflected in changes in the duty cycle (and pulse width) of the even-odd and odd-even signals. The filter 803 filters the differential current, and the filtered current is input to the operational amplifier 805. The operational amplifier 805 has a series resistor 811 and a series capacitor 815 in the feedback. The series capacitor 815 acts as an integrating capacitor for the loop, and the resistor 811 sets the zero to cancel any poles in the input network. The output 816 of the operational amplifier is provided to the input of the sine-to-square converter 303 through a bias resistor 817 to adjust the threshold of the sine-to-square converter based on the pulse width difference of the even-odd and odd-even signals (of opposite polarity).

[0029] Referring again to FIG. 4 and Figure 8If the even / odd signal is low, current source 807 provides current to the negative input of operational amplifier 805 for the duration of the low pulse width. Simultaneously, if the odd / even signal is high, current source 809 provides the same magnitude of current with opposite polarity to the positive input of operational amplifier 805. It is assumed that the high pulse width of the odd / even signal is equal to the low pulse width of the even / odd signal. As can be seen from Figure 4, even / odd and odd / even signals nominally have equal pulse widths but opposite polarities. Similarly, when the even / odd signal is high and the odd / even signal is low, assuming equal pulse widths with opposite polarities, equal and opposite currents will be provided to the amplifier input. If the pulse widths of the even / odd signal and the odd / even signal with opposite polarities are not equal, current sources 807 and 809 will not provide currents of equal magnitude. The current difference is then integrated by the operational amplifier circuit and reflected in the bias voltage provided by the operational amplifier 805 to the input of the sine wave to square wave converter circuit 303 through the bias resistor 817, in order to adjust the threshold for the circuit to switch from high to low and from low to high.

[0030] Figure 9A An embodiment using a single-ended charge pump 901 and an operational amplifier 903 is shown. When the even-odd signal is high, switch 902 is closed, and current from the PMOS current source 905 flows to the operational amplifier 903; and when the odd-even signal is high, switch 906 is closed, and current from the NMOS current source 907 flows to the operational amplifier 903. Because when f... 1x Signal 306 (see Figure 3 When the duty cycle of the signal is not 50%, the "high" pulse widths of the even-odd signal and the odd-even signal are not equal. Therefore, the difference will be integrated into the operational amplifier and the duty cycle will be corrected to 50%. Figure 9A The embodiments described are sensitive to device mismatch in current sources 905 and 907. For example... Figure 9B As shown, if the PMOS current (Ipmos) from current source 905 (implemented by one or more PMOS transistors) and the NMOS current (Inmos) from current source 907 (implemented by one or more NMOS transistors) are equal, then the current supplied by the charge pump is 921. Figure 9B At 923, it is shown how mismatch affects the current i supplied to the operational amplifier when Ipmos is not equal to Inmos. out If Ipmos is not equal to Inmos, it may itself cause errors in the final duty cycle calibration. This necessitates calibrating both Ipmos and Inmos to ensure the circuit accurately corrects the duty cycle to 50%.

[0031] The loop gain is a function of the amplitude A of the input signal Vin to the sine-to-square wave converter. Therefore, the feedback circuit will not function properly until the input signal has sufficient amplitude. Figure 10The illustrated embodiment utilizes a start-up circuit to keep the feedback loop open (keep the duty cycle correction circuit 307 Figure 3 open) until the amplitude of the input signal is above a threshold voltage. The start-up circuit includes a peak detector circuit 1001 that compares the peak amplitude of the sine wave to determine when the peak amplitude A > A th , where A th is the threshold voltage above which the loop will operate normally. A capacitor 1002 stores the detected peak amplitude and compares the value to a peak amplitude threshold A th . Once the peak amplitude A > A th , a switch 1003 closes, thereby coupling the duty cycle correction circuit 800 to the input of the sine to square converter circuit 303, and thus the feedback loop is closed. Once the peak amplitude of the input sine wave is high enough, this will cause the feedback loop to correct the duty cycle based on the pulse width difference of the even and odd pulses. Additionally, during start-up, while the peak amplitude A < A th , a fixed voltage V mid is provided through a switch 1005 to adjust the threshold of the sine to square converter circuit 303. The voltage V mid causes the sine to square converter to switch, for example, at the nominal zero crossing of the input sine wave.

[0032] Accordingly, various aspects related to eliminating noise in a sine to square converter have been described. The description of the application set forth herein is illustrative and is not intended to limit the scope of the application as set forth in the following claims. Other variations and modifications of the embodiments disclosed herein, can be made based on the description set forth herein, without departing from the scope of the application as set forth in the following claims.

Claims

1. An apparatus for a sine-to-square converter, comprising: a sine-to-square converter circuit coupled to receive a sine wave signal and provide a first square wave signal having a first frequency; a clock multiplier circuit coupled to receive the first square wave signal and provide a second square wave signal having a second frequency; a duty cycle correction circuit coupled to the sine-to-square converter circuit to adjust a threshold of the sine-to-square converter circuit based on a pulse width difference between a first signal having the first frequency and a second signal having the first frequency; a first storage element having an input coupled to the first square wave signal, the first storage element clocked by the second square wave signal provided by the clock multiplier circuit, the first storage element providing an even-odd signal as a first signal; and a second storage element having an input coupled to the even-odd signal, the second storage element clocked by the second square wave signal, and the second storage element providing an odd-even signal as a second signal. The first storage element is coupled to the first square wave signal through a delay circuit.

2. The apparatus of claim 1, wherein, The duty cycle correction circuit includes:

3. The apparatus of claim 1, wherein, a charge pump responsive to provide a current that reflects a pulse width difference between the odd-even signal and the even-odd signal; and an operational amplifier coupled between the charge pump and an input of the sine-to-square converter circuit. The charge pump is a differential charge pump.

4. The apparatus of claim 3, wherein, 5. The apparatus of claim 4, further comprising: a first resistor and a first capacitor coupled in series between a first input of the operational amplifier and a first output of the operational amplifier; and a second resistor and a second capacitor coupled in series between a second input of the operational amplifier and a second output of the operational amplifier.

6. The apparatus of claim 3, further comprising: a bias resistor coupled between an output of the operational amplifier and an input of the sine-to-square converter circuit. The second frequency is twice the first frequency. The duty cycle correction circuit is coupled to provide a voltage to an input of the sine-to-square converter circuit to adjust a threshold of the sine-to-square converter circuit.

7. The apparatus of claim 1, wherein, 9. The apparatus of claim 1, further comprising:

8. The apparatus of claim 1, wherein, an enable circuit configured to cause the duty cycle correction circuit to adjust the threshold of the sine-to-square converter circuit only after a peak amplitude of the sine wave signal is above a threshold voltage. The enable circuit further includes: a peak detector circuit to compare the peak amplitude of the sine wave signal to the threshold voltage and provide a peak detect signal indicative thereof; and 10. The apparatus of claim 9, wherein, a first switch to couple an output of the duty cycle correction circuit to the sine-to-square converter circuit in response to the peak detect signal indicating that the peak amplitude of the sine wave signal is above the threshold voltage and to decouple the output of the duty cycle correction circuit from the sine-to-square converter circuit in response to the peak detect signal indicating that the peak amplitude of the sine wave signal is not above the threshold voltage. The enable circuit further includes: ​ 11. The apparatus of claim 10, wherein, ​ a second switch to couple a fixed voltage to the sine-to-square converter circuit in response to a peak detection signal indicating that a peak amplitude of the sine wave signal is not higher than the threshold voltage, and to decouple the fixed voltage from the sine-to-square converter circuit in response to a peak detection signal indicating that a peak amplitude of the sine wave signal is higher than the threshold voltage.

12. The apparatus of any of claims 1-11, further comprising: a phase-locked loop coupled to receive the second square wave signal as a reference signal.

13. The apparatus of any of claims 1-11, further comprising: a crystal oscillator coupled to provide the sine wave signal to the sine-to-square converter circuit.

14. A method for a sine-to-square converter, comprising: converting a sine wave signal to a first square wave signal having a first frequency in a sine-to-square converter circuit; multiplying the first square wave signal in a clock multiplier circuit and providing a second square wave signal having a second frequency, the second frequency being twice the first frequency; generating a first signal having the first frequency and a second signal having the first frequency; adjusting a threshold of the sine-to-square converter circuit according to a pulse width difference between the first signal and the second signal; providing a delayed version of the first square wave signal to a first storage element; clocking the first storage element using the second square wave signal and providing an even-odd signal from the first storage element as the first signal; and providing the even-odd signal to a second storage element; and clocking the second storage element using the second square wave signal and providing an odd-even signal from the second storage element as the second signal.

15. The method of claim 14, further comprising: generating a current reflecting a pulse width difference between opposite polarities of the odd-even signal and the even-odd signal; providing the current to an operational amplifier having an integrating capacitor; and adjusting the threshold of the sine-to-square converter circuit according to an output of the operational amplifier.

16. The method of claim 15, further comprising: preventing adjustment of the threshold of the sine-to-square converter circuit based on a difference in duty cycle between the even-odd signal and the odd-even signal until a peak amplitude of the sine wave signal is higher than a threshold voltage.

17. The method of claim 16, further comprising: comparing the peak amplitude of the sine wave signal to the threshold voltage and providing a peak detection signal indicating thereof; coupling, by a first switch, the output of the operational amplifier to the sine-to-square converter circuit in response to the peak detection signal indicating that the peak amplitude of the sine wave signal is higher than the threshold voltage; and maintaining, by the first switch, the coupling of the output of the operational amplifier to the sine-to-square converter circuit in response to the peak detection signal indicating that the peak amplitude of the sine wave signal is not higher than the threshold voltage.

18. The method of claim 17, further comprising: ​ in response to a peak detection signal indicating that a peak amplitude of the sinusoidal signal is not higher than the threshold voltage, coupling a fixed voltage to the sine-to-square converter circuit through a second switch; and in response to a peak detection signal indicating that a peak amplitude of the sinusoidal signal is higher than the threshold voltage, preventing coupling of the fixed voltage to the sine-to-square converter circuit through the second switch.

19. The method of claim 14, further comprising: generating a sinusoidal signal in a crystal oscillator; providing the sinusoidal signal to the sine-to-square converter circuit; and providing the second square wave signal as a reference signal to a phase-locked loop.

20. An apparatus for a sine-to-square converter, comprising: a sine-to-square converter circuit coupled to receive a sinusoidal signal and provide a first square wave signal having a first frequency; a clock multiplier circuit coupled to receive the first square wave signal and provide a second square wave signal having a second frequency, the second frequency being twice the first frequency; a first storage element having an input coupled to a delayed version of the first square wave signal, the first storage element clocked by the second square wave signal provided by the clock multiplier circuit, and the first storage element providing an even-odd signal; a second storage element having an input coupled to the even-odd signal, the second storage element clocked by the second square wave signal, and the second storage element providing an odd-even signal; and a duty cycle correction circuit coupled to provide a voltage to an input of the sine-to-square converter circuit to adjust a conversion threshold of the sine-to-square converter circuit based on a pulse width difference between the even-odd signal and the odd-even signal.

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