A memory and a device including the memory

Abstract

The present disclosure relates to a memory and a device including the memory. The memory may be included in a combined processing device, which may further include a computing device, a general-purpose interconnect interface, and other processing devices. The computing device interacts with the other processing devices to jointly complete a computing operation specified by a user. The storage device is respectively connected to the computing device and the other processing devices and is used for storing data of the computing device and the other processing devices. The solution of the present disclosure can be widely applied to various data storage fields.

Description

Technical Field

[0001] The present disclosure relates to the field of memories, and more particularly, to the field of DDR memories. Background Art

[0002] In the on-die termination (ODT) control method of Low Power Dual Data Rate (LPDDR4), there is a unique operation mode, that is, the die accessed during writing and the system on chip (SOC) accessed during reading can choose to turn on or turn off the ODT.

[0003] In the ODT control method of LPDDR5, there is a more flexible operation mode, that is, during writing, whether the accessed die or the unaccessed die can choose to turn on or turn off the ODT. The main reason for this flexible operation mode is that as the operation speed of LPDDR5 gradually increases to 6.4 Gbps, the signal integrity (SI) and the quality of signal transmission on the channel gradually decline. Therefore, in order to obtain better signal quality, LPPDR has developed a dual-die architecture in which the accessed and unaccessed dies can be separately selected to turn on and turn off the ODT, and different ODT values can be set. However, this operation mode that seemingly solves the signal quality during the writing process has the following defects: during the process of switching from writing to reading, the unaccessed die cannot turn off the ODT, which often affects the signal quality during the reading process. The final setting method cannot use the ODT setting value with the best signal quality due to this defect, resulting in poor signal quality and inability to increase the operation speed. Summary of the Invention

[0004] An object of the present disclosure is to solve the defect in the prior art that the data access speed in the memory cannot be further increased.

[0005] According to a first aspect of the present disclosure, there is provided a memory including: at least three dies D1-Dn, each die including a termination resistor ODT1-ODTn, and a communication path is provided between the dies D1-Dn; wherein, one of the dies D1-Dn is a target die T-D, the termination resistor of the target die T-D is a target termination resistor T-ODT, and the other dies are non-target dies NT-D, the termination resistor of the non-target die NT-D is a non-target termination resistor NT-ODT, and the operating modes of the target termination resistor T-D include a read mode and a write mode; the target die T-D sends a notification signal to the non-target die NT-D through the communication path to notify the non-target die NT-D of the operating mode of the target die NT-D.

[0006] According to a second aspect of the present disclosure, there is provided a package including the memory as described above, wherein the communication path is provided inside the package and directly connects the dies D1-Dn.

[0007] According to a third aspect of the present disclosure, there is provided a package including the memory as described above, wherein external terminals are provided outside the package, and the communication path connects the dies D1-Dn through the external terminals.

[0008] According to a fourth aspect of the present disclosure, there is provided a processor system including a processor chip and the memory as described above, the processor chip is connected to the dies D1-Dn, wherein the processor chip sets the resistance values of the target termination resistor T-ODT and the non-target termination resistor NT-ODT, and / or the termination resistor of the processor chip according to different operating modes of the target die T-D.

[0009] According to a fifth aspect of the present disclosure, there is provided a board card including: the memory as described above; or including the package as described above; or including the processor system as described above.

[0010] According to a sixth aspect of the present disclosure, there is provided an electronic device including: the memory as described above; or including the package as described above; or including the processor system as described above; or including the board card as described above.

[0011] According to a seventh aspect of the present disclosure, there is also provided a storage method executed on a memory, the memory including: at least three die D1-Dn, each die including a termination resistor ODT1-ODTn, and a communication path is provided between the die D1-Dn; wherein, one of the die D1-Dn is a target die T-D, the termination resistor of the target die T-D is a target termination resistor T-ODT, the other die are non-target die NT-D, the termination resistor of the non-target die NT-D is a non-target termination resistor NT-ODT, and the operating modes of the target termination resistor T-D include a read mode and a write mode; the method includes: sending a notification signal from the target die T-D to the non-target die NT-D to notify the non-target die NT-D of the operating mode of the target die NT-D.

[0012] One beneficial effect of the technical solution provided by the present disclosure is that it can improve the data transfer speed rate of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0014] Figure 1a A schematic diagram of the basic structure of a conventional LPDDR5 memory in the read mode is shown.

[0015] Figure 1b A schematic diagram of the basic structure of a conventional LPDDR5 memory in the write mode is shown.

[0016] Figure 2a A timing diagram of the write mode in the LPDDR5 specification (Item#1854.99A) according to the present disclosure is shown.

[0017] Figure 2b A timing diagram of the read mode in the LPDDR5 specification (Item#1854.99A) according to the present disclosure is shown.

[0018] Figure 3 A schematic diagram of a memory according to one aspect of the present disclosure is shown.

[0019] Figure 4 A schematic diagram of a communication path according to an embodiment of the present disclosure is shown.

[0020] Figure 5 A schematic diagram of a communication path according to another embodiment of the present disclosure is shown.

[0021] Figure 6 Shows a schematic diagram of a memory according to another embodiment of the present disclosure.

[0022] Figure 7 Shows a simple timing diagram for sending a notification signal according to an embodiment of the present disclosure.

[0023] Figures 8a to 8d Shows a schematic diagram of various connection relationships between multiple dies.

[0024] Figure 9 Shows a schematic block diagram of a processor system according to another embodiment of the present disclosure.

[0025] Figure 10 Shows a flowchart of a storage method executed on a memory according to another aspect of the present disclosure.

[0026] Figure 11 Is a schematic diagram of a combined processing device according to an aspect of the present disclosure. Detailed Description

[0027] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0028] It should be understood that the terms "first", "second", "third", and "fourth", etc. in the claims, the description, and the drawings of the present disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the description and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0029] It should also be understood that the terms used in the description of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the description and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term " / and / " used in the description and claims of the present disclosure refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0030] As used in this specification and the claims, the term "if" may be construed, depending on the context, as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be construed, depending on the context, to mean "once determined" or "in response to determining" or "once [described condition or event] is detected" or "in response to detecting [described condition or event]".

[0031] Figure 1a Fig. shows a schematic diagram of the basic structure of a conventional LPDDR5 memory in read mode.

[0032] In Figure 1a , die D1 is in an operating state, for example in read mode, and thus die D1 can be referred to as the target die T-D; while die D2 is in a non-operating state, and thus die D2 can be referred to as the non-target die NT-D. The SoC is accordingly also in an operating state. It should be understood that the target die T-D and the non-target die NT-D can change. Here, representing die D1 as the target die T-D and die D2 as the non-target die NT-D is only for example purposes and does not impose any limitations on the functions of die D1 and D2.

[0033] In Figure 1a In the read mode shown, the receiving terminal Rx1 in the target die T-D is in a non-operating state, while the transmitting terminal Tx1 is in an operating state. In Figure 1a , for ease of understanding and reading, the input and output terminals in the non-operating state are set to be shown in gray.

[0034] The transmitting terminal Txs in the system-on-chip SoC is in a non-operating state, while the receiving terminal Rxs in the SoC is in an operating state.

[0035] In the non-target die NT-D, both its transmitting terminal Tx2 and receiving terminal Rx2 are in non-operating states.

[0036] Furthermore, as shown in Figure 1a In the read mode, the termination resistor (herein referred to as T-ODT) in the target die T-D is disconnected (which can also be understood as having an infinite resistance value), while the SoC-ODT in the system-on-chip SoC is in an operating state.

[0037] Figure 1b Fig. shows a schematic diagram of the basic structure of a conventional LPDDR5 memory in write mode.

[0038] In Figure 1bAmong them, die D1 is in the working state, for example, in the write mode. Therefore, we still refer to die D1 as the target die T-D; while die D2 is in the non-working state, so we still refer to die D2 as the non-target die NT-D. The SoC is correspondingly also in the working state.

[0039] In Figure 1b the shown write mode, the receiving terminal Rx1 in the target die T-D is in the working state, while the transmitting terminal Tx1 is in the non-working state. In Figure 1b order to facilitate understanding and reading, the input and output terminals in the non-working state are also set to be represented in gray.

[0040] The transmitting terminal Txs in the system-on-chip SoC is in the working state, while the receiving terminal Rxs in the SoC is in the non-working state.

[0041] In the non-target die NT-D, its transmitting terminal Tx2 and receiving terminal Rx2 are both in the non-working state.

[0042] Furthermore, as shown in Figure 1b in the write mode, the termination resistor (here called T-ODT) in the target die T-D is closed, while the SoC-ODT in the system-on-chip SoC is disconnected and in the non-working state.

[0043] From Figure 1a and Figure 1b it can be seen that since the non-target die NT-D cannot directly know the working mode of the target die T-D, its non-target termination resistor NT-ODT does not change with the different working modes of the target die T-D, that is, whether the target die T-D is in the read mode or in the write mode, the non-target termination resistor NT-ODT of the non-target die NT-D does not change.

[0044] Figure 2a shows the timing diagram of the write mode in the LPDDR5 specification (Item#1854.99A) according to the present disclosure.

[0045] In Figure 2a (it can also be seen from Figure 164 of Item#1854.99A of the LPDDR5 specification), in the mode where the non-target ODT is enabled, the ODT timing (ODTLon and ODTLoff) is referenced to WL after the write command, and the ODT value in the target die can be updated in the tODTon.max time slot. After the write operation, the target ODT value should be restored to the preset non-target ODT value in the tODToff.max time slot.

[0046] Figure 2bShows the timing diagram of the read mode in the LPDDR5 specification (Item#1854.99A) according to the present disclosure.

[0047] In Figure 2b (see also Figure 165 of Item#1854.99A of the LPDDR5 specification), in the mode where the non-target ODT is enabled, the ODT timing (ODTLoff_RD / RD_DQ / RDQS) is referenced to RL after the read command, and the ODT value in the target die can be disabled in the tODT_RDoff,max time slot. After the read operation, the disabled ODT should be restored to a predetermined non-target ODT value in the tODT_RDon,max time slot.

[0048] In the above Figure 2a and Figure 2b ODT_Rank0 can represent the target terminal resistance T-ODT of the target die T-D, while ODT_Rank1 can represent the non-target terminal resistance NT-ODT of the non-target die NT-D. It will be further described hereinafter.

[0049] From Figure 1a , Figure 1b , Figure 2a and Figure 2b It can be seen that in the LPDDR5 specification (Item#1854.99A), the non-target terminal resistance NT-ODT in the non-target die NT-D is always active. In this case, it has little impact on low-speed data transmission, but as the data transmission rate increases, the impact of the non-target terminal resistance NT-ODT in the non-target die NT-D gradually increases. In addition, in the existing specification, the target die T-D does not have any impact on the non-target die NT-D, and the non-target die NT-D cannot directly obtain the working state of the target die T-D.

[0050] Figure 3 Shows a schematic diagram of a memory according to an aspect of the present disclosure.

[0051] As Figure 3 shown, according to an aspect of the present disclosure, a memory is provided, at least three dies D1-D3 (three dies are exemplarily shown in Figure 3 ), and each die includes a corresponding terminal resistance ODT1-ODT3.

[0052] In Figure 3Among them, one of the dies D1 - D3 is a target die T - D (for example, die D1 is the target die, the terminal resistance ODT1 of this target die T - D is the target terminal resistance T - ODT, and the other dies (D2 and D3) are non - target dies NT - D, the terminal resistance OTD of this non - target die NT - D is the non - target terminal resistance NT - ODT, and the operating mode of the target die T - D can include a read mode and a write mode).

[0053] In Figure 3 Among them, a communication path can be provided between die D1 (also denoted as T - D in FIG. 2), D2 (also denoted as NT - D in FIG. 2), and D3 (also denoted as NT - D in FIG. 2), and the target die T - D can send a notification signal to the non - target die NT - D through this communication path to notify the non - target die NT - D of the operating mode of the target die T - D.

[0054] Unlike Figure 1a and Figure 1b the storage of the present disclosure includes at least 3 dies, a communication path can be provided between die D1 and die D2, and a communication path can also be provided between die D2 and die D3. As for between die D1 and D3, a communication path can be provided or not, which depends on the connection structure between dies D1 - D3. This will be described in detail later.

[0055] In Figure 1a and Figure 1b in the structure shown, the target die T - D and the non - target die NT - D are in an isolated state. When the operating mode of the target die T - D changes, the target die does not notify the non - target die NT - D, and the non - target die NT - D is also unaware of the change in the operating mode of the target die T - D. Thus, a good cooperation cannot be formed between the target die T - D and the non - target die NT - D.

[0056] Whereas in Figure 3 in the structure shown, there is a communication path between the target die T - D and the non - target die NT - D. Thus, after the pass - through mode of the target die T - D changes, the target die T - D can send a notification signal to the non - target die NT - D through this communication path to notify the non - target die NT - D of the operating mode of the target die T - D so that the non - target die NT - D can make corresponding settings.

[0057] Figure 3 also exemplarily shows an SoC chip, which includes an SoC terminal resistance SoC - ODT, and this SoC chip is connected to the dies D1 - D3. Among them, the SoC - ODT is set to have different resistance values according to different operating modes. It should be understood that althoughFigure 3 An SoC chip is shown, but alternatively, it can also be any processing unit with control functions such as a CPU chip, a GPU chip, etc.

[0058] Combined with Figure 1a and Figure 1b the description of, in the read mode, the termination resistor T-ODT in the target die T-D can be set to open (infinity), and in the write mode, the termination resistor SoC-ODT of the system-on-chip SoC can be set to open (infinity).

[0059] According to an embodiment of the present disclosure, the non-target die NT-D can be configured to, in response to receiving the notification signal from the target die T-D, set the non-target termination resistor NT-ODT to different resistance values according to different working modes of the target die T-D.

[0060] The above communication path will be described in detail below with reference to the accompanying drawings.

[0061] Figure 4 A schematic diagram of a communication path according to an embodiment of the present disclosure is shown. According to this embodiment, the communication path is a single bidirectional communication path.

[0062] As Figure 4 shown, pins Pin11 and Pin12, pins Pin21 and Pin22, and pins Pin31 and Pin32 can be respectively provided in dies D1-D3, and the above pins are directly connected through a bidirectional path. Here, the pins Pin11 and Pin12 can be represented as ODT_Ctrl_Rank0, the pins Pin21 and Pin21 can be represented as ODT_Ctrl_Rank1, and the pins Pin31 and Pin32 can be represented as ODT_Ctrl_Rank2, which means that a notification signal or a control signal can be sent through these pins.

[0063] Such a beneficial effect is that in a package including dies D1-D3, there is no need to add new connection points or terminals outside the package, so that fewer modifications can be made on the basis of existing dies and specifications, thereby reducing costs. In addition, through the above embodiment, only one pin needs to be added to the original die, which reduces the complexity of modifying the die.

[0064] In addition, a single bidirectional communication path is beneficial to reducing the number of pins, thereby further reducing the manufacturing process and shrinking the chip area.

[0065] Figure 5 A schematic diagram of a communication path according to another embodiment of the present disclosure is shown. According to this embodiment, the communication path is two reverse unidirectional communication paths.

[0066] As Figure 5 shown, in die D1, pin Pin11 and pin Pin12 can be respectively provided; in die D2, pin Pin21, pin Pin22, pin P23 and pin P24 can be respectively provided; and in die D3, pin P31 and pin P32 can be respectively provided. A communication path can connect from pin Pin11 to pin Pin21, and another communication path can connect from pin Pin22 to pin Pin12. Further, a communication path can connect from pin Pin23 to pin Pin31, and another communication path can connect from pin P32 to pin P24. Here, pin Pin11 can be denoted as ODT_Ctrl_Rank0, pin Pin21 can be denoted as ODT_Ctrl_Rank1, and pin Pin31 can be denoted as ODT_Ctrl_Rank2, which means that notification signals or control signals can be sent or received through this pin. Of course, after the roles of die D1, die D2 and pin D3 are interchanged (for example, die D2 becomes the target die, and die D1 and die D3 become non-target dies), then pin Pin22 and Pin23 can be denoted as ODT_Ctrl_Rank0, and Pin12 and Pin31 can be respectively denoted as ODT_Ctrl_Rank1 and ODT_Ctrl_Rank2.

[0067] It should also be understood that Figure 5 the connection between die D3 and die D1 is omitted, and the two can also be connected through a bidirectional or unidirectional communication path.

[0068] Such a beneficial effect is that in the package including die D1 - D3, there is no need to add new connection points or terminals outside the package, so that the least amount of changes can be made on the basis of the existing die and specifications, thereby reducing costs.

[0069] Furthermore, through the two communication paths, the transmission and reception of notification signals can be isolated, reducing or eliminating possible interference or conflicts between signals.

[0070] Figure 6 Fig. shows a schematic diagram of a memory according to another embodiment of the present disclosure.

[0071] As Figure 6 shown, the memory shown in Fig. 1 - Figure 5 shown is located in a package. In the Figure 6 embodiment shown, for the sake of explanation, the system on chip SoC is omitted.

[0072] In this package, the pin Pin1 of die D1 is connected to terminal 1 outside the package, the pin Pin2 of die D2 is connected to terminal 2 outside the package, and the pin Pin3 of die D3 is connected to terminal 3 outside the package. Terminals 1, 2, and 3 can be formed as separate connection terminals outside the package, so that when terminals 1, 2, and 3 are connected, a complete communication path can be formed.

[0073] It should also be understood that the connections between multiple dies do not necessarily all have to be outside the die or all inside the die, but some can be outside the die and some can be inside the die.

[0074] It should be understood that Figure 6 The settings in are just an example. The number of external terminals of the package can also be other numbers. For example, one terminal can be set outside the package, and a bidirectional communication link is connected to this one terminal. In another example, two terminals can be set outside the package. The unidirectional communication path from die D1 to die D2 passes through the first terminal, and the unidirectional communication path from die D2 to die D1 passes through the second terminal.

[0075] In addition, similar to Figure 4 and Figure 5 , the pin or terminal starting from die D1 can be represented as ODT_Ctrl_Rank0, the pin or terminal starting from die D2 can be represented as ODT_Ctrl_Rank1, and the pin or terminal starting from die D3 can be represented as ODT_Ctrl_Rank2.

[0076] Figures 3 - 6 does not indicate which transmitter and receiver are in the working state and which are in the non-working state as in Figure 1a and Figure 1b , nor does it label which ODT is disconnected. However, those skilled in the art need to understand that Figures 3 - 6 only shows the general connection situation, and the specific working state of the components will be described in detail below.

[0077] The type of the notification signal can be in various ways. According to an embodiment of the present disclosure, the notification signal can be a step signal, which is emitted in the read mode and includes a front step edge and a rear step edge. And the front step edge (such as the rising edge) of the step signal occurs before the start of data transmission in the read mode, and the rear step edge (such as the falling edge) occurs after the end of data transmission in the read mode.

[0078] From Figure 2a and Figure 2bAs can be seen from the timing diagram, it takes multiple clock cycles to switch from one mode to another and complete data transmission in another mode. For example, Figure 2a As shown, enter the WR mode between clock cycles Ta2 and Ta3. After several clock cycles, next, between clock cycles Td0 and Te1, data transmission is performed. Thus, as long as the non-target termination resistor NT-ODT is set to an appropriate resistance value before data transmission, the beneficial effects desired by the present disclosure can be achieved.

[0079] Figure 7 Fig. shows a simple timing diagram for sending a notification signal according to an embodiment of the present disclosure.

[0080] For example, Figure 7 As shown, within the NT-ODT OFF (NT-ODT disconnected) clock cycle of ODT_Rank0, the entire cycle of data transmission in DQ(15:0) is covered. Thus, before the start of the NT-ODT OFF clock cycle, a step signal can be sent by the pin ODT_Ctrl_Rank0. At the rising edge of this step signal, the non-target termination resistor NT-ODT is notified to be set to the corresponding resistance value. Thereafter, ODT_Ctrl_Rank0 can remain high (or can remain low) during the NT-ODT OFF clock cycle. After the end of the NT-ODT OFF cycle, the step signal jumps from high to low, whereby the resistance value of the non-target termination resistor NT-ODT can be restored to the previous setting.

[0081] Preferably, Figure 7 the step signal shown can occur during Figure 2b the NT-ODT OFF clock cycle of, during which the NT-ODT can be turned off. After the end of this NT-ODT OFF clock cycle, the NT-ODT is restored to the previous setting. The beneficial effect of this is that the "NT-ODT OFF" clock cycle in the existing specification can be utilized to set this step signal, with very little modification to the existing timing diagram.

[0082] Next, the target die T-D enters the write mode. In this mode, since the NT-ODT has been restored to the previous appropriate setting, there is no need to send a step signal in the write mode.

[0083] Optionally, the step signal can be issued in the write mode. The rising edge of the step signal can be before the start of the NT-ODT OFF clock cycle of the write mode, and the falling edge can be after the start of the NT-ODT OFF clock cycle of the write mode. Thus, within the NT-ODT OFF clock cycle, the resistance value of the NT-ODT can be set to the desired threshold, and after the end of the NT-ODT OFF clock cycle, the NT-ODT can be turned off.

[0084] The non-target terminal resistor NT-ODT and the settings of other terminal resistors will be described in detail below with reference to a table.

[0085] Table 1 shows the performance of data transmission under different resistance value combinations of the on-chip system SoC's terminal resistor SoC-ODT and the non-target terminal resistor NT-ODT in the read mode. It can be understood that in the read mode, the target terminal resistor T-ODT can be disconnected (resistance value is infinite), or the resistance value of the target terminal resistor T-ODT can be set to be large enough so that the resistance value of the target terminal resistor T-ODT is not lower than the resistance value of the non-target terminal resistor NT-ODT.

[0086]

[0087] Table 1

[0088] In Table 1, EW represents the eye diagram width, DQ0 - DQ7, DM10, and RDQS_T represent the corresponding pins respectively. It can be seen from Table 1 that in the read mode, when SoC-ODT is 48 ohm and the non-target terminal resistor NT-ODT is disconnected, the average eye diagram width is 67.58 ps; when Soc-ODT is 60 ohm and the non-target terminal resistor NT-ODT is 120 ohm, the average eye diagram width is 67.02 ps; when Soc-ODT is 80 ohm and the non-target terminal resistor NT-ODT is 80 ohm, the average eye diagram width is 64.09 ps; when Soc-ODT is 120 ohm and the non-target terminal resistor NT-ODT is 60 ohm, the average eye diagram width is 60.01 ps; and when Soc-ODT is disconnected and the non-target terminal resistor NT-ODT is 48 ohm, the average eye diagram width is 30.89 ps.

[0089] As can be seen from Table 1, in read mode, when the target terminal resistance T-ODT is set to open, the smaller the ratio of SoC-ODT to the non-target terminal resistance NT-ODT, the better the signal integrity (SI) or signal quality. When the resistance value of SoC-ODT gradually increases and the resistance value of the non-target terminal resistance NT-ODT gradually decreases, the signal quality will gradually deteriorate until the signal quality seriously deteriorates after SoC-ODT is disconnected.

[0090] On the other hand, as can be seen from Table 1, in read mode, the resistance value of the non-target terminal resistance NT-ODT can be set to not less than 60 ohm. In this case, although the signal quality deteriorates, the degree of deterioration is still within an acceptable range. Preferably, in read mode, the non-target terminal resistance (NT-ODT) can be disconnected, that is, its resistance value is infinite.

[0091] Table 2 shows the performance of data transmission under different resistance value combinations of the target terminal resistance T-ODT and the non-target terminal resistance NT-ODT of the target die T-D in write mode. It can be understood that in write mode, the SoC terminal resistance SoC-ODT can be disconnected (resistance value is infinite), or the resistance value of the SoC terminal resistance SoC-ODT can be set to be large enough.

[0092]

[0093] Table 2

[0094] As can be seen from Table 2, in write mode, when T-ODT is 48 ohm and the non-target terminal resistance NT-ODT is disconnected, the average eye diagram width is 64.97 ps; when the target terminal resistance T-ODT is 60 ohm and the non-target terminal resistance NT-ODT is 120 ohm, the average eye diagram width is 69.85 ps; when the target terminal resistance T-ODT is 80 ohm and the non-target terminal resistance NT-ODT is 80 ohm, the average eye diagram width is 71.13 ps; when the target terminal resistance T-ODT is 120 ohm and the non-target terminal resistance NT-ODT is 60 ohm, the average eye diagram width is 79.99 ps; and when the target terminal resistance T-ODT is disconnected and the non-target terminal resistance NT-ODT is 48 ohm, the average eye diagram width is 89.21 ps.

[0095] As can be seen from Table 2, in the write mode, when the SoC termination resistance SoC-ODT is set to open, the smaller the ratio of the target termination resistance T-ODT to the non-target termination resistance NT-ODT, the worse the signal integrity (SI) or signal quality. When the resistance value of the target termination resistance T-ODT gradually increases and the resistance value of the non-target termination resistance NT-ODT gradually decreases, the signal quality will gradually improve. When the target termination resistance T-ODT is open and the non-target termination resistance NT-ODT is 48 ohm, the signal quality is optimal.

[0096] On the other hand, as can be seen from Table 2, in the write mode, the resistance value of the non-target termination resistance NT-ODT can be set to not greater than 120 ohm. In this case, although the signal quality is not optimal, it is still within an acceptable range. Thus, preferably, in the write mode, the target termination resistance T-ODT is set to open.

[0097] For the non-target termination resistance NT-ODT, its resistance value is set to multiple cases. For example, it can be any one of 240 / N ohm, where N is any integer from 2 to 10. That is, the resistance value of this non-target termination resistance can be 120 ohm, 80 ohm, 60 ohm, 48 ohm, 40 ohm, 34 ohm, 30 ohm, 27 ohm or 24 ohm, etc.

[0098] It should be understood that the above resistance values are only examples, and those skilled in the art can adopt other resistance values within the above resistance value range.

[0099] Table 3 shows the comparison of the resistance values of the target termination resistance T-ODT, the non-target termination resistance NT-ODT, and the Soc termination resistance SoC-ODT according to an embodiment of the present disclosure.

[0100] Operating mode T - ODT NT - ODT SoC - ODT Read mode Disconnect Disconnect 48 ohm Write mode Disconnect 48 ohm Disconnect

[0101] Table 3

[0102] As can be seen from Table 1, Table 2, and Table 3, the target termination resistance T-ODT of the target die T-D can preferably be set to be large enough, more preferably to be open, whether in the read mode or the write mode. The non-target termination resistance NT-ODT can be set to be large enough in the read mode, preferably to be open, and in the write mode, it can be set to be small, preferably to be 48 ohm. The SoC termination resistance SoC-ODT can be set to be small in the read mode, preferably to be 48 ohm, and in the write mode, it can be set to be large enough, preferably to be open.

[0103] According to an embodiment of the present disclosure, the notification signal is sent after the target die T-D starts to switch its working mode and before transmitting data in the working mode. In other words, according to the above embodiment of the present disclosure, for both the read mode and the write mode, the transmission of the notification signal from the target die T-D to the non-target die NT-D needs to be at least before the start of data transmission in the read mode or the write mode, so that the non-target die NT-D can complete the corresponding settings before data transmission, which is beneficial to the transmission of data in the read mode or the write mode. It can be understood that the target output driver termination T-ODT of the target die T-D and the non-target output driver termination NT-ODT of the non-target die NT-D can be switched. Therefore, preferably, for the batch manufacturing of components, the output driver termination in the die can be uniformly set to a fixed value (for example, 48 ohm), and then the resistance values of T-ODT and NT-ODT can be controlled by the opening and closing of the switch. For example, the resistance is infinite when the switch is open and, for example, 48 ohm when the switch is closed.

[0104] In addition, it should also be understood that 48 ohm is only an exemplary resistance value, and those skilled in the art can adopt any other suitable resistance value or the resistance value specified in the LPDDR5 specification.

[0105] According to another embodiment of the present disclosure, the memory may further include a mode register MR (not shown in the figure), and a parameter list is stored in the mode register so that the memory can set at least the dies D1-Dn according to the parameter list.

[0106] The parameter list may include, for example, the states that the output driver termination should be in for different working modes, the magnitudes of the resistance values in different states, etc., and the events that should occur under each clock signal, etc. The mode register may be set in the memory including the dies D1-Dn, or may be set in each die.

[0107] According to another embodiment of the present disclosure, the above-mentioned memory may further include a memory controller, which is connected to the dies D1-Dn and is configured to control the resistance value of the target output driver termination T-ODT of the target die T-D. Optionally, the controller may be further configured to control the resistance value of the non-target output driver termination NT-ODT of the non-target die NT-D.

[0108] In this embodiment, the target die T-D and the target output driver termination T-ODT therein can be controlled by an external memory controller. The memory controller can also control the non-target die NT-D and its non-target output driver termination NT-ODT, which is beneficial to forming a reliable backup when a communication path fails.

[0109] The memory controller can be separate or integrated into an external processor chip, such as a CPU chip, a GPU chip, or an SoC chip.

[0110] The memory described above can be a Low Power Double Data Rate (LPDDR) memory or any other memory that meets this architecture. In the case of an LPDDR memory, the memory control can be a DDR controller.

[0111] Figures 8a to 8d Schematic diagrams of various connection relationships between multiple dies are shown. For simplicity, Figure 8a and Figure 8d a description is given with four dies as an example, and the internal structure of each die is ignored.

[0112] As Figure 8a shown, the communication paths are set between every two dies. As Figure 8a shown, die D1 is respectively connected to dies D2, D3, and D4; die D2 is respectively connected to dies D1, D3, and D4; die D3 is respectively connected to dies D1, D2, and D4; and die D4 is respectively connected to dies D1, D2, and D3.

[0113] The above Figure 8a shown embodiments are beneficial for forming backups. Once a die has a problem or is damaged, it will not affect the normal operation of other dies.

[0114] As Figure 8b shown, the communication paths connect the dies in a ring so that each die can communicate with its adjacent dies. As Figure 8b shown, die D1 is respectively connected to adjacent dies D2 and D3, die D2 is respectively connected to adjacent dies D1 and D4, die D3 is respectively connected to adjacent dies D1 and D4, and die D4 is respectively connected to adjacent dies D2 and D3.

[0115] The above Figure 8b shown connection method is beneficial for simplifying the connection relationships between dies, reducing the establishment of communication paths, and thus reducing the chip area. At the same time, signals can be conducted between dies. For example, when die D1 is the target die T-D, it can directly notify dies D2 and D3 as non-target dies, and through the transmission of die D2 or D3, it can notify die D4. In addition, even if Figure 8b one of the communication paths has a problem, it will not affect its signal transmission.

[0116] As Figure 8cAs shown, the communication paths form a star connection of the dies, including a central die and edge dies, where the central die is in a central position and the edge dies are connected to the central die. In Figure 8c , die D4 serves as the central die, which forms connections with the other edge dies D1 - D3 respectively. When die D4 becomes the target die T - D, it can directly notify the other dies D1 - D3 that are non - target dies; while when one of D1 - D3 becomes the target die T - D, it can notify the other dies through die D4. The above connection method can form as few communication paths as possible, which is beneficial to reducing the area of the chip.

[0117] As Figure 8d shown, the edge dies D1 - D3 are connected, so that each die has three communication paths with the other dies. Although in the case of 4 dies Figure 8a and Figure 8d are actually equivalent, for a larger number of dies, Figure 8a the connection method will appear more complex, while Figure 8d the connection method, while ensuring sufficient backup, also makes the connection of communication paths as few as possible to avoid an overly large chip area.

[0118] Figure 9 shows a schematic block diagram of a processor system according to another embodiment of the present disclosure.

[0119] As Figure 9 shown, the present disclosure also provides a processor system, including a processor chip and the memory described above. The processor chip is connected to the dies D1 - Dn. Among them, the processor chip sets the resistance values of the target termination resistor T - ODT, the non - target termination resistor NT - ODT, and / or the termination resistor of the processor chip according to different working modes of the target die T - D.

[0120] The above - mentioned processor chip may include a CPU chip, a GPU chip, or a SoC chip, etc.

[0121] According to an embodiment of the present disclosure, in the read mode, the termination resistor of the processor chip is set to be not greater than 120 ohm.

[0122] According to an embodiment of the present disclosure, the processor system is set to 240 / N, where N is an integer between 2 and 10.

[0123] According to an embodiment of the present disclosure, in the write mode, the termination resistor of the processor system is set to be disconnected.

[0124] The present disclosure also provides a board card, including: the memory described above; or including the package described above; or including the processor system described above.

[0125] The present disclosure also provides an electronic device, including: the memory described above; or including the package described above; or including the processor system described above; or including the board card described above.

[0126] Figure 10 The flowchart of a storage method executed on a memory according to another aspect of the present disclosure is shown.

[0127] As Figure 10 shown, there are at least three die D1-Dn, each die including a termination resistor ODT1-ODTn, and a communication path is provided between the die D1-Dn; wherein, one of the die D1-Dn is a target die T-D, the termination resistor of this target die T-D is a target termination resistor T-ODT, and the other die are non-target die NT-D, the termination resistor of this non-target die NT-D is a non-target termination resistor NT-ODT, and the operating modes of the target termination resistor T-D include a read mode and a write mode.

[0128] The method includes: in operation S1010, sending a notification signal from the target die T-D to the non-target die NT-D to notify the non-target die NT-D of the operating mode of the target die NT-D.

[0129] According to another embodiment of the present disclosure, the above storage method may further include: in operation S1020, when the non-target die NT-D responds to receiving the notification signal from the target die T-D, setting the non-target termination resistor NT-ODT to different resistance values according to the different operating modes of the target die T-D.

[0130] Other operation steps of the storage method of the present disclosure can be obtained in combination with the above Figures 1a - 9 description and will not be elaborated here.

[0131] Figure 11 A combined processing device 1100 is also disclosed to describe a specific application scenario of the memory of the present disclosure. The combined processing device 1100 includes a computing device 1102, a general interconnection interface 1104, other processing devices 1106, and a storage device 1108, and the storage device may be or may include the memory described above. The computing device interacts with other processing devices to jointly complete the operations specified by the user.

[0132] Other processing devices, including one or more types of general-purpose / special-purpose processors such as a central processing unit (CPU), a graphics processing unit (GPU), and a neural network processor. The number of processors included in the other processing devices is not limited. The other processing device serves as an interface for machine learning computing devices to external data and control, including data transfer, and completes basic controls such as starting and stopping the machine learning computing device; the other processing device can also cooperate with the machine learning computing device to jointly complete computing tasks.

[0133] A general-purpose interconnect interface for transmitting data and control instructions between a computing device (including, for example, a machine learning computing device) and other processing devices. The computing device obtains the required input data from the other processing device and writes it into the storage device on the chip of the computing device; it can obtain control instructions from the other processing device and write them into the control cache on the chip of the computing device; it can also read the data in the storage module of the computing device and transmit it to the other processing device.

[0134] The storage device 1108 is respectively connected to the computing device and the other processing device. The storage device 1108 is used to store data in the computing device and the other processing device, especially suitable for data that cannot be fully stored in the internal storage of the computing device or the other processing device for the required operations.

[0135] This combined processing device can be used as a system-on-chip (SOC) for devices such as mobile phones, robots, drones, and video surveillance devices, effectively reducing the core area of the control part, improving the processing speed, and reducing the overall power consumption. In this case, the general-purpose interconnect interface of the combined processing device is connected to certain components of the device. Certain components such as cameras, displays, mice, keyboards, network cards, and Wi-Fi interfaces.

[0136] In some embodiments, the present disclosure also discloses a chip, which includes the above storage device or combined processing device.

[0137] In some embodiments, the present disclosure also discloses a chip packaging structure, which includes the above chip.

[0138] In some embodiments, the present disclosure also discloses an electronic device or apparatus, which includes the memory described in the present disclosure.

[0139] The electronic device or apparatus includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device.

[0140] The transportation means include airplanes, ships, and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical devices include nuclear magnetic resonance instruments, B-ultrasound instruments, and / or electrocardiogram instruments.

[0141] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that this disclosure is not limited by the described action sequence, because according to this disclosure, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0142] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0143] In several embodiments provided by this disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, optical, acoustic, magnetic, or other forms.

[0144] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0145] In addition, in each embodiment of this disclosure, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software program modules.

[0146] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of this disclosure can be embodied in the form of a software product, the computer software product is stored in a memory and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this disclosure. The aforementioned memory includes various media that can store program codes, such as USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks, or optical discs.

[0147] The above has introduced the embodiments of this disclosure in detail. Specific examples are used in this article to elaborate on the principles and implementation manners of this disclosure. The description of the above embodiments is only used to help understand the method and its core idea of this disclosure; at the same time, for those of ordinary skill in the art, according to the idea of this disclosure, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this disclosure.

[0148] The content of this disclosure can be more clearly understood according to the following clauses.

[0149] Clause A1. A memory, comprising:

[0150] At least three die (D1 - Dn), each die including a termination resistor (ODT1 - ODTn), and a communication path is provided between the die (D1 - Dn);

[0151] Wherein,

[0152] One of the die (D1 - Dn) is a target die (T - D), the termination resistor of this target die (T - D) is a target termination resistor (T - ODT), the other die are non - target die (NT - D), the termination resistor of this non - target die (NT - D) is a non - target termination resistor (NT - ODT), and the operating modes of the target termination resistor (T - D) include a read mode and a write mode;

[0153] The target die (T - D) sends a notification signal to the non - target die (NT - D) through the communication path to notify the non - target die (NT - D) of the operating mode of the target die (NT - D).

[0154] Clause A2. The memory according to Clause A1, wherein the non-target die (NT-D) is configured to set the non-target output driver termination (NT-ODT) to different resistance values in response to receiving the notification signal from the target die (T-D), depending on the operating mode of the target die (T-D).

[0155] Clause A3. The memory according to Clause A1 or A2, wherein the notification signal is a step signal including a leading edge and a trailing edge, the step signal is issued in the read mode, and the leading edge of the step signal occurs before the start of data transfer in the read mode of the target die (T-D), and the trailing edge occurs after the end of data transfer in the read mode of the target die (T-D).

[0156] Clause A4. The memory according to any one of Clauses A1 - A3, wherein the resistance value of the target output driver termination (T-ODT) is set to be not lower than the resistance value of the non-target output driver termination (NT-ODT).

[0157] Clause A5. The memory according to any one of Clauses A1 - A4, wherein the target output driver termination (T-ODT) is disconnected.

[0158] Clause A6. The memory according to any one of Clauses A1 - A5, wherein in the read mode, the resistance value of the non-target output driver termination (NT-ODT) is set to be not less than 60 ohm.

[0159] Clause A7. The memory according to any one of Clauses A1 - A6, wherein in the read mode, the non-target output driver termination (NT-ODT) is set to be disconnected.

[0160] Clause A8. The memory according to any one of Clauses A1 - A7, wherein in the write mode, the resistance value of the non-target output driver termination (NT-ODT) is set to be not greater than 120 ohm.

[0161] Clause A9. The memory according to any one of Clauses A1 - A8, wherein the resistance value of the non-target output driver termination (NT-ODT) is set to any one of 240 / N ohm, where N is any integer from 2 to 10.

[0162] Clause A10. The memory according to any one of Clauses A1 - A9, wherein the communication path is provided between every two dies (D1 - Dn).

[0163] Clause A11. The memory according to any one of Clauses A1 - A10, wherein the communication path forms a ring connection of the dies (D1 - Dn) such that each die can communicate with its adjacent die.

[0164] Clause A12. The memory according to any one of Clauses A1 - A11, wherein the communication path forms a star connection of the dies (D1 - Dn), including a central die and edge dies, wherein the central die is in a central position and the edge dies are connected to the central die.

[0165] Clause A13. The memory according to any one of Clauses A1 - A12, wherein the adjacent edge dies are connected to each other.

[0166] Clause A14. The memory according to any one of Clauses A1 - A13, wherein the communication path is a single bidirectional communication path.

[0167] Clause A15. The memory according to any one of Clauses A1 - A14, wherein the communication path is two reverse unidirectional communication paths.

[0168] Clause A16. The memory according to any one of Clauses A1 - A15, further comprising a mode register (MR), wherein a parameter list is stored in the mode register such that the memory can set at least the multiple dies (D1 - Dn) according to the parameter list.

[0169] Clause A17. The memory according to any one of Clauses A1 - A16, further comprising a memory controller, wherein the memory controller is connected to the multiple dies (D1 - Dn) and is configured to control the resistance value of the target output driver termination (T - ODT) of the target die (T - D).

[0170] Clause A18. The memory according to any one of Clauses A1 - A17, wherein the controller is further configured to control the resistance value of the non - target output driver termination (NT - ODT) of the non - target die (NT - D).

[0171] Clause A19. The memory according to any one of Clauses A1 - A18, wherein the memory is a low - power double - data - rate memory LPDDR.

[0172] Clause A20. An encapsulation, comprising the memory according to any one of Clauses A1 - A19, wherein the communication path is disposed inside the encapsulation and directly connects the dies (D1 - Dn).

[0173] Clause A21. An encapsulation body includes the memory described in any one of Clauses A1 - A19. Wherein, external terminals are provided outside the encapsulation body, and the communication path connects the die (D1 - Dn) through the external terminals.

[0174] Clause A22. A processor system includes a processor chip and the memory described in any one of Clauses A1 - A19. The processor chip is connected to the die (D1 - Dn). Wherein, the processor chip sets the resistance values of the target termination resistor (T - ODT) and the non - target termination resistor (NT - ODT), and / or the termination resistor of the processor chip according to different operating modes of the target die (T - D).

[0175] Clause A23. The processor system according to Clause A22, wherein the processor chip includes a CPU chip, a GPU chip or an SoC chip.

[0176] Clause A24. The processor system according to Clause A22 or A23, wherein in the read mode, the termination resistor of the processor chip is set to be not greater than 120 ohm.

[0177] Clause A25. The processor system according to any one of Clauses A22 - A24, wherein the processor system is set to 240 / N, where N is an integer between 2 and 10.

[0178] Clause A26. The processor system according to any one of Clauses A22 - A25, wherein in the write mode, the termination resistor of the processor system is set to be disconnected.

[0179] Clause A27. A board card includes:

[0180] The processor system according to any one of Clauses A1 - A19; or

[0181] The encapsulation body according to Clause A20 or A21; or

[0182] The processor system according to any one of Clauses A22 - A26.

[0183] Clause A28. An electronic device includes:

[0184] The processor system according to any one of Clauses A1 - A19; or

[0185] The encapsulation body according to Clause A20 or A21; or

[0186] The processor system according to any one of Clauses A22 - A26; or

[0187] The board card as described in Clause A27.

[0188] Clause A29. A storage method executed on a memory, the memory including: at least three die (D1 - Dn), each die including a termination resistor (ODT1 - ODTn), a communication path being provided between the die (D1 - Dn); wherein, one of the die (D1 - Dn) is a target die (T - D), the termination resistor of this target die (T - D) is a target termination resistor (T - ODT), the other die are non - target die (NT - D), the termination resistor of this non - target die (NT - D) is a non - target termination resistor (NT - ODT), the operating modes of the target termination resistor (T - D) include a read mode and a write mode;

[0189] The method includes:

[0190] Sending a notification signal from the target die (T - D) to the non - target die (NT - D) to notify the non - target die (NT - D) of the operating mode of the target die (NT - D).

[0191] Clause A30. The storage method according to Clause A29, wherein, at the non - target die (NT - D), in response to receiving the notification signal from the target die (T - D), the non - target termination resistor (NT - ODT) is set to different resistance values according to the different operating modes of the target die (T - D).

[0192] Clause A31. The storage method according to Clause A29 or A30, wherein, the notification signal is a step signal, including a front step edge and a rear step edge, the step signal is issued in the read mode, and the front step edge of the step signal occurs before the start of data transmission in the read mode of the target die (T - D), and the rear step edge occurs after the end of data transmission in the read mode of the target die (T - D).

[0193] Clause A32. The storage method according to any one of Clauses A29 - A31, wherein, the resistance value of the target termination resistor (T - ODT) is set to be not lower than the resistance value of the non - target termination resistor (NT - ODT).

[0194] Clause A33. The storage method according to any one of Clauses A29 - A32, wherein, the target termination resistor (T - ODT) is disconnected.

[0195] Clause A34. The storage method according to any one of Clauses A29 - A33, wherein, in the read mode, the resistance value of the non - target termination resistor (NT - ODT) is set to be not less than 60 ohm.

[0196] Clause A35. The storage method according to any one of Clauses A29 - A34, wherein, in the read mode, the non-target terminal resistor (NT-ODT) is set to be disconnected.

[0197] Clause A36. The storage method according to any one of Clauses A29 - A35, wherein, in the write mode, the resistance value of the non-target terminal resistor (NT-ODT) is set to be not greater than 120 ohm.

[0198] Clause A37. The storage method according to any one of Clauses A29 - A36, wherein the resistance value of the non-target terminal resistor (NT-ODT) is set to any one of 240 / N ohm, where N is any integer from 2 to 10.

[0199] Clause A38. The storage method according to any one of Clauses A29 - A37, wherein the communication path is set between every two die (D1 - Dn).

[0200] Clause A39. The storage method according to any one of Clauses A29 - A38, wherein the communication path forms a ring connection of the die (D1 - Dn) so that each die can communicate with its adjacent die.

[0201] Clause A40. The storage method according to any one of Clauses A29 - A39, wherein the communication path forms a star connection of the die (D1 - Dn), including a central die and edge dies, wherein the central die is in the central position and the edge dies are connected to the central die.

[0202] Clause A41. The storage method according to any one of Clauses A29 - A40, wherein the adjacent edge dies are connected.

[0203] Clause A42. The storage method according to any one of Clauses A29 - A41, wherein the communication path is a single bidirectional communication path.

[0204] Clause A43. The storage method according to any one of Clauses A29 - A42, wherein the communication path is two reverse unidirectional communication paths.

[0205] Clause A44. The storage method according to any one of Clauses A29 - A43, the memory further includes a mode register (MR), and a parameter list is stored in the mode register so that the memory can set at least the multiple die (D1 - Dn) according to the parameter list.

[0206] Clause A45. The storage method according to any one of Clauses A29 - A44 further includes controlling the resistance value of the target output driver termination (T-ODT) of the target die (T-D) through a storage controller connected to the plurality of dies (D1 - Dn).

[0207] Clause A46. The storage method according to any one of Clauses A29 - A45, wherein the resistance value of the non-target output driver termination (NT-ODT) of the non-target die (NT-D) is controlled by the controller.

[0208] Clause A47. The storage method according to any one of Clauses A29 - A46, wherein the memory is a low power double data rate memory LPDDR.

Claims

1. A memory device, comprising: At least three die (D1-Dn), each die including a termination resistor (ODT1-ODTn), and a communication path is provided between the die (D1-Dn); Wherein, One of the die (D1-Dn) is a target die (T-D), the termination resistor of the target die (T-D) is a target termination resistor (T-ODT), and the other die are non-target die (NT-D), the termination resistor of the non-target die (NT-D) is a non-target termination resistor (NT-ODT), and the operating modes of the target termination resistor (T-D) include a read mode and a write mode; The target die (T-D) sends a notification signal to the non-target die (NT-D) through the communication path to notify the non-target die (NT-D) of the operating mode of the target die (NT-D); Wherein, the notification signal is a step signal, including a front step edge and a rear step edge, the step signal is issued in the read mode, and the front step edge of the step signal occurs before the start of data transmission in the read mode of the target die (T-D), and the rear step edge occurs after the end of data transmission in the read mode of the target die (T-D).

2. The memory according to claim 1, wherein, The non-target die (NT-D) is configured to, in response to receiving the notification signal from the target die (T-D), set the non-target termination resistor (NT-ODT) to different resistance values according to the different operating modes of the target die (T-D).

3. The memory according to claim 1, wherein The resistance value of the target termination resistor (T-ODT) is set to be not lower than the resistance value of the non-target termination resistor (NT-ODT).

4. The memory according to claim 3, wherein, The target termination resistor (T-ODT) is disconnected.

5. The memory according to claim 1, wherein, In the read mode, the resistance value of the non-target termination resistor (NT-ODT) is set to be not less than 60 ohm.

6. The memory according to claim 5, wherein, In the read mode, the non-target termination resistor (NT-ODT) is set to be disconnected.

7. The memory according to claim 1, wherein, In the write mode, the resistance value of the non-target termination resistor (NT-ODT) is set to be not greater than 120 ohm.

8. The memory according to claim 7, wherein The resistance value of the non-target termination resistor (NT-ODT) is set to any one of 240 / N ohm, where N is any integer from 2 to 10.

9. The memory according to claim 1, wherein The communication path is provided between every two die (D1-Dn).

10. The memory according to claim 1, wherein, The communication path forms a ring connection of the die (D1-Dn) so that each die can communicate with its adjacent die.

11. The memory according to claim 1, wherein, The communication path forms a star connection of the die (D1-Dn), including a central die and edge die, wherein the central die is in a central position and the edge die are connected to the central die.

12. The memory according to claim 11, wherein, Adjacent edge die are connected.

13. The memory according to claim 1, wherein, The communication path is a single bidirectional communication path.

14. The memory according to claim 1, wherein, The communication path is two reverse unidirectional communication paths.

15. The memory device according to claim 1, further comprising a mode register (MR), and a parameter list is stored in the mode register so that the memory device can set the die (D1-Dn) according to the parameter list.

16. The memory according to claim 1 further includes a memory controller, which is connected to the dies (D1-Dn) and configured to control the resistance value of the target output driver termination (T-ODT) of the target die (T-D).

17. The memory according to claim 16, wherein, The controller is further configured to control the resistance value of the non-target output driver termination (NT-ODT) of the non-target die (NT-D).

18. The memory according to claim 1, wherein, The memory is a low power double data rate memory LPDDR.

19. An encapsulation body, comprising the memory according to any one of claims 1-18, wherein, The communication path is disposed inside the package and directly connects the dies (D1-Dn).

20. An encapsulation body, comprising the memory according to any one of claims 1-18, wherein, External terminals are provided outside the package, and the communication path connects the dies (D1-Dn) through the external terminals.

21. A processor system, comprising a processor chip and a memory as described in any one of claims 1-18, wherein the processor chip is connected to the die (D1-Dn), where, The processor chip sets the resistance value of the target output driver termination (T-ODT), the non-target output driver termination (NT-ODT), and / or the output driver termination of the processor chip according to different operating modes of the target die (T-D).

22. The processor system according to claim 21, wherein, The processor chip includes a CPU chip, a GPU chip, or a SoC chip.

23. The processor system according to claim 21, wherein, In the read mode, the output driver termination of the processor chip is set to be no greater than 120 ohm.

24. The processor system according to claim 23, wherein, The processor system is set to 240 / N, where N is an integer between 2 and 10.

25. The processor system according to any one of claims 21-24, wherein, In the write mode, the output driver termination of the processor system is set to be disconnected.

26. A board card, comprising: The memory according to any one of claims 1-18; Or The package according to claim 19 or 20; Or The processor system according to any one of claims 22-25.

27. An electronic device, comprising: The memory according to any one of claims 1-18; Or The package according to claim 19 or 20; Or The processor system according to any one of claims 21-25; or The board card according to claim 26.

28. A storage method performed on a memory, the memory comprising: At least three dies (D1-Dn), each die includes an output driver termination (ODT1-ODTn), and a communication path is provided between the dies (D1-Dn); wherein, one of the dies (D1-Dn) is a target die (T-D), the output driver termination of the target die (T-D) is the target output driver termination (T-ODT), the other dies are non-target dies (NT-D), the output driver termination of the non-target die (NT-D) is the non-target output driver termination (NT-ODT), and the operating modes of the target output driver termination (T-D) include a read mode and a write mode; The method includes: Sending a notification signal from the target die (T-D) to the non-target die (NT-D) to notify the non-target die (NT-D) of the operating mode of the target die (NT-D); Wherein, the notification signal is a step signal, including a front step edge and a rear step edge, the step signal is issued in the read mode, and the front step edge of the step signal occurs before the start of data transmission in the read mode of the target die (T-D), and the rear step edge occurs after the end of data transmission in the read mode of the target die (T-D).

29. The storage method according to claim 28, wherein, At the non-target die (NT-D), in response to receiving the notification signal from the target die (T-D), the non-target output driver termination (NT-ODT) is set to different resistance values according to different operating modes of the target die (T-D).

30. The storage method according to claim 28, wherein, Set the resistance value of the target output driver termination (T-ODT) to be not lower than the resistance value of the non-target output driver termination (NT-ODT).

31. The storage method according to claim 30, wherein, Disconnect the target output driver termination (T-ODT).

32. The storage method according to claim 28, wherein In the read mode, set the resistance value of the non-target output driver termination (NT-ODT) to be not less than 60 ohm.

33. The storage method according to claim 32, wherein In the read mode, set the non-target output driver termination (NT-ODT) to be disconnected.

34. The storage method according to claim 28, wherein, In the write mode, set the resistance value of the non-target output driver termination (NT-ODT) to be not greater than 120 ohm.

35. The storage method according to claim 34, wherein, Set the resistance value of the non-target output driver termination (NT-ODT) to any one of 240 / N ohm, where N is any integer from 2 to 10.

36. The storage method according to claim 28, wherein, Set the communication path between every two dies (D1-Dn).

37. The storage method according to claim 28, wherein The communication path forms a ring connection of the dies (D1-Dn) so that each die can communicate with its adjacent die.

38. The storage method according to claim 28, wherein, The communication path forms a star connection of the dies (D1-Dn), including a central die and peripheral dies, where the central die is in the central position and the peripheral dies are connected to the central die.

39. The storage method according to claim 38, wherein, Connect between adjacent peripheral dies.

40. The storage method according to claim 28, wherein, The communication path is a single bidirectional communication path.

41. The storage method according to claim 28, wherein The communication path is two reverse unidirectional communication paths.

42. The storage method according to claim 28, wherein the memory further includes a mode register (MR), and a parameter list is stored in the mode register so that the memory can set the dies (D1-Dn) according to the parameter list.

43. The storage method according to claim 28, further including controlling the resistance value of the target output driver termination (T-ODT) of the target die (T-D) through a storage controller connected to the dies (D1-Dn).

44. The storage method according to claim 43, wherein, Control the resistance value of the non-target output driver termination (NT-ODT) of the non-target die (NT-D) through the controller.

45. The storage method according to claim 28, wherein, The memory is a low power double data rate memory LPDDR.

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