Data transmission apparatus and method

Abstract

Data transmission apparatus and methods are provided. The data transmission apparatus comprises first and second lines and a transmitter configured to convert received binary data into ternary data and output the ternary data onto the first and second lines by switching only one of the first and second lines during each of a plurality of consecutive 2-bit data transmission time intervals. A receiver is also provided, the receiver being configured to receive the ternary data from the first and second lines and convert the received ternary data into binary data. The transmitter is configured to output the ternary data onto the first and second lines using return-to-zero switching during each 2-bit data transmission time interval.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0140135, filed on November 5, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a data transmission apparatus including an integrated circuit memory device and a method for operating the data transmission apparatus. Background Technology

[0003] Typically, semiconductor memory devices, already widely used in high-performance electronic systems, are increasing in both capacity and speed. As an example of a semiconductor memory device, Dynamic Random Access Memory (DRAM) is volatile memory and determines data based on the charge stored in a capacitor. Summary of the Invention

[0004] The example embodiments provide a data transmission device with reduced power consumption, a memory device including the data transmission device, and a method of operating the data transmission device.

[0005] According to some embodiments of the invention, the data transmission apparatus includes: first and second lines; and a transmitter configured to convert received binary data into ternary data, and to output ternary data to the first and second lines by switching only one of the first and second lines during each of a plurality of consecutive 2-bit data transmission time intervals. A receiver is also provided, configured to convert the ternary data received from the first and second lines back into binary data.

[0006] In some of these embodiments, the transmitter may be configured to use a return-to-zero switch to output ternary data to the first and second lines during each 2-bit data transmission time interval. Additionally, the transmitter may be configured to output each bit of the ternary data as a logic value within a group consisting of -1 corresponding to a first voltage level, 0 corresponding to a second voltage level, and 1 corresponding to a third voltage level. In some embodiments, the first voltage level is smaller than the second voltage level, and the second voltage level is smaller than the third voltage level.

[0007] The receiver can also be configured to convert four different combinations of ternary data into corresponding logical state pairs in the following logical state pairs: (0, 0), (0, 1), (1, 0), and (1, 1). Furthermore, the receiver may include a decoder configured to generate binary data by performing a NOR operation on each logical state pair.

[0008] According to a further embodiment of the invention, the method of transmitting data may include: (i) converting two consecutive bits of serially received binary data into ternary data, providing the ternary data to a pair of signal lines using a return-to-zero switching operation, wherein the return-to-zero switching operation is applied to only one of the pair of signal lines during each of a plurality of consecutive 2-bit data transmission time intervals; and then (ii) decoding the ternary data received on the pair of signal lines into binary data. Furthermore, during each 2-bit data transmission time interval, only the first signal line of the pair of signal lines is driven at a +1 logic level or a -1 logic level, while the second signal line of the pair of signal lines is driven at a reference logic level.

[0009] According to an additional embodiment, the data transmission apparatus includes: a first line; a second line; and a transmitter configured to: receive binary data, convert the binary data into ternary data, and output the converted ternary data to the first line and the second line. A receiver is also provided, configured to: receive ternary data via the first line and the second line, and convert the received ternary data into binary data. In some embodiments of these embodiments, when ternary data is transmitted to the first line and the second line, one of the first line and the second line is not switched.

[0010] According to another example embodiment, the memory device includes: a first transistor having a drain connected to a power supply terminal and a gate connected to a first local input / output line; a second transistor having a drain connected to the source of the first transistor and a gate of an inverted version connected to the first local input / output line; a third transistor having a drain connected to the source of the second transistor, a source connected to a ground terminal, and a gate for receiving a local sense amplifier enable signal; a fourth transistor having a drain connected to the source of the first transistor and a gate of an inverted version connected to a second local input / output line; a fifth transistor having a drain connected to the source of the fourth transistor, a source connected to a first global input / output line, and a gate for receiving a local sense amplifier enable signal; a sixth transistor having a drain connected to the source of the first transistor and a gate connected to the second local input / output line; and a seventh transistor having a drain connected to the source of the sixth transistor, a source connected to the second global input / output line, and a gate for receiving a local sense amplifier enable signal.

[0011] According to yet another embodiment, the data transmission operation method includes: converting binary data into ternary data using code mapping in a transmitter; and transmitting the converted ternary data in the transmitter via two lines. The code mapping uses a state where the lines are not simultaneously switched to map the ternary data corresponding to the binary data. Attached Figure Description

[0012] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 A data transmission apparatus according to an example embodiment is shown.

[0014] Figure 2 This illustrates data sent to two lines in a non-toggle manner according to an example embodiment.

[0015] Figure 3 A transmitter according to an example embodiment is shown.

[0016] Figure 4 A receiver according to an example embodiment is shown.

[0017] Figure 5 Show Figure 4 The ternary-to-bin (T-to-B) decoder in the middle.

[0018] Figure 6 A table illustrating the decoding process of the receiver according to an example embodiment is shown.

[0019] Figure 7 This is a flowchart illustrating the operation method of a transmitter according to an example embodiment.

[0020] Figure 8 This is a flowchart illustrating the operation method of the receiver according to an example embodiment.

[0021] Figure 9 A memory device according to another example embodiment is shown.

[0022] Figure 10 yes Figure 9 A detailed diagram of a portion of the memory array shown in the image.

[0023] Figure 11 Show Figure 10 The bit line sensing amplifier is shown in the figure.

[0024] Figure 12 Show Figure 11 The local sensing amplifier circuit is shown in the figure.

[0025] Figure 13 The binary data sent to the global input / output line according to an example embodiment is shown.

[0026] Figure 14 A transmitter for global input / output line signaling is shown according to an example embodiment.

[0027] Figure 15A receiver for global input / output line signaling is shown according to an example embodiment.

[0028] Figure 16 A decoding table for global input / output lines is shown according to an example embodiment.

[0029] Figure 17A , 17B Figures 17C and 17D illustrate examples of code mappings according to example embodiments.

[0030] Figure 18 A mobile device according to an example embodiment is shown. Detailed Implementation

[0031] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0032] Figure 1 A data transmission apparatus 100 according to an example embodiment is shown. (Refer to...) Figure 1 The data transmission device 100 may include a transmitter 110 and a receiver 120. The transmitter (TX) 110 may be configured to receive binary data and transmit ternary codes (also referred to as ternary data) corresponding to the binary data via two lines Q0 and Q1. The ternary code may be represented by one of "-1", "0", and "1". In an example embodiment, when the ternary data is "-1", the ternary data may have a first level. When the ternary data is "0", the ternary data may have a second level. When the ternary data is "1", the ternary data may have a third level. The first level may be lower than the second level, and the third level may be higher than the second level, where the second level may be a reference voltage level.

[0033] Transmitter 110 may include encoder 114, which receives binary data and uses a codemap to output a ternary code corresponding to the binary data. In one example embodiment, the codemap may be configured such that data causing simultaneous switching of the two lines Q0 and Q1 is not transmitted.

[0034] Receiver (RX) 120 can be configured to receive ternary code via two lines Q0 and Q1 and output binary data corresponding to the ternary code. Receiver 120 may include decoder 124, which receives ternary code and uses code mapping to output binary data corresponding to the ternary code. Figure 1 The transmitter 110 and receiver 120 shown can be implemented as a single integrated circuit, but this application is not limited thereto. The transmitter 110 and receiver 120 can each be implemented as a corresponding integrated circuit.

[0035] The data transmission apparatus 100 according to the example embodiment can convert two-bit binary data into ternary data, and can send the converted ternary data to two lines Q0 and Q1 using a code mapping that supports non-switching conditions. Therefore, the data transmission apparatus 100 can reduce the number of switching operations.

[0036] Figure 2 This illustrates data transmitted to two lines Q0 and Q1 in a non-toggle state, according to an example embodiment. (Refer to...) Figure 2 When the first line Q0 has the same voltage level as the reference voltage VREF and the second line Q1 has a voltage level lower than the reference voltage VREF, the two-bit binary data can correspond to "00". When either the first line Q0 or the second line Q1 is the reference voltage VREF, the ternary data is "0". When either the first line Q0 or the second line Q1 has a voltage level lower than the reference voltage VREF, the ternary data is "-1". Furthermore, when the first line Q0 has a voltage level lower than the reference voltage VREF and the second line Q1 has the same voltage level as the reference voltage VREF, the two-bit binary data can correspond to "10". Additionally, when the first line Q0 has the same voltage level as the reference voltage VREF and the second line Q1 has a voltage level higher than the reference voltage VREF, the two-bit binary data can correspond to "11". When either the first line Q0 or the second line Q1 has a voltage level higher than the reference voltage VREF, the ternary data is "1". Finally, when the first line Q0 has a level higher than the reference voltage VREF and the second line Q1 has the same level as the reference voltage VREF, the two bits of binary data can correspond to "01".

[0037] like Figure 2 As shown, the data transmitted in each of the two lines Q0 and Q1 can be a return-to-zero (RZ) signaling signal. For example, a reset period RST exists after transmitting two bits of data using ternary code. The level of the reset period RST can be the level of the reference voltage VREF, but this disclosure is not limited thereto. The data transmitted in each of the two lines Q0 and Q1 can be a non-return-to-zero (NRZ) signaling signal. It will be understood that, with... Figure 2 The binary data corresponding to the non-switching ternary data between the two lines Q0 and Q1 shown is only an example.

[0038] Figure 3 A transmitter 110 according to an example embodiment is shown. (Refer to...) Figure 3 The transmitter 110 may include transistors T1 to T7 and switches SW1 and SW2. For ease of description, in Figure 3 In this context, we will assume that two-bit binary data includes a first data bit D0 and a second data bit D1.

[0039] The first transistor T1 may have a drain connected to the power supply terminal VDD and a gate for receiving the first data bit D0. The second transistor T2 may have a drain connected to the source of the first transistor T1 and a gate for receiving the inverted version D0B of the first data bit D0. The third transistor T3 may have a drain connected to the source of the second transistor T2, a source connected to the ground terminal GND, and a gate for receiving the enable signal EN. The fourth transistor T4 may have a drain connected to the source of the first transistor T1 and a gate for receiving the inverted version D1B of the second data bit D1. The fifth transistor T5 may have a drain connected to the source of the fourth transistor T4, a source connected to the first line Q0, and a gate for receiving the enable signal EN. The sixth transistor T6 may have a drain connected to the source of the first transistor T1 and a gate for receiving the second data bit D1. The seventh transistor T7 may have a drain connected to the source of the sixth transistor T6, a source connected to the second line Q1, and a gate for receiving the enable signal EN.

[0040] The first switch SW1 can supply the precharge voltage VPRE to the first line Q0 in response to the precharge signal P_PRE. The second switch SW2 can supply the precharge voltage VPRE to the second line Q1 in response to the precharge signal P_PRE. It will be understood that... Figure 3 The configuration of transmitter 110 shown is merely an example according to an embodiment of the invention.

[0041] Figure 4 A receiver 120 according to an example embodiment is shown. (Refer to...) Figure 4 The receiver 120 may include a first comparator 121, a second comparator 122, and a T-to-B decoder 124 (i.e., a ternary-to-bin decoder).

[0042] The first comparator 121 can be configured to compare the voltage of the first line Q0 with the voltage of the second line Q1 and output a first comparison voltage F_DIFF. The first comparison voltage F_DIFF can be a differential voltage. The first comparator 121 can be referred to as a differential latch (Q1-Q0).

[0043] The second comparator 122 can be configured to compare the common voltage ((Q0+Q1) / 2) of the voltages of the first line Q0 and the second line Q1 with a reference voltage VREF, and output a comparison voltage F_CM. When using ternary code to transmit binary data, one of the voltages of the first line Q0 and the second line Q1 can be the reference voltage VREF. Alternatively, the second comparison voltage F_CM can be a common-mode voltage. The second comparator 122 can be referred to as a common-mode detector ((Q0+Q1) / 2). As shown, the first comparator 121 and the second comparator 122 can be activated in response to a clock signal CLK. The T-to-B decoder 124 can be configured to receive the first comparison voltage F_DIFF and the second comparison voltage F_CM, and output the corresponding binary data to the first data line D0 and the second data line D1.

[0044] Figure 5 Show Figure 4 The T-to-B decoder 124 in [the document / reference]. Figure 5 The T-to-B decoder 124 may include inverters INV1 to INV4 and transistors T8 to T12. The first inverter INV1 receives a second comparison voltage F_CM and inverts the second comparison voltage F_CM. The second inverter INV2 inverts the output value of the first inverter INV1 and sends the inverted output value to the first data line D0. The third inverter INV3 inverts the first comparison voltage F_DIFF. The fourth inverter INV4 inverts the second comparison voltage F_CM. The eighth transistor T8 may have a drain receiving the first comparison voltage F_DIFF, a source connected to the second data line D1, and a gate receiving the second comparison voltage F_CM. The ninth transistor T9 may have a source receiving the first comparison voltage F_DIFF, a drain connected to the second data line D1, and a gate receiving the output value of the fourth inverter INV4. The tenth transistor T10 may have a drain that receives the output value of the third inverter INV3, a source connected to the second data line D1, and a gate that receives the output value of the fourth inverter INV4. The eleventh transistor T11 may have a source that receives the output value of the third inverter INV3, a drain connected to the second data line D1, and a gate that receives the second comparison voltage F_CM. The twelfth transistor T12 may have a drain connected to the second data line D1, a source connected to the ground terminal GND, and a gate that receives the inverted version of the clock signal CLK, CLKB.

[0045] In one example embodiment, as shown, each of the eighth transistor T8, the tenth transistor T10, and the twelfth transistor T12 may include an n-channel metal-oxide-semiconductor field-effect transistor (FET), while each of the ninth transistor T9 and the eleventh transistor T11 may include a p-channel metal-oxide-semiconductor field-effect transistor (FET).

[0046] Figure 6 A table illustrating the decoding process of receiver 120 according to an example embodiment is shown. (Refer to...) Figure 6 The bit of the first data line D0 (i.e., the first data bit D0, where D0 represents the first data line when representing a data line and the bit when representing a bit) can be a value corresponding to the second comparison voltage F_CM. The bit of the second data line D1 (i.e., the second data bit D1, where D1 represents the second data line when representing a data line and the bit when representing a bit) can be a value obtained by performing an XNOR operation on the first comparison voltage F_DIFF and the second comparison voltage F_CM.

[0047] When the code value of the first line Q0 is "1" and the code value of the second line Q1 is "0", the value of the first comparison voltage F_DIFF is "0" and the value of the second comparison voltage F_CM is "1". Therefore, the decoded binary data (D1, D0) is "01". Furthermore, when the code value of the first line Q0 is "-1" and the code value of the second line Q1 is "0", the value of the first comparison voltage F_DIFF is "1" and the value of the second comparison voltage F_CM is "0". Therefore, the decoded binary data (D1, D0) is "00". And, when the code value of the first line Q0 is "0" and the code value of the second line Q1 is "1", the value of the first comparison voltage F_DIFF is "1" and the value of the second comparison voltage F_CM is "1". Therefore, the decoded binary data (D1, D0) is "11". Finally, when the code value of the first line Q0 is "0" and the code value of the second line Q1 is "-1", the value of the first comparison voltage F_DIFF is "0" and the value of the second comparison voltage F_CM is "0". Therefore, the decoded binary data is "10".

[0048] Figure 7 This is a flowchart illustrating an operation method of transmitter 110 according to an example embodiment. (Refer to...) Figures 1 to 7 The operation of transmitter 110 will be described below. Transmitter 110 can receive binary data. Transmitter 110 can use code mapping to convert the received binary data into ternary data (S110). The converted ternary data can be transmitted through two lines Q0 and Q1 (S120). The code mapping can be set so that no data is generated that switches between lines Q0 and Q1.

[0049] In the data transmission method according to the example embodiment, when transmitting serial data across two or more pins, two bits of binary data are converted to ternary data (-1, 0, 1) and then transmitted in a return-to-zero (RZ) manner to both lines. When both lines are switched, two bits of binary data can be transmitted using states other than those where neither line is switched. Therefore, when RZ transmission is performed via two-line pair encoding, the number of switching operations can be advantageously reduced by half compared to binary RZ transmission.

[0050] Figure 8 This is a flowchart illustrating an operation method of receiver 120 according to an example embodiment. (Refer to...) Figures 1 to 8 The operation of receiver 120 will be described below. Receiver 120 can receive ternary data via two lines Q0 and Q1 (S210). Receiver 120 can use code mapping to convert the received ternary data into binary data (S220). The data transmission scheme according to the example embodiment can be used to transmit internal data of dynamic random access memory (DRAM). For example, the data transmission scheme of this application can be applied to global input / output line (GIO) signaling in DRAM.

[0051] Figure 9 A memory device 200 according to another example embodiment is shown. (Refer to...) Figure 9 The memory device 200 may include a memory cell array 210, a row decoder 220, a column decoder 230, a sense amplifier circuit 240, an address register 250, a memory bank control logic 252, a refresh counter 254, a row address multiplexer 256, a column address latch 258, control logic 260, a timing control circuit 264, an input / output (I / O) gating circuit system 270, an error correction circuit 280, and a data input / output (I / O) buffer 282.

[0052] The memory cell array 210 may include first memory bank arrays 211 to eighth memory bank arrays 218. It will be understood that the number of memory bank arrays constituting the memory cell array 210 is not limited thereto. The row decoder 220 may include first memory bank row decoders 221 to eighth memory bank row decoders 228 respectively connected to the first memory bank arrays 211 to eighth memory bank arrays 218. The column decoder 230 may include first memory bank column decoders 231 to eighth memory bank column decoders 238 respectively connected to the first memory bank arrays 211 to eighth memory bank arrays 218. The sense amplifier circuit 240 may include first memory bank sense amplifiers 241 to eighth memory bank sense amplifiers 248 respectively connected to the first memory bank arrays 211 to eighth memory bank arrays 218. The first memory arrays 211 to 218, the first memory row decoders 221 to 228, the first memory column decoders 231 to 238, and the first memory sense amplifiers 241 to 248 can respectively constitute the first to eighth memory arrays. Each of the first memory arrays 211 to 218 may include a plurality of memory cells MC formed at the intersection of word line WL and bit line BL.

[0053] Address register 250 can receive and store address ADDR, which has bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the external memory controller. Address register 250 can provide the received bank address BANK_ADDR to the bank control logic 252, the received row address ROW_ADDR to the row address multiplexer 256, and the received column address COL_ADDR to the column address latch 258.

[0054] The memory bank control logic 252 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. Among the first memory bank row decoders 221 to the eighth memory bank row decoders 228, the memory bank row decoder corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal. Among the first memory bank column decoders 231 to the eighth memory bank column decoders 238, the memory bank column decoder corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0055] Row address multiplexer 256 can receive row address ROW_ADDR from address register 250 and refresh row address REF_ADDR from refresh counter 254. Row address multiplexer 256 can selectively output row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 256 can be applied to each of the first bank row decoders 221 to the eighth bank row decoders 228.

[0056] Among the first bank row decoders 221 to the eighth bank row decoders 228, the bank row decoder activated by the bank control logic 252 can decode the row address RA output from the row address multiplexer 256 to activate the word line corresponding to the row address RA. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0057] Column address latch 258 can receive column address COL_ADDR from address register 250 and can temporarily store the received column address COL_ADDR. Additionally, column address latch 258 can gradually increment the received column address COL_ADDR in burst mode. Column address latch 258 can apply the temporarily stored or gradually incremented column address COL_ADDR to each of the first bank column decoders 231 to the eighth bank column decoders 238. Among the first bank column decoders 231 to the eighth bank column decoders 238, the bank column decoder activated by bank control logic 252 can activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through input / output gating circuitry system 270.

[0058] Each input / output gating circuit in the input / output gating system 270, in addition to circuitry configured to gating input / output data, may also include input data mask logic, a read data latch, and a write driver. The read data latch is configured to store data output from the first memory array 211 to the eighth memory array 218, and the write driver is configured to write data to the first memory array 211 to the eighth memory array 218. Furthermore, the input / output gating system 270 may be... Figures 1 to 6 The data transmission device 100 and its data transmission scheme shown herein are used to implement this.

[0059] The codeword CW to be read from one of the memory arrays 211 to 218 can be sensed by a sense amplifier corresponding to that memory array and stored in a read data latch. The codeword CW stored in the read data latch can be provided to the memory controller via a data input / output buffer 282 after being ECC decoded by the error correction circuit 280. The data DQ to be written to one of the memory arrays 211 to 218 can be written to that memory array via a write driver after being ECC encoded by the error correction circuit 280.

[0060] The data input / output buffer 282 can provide data DQ to the error correction circuit 280 based on the clock signal CLK provided from the memory controller during a write operation, and can provide data DQ provided from the error correction circuit 280 to the memory controller during a read operation.

[0061] Error correction circuit 280 can generate parity bits based on the data bits of data DQ provided from data input / output buffer 282 during write operation, and can provide codeword CW including data DQ and parity bits to input / output gating circuit system 270, and input / output gating circuit system 270 can write codeword CW to memory bank array.

[0062] Additionally, error correction circuit 280 can receive a codeword CW read from a memory bank array from input / output gating circuit system 270 during a read operation. Error correction circuit 280 can perform ECC decoding on data DQ using parity bits included in the read codeword CW to correct at least one erroneous bit included in data DQ, and provide the corrected erroneous bit to input / output buffer 282.

[0063] Control logic circuitry 260 can be configured to control the operation of memory device 200. For example, control logic circuitry 260 can generate control signals that cause semiconductor memory device 200 to perform write or read operations. Control logic circuitry 260 may include command decoder 261 and mode register 262, command decoder 261 being configured to decode commands (CMD) received from memory controller, and mode register 262 being configured to set the operating mode of memory device 200.

[0064] For example, command decoder 261 can decode write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, etc., to generate operation control signals ACT, PCH, WR, and RD corresponding to command CMD. Control logic circuit 260 can provide operation control signals ACT, PCH, WR, and RD to timing control circuit 264. Control signals ACT, PCH, WR, and RD may include activation signal ACT, precharge signal PCH, write signal WR, and read signal RD. Timing control circuit 264 can generate a first control signal CTL1 controlling the voltage level of word line WL and a second control signal CTL2 controlling the voltage level of bit line BL in response to operation control signals ACT, PCH, WR, and RD, and can provide the first control signal CTL1 and the second control signal CTL2 to memory cell array 210.

[0065] Figure 10 yes Figure 9 A detailed diagram of a portion of the memory array is shown. (Refer to...) Figure 9 and Figure 10 The memory array includes a subarray block SCB, a bit line sense amplifier region BLSAB, a subword line driver region SWB, and a bonding region CONJ.

[0066] The subarray block SCB may include multiple word lines WL1 to WL4 extending in the row direction (first direction) and multiple bit line pairs BL1 to BL2 and BLB1 to BLB2 extending in the column direction (second direction). The subarray block SCB may include memory cells MC disposed at the intersections of the multiple word lines WL1 to WL4 and the multiple bit line pairs BL1 to BL2 and BLB1 to BLB2.

[0067] The sub-word line driver area SWB may include sub-word line drivers SWD, which are respectively configured to drive word lines WL1 to WL4. The sub-word line drivers SWD may be alternately located on the left and right sides of the subarray block SCB.

[0068] The bit line sense amplifier region BLSAB may include bit line sense amplifiers BLSA and local sense amplifier circuits LSA connected to bit line pairs BL1 to BL2 and BLB1 to BLB2. The bit line sense amplifiers BLSA amplify the difference between the voltage levels sensed by the bit line pairs BL and BLB, and provide the amplified difference to the local input / output pairs LIO and LIOB. The local sense amplifier circuits LSA control the connection between the local input / output pairs LIO1 and LIOB1 and the global input / output pairs GIO1 and GIOB1 in response to a gating enable signal GEN1 and a local control signal LCTL.

[0069] The local sense amplifier circuit LSA can control the connection between the local input / output pairs LIO2 and LIOB2 and the global input / output pairs GIO2 and GIOB2 in response to the corresponding gating enable signal and the corresponding local control signal.

[0070] In one example embodiment, such as Figure 8 As shown, the bit line sense amplifier (BLSA) can be alternately positioned above and below the subarray block (SCB). In one example embodiment, the combination region CONJ can be configured to be adjacent to the bit line sense amplifier region BLSAB, the subword line driver region SWB, and the subarray block (SCB). Block control circuitry can be located in the combination region CONJ. The block control circuitry can provide a gating enable signal GEN1 to the local sense amplifier circuit LSA in response to the enable signal EN1 and the select signal SEL1. The local sense amplifier circuit LSA can selectively provide or block connections to the global input / output pairs GIO1 and GIOB1 in response to the gating enable signal GEN1. Although Figure 10 This shows a portion of a memory bank array with a folded bitline structure, but with... Figure 10 The descriptions can be applied in essentially the same way to open bitline structures.

[0071] Figure 11 Show Figure 10 The bit line sensing amplifier BLSA is shown in the image. (Refer to...) Figure 11 The bit line sense amplifier 650 can be connected to bit lines BL and BLB of each of the memory cells 660 and 670 included in the memory cell array. The bit line sense amplifier 650 may include an N-type sense amplifier (NSA) 651, a P-type sense amplifier (PSA) 652, a precharge circuit 653, column selection switches 654a and 654b, an NSA driver 655, and a PSA driver 656.

[0072] The N-type sense amplifier 651 can discharge a low-potential bit line among bit lines BL and BLB during sensing operation. The N-type sense amplifier 651 may include NMOS transistors NM1 and NM2. The gate of NMOS transistor NM1 may be connected to bit line BLB, the drain of NMOS transistor NM1 may be connected to bit line BL, and the source of NMOS transistor NM1 may be connected to the sense enable line LAB. The gate of NMOS transistor NM2 may be connected to bit line BL, the drain of NMOS transistor NM2 may be connected to bit line BLB, and the source of NMOS transistor NM2 may be connected to the sense enable line LAB. The N-type sense amplifier 651 can discharge the low-potential bit line using a ground voltage VSS supplied to the sense enable line LAB. Based on data stored in memory cells 660 and 670, the low-potential bit line may be one of bit lines BL and BLB.

[0073] The P-type sense amplifier 652 can charge the high-potential bit line in bit lines BL and BLB to the supply voltage (VDD) level during sensing operation. The P-type sense amplifier 652 may include PMOS transistors PM1 and PM2. The gate of PMOS transistor PM1 is connected to bit line BLB, the source of PMOS transistor PM1 is connected to bit line BL, and the drain of PMOS transistor PM1 is connected to the sense enable line LA. The gate of PMOS transistor PM2 is connected to bit line BL, the source of PMOS transistor PM2 is connected to bit line BLB, and the drain of PMOS transistor PM2 is connected to the sense enable line LA. The P-type sense amplifier 652 can charge the high-potential bit line in bit lines BL and BLB using the supply voltage VDD provided to the sense enable line LA. In this case, the charging voltage VDD provided from the PSA driver 656 can be provided to the sense enable line LA to turn off transistor PM2, which has a gate connected to bit line BL, where the voltage increases through charge sharing.

[0074] Figure 12 Show Figure 11 The local sense amplifier circuit LSA is shown in the image. (Refer to...) Figure 12 The local sensing amplifier circuit 700 may include a local sensing amplifier 710, a local input / output line controller 720, and an activation control circuit 730. The activation control circuit 730 may perform an XOR operation on a first local sensing enable signal PLSAEN1, a first connection control signal PMUXON1, a second connection control signal PMUXON2, and a gating enable signal GEN1 to output a second local sensing enable signal PLSAEN2, a third connection control signal PMUXON3, and a fourth connection control signal PMUXON4. Therefore, depending on the logic level of the gating enable signal GEN1, the logic levels of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 may be maintained or inverted, and may be provided as the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4. The activation control circuit 730 may have first XOR gates to third XOR gates 731, 732, and 733.

[0075] The local sensing amplifier 710 can amplify the voltage difference between the local input / output line pairs LIO1 and LIOB1 in response to the second local sensing enable signal PLSAEN2, and can send the data corresponding to the amplified voltage difference to the global input / output line pairs GIO1 and GIOB1.

[0076] The local input / output line controller 720 may include first NMOS transistors to fourth NMOS transistors 721, 722, 723 and 724, and may control the connection between local input / output line pairs LIO1 and LIOB1 and global input / output line pairs GIO1 and GIOB1 in response to a third connection control signal PMUXON3 and a fourth connection control signal PMUXON4.

[0077] In one example embodiment, when each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 is high and the gating enable signal GEN1 is high, each of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 may be low. Therefore, the local sensing amplifier 710 is deactivated, and the local input / output line controller 720 can block the connection between the local input / output line pairs LIO1 and LIOB1 and the global input / output line pairs GIO1 and GIOB1.

[0078] In one example embodiment, when each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 is high and the gating enable signal GEN1 is low, each of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 may be high. Therefore, the local sensing amplifier 710 can be activated, and the local input / output line controller 720 can provide connectivity between local input / output line pairs LIO1 and LIOB1 and global input / output line pairs GIO1 and GIOB1.

[0079] The data transmission method of this application can be applied to data transmitted via global input / output lines. Therefore, 2-GIO can be ternary encoded to be represented as two bits, which will be referred to as multi-level single global input / output line (multi-level single GIO).

[0080] Figure 13 This illustrates binary data sent to global input / output lines GIO0 and GIO1 according to an example embodiment. (Refer to...) Figure 13The binary data "11" can be represented as the first global input / output line GIO0 having a gradually increasing level while the second global input / output line GIO1 is held at a constant level. The binary data "10" can be represented as the first global input / output line GIO0 being held at a constant level while the second global input / output line GIO1 has a gradually increasing level. The binary data "01" can be represented as the first global input / output line GIO0 having a gradually decreasing level while the second global input / output line GIO1 is held at a constant level. The binary data "00" can be represented as the first global input / output line GIO0 having a constant level while the second global input / output line GIO1 has a gradually decreasing level.

[0081] like Figure 13 As shown, the voltage difference ΔGIO between the first global input / output line GIO0 and the second global input / output line GIO1 can be used to distinguish data, and one of the first global input / output line GIO0 and the second global input / output line GIO1 is always non-switched.

[0082] Figure 14 A transmitter 272 for global input / output line signaling is shown according to an example embodiment. (Refer to...) Figure 14 Transmitter 272 can be used with Figure 3 It is implemented in the same way as the transmitter 110 shown in the diagram. Similar to... Figure 3 Unlike in China, in Figure 14 In this context, binary data consists of local input / output lines LIO0 and LIO2, and ternary data corresponding to the local input / output lines can be provided to global input / output lines GIO_0 and GIO_2.

[0083] The transmitter 272 according to the example embodiment may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The first transistor T1 has a drain connected to the power supply terminal VDD. The second transistor T2 has a drain connected to the source of the first transistor T1 and a gate connected to the inverted version LIO0B of the first local input / output line LIO0. The third transistor T3 has a drain connected to the source of the second transistor T2, a source connected to the ground terminal GND, and a gate for receiving the local sense amplifier enable signal LSA_EN. The fourth transistor T4 has a drain connected to the first transistor T1 and a gate connected to the first transistor T6. The first transistor T1 has a source and a drain, and a gate connected to the inverted version LIO2B of the second local input / output line LIO2. The fifth transistor T5 has a source and a drain connected to the source of the fourth transistor T4, a source connected to the first global input / output line GIO_0, and a gate that receives the local sense amplifier enable signal LSA_EN. The sixth transistor T6 has a source and a drain connected to the source of the first transistor T1 and a gate connected to the second local input / output line LIO2. The seventh transistor T7 has a source and a drain connected to the source of the sixth transistor T6, a source connected to the second global input / output line GIO_2, and a gate that receives the local sense amplifier enable signal LSA_EN. In one example embodiment, each of the first transistor T1 to the seventh transistor T7 may include an NMOS transistor.

[0084] In one example embodiment, transmitter 272 may further include a first switch SW1 and a second switch SW2, the first switch SW1 being configured to provide a global input / output line precharge voltage VGIOPRE to a first global input / output line GIO_0, and the second switch SW2 being configured to provide a global input / output line precharge voltage VGIOPRE to a second global input / output line GIO_2.

[0085] Figure 15 A receiver 274 for global input / output line signaling is shown according to an example embodiment. (Refer to...) Figure 15 Receiver 274 can be connected with Figure 4 It is implemented in the same way as the receiver 120 shown in the diagram. (Similar to...) Figure 4 Unlike in China, in Figure 15 In this configuration, receiver 274 receives ternary data from global input / output lines GIO_0 and GIO_2, and can perform a comparison operation in response to the enable signal IOSA_EN of the input / output sense amplifier to output binary data based on the comparison result.

[0086] Receiver 274 may include a differential comparator 274-1, a common-mode detector 274-2, and a decoder 274-4. The differential comparator 274-1 is configured to compare a first voltage of a first global input / output line GIO_0 with a second voltage of a second global input / output line GIO_2 in response to an input / output sense amplifier enable signal IOSA_EN. The common-mode detector 274-2 is configured to compare a common voltage of the first and second voltages with a reference voltage (e.g., the global input / output line precharge voltage VGIOPRE) in response to the input / output sense amplifier enable signal IOSA_EN. The decoder 274-4 is configured to receive a first output value IOSA_DIFF of the differential comparator 274-1 and a second output value IOSA_LVL of the common-mode detector 274-2, and output a first bit D0 (B_LIO0) and a second bit D1 (B_LIO2) corresponding to the first local input / output line LIO0 and the second local input / output line LIO2, respectively.

[0087] In one example embodiment, decoder 274-4 may perform an XNOR operation on the first output value IOSA_DIFF and the second output value IOSA_LVL to output the first bit B_LIO0 and the second bit B_LIO2 corresponding to the second output value IOSA_LVL.

[0088] Figure 16 The summary shown is based on embodiments of the invention. Figures 14 to 15 The transmitter and receiver logic performs operations on a decoding table. As shown, as described above, the four combinations of local input / output data LIO0, LIO2 (i.e., (1,1), (0,1), (1,0), and (0,0)) are converted into ternary data by transmitter 272. This ternary data is provided as the following "ternary" combinations to a pair of global input / output lines GIO_0, GIO_2: (0,1), (0,-1), (1,0), and (-1,0). Figures 15 to 16 As shown, these ternary combinations are converted by receiver 274 into the following combinations of the first output value IOSA_DIFF and the second output value IOSA_LVL: (0, 1), (1, 0), (1, 1), and (0, 0), and then decoded into the following binary data signals D1 and D0, where:

[0089] D1 = B_LIO2 = IOSA_LVL, and

[0090] D0=B_LIO0=XNOR(IOSA_LVL,IOSA_DIFF).

[0091] Figure 17A , 17BFigures 17C and 17D illustrate examples of code mappings according to exemplary embodiments. (See also...) Figure 17A , 17B 17C and 17D can have 16 cases related to the mapping of ternary data to binary data.

[0092] The first case corresponds to Figures 2 to 6 The code mapping described in the diagram. Ternary data sent to the corresponding lines in two lines Q0 and Q1 to correspond to binary data "11" are "0" and "1", ternary data sent to the corresponding lines in two lines Q0 and Q1 to correspond to binary data "10" are "1" and "0", ternary data sent to the corresponding lines in two lines Q0 and Q1 to correspond to binary data "01" are "-1" and "0", and ternary data sent to the corresponding lines in two lines Q0 and Q1 to correspond to binary data "00" are "0" and "-1".

[0093] In the second case, the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "11" are "1" and "0", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "10" are "0" and "1", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "01" are "0" and "-1", and the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "00" are "-1" and "0".

[0094] In the third case, the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "1", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "10" are "1" and "0", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "01" are "-1" and "0", and the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "00" are "0" and "-1".

[0095] In the fourth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "0" and "-1", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "-1" and "0".

[0096] In the fifth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "-1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "0" and "-1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "1" and "0", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "0" and "1".

[0097] In the sixth case, the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "-1", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "10" are "-1" and "0", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "01" are "1" and "0", and the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "00" are "0" and "1".

[0098] In the seventh case, the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "11" are "-1" and "0", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "10" are "0" and "-1", the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "01" are "0" and "1", and the ternary data sent to the corresponding lines in the two lines Q0 and Q1 to correspond to the binary data "00" are "1" and "0".

[0099] In the eighth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "-1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "-1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "0" and "1", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "1" and "0".

[0100] In the ninth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "-1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "0" and "1", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "0" and "-1".

[0101] In the tenth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" is "-1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" is "1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" is "0" and "1", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" is "0" and "-1".

[0102] In the eleventh case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "-1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "0" and "-1", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "0" and "1".

[0103] In the twelfth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "-1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "1" and "0", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "0" and "-1", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "0" and "1".

[0104] In the thirteenth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "0" and "-1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "1" and "0", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "-1" and "0".

[0105] In the fourteenth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "0" and "-1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "-1" and "0", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "1" and "0".

[0106] In the fifteenth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "-1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "0" and "1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "1" and "0", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "-1" and "0".

[0107] In the sixteenth case, the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "11" are "0" and "-1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "10" are "0" and "1", the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "01" are "-1" and "0", and the ternary data sent to the corresponding lines of the two lines Q0 and Q1 to correspond to the binary data "00" are "1" and "0".

[0108] The logic circuitry constituting the decoder of the receiver may include a first logic circuit configured to output a first data bit D0 and a second logic circuit configured to output a second data bit D1. The first logic circuitry may include an inverting (INV) arithmetic unit, and the second logic circuitry may include an XOR arithmetic unit, an XNOR arithmetic unit, or an INV arithmetic unit.

[0109] In each data reception method, current consumption can be reduced by half compared to pseudo-differential or single-ended methods, thus doubling the power efficiency while maintaining the same signal-VREF in receiver Rx.

[0110] The memory device according to the example embodiment can be applied to a mobile device. For example, Figure 18 A mobile device 3000 according to an example embodiment is shown. (Refer to...) Figure 18 The mobile device 3000 may include an application processor (AP) 3100, at least one DRAM 3210, at least one storage device 3300, at least one sensor 3400, a display device 3500, an audio device 3600, a network processor 3700, and at least one input / output device 3800. For example, the mobile device 3000 may be implemented as a laptop computer, mobile phone, smartphone, tablet PC, or wearable computer.

[0111] Application processor 3100 can be implemented to control the overall operation of mobile device 3000. Application processor 3100 can execute applications (such as web browsers, game applications, video players, etc.). According to example embodiments, application processor 3100 may include single-core or multi-core processors. For example, application processor 3100 may be a multi-core processor (such as a dual-core processor, quad-core processor, hexa-core processor, etc.). Application processor 3100 may also include internal or external cache memory.

[0112] Application processor 3100 may include controller (CNTL) 3110, neural processing unit (NPU) 3120, and interface (IF) 3130. In one example embodiment, NPU 3120 may optionally be provided.

[0113] In one example embodiment, the application processor 3100 may be implemented as a system-on-a-chip (SoC). The kernel of the operating system driven in the SoC may include a device driver configured to control the input / output (I / O) scheduler and the storage device 3300. The device driver may control the access performance of the storage device 3300, or control the CPU mode, dynamic voltage and frequency scaling (DVFS) level, etc., in the SoC, by referring to the number of synchronization queues managed in the I / O scheduler.

[0114] DRAM 3210 can be connected to controller 3110. DRAM 3210 can store data required for the operation of application processor 3100. For example, DRAM 3210 can temporarily store operating system (OS) and application data, or can be used as execution space for various software code.

[0115] As referenced above Figures 1 to 1As described in section 7, DRAM 3210 and DRAM 3220 can be configured to convert binary data into ternary data and send the converted ternary data to two lines. DRAM 3210 has relatively lower latency and greater bandwidth (BW) than I / O devices or flash memory. DRAM 3210 can be initialized during the power-on of the mobile device and can be used as space to load and temporarily store OS and application data, or as space to execute various software code. The mobile device performs multitasking operations by simultaneously loading several applications, and the switching and execution speed between applications can be used as a performance indicator of the mobile device. DRAM 3220 can be connected to NPU 3120. DRAM 3220 can store data related to artificial intelligence computing.

[0116] Storage device 3300 can be connected to interface 3130. In one example embodiment, interface 3130 may be driven by one of the following communication protocols: Dual Data Rate (DDR), DDR2, DDR3, DDR4, Low Power DDR (LPDDR), Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), High-Speed ​​Non-Volatile Memory (NVMe), High-Speed ​​Peripheral Component Interconnect (PCIe), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Universal Storage Bus (USB) Attached SCSI (UAS), Internet Small Computer System Interface (iSCSI), Fibre Channel, and Fibre Channel over Ethernet (FCoE). In one example embodiment, a single storage device 3300 may be included in a mobile device 3000 in an embedded form. In another example embodiment, a single storage device 3300 may be removably included in the mobile device 3000.

[0117] Storage device 3300 can be configured to store user data. For example, storage device 3300 can store data collected from sensor 3400, or it can store data network data, augmented reality (AR) / virtual reality (VR) data, and high-definition (HD) 4K content. Storage device 3300 may include at least one non-volatile memory device. For example, storage device 3300 may include a solid-state drive (SSD), an embedded multimedia card (eMMC), etc.

[0118] In one example embodiment, the storage device 3300 may be implemented as an additional chip in the application processor 3100, or may be implemented together with the application processor 3100 in a single package.

[0119] In one example embodiment, the storage device 3300 can be mounted using various types of packages. For example, the storage device 3300 can be mounted using packages such as PoP, BGA, CSP, PLCC, PDIP, die-in-waffle pack, die-in-wafer form, COB, CERDIP, MQFP, TQFP, SOIC, SSOP, TSOP, SIP, MCP, WFP, WSP, and WSP.

[0120] Sensor 3400 can be configured to sense the external environment of mobile device 3000. In one example embodiment, sensor 3400 may include an image sensor configured to sense an image. In this case, sensor 3400 may send the generated image information to application processor 3100. In another example embodiment, sensor 3400 may include a biosensor configured to detect biometric information. For example, sensor 3400 may detect fingerprints, iris patterns, vascular patterns, heart rate, blood glucose, etc., and may generate sensing data corresponding to the detected information. It will be understood that sensor 3400 is not limited to image sensors and biosensors. Sensor 3400 of this application may include any sensor (such as an illuminance sensor, an acoustic sensor, an accelerometer, etc.).

[0121] The display device 3500 can be configured to output data. For example, the display device 3500 can output image data sensed by the sensor 3400, or data calculated by the application processor 3100.

[0122] The audio device 3600 can be configured to output voice data to an external entity or detect external voice.

[0123] The network processor 3700 can be configured to communicate with external devices using either wired or wireless communication methods.

[0124] The input / output device 3800 can be configured to input data to or output data from the mobile device 3000. The input / output device 3800 may include devices configured to provide digital input and output functions (such as USB, storage devices, digital cameras, SD cards, touch screens, DVDs, modems, network adapters, etc.).

[0125] According to an example embodiment, the mobile device 3000 can transmit multi-level data so that it is not switched simultaneously to achieve low current and low power.

[0126] Figures 1 to 18 The data transmission method and apparatus described above transmit ternary codes via two lines. However, the transmission of ternary codes is not limited to this. The data transmission apparatus and method of this application can transmit ternary codes via three lines.

[0127] Already referred to Figures 1 to 18 A method for converting binary data into ternary data and sending the converted ternary data is described. However, this application is not limited to this. This application can be extended to a method for converting binary data into multi-level data other than ternary data and sending the converted multi-level data.

[0128] As described above, according to the example embodiment, ternary data that is not switched simultaneously can be sent to two lines to reduce the number of data lines and reduce power consumption during data transmission.

[0129] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A data transmission apparatus comprising: a pair of signal lines consisting of a first line and a second line; a transmitter configured to convert received binary data to ternary data and output the converted ternary data onto the first and second lines by switching only one of the first and second lines during each of a plurality of successive 2-bit data transmission time intervals; and a receiver configured to convert ternary data received from the pair of signal lines to binary data.

2. The data transmission device of claim 1, wherein, The transmitter is configured to output the ternary data onto the first and second lines using a return-to-zero switching during each 2-bit data transmission time interval.

3. The data transmission apparatus of claim 1 or claim 2, wherein, The transmitter is configured to output each bit of the ternary data as a logic value within a group consisting of -1 corresponding to a first voltage level, 0 corresponding to a second voltage level, and 1 corresponding to a third voltage level.

4. The data transmission apparatus of claim 3, wherein, The first voltage level is less than the second voltage level, and the second voltage level is less than the third voltage level.

5. The data transmission apparatus of claim 3, wherein, The receiver is configured to convert four different combinations of the ternary data to corresponding pairs of logic states from the following pairs of logic states: (0, 0), (0, 1), (1, 0), and (1, 1).

6. The data transmission apparatus of claim 5, wherein, The receiver includes a decoder configured to produce the binary data by performing an exclusive-OR operation on each pair of logic states.

7. A method of transmitting data comprising: converting two successive bits of serially received binary data to ternary data, providing the converted ternary data onto a pair of signal lines using a return-to-zero switching operation that is applied to only one of the pair of signal lines during each of a plurality of successive 2-bit data transmission time intervals; and decoding the ternary data received on the pair of signal lines into binary data.

8. The method of claim 7, wherein, During each 2-bit data transmission time interval, a first signal line of the pair of signal lines is driven with a reference logic level, a +1 logic level, or a -1 logic level, and a second signal line of the pair of signal lines is driven with only the reference logic level.

9. The method of claim 7 or claim 8, wherein, During the decoding, four different combinations of the ternary data are converted to corresponding pairs of logic states from the following pairs of logic states: (0, 0), (0, 1), (1, 0), and (1, 1).

10. A data transmission apparatus comprising: a pair of signal lines consisting of a first line and a second line; a transmitter configured to receive binary data, convert the binary data to ternary data, and output the converted ternary data to the first and second lines; and a receiver configured to receive ternary data through the pair of signal lines and convert the received ternary data to binary data, wherein when the converted ternary data is transmitted to the first and second lines, one of the first and second lines is not switched.

11. The data transmission device of claim 10, wherein, The ternary data is transmitted in a return-to-zero manner.

12. The data transmission device of claim 10 or claim 11, wherein, The ternary data is represented as one of "-1", "0", and "1", when the ternary data is "-1", the ternary data has a first level, when the ternary data is "0", the ternary data has a second level, and when the ternary data is "1", the ternary data has a third level. The ternary data has a third level when the ternary data is "1".

13. The data transmission device of claim 12, wherein, The first level is lower than the second level, The third level is higher than the second level, and The second level is a level of a reference voltage.

14. The data transmitting apparatus of claim 10, wherein, The transmitter includes an encoder configured to receive binary data and encode the received binary data into ternary data.

15. The data transmission device of claim 10, wherein, The transmitter includes: a first transistor having a drain connected to a power terminal and a gate receiving a first bit of binary data; a second transistor having a drain connected to a source of the first transistor and a gate receiving an inverted version of the first bit; a third transistor having a drain connected to a source of the second transistor, a source connected to a ground terminal, and a gate receiving an enable signal; a fourth transistor having a drain connected to a source of the first transistor and a gate receiving a second bit of binary data; a fifth transistor having a drain connected to a source of the fourth transistor, a source connected to a first line, and a gate receiving the enable signal; a sixth transistor having a drain connected to a source of the first transistor and a gate receiving the second bit; and a seventh transistor having a drain connected to a source of the sixth transistor, a source connected to a second line, and a gate receiving the enable signal.

16. The data transmission device of claim 15, wherein, The transmitter further includes: a first switch configured to provide a pre-charge voltage to the first line in response to a pre-charge signal; and a second switch configured to provide the pre-charge voltage to the second line in response to the pre-charge signal.

17. The data transmitting apparatus of claim 10, wherein, The receiver includes: a first comparator configured to compare a voltage of the first line and a voltage of the second line with each other in response to a clock signal; a second comparator configured to compare a common voltage of the first line and the second line and a reference voltage with each other in response to the clock signal; and a decoder configured to receive a first comparison voltage of the first comparator and a second comparison voltage of the second comparator, and output a first bit and a second bit of binary data.

18. The data transmission device of claim 17, wherein, The decoder calculates the first comparison voltage and the second comparison voltage to output the first bit.

19. The data transmitting apparatus of claim 17, wherein, The decoder outputs the second bit corresponding to the second comparison voltage.

20. The data transmission device of claim 17, wherein, The decoder includes: a first inverter connected to an output terminal of the second comparator and configured to invert the second comparison voltage; a second inverter configured to invert an output value of the first inverter to output the second bit; a third inverter connected to an output terminal of the first comparator and configured to invert the first comparison voltage; a fourth inverter connected to an output terminal of the second comparator and configured to invert the second comparison voltage; an eighth transistor having a drain connected to the output terminal of the first comparator, a source connected to the first data line, and a gate receiving the second comparison voltage; a ninth transistor having a source connected to the output terminal of the first comparator, a drain connected to the first data line, and a gate connected to an output terminal of the fourth inverter; a tenth transistor having a drain connected to an output terminal of the third inverter, a source connected to the first data line, and a gate connected to the output terminal of the fourth inverter; a twelfth transistor having a drain connected to the first data line, a source connected to a ground terminal, and a gate that receives an inverted version of the clock signal. and a twelfth transistor having a drain connected to the first data line, a source connected to a ground terminal, and a gate that receives an inverted version of the clock signal.

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