Integrated circuit comprising integrated standard cell structures

Abstract

An integrated circuit includes a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor; a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor, and a fourth first-type transistor; and a plurality of wiring layers disposed over the first standard cell and the second standard cell and including a first wiring layer, a second wiring layer, and a third wiring layer sequentially stacked. A source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected by a first power rail of the plurality of wiring layers, and a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected by a second power rail of the plurality of wiring layers.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0139527, filed on November 4, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This invention relates to an integrated circuit including an integrated standard cell structure. Background Technology

[0004] Integrated circuits can be designed based on standard cells. Specifically, the layout of the integrated circuit can be generated by arranging standard cells according to the data defining the integrated circuit and by connecting the arranged standard cells with wires. These standard cells are pre-designed and stored in a cell library.

[0005] As semiconductor manufacturing processes become miniaturized, the size of patterns in standard cells can be reduced, and the size of standard cells can also be reduced. Summary of the Invention

[0006] Various aspects of the present invention provide an integrated circuit that can improve the integration density of the layout and enhance the performance and reliability of the designed semiconductor device by utilizing multiple wiring layers to wire-connect the source terminals of transistors.

[0007] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the following detailed description of this disclosure.

[0008] According to embodiments of this disclosure, an integrated circuit includes: a first standard unit, the first standard unit including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor; a second standard unit, the second standard unit including a second first-type transistor, a second second-type transistor, a fourth second-type transistor, and a fourth first-type transistor; and a plurality of wiring layers disposed on the first standard unit and the second standard unit, the plurality of wiring layers including a first wiring layer, a second wiring layer, and a third wiring layer stacked sequentially. The source contacts of the first first-type transistor and the source contacts of the second first-type transistor are electrically connected through a first power rail of the plurality of wiring layers, the source contacts of the third first-type transistor and the source contacts of the fourth first-type transistor are electrically connected through a second power rail of the plurality of wiring layers, and the drain contacts of the first first-type transistor, the first second-type transistor, the third second-type transistor, and the third first-type transistor of the first standard unit, as well as the drain contacts of the second first-type transistor, the second second-type transistor, the fourth second-type transistor, and the fourth first-type transistor of the second standard unit, are all electrically connected through the first wiring layer, the second wiring layer, and the third wiring layer.

[0009] According to another embodiment of this disclosure, an integrated circuit includes: a first standard cell, the first standard cell including a first p-type transistor and a first n-type transistor; a second standard cell, the second standard cell being disposed adjacent to the first standard cell and including a second p-type transistor and a second n-type transistor; and a plurality of wiring layers disposed on the first standard cell and the second standard cell and including a first wiring layer, a second wiring layer, and a third wiring layer stacked sequentially. The source contacts of the first p-type transistor and the source contacts of the second p-type transistor are electrically connected through power rails of the plurality of wiring layers; the drain contacts of the first p-type transistor and the drain contacts of the first n-type transistor are connected to each other; the drain contacts of the second p-type transistor and the drain contacts of the second n-type transistor are connected to each other; the drain contacts of the transistors in the first standard cell and the second standard cell are electrically connected through wiring lines of the first wiring layer, the second wiring layer, and the third wiring layer; the wiring lines of the second wiring layer are configured to be parallel to each other in a first direction with respect to the drain contacts of the transistors in the first standard cell and the second standard cell; and the wiring lines of the first wiring layer and the wiring lines of the third wiring layer are configured to extend in a second direction perpendicular to the first direction.

[0010] According to other embodiments of this disclosure, an integrated circuit includes: a first standard unit, the first standard unit including a first first type transistor and a first second type transistor; a second standard unit, the second standard unit being disposed adjacent to the first standard unit in a first direction and including a second first type transistor and a second second type transistor; and a plurality of wiring layers formed on the first standard unit and the second standard unit, the plurality of wiring layers including a first wiring layer, a second wiring layer and a third wiring layer stacked in sequence. The source contacts of the first type of transistor and the second type of transistor are independently disposed, and the power rails of the plurality of wiring layers are electrically connected such that the source contacts of the first type of transistor and the second type of transistor are shared and the power supply voltage is applied. The first wiring line and the third wiring line of the first wiring layer are electrically connected to the drain contacts of the transistors of the first standard cell and the second standard cell and extend in the first direction. The second wiring line of the first wiring layer is electrically connected to the gate contacts of the transistors of the first standard cell and the second standard cell and extends in the first direction. The first wiring line and the third wiring line of the second wiring layer are electrically connected to the first wiring line and the third wiring line of the first wiring layer and extend in the second direction perpendicular to the first direction. The second wiring line of the second wiring layer is electrically connected to the second wiring line of the first wiring layer and extends in the second direction.

[0011] Other features and embodiments will become apparent from the following detailed description, drawings, and claims. Attached Figure Description

[0012] The above and other embodiments and features of this disclosure will become more apparent from the detailed description of the embodiments with reference to the accompanying drawings, wherein:

[0013] Figure 1 This is a top view showing an integrated circuit up to FEOL (front-end process) according to some embodiments.

[0014] Figure 2 It is according to some embodiments along Figure 1 A cross-sectional view taken from line A-A'.

[0015] Figure 3 It is a cross-sectional view taken along line B-B' according to some embodiments.

[0016] Figure 4 It is according to some embodiments along Figure 1 A cross-sectional view taken from line C-C'.

[0017] Figure 5 This is a top view showing an integrated circuit up to the MOL (Mid-Process) according to some embodiments.

[0018] Figure 6A and Figure 6B It is according to some embodiments along Figure 5 The cross-sectional view taken by line D-D'.

[0019] Figure 7A and Figure 7B According to some embodiments, it is achieved by cutting along the second direction Y. Figure 5 Various views can be seen from the source / drain contacts 170 and 170_1.

[0020] Figures 8 to 10 This is a top view showing an integrated circuit from MOL (Mid-Process) to BEOL (Back-Process) according to some embodiments.

[0021] Figure 11A and Figure 11B It is according to some embodiments along Figure 10 Other exemplary cross-sectional views taken by lines G-G' and H-H'.

[0022] Figure 12 It is along Figure 10 The cross-sectional view taken from line E-E'.

[0023] Figure 13 It is according to some embodiments along Figure 10 The cross-sectional view taken by line F-F'.

[0024] Figure 14 This is a top view showing an integrated circuit up to FEOL (front-end process) according to some embodiments.

[0025] Figure 15 This is a top view of an integrated circuit up to the first wiring layer according to some embodiments.

[0026] Figure 16 This is a top view showing an integrated circuit with a second wiring layer according to some embodiments.

[0027] Figure 17 This is a top view of an integrated circuit with a third wiring layer according to some embodiments. Detailed Implementation

[0028] In the following description, formation on a substrate ( Figure 2Integrated circuits of various embodiments are laid out on (e.g., a semiconductor substrate). The integrated circuits have a layout including various standard cells. Standard cells are integrated circuit structures pre-designed for reuse in the design of various integrated circuits. An effective integrated circuit design layout can include various pre-designed standard cells and predefined rules relating to the placement of standard cells to enhance circuit performance and reduce circuit area.

[0029] An integrated circuit according to some embodiments may include one or more standard cells arranged in the integrated circuit layout according to predefined rules. Such standard cells are reused in the integrated circuit design. Therefore, the standard cells are pre-designed according to manufacturing techniques and stored in a standard cell library. Integrated circuit designers can retrieve such standard cells and include them in the integrated circuit design, and can place them in the integrated circuit layout according to predefined placement rules.

[0030] Standard cells can include various basic circuit devices, such as inverters, AND, NAND, OR, XOR, and NOR converters commonly used in designing digital circuits for electronic devices (e.g., central processing unit (CPU), graphics processing unit (GPU), and system-on-a-chip (SoC) designs). Standard cells can also include other elements frequently used in circuit blocks, such as flip-flops and latches.

[0031] Figures 1 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figures 8 to 10 , Figure 11A , Figure 11B , Figure 12 and Figure 13 This is a diagram used to illustrate an integrated circuit according to some embodiments.

[0032] Figure 1 This is a top view showing an integrated circuit up to the front-end process (FEOL) according to some embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken from line AA. Figure 3 It is a cross-sectional view taken along line BB. Figure 4 It is along Figure 1 A cross-sectional view taken from line CC. For reference, in Figure 4 In this context, XX and YY can represent the cutting direction. Figure 5 This is a top view showing an integrated circuit up to the mid-process (MOL) according to some embodiments. Figure 6A and Figure 6B They are along Figure 5 The cross-sectional view taken by line D-D'. Figure 7A and Figure 7B By cutting along the second direction Y Figure 5 Various views can be seen from the source / drain contacts 170 and 170_1. Figures 8 to 10 This is a top view of an integrated circuit according to some embodiments, showing the process from intermediate stage (MOL) to final stage (BEOL). Figure 11A and Figure 11B It is along Figure 10 Other exemplary cross-sectional views taken by lines G-G' and H-H'. Figure 12 It is along Figure 10 The cross-sectional view taken from line E-E'. Figure 13 It is along Figure 10 The cross-sectional view taken by line F-F'.

[0033] Reference Figures 1 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figures 8 to 10 , Figure 11A , Figure 11B , Figure 12 and Figure 13 According to some embodiments, the integrated circuit 10 may include a first standard unit 20 and a second standard unit 22. Figure 1 In this process, two standard cells 20 and 22 that are adjacent to each other in the X direction can be divided based on the insulating gate 150.

[0034] In some embodiments, the first standard unit 20 may include four inverters having eight transistors, and the second standard unit 22 may include four inverters having eight transistors. Although both the first standard unit 20 and the second standard unit 22 are shown as having a four-inverter structure, the embodiments are not limited thereto. In some examples, both the first standard unit 20 and the second standard unit 22 may include two inverters having four transistors.

[0035] In integrated circuit manufacturing processes, FEOL (Feature-on-Line) process can be referred to as the process of forming individual components such as transistors, capacitors, and resistors on a substrate. For example, FEOL process can include planarizing and cleaning the wafer, forming trenches, forming wells, forming gate lines, forming source / drain electrodes, etc.

[0036] The substrate 100 may be a silicon substrate or silicon-on-insulator (SOI). Alternatively, the substrate 100 may include, but is not limited to, silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0037] Reference Figures 1 to 12A first active region (upper end 112) and a third active region (lower end 112) can be defined along a first direction X. The first active region (upper end 112) and the third active region (lower end 112) can be defined by a deep trench DT. The first active region (upper end 112) and the third active region (lower end 112) can be regions in which p-type transistors are formed. Both the first active region (upper end 112) and the third active region (lower end 112) can include, for example, well regions doped with n-type impurities.

[0038] Both the first active region (upper end 112) and the third active region (lower end 112) may include a first lower active region 112B, a first upper active region 112U, and a first nanosheet 112NS. The first lower active region 112B may have sidewalls defined by a deep trench DT. The first upper active region 112U may have fins protruding from the first lower active region 112B. The first upper active region 112U may have sidewalls defined by trenches shallower than the deep trench DT. The first nanosheet 112NS may be configured to be spaced apart from the first upper active region 112U. Although two first nanosheets 112NS are shown, this is only for illustrative purposes, and their number is not limited thereto.

[0039] The second active region 114 may be defined along the first direction X. It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. Unless the context otherwise indicates, these terms are used only to distinguish one element, component, region, layer, or portion from another, for example, as a naming convention. Therefore, without departing from the teachings of the invention, the first element, component, region, layer, or portion discussed below in one part of the specification may be referred to as the second element, component, region, layer, or portion in another part of the specification or in the claims. Additionally, in some cases, even if the terms "first," "second," etc., are not used in the specification, they may still be referred to as "first" or "second" in the claims to distinguish the different claimed elements. The second active region 114 may be defined as being spaced apart from the first active region 112 in a second direction Y that intersects (e.g., is substantially perpendicular to) the first direction X. The first active region 112 and the second active region 114 may be separated by a deep trench DT. The second active region 114 may be a region in which an n-type transistor is formed. The second active region 114 may include, for example, a well region doped with p-type impurities.

[0040] The second active region 114 may include a second lower active region 114B, a second upper active region 114U, and a second nanosheet 114NS. The second lower active region 114B may have sidewalls defined by a deep trench DT. The second upper active region 114U may have fins protruding from the second lower active region 114B. The second upper active region 114U may have sidewalls defined by trenches shallower than the deep trench DT. The second nanosheet 114NS may be configured to be spaced apart from the second upper active region 114U. Although two second nanosheets 114NS are shown, this is only for illustrative purposes, and their number is not limited thereto.

[0041] Each standard unit may include a first active region 112, a second active region 114, and a third active region 112.

[0042] An active region isolation film 105 may be formed on the substrate 100. The active region isolation film 105 may traverse between the first active region 112 and the second active region 114, and between the second active region 114 and the third active region 112. The active region isolation film 105 may extend along a first direction X. The active region isolation film 105 may fill the deep trench DT that divides the first active region 112 and the second active region 114 into a first standard cell.

[0043] A unit isolation film 106 may be formed on the substrate 100. The unit isolation film 106 may fill the deep trench DT that divides the first active region 112, the second active region 114, and the third active region 112 of the first standard unit, and the first active region 112, the second active region 114, and the third active region 112 of the second standard unit. The unit isolation film 106 may extend in a first direction X along the boundary between the first and second standard units. Both the active region isolation film 105 and the unit isolation film 106 may each include an insulating material.

[0044] The active region isolation membrane 105 and the cell isolation membrane 106 may include an insulating material filling the deep trench DT defining the first active region 112, the second active region 114, and the third active region 112. In the following description, the active region isolation membrane 105 may be an insulating material membrane disposed between the first active region 112 and the second active region 114 included in a single cell (hereinafter, a cell may be referred to as a standard cell) and between the second active region 114 and the third active region 112 included in a single cell. For example, the active region isolation membrane 105 may be interpreted as an insulating material membrane disposed within the cell. The cell isolation membrane 106 may be an insulating material membrane not disposed within the cell but extending along the cell boundary in a first direction X. For example, the cell isolation membrane 106 may be interpreted as an insulating material membrane disposed along the cell boundary.

[0045] An integrated circuit according to some embodiments may include a plurality of gate stacks 120 and a plurality of insulated gates 150. The gate stacks 120 and the insulated gates 150 may each extend along a second direction Y. The gate stacks 120 and the insulated gates 150 may be arranged to be adjacent to each other in a first direction X.

[0046] As an example, gate stacks 120 arranged adjacent to each other in the first direction X can be spaced apart by 1 CPP (contact polycrystalline pitch; it is referred to not only as "CPP" but also as "grid"). As another example, gate stacks 120 and insulating gates 150 arranged adjacent to each other can be spaced apart by 1 CPP.

[0047] For example, assuming there are first gate stacks and second gate stacks that are adjacent to each other, if the distance between the center line of the first gate stack extending along the second direction Y and the center line of the second gate stack extending along the second direction Y is 1 CPP, this may mean that there are no other gate stacks or insulating gates between the first gate stack and the second gate stack.

[0048] Gate stack 120 and insulating gate 150 may be disposed above the first active region 112, the second active region 114, and the third active region 112, respectively. Gate stack 120 and insulating gate 150 may intersect with the active region isolation film 105. A portion of gate stack 120 and a portion of insulating gate 150 may extend onto each cell isolation film 106.

[0049] exist Figure 13 In this configuration, gate stack 120 may include gate electrode 122, gate insulating film 124, gate spacer 126, and gate capping film 128. In some examples, gate stack 120 may not include gate capping film 128. Gate spacer 126 may define gate trenches in which gate insulating film 124 and gate electrode 122 may be formed. Gate spacer 126 may include, for example, an insulating material. Gate insulating film 124 may be formed along the periphery of first nanosheet 112NS. Although not shown, gate insulating film 124 may be formed along the periphery of second nanosheet 114NS. Gate insulating film 124 may include at least one of, for example, silicon oxide or a high dielectric constant material. The high dielectric constant material may be, for example, a material with a dielectric constant higher than silicon oxide. Gate electrode 122 may be formed on gate insulating film 124. Gate electrode 122 may encapsulate first nanosheet 112NS. Although not shown, gate electrode 122 may encapsulate second nanosheet. The gate electrode 122 may include at least one of, for example, a metal (intended to include metal alloys comprising two or more metals), a metal nitride, a metal carbide, a metal silicide, and a semiconductor material. A gate capping film 128 may be disposed on the gate electrode 122. The gate capping film 128 may include, for example, an insulating material.

[0050] The insulating gate 150 can divide at least a portion of the first active region 112 into separate sub-regions, at least a portion of the third active region 112 into separate sub-regions, and at least a portion of the second active region 114 into separate sub-regions. The insulating gate 150 may include, for example, an insulating material. Although the insulating gate 150 is shown as a single film, the embodiments are not limited thereto. For example, the insulating gate 150 may include a stacked structure having at least two films. Figure 2 As shown, the insulating gate 150 can separate the first upper active region 112U of the first and third active regions 112. Although the insulating gate 150 is shown as penetrating a portion of the first lower active region 112B of the first and third active regions 112, the embodiment is not limited thereto. To electrically isolate adjacent elements, the insulating gate 150 can completely separate the first lower active region 112B. Although not shown, the insulating gate 150 can separate the second upper active region 114U of the second active region 114 and can penetrate a portion of the second lower active region 114B. Considering the manufacturing process of forming the insulating gate 150, after removing at least a portion of the first active region 112 and at least a portion of the second active region 114, insulating material is filled in the portions of the second active region 114 and the first active region 112 that have been removed. Thus, the insulating gate 150 can be formed. Therefore, a portion of the sidewall of the insulating gate 150 can contact the first active region 112 and the second active region 114. A portion of the sidewall of the insulating gate 150 may contact a semiconductor material film included in the first active region 112 and the second active region 114.

[0051] exist Figure 3 In this configuration, the insulating gate 150 may intersect with the active region isolation film 105. The insulating gate 150 may be disposed on the active region isolation film 105. A portion of the insulating gate 150 may be recessed into the active region isolation film 105. During the formation of the insulating gate 150, a portion of the active region isolation film 105 may be removed. Therefore, a portion of the insulating gate 150 may be recessed into the active region isolation film 105. Gate spacers 126 may be disposed on the sidewalls of the insulating gate 150.

[0052] In an integrated circuit according to some embodiments, at least a portion of the insulating gate 150 may be located at the boundary of a standard cell extending along the second direction Y to separate adjacent standard cells. The insulating gate 150 may also be located inside a standard cell, in addition to being located at the boundary of the standard cell. However, hereinafter, the insulating gate 150 may be interpreted as being located at the boundary of a standard cell extending along the second direction Y.

[0053] exist Figure 2In this configuration, a semiconductor pattern 130 can be formed between adjacent gate stacks 120 and insulating gates 150. The semiconductor pattern 130 can be formed by removing a portion of active regions 112 and 114 to form a recess, and then filling the recess via an epitaxial process. The semiconductor pattern 130 can be formed on the first active region 112. Figure 6A and Figure 6B In this process, a semiconductor pattern 130 may be formed on the second active region 114. At least a portion of the semiconductor pattern 130 may be included in the source / drain regions of the transistor. The semiconductor pattern 130 formed on the first active region 112 may be doped with impurities of a different conductivity type than that of the semiconductor pattern 130 formed on the second active region 114. The semiconductor pattern 130 may also be formed adjacent to the insulating gate 150.

[0054] exist Figure 1 , Figure 3 and Figure 4 In this configuration, a cell gate dicing pattern 160 may be disposed on a cell isolation film 106. The cell gate dicing pattern 160 may extend along a first direction X. The cell gate dicing pattern 160 may extend along the boundary between a first standard cell and a second standard cell in the first direction X. A gate stack 120 and an insulating gate 150 may be disposed between cell gate dicing patterns 160 spaced apart from each other along a second direction Y. The cell gate dicing pattern 160 may include, for example, an insulating material.

[0055] The cell gate dicing pattern 160 can dice the gate stack 120 or the insulating gate 150 at the boundary of the cell. The cell gate dicing pattern 160 can contact the gate stack 120 and the insulating gate 150. The cell gate dicing pattern 160 can contact the short side of the gate stack 120 extending along the first direction X and the short side of the insulating gate 150 extending along the first direction X. The first standard cell 20 and the second standard cell 22 may also include the cell gate dicing pattern 160 formed along the boundary extending in the first direction X.

[0056] exist Figure 4 In this context, X-X' and Y-Y' can refer to the cutting direction. According to some embodiments, the gate insulating film 124 may not be formed on the sidewalls of the cell gate dicing pattern 160. Although not shown, according to some embodiments, the gate insulating film 124 may extend along the sidewalls of the cell gate dicing pattern 160. This difference can vary depending on the steps involved in forming the cell gate dicing pattern 160. When the cell gate dicing pattern 160 is formed after the gate electrode 122 is formed, as... Figure 4As shown, the gate insulating film 124 may not be formed on the sidewall of the cell gate dicing pattern 160. For example, when the cell gate dicing pattern 160 is formed before the formation of the gate electrode 122 (the molding gate step for forming the gate electrode 122), the gate insulating film 124 may extend along the sidewall of the cell gate dicing pattern 160.

[0057] The first standard cell 20 may include one or more gate stacks 120 disposed between insulating gates 150 at the boundary of the first standard cell. In Figure 1, the first standard cell may have a width of 3 CPP.

[0058] The second standard cell 22 may form a boundary with the first standard cell based on the insulating gate 150. The second standard cell 22 may include one or more gate stacks 120 disposed between the insulating gates 150 at the boundary of the second standard cell 22. In Figure 1, the second standard cell 22 may have a width of 3 CPP.

[0059] The first standard cell 20 may include a first active region 112, a second active region 114, and a third active region 112. The gate stack 120 included in the first standard cell 20 may intersect with the first active region 112, the second active region 114, and the third active region 112.

[0060] In some embodiments, Figure 5 In this embodiment, the first standard unit 20 may include a first p-type transistor 134, a first n-type transistor 138, a second n-type transistor 138, and a second p-type transistor 134. The second standard unit 22 may include a first p-type transistor 134, a first n-type transistor 138, a second n-type transistor 138, and a second p-type transistor 134. From a design perspective, for ease of layout of the active region, although the p-type active region and the n-type active region are arranged alternately, the transistors are arranged continuously in the order of p-type-n-n-p-type. However, this is only for ease of description, and it is obvious that this embodiment is also applicable to the following situation: impurity type exchange, so that p-type becomes n-type, and n-type becomes p-type.

[0061] The first p-type transistor 134 can be formed at the intersection of the gate stack 120 and the first active region 112, and the first n-type transistor 138 and the second n-type transistor 138 can be formed at the intersection of the gate stack 120 and the second active region 114, and the second p-type transistor 134 can be formed at the intersection of the gate stack 120 and the third active region 112. For example, both the first and second p-type transistors 134 may include a gate electrode 122, a first nanosheet 112NS as a channel region, and a semiconductor pattern 130 as a source / drain region.

[0062] The first p-type transistor 134 and the second p-type transistor 134 are formed on the first active region 112, and the first n-type transistor 138 and the second n-type transistor 138 are formed on the second active region 114.

[0063] Reference Figure 5 , Figure 6A , Figure 6B , Figure 7A and Figure 7B According to some embodiments, the integrated circuit may include source / drain contacts 170 and 170_1.

[0064] Source / drain contacts 170 and 170_1 may be disposed on the first active region 112, the second active region 114, and the third active region 112. Source / drain contacts 170 and 170_1 may be connected to a semiconductor pattern 130 formed on the first active region 112, the second active region 114, and the third active region 112. As used herein, the term "electrical connection" may be used to describe a term configured to allow an electrical signal to be transmitted from one item to another. In contrast, passive conductive components physically connected to an insulating layer (e.g., wiring, pads, internal wires, etc.) are not electrically connected to the component. Source / drain contacts 170 and 170_1 may include a normal source / drain contact 170 and an extended source / drain contact 170_1. The normal source / drain contact 170 may typically overlap with the first active region 112, the second active region 114, or the third active region 112. A portion of the extended source / drain contact 170_1 may extend onto the cell isolation film 106 and the cell gate dicing pattern 160. The extended source / drain contact 170_1 may be connected to a power rail, as described below. Figure 8 (195_1 and 195_2).

[0065] exist Figure 12 In this configuration, gate contact 175 is formed on gate electrode 122 of gate stack 120 and not on insulated gate 150. Gate contact 175 can be connected to gate stack 120. For example, gate contact 175 can be electrically connected to gate electrode 122 of gate stack 120.

[0066] Although not shown, gate contact 175 may be disposed on the first active region 112, the second active region 114, and the third active region 112. Alternatively, gate contact 175 may also be formed on the active region isolation film 105. In an integrated circuit according to some embodiments, at least one gate contact may be disposed at a location where it overlaps with one of the first active region 112, the second active region 114, and the third active region 112.

[0067] Reference Figure 5Each of the first standard cell 20 and the second standard cell 22 may further include a normal source / drain contact 170, an extended source / drain contact 170_1, and a gate contact 175. The normal source / drain contact 170 of the first standard cell 20 or the second standard cell 22 may be continuously arranged within each standard cell along the Y direction. For example, the extended source / drain contact 170_1 of the first standard cell 20 or the second standard cell 22 may be discontinuously arranged within each standard cell along the Y direction.

[0068] In integrated circuit manufacturing processes, the Modeling Online (MOL) process describes the process of forming individual components such as transistors, capacitors, and resistors on a contact substrate. For example, the MOL process may include forming source / drain contacts, etc.

[0069] exist Figure 6A In this configuration, the extended source / drain contact 170_1 may include a contact barrier film 170a and a contact fill film 170b. The contact fill film 170b may fill the trench defined by the contact barrier film 170a. For example, in... Figure 6B In this configuration, the contact barrier film 170a may be formed only between the semiconductor pattern 130 and the contact fill film 170b, and may not be formed between the interlayer insulating film 190 and the contact fill film 170b. The normal source / drain contact 170 may also have... Figure 6A and Figure 6B The shapes shown are as follows. In the following figures, the contact barrier film 170a and the contact filler film 170b can be indistinguishably shown as a single film.

[0070] Figure 7A and Figure 7B An exemplary cross-section of source / drain contacts 170 and 170_1 is shown. Figure 7A and Figure 7B It can be a cross-sectional view taken along the second direction Y.

[0071] When gate contacts (not shown) are disposed on the first active region 112, the second active region 114, and the third active region 112, a short margin between the gate contacts and the source / drain contacts 170 and 170_1 can be considered. For example, depending on whether the gate contacts are located around the source / drain contacts 170 and 170_1, the cross-section of the source / drain contacts 170 and 170_1 is L-shaped. Figure 7A ) or a T-shape rotated 180 degrees ( Figure 7B If no gate contact is provided around the source / drain contacts 170 and 170_1, the source / drain contacts 170 and 170_1 may have the following characteristics: Figure 6A and Figure 6B The cross-section shown.

[0072] exist Figures 8 to 10 , Figure 11A , Figure 11B , Figure 12 and Figure 13 In some embodiments, the integrated circuit may include: Figure 5 The source / drain contacts 170 and 170_1 are disposed across the first active region 112, the second active region 114 and the third active region 112 extending along the first direction X; the gate stack 120 and the insulating gate stack 150 are traversed in the second direction Y; and a plurality of wiring layers are located above the gate contacts.

[0073] exist Figure 8 In some embodiments, the integrated circuit may further include: source / drain paths 196 and 197, gate path 198, wiring patterns (or wiring lines) 191, 192 and 193, and power rails 195_1 and 195_2.

[0074] In integrated circuit manufacturing processes, BEOL (Block Interconnection and Offset) technology describes the process of interconnecting individual components such as transistors, capacitors, and resistors on a substrate. For example, BEOL processes may include: siliconizing the gate, source, and drain regions; adding a dielectric; planarizing; forming vias; adding a metal layer; forming a via; forming a passivation layer, etc.

[0075] The first wiring layer may include multiple wiring patterns (or wiring lines) extending in the X direction and parallel to the Y direction. The first wiring layer may include, for example, six wirings. The six wirings may be the first to sixth wiring patterns 191, 193, 192, 192, 193, and 191. Both the first standard unit 20 and the second standard unit 22 may include: source / drain paths 196 and 197 connecting the wiring patterns 191 and 192 of the first wiring layer to the source / drain contact 170, a gate path 198 connecting the wiring pattern 193 of the first wiring layer to the gate contact 175, the wiring patterns 191, 192, and 193 of the first wiring layer, and power rails 195_1 and 195_2.

[0076] A gate path 198 may be formed on a gate contact 175. The gate path 198 connects the gate contact 175 to wiring patterns 191, 192, and 193. The source / drain path may further include a power rail path 199. Source / drain paths 196, 197, and 199 may be formed on source / drain contacts 170 and 170_1. Source / drain paths 196, 197, and 199 may be connected to at least a portion of source / drain contacts 170 and 170_1. Source / drain paths 196, 197, and 199 may include: normal paths 196 and 197 connecting normal source / drain contacts 170 to wiring patterns 191 and 193, and a power rail path 199 connecting extended source / drain contacts 170_1 to power rails 195_1 and 195_2. The power rail path 199 may also extend along the Y direction beyond the extended source / drain contact 170_1. Power rails 195_1 and 195_2 may include an upper power rail 195_1 supplied with a first voltage and a lower power rail 195_2 supplied with a second voltage. The upper power rail 195_1 may supply power to a p-type transistor, and the lower power rail 195_2 may supply power to an n-type transistor. For example, the upper power rail 195_1 may supply a high voltage (e.g., VCC or VDD) to the p-type transistor, and the lower power rail 195_2 may supply a low voltage (e.g., GND) to the n-type transistor.

[0077] exist Figure 11A Although not shown, intermediate contact 176 may be further arranged between source / drain paths 196 and 197 and source / drain contact 170. Intermediate contact 176 may also be arranged between power rail path 199 and source / drain contact 170_1. Intermediate contact 176 may also be arranged between gate path 198 and gate contact 175. Although wiring pattern 193 and gate path 198 are shown as having an integrated structure, the embodiment is not limited thereto. Wiring pattern 193 and gate path 198 may be separated by a barrier film.

[0078] exist Figure 11B Although not shown, source / drain contact 170 can be connected to wiring patterns 191 and 192 without source / drain paths 196 and 197. Source / drain contact 170_1 can be connected to power rails 195_1 and 195_2 without power rail path 199. Gate contact 175 can be connected to wiring pattern 193 without gate path 198.

[0079] The first wiring layer may include multiple wiring lines extending in the X direction and arranged parallel to the Y direction. The first wiring layer may include, for example, six wiring lines. The first wiring line 191 can be connected via a source / drain path 197 to the drain contact of the first p-type transistor 134 of the first standard cell 20 and the drain contact of the second p-type transistor 134 of the second standard cell 22. The second wiring line 193 can be connected via a gate path 198 to the gate contact of the first p-type transistor 134 of the first standard cell 20 and the gate contact of the first n-type transistor 138 of the first standard cell 20, and can also be connected via the gate path 198 to the gate contact of the second p-type transistor 134 of the second standard cell 22 and the gate contact of the second n-type transistor 138 of the second standard cell 22. The third wiring line 192 can be connected via a source / drain path 196 to the drain contact of the first n-type transistor 138 of the first standard cell 20 and the drain contact of the second n-type transistor 138 of the second standard cell 22. The fourth wiring line 192 can connect the drain contact of the third n-type transistor 138 of the first standard unit 20 and the drain contact of the fourth n-type transistor of the second standard unit 22 via the source / drain path 196. The fifth wiring line 193 can connect the third and fourth p-type transistors 134 of each of the first standard unit 20 and the second standard unit 22 to the gate contacts of the third and fourth n-type transistors 138 of each of the first standard unit 20 and the second standard unit 22 via the gate path 198. The sixth wiring line 191 can connect the drain contact of the third p-type transistor 134 of the first standard unit 20 and the drain contact of the fourth p-type transistor 134 of the second standard unit 22 via the source / drain path 197. For example, each drain contact of the first and third p-type transistors 134 of the first standard unit 20 is arranged continuously along the Y direction, and each drain contact of the second and fourth n-type transistors 138 is arranged continuously along the Y direction.

[0080] In some embodiments, the second wiring line 193 and the fifth wiring line 193 may be connected to each gate contact 175 without the gate path 198.

[0081] exist Figure 9 In some embodiments, the integrated circuit may further include a second wiring layer, which includes a plurality of wiring lines extending in the Y direction and arranged parallel to the X direction.

[0082] The second wiring layer may include at least three wiring lines. These three wiring lines may be the seventh through ninth wiring lines 210, 220, and 210. The seventh wiring line 210 can be electrically connected via path 215 to the first wiring line 191, the third wiring line 192, the fourth wiring line 192, and the sixth wiring line 191 of the first standard unit 20. The eighth wiring line 220 can be electrically connected via path 225 to the second wiring line 193 and the fifth wiring line 193. The ninth wiring line 210 can be electrically connected via path 215 to the first wiring line 191, the third wiring line 192, the fourth wiring line 192, and the sixth wiring line 191 of the second standard unit 22.

[0083] According to some embodiments, a seventh wiring line 210 may be disposed on the gate stack 120 of the first standard cell 20 and spaced apart in the Z direction perpendicular to the top surface of the substrate 100. An eighth wiring line 220 may be configured to overlap with a portion of the extended source / drain contact 170_1 of the second standard cell 22, while being formed to extend in the Y direction. A ninth wiring line 210 may be configured to overlap with a portion of the normal source / drain contact 170 of the second standard cell 22.

[0084] According to some embodiments, the seventh wiring line 210 to the ninth wiring line 210 can all be configured not to overlap with the upper part of the gate stack 120 of the first standard cell 20, the extended source / drain contact 170_1 of the second standard cell 22, and the normal source / drain contact 170 of the second standard cell 22, or can be configured to completely overlap with them.

[0085] exist Figure 10 In some embodiments, the integrated circuit may further include a third wiring layer, which includes a plurality of wiring lines extending in the X direction and arranged parallel to the Y direction. The third wiring layer may include a tenth wiring line 310 and an eleventh wiring line 320.

[0086] The tenth wiring line 310 is connected to the eighth wiring line 220 via a path 315 and can input an input signal. The tenth wiring line 310 can be located on the second wiring layer and crosses the seventh wiring line 210, the eighth wiring line 220 and the ninth wiring line 210 extending along the Y direction in the X direction.

[0087] Eleventh wiring line 320 can be electrically connected to seventh wiring line 210 and ninth wiring line 210 through passage 325, and can output an output signal. Eleventh wiring line 320 can be set on the second wiring layer, and simultaneously crosses the seventh wiring line 210, eighth wiring line 220 and ninth wiring line 210 extending along the Y direction in the X direction.

[0088] According to some embodiments, the tenth wiring line 310 and the eleventh wiring line 320 can both be configured to partially or completely overlap with the upper portion of the third wiring line 192 and the upper portion of the fourth wiring line 192.

[0089] According to some embodiments, the first wiring line 191, the third wiring line 192, and the seventh wiring line 210 can be configured to be parallel to the upper part of the first active region 112, the second active region 114, or the third active region 112. In this case, the second wiring line 193 and the eighth wiring line 220 can be configured to be parallel to the upper part of the active region isolation membrane 105.

[0090] In an integrated circuit according to some embodiments, if a first power supply voltage is supplied to the source / drain contacts 170_1 (e.g., source contacts) of the first and third p-type transistors 134 of the first standard cell 20 and the source / drain contacts 170_1 (e.g., source contacts) of the second and fourth p-type transistors 134 of the second standard cell 22 through multiple wiring layers (e.g., upper power rail 195_1), and to the first and third n-type transistors 138 of the first standard cell 20 through multiple wiring layers (e.g., lower power rail 195_2), A second power supply voltage is supplied through the source / drain contact 170_1 (e.g., source contact) of the first to fourth p-type transistors 138 in the second standard cell 20 and the source / drain contact 170_1 (e.g., source contact) of the second standard cell 22. The output signal, along with the first and second power supply voltages, is output through the path 315 of the tenth wiring line 310 at the source / drain contact 170 (e.g., drain contact) of the first to fourth p-type transistors and the first to fourth n-type transistors in each of the first standard cell 20 and the second standard cell 22. For example, the output signal depends on the voltage of the gate stack 120 applied through the second and fifth wiring lines 193. For example, the first power supply voltage is a high voltage (e.g., VCC, VDD, etc.), and the second power supply voltage is a low voltage (e.g., VSS, GND, negative voltage, etc.).

[0091] In the example embodiment, for each transistor, the source region of each p-type transistor in the first to fourth p-type transistors of the first standard unit 20 and the source region of each transistor in the second standard unit 22 are configured independently. Here, the expression "configured independently" means that each transistor uses an independent source region, rather than that multiple transistors share a single source region. For example, the source regions of each transistor in the first standard unit 20 and the respective source regions of the transistors in the second standard unit 22 are configured to be separated from each other.

[0092] In other example embodiments, for each transistor, the source contacts of the transistor in the first standard cell 20 and the source contacts of the transistor in the second standard cell 22 are set independently. Here, the expression "set independently" means that one source contact is used for each transistor, and does not mean that one source contact is shared by multiple transistors.

[0093] The second wiring layer, located on the wiring of the first wiring layer, can output signals through the third wiring layer based on signals to be output from the drain contact of the transistor in the first standard cell 20 and signals to be output from the drain contact of the transistor in the second standard cell 22. By connecting the first standard cell 20 and the second standard cell 22, each comprising two or more p-type transistors and n-type transistors, the wiring in the first wiring layer, which has a relatively large resistance, is used for short circuits, and electrical connection loops are formed using the wiring in the second and third wiring layers, which have lower resistances than the first wiring layer. Compared to the case where each standard cell comprises one p-type transistor and one n-type transistor, this electrical connection loop reduces the total resistance and improves the operating speed attributable to RC delay.

[0094] Figures 14 to 17 This is a diagram used to illustrate an integrated circuit according to some embodiments. In the following description and drawings, details may be simplified or omitted. Figures 1 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figures 8 to 10 , Figure 11A , Figure 11B , Figure 12 and Figure 13 The content described in the document is repeated.

[0095] Figure 14 This is a top view showing an integrated circuit up to FEOL according to some embodiments. Figure 15 This is a top view of an integrated circuit according to some embodiments, up to the first wiring layer. Figure 16 This is a top view of an integrated circuit according to some embodiments, showing the second wiring layer. Figure 17 This is a top view of an integrated circuit according to some embodiments, showing the third wiring layer.

[0096] exist Figures 14 to 17 In this design, standard cells are divided by an insulated gate stack of 150. Figures 1 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figures 8 to 10 , Figure 11A , Figure 11B , Figure 12 and Figure 13 In the embodiments, although the first standard unit 20 has a first height 23 and the second standard unit 22 has a second height 24, wherein the two groups of four transistors are connected in series, Figures 14 to 17 The standard cell can be as low as 25mm in height, with two sets of two transistors connected in series.

[0097] In some embodiments, a standard cell may be formed on a substrate 100 extending along the X direction and may include a first active region 112, a second active region 114, and an active region isolation film 105 defined by a deep trench DT.

[0098] According to one embodiment, the first active region 112 may be a region in which a p-type transistor is formed, and the second active region 114 may be a region in which an n-type transistor is formed. According to another embodiment, the first active region 112 may be a region in which an n-type transistor is formed, and the second active region 114 may be a region in which a p-type transistor is formed. The first active region 112 and the second active region 114 may include well regions doped with other types of impurities.

[0099] Because the first active region 112 and the second active region 114 are... Figures 2 to 5 , Figure 6A , Figure 6B , Figure 7A and Figure 7B The description is the same as that described herein, and therefore can be omitted. The active region isolation membrane 105 and the cell isolation membrane 106 may include insulating material filling the deep trench DT defining the first active region 112 and the second active region 114. The cell isolation membrane 106 may be an insulating material membrane that is not disposed inside the cell but extends along the cell boundary in the first direction X. For example, the cell isolation membrane 106 can be interpreted as an insulating material membrane disposed along the cell boundary.

[0100] An integrated circuit according to some embodiments may include a plurality of gate stacks 120 and a plurality of insulated gates 150. The gate stacks 120 and the insulated gates 150 may each extend along the Y direction. The gate stacks 120 and the insulated gates 150 may be arranged to be adjacent and parallel in the X direction.

[0101] The gate stack 120 and the insulating gate 150, which are configured to be adjacent to each other in the X direction, can be spaced apart by 1 CPP (contact polycrystalline pitch). As an example, adjacent gate stacks 120 can be spaced apart by 1 CPP. As another example, adjacent gate stacks 120 and the insulating gate 150 can be spaced apart by 1 CPP.

[0102] An insulating gate 150 can separate at least a portion of the first active region 112 from at least a portion of the second active region 114. The insulating gate 150 can also separate a first active region 112U of the first active region 112.

[0103] according to Figures 14 to 17 In some embodiments, the width of a standard cell in the X direction can be 5 CPP, and its length in the Y direction can be the length in the Y direction of four groups of two transistors included in a standard cell (e.g., referred to as a single height). In contrast, according to Figures 1 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figures 8 to 10 , Figure 11A , Figure 11B , Figure 12 and Figure 13 In some embodiments, the width of a standard cell in the X direction can be 3 CPP, and its length in the Y direction can be the length in the Y direction of two sets of four transistors included in a standard cell (e.g., referred to as double height).

[0104] Reference Figure 14 The standard unit may include a first active region 112, an active region isolation membrane 105, and a second active region 114.

[0105] A normal source / drain contact 170 may be formed in at least a portion of the semiconductor pattern 130. An extended source / drain contact 170_1 may be formed in at least a portion of the semiconductor pattern 130. The normal source / drain contact 170 may typically overlap with the first active region 112 or the second active region 114. A portion of the extended source / drain contact 170_1 may extend onto the cell isolation film 106 and the cell gate dicing pattern 160. The extended source / drain contact 170_1 may be connected to a power rail via a power rail path 199. Figure 8 (195_1 and 195_2).

[0106] Normal source / drain contacts 170 can be arranged continuously in the Y direction within a standard cell. Extended source / drain contacts 170_1 can be arranged discontinuously in the Y direction within each standard cell.

[0107] In some embodiments, the standard unit may further include multiple wiring layers. Each wiring layer includes multiple wiring lines, and the portions without wiring lines may be filled with an interlayer insulating film 190.

[0108] exist Figure 15In FEOL's integrated circuits, a first wiring layer comprising multiple wiring lines is formed on a standard cell. The first wiring layer may include multiple wiring lines extending in the X direction and arranged parallel to the Y direction. The first wiring layer may include first to third wiring lines. The first to third wiring lines may be wiring lines 191, 193, and 192.

[0109] A first wiring line 191 is formed on the first active region 112 and is configured to span the gate stack 120, the insulated gate 150, the semiconductor pattern 130, and the associated source / drain contacts 170 to 170_1. The first wiring line 191 is electrically connected to the first active region 112 and the normal source / drain contact 170 via a passage 197. For example, the first wiring line 191 is connected to the drain contact of the p-type transistor 134.

[0110] A second wiring line 193 is formed on the active region isolation film 105 and is configured to span the gate stack 120, the insulated gate 150, and the associated source / drain contact 170. The second wiring line 193 is electrically connected via a path 198 to the gate contact 175 located on the active region isolation film 105. For example, the second wiring line 193 is connected to the gate contacts 175 of p-type transistor 134 and n-type transistor 138.

[0111] A third wiring line 192 is formed on the second active region 114 and is configured to span the gate stack 120, the insulated gate 150, the semiconductor pattern 130, and the associated source / drain contacts 170 to 170_1. The third wiring line 192 is electrically connected to the normal source / drain contact 170 of the second active region 114 via a path 196. For example, the third wiring line 192 is connected to the drain contact of an n-type transistor 138.

[0112] Additionally, in some embodiments, the integrated circuit may include: source / drain paths 196 and 197 connecting the first wiring layer and the source / drain contact 170, a gate path 198 connecting the first wiring layer and the gate contact 175, wiring patterns 191, 192 and 193 of the first wiring layer, power rails 195_1 and 195_2, and a power rail path 199 connecting the power rails 195_1 and 195_2 to the source / drain contact 170_1.

[0113] exist Figure 16 In this embodiment, a second wiring layer comprising multiple wiring lines is formed on a first wiring layer in the integrated circuit. The second wiring layer may include multiple wiring lines extending in the Y direction and arranged parallel to the X direction. The second wiring layer may include fourth to sixth wiring lines. The fourth to sixth wiring lines may be wiring lines 210, 220, and 210.

[0114] The fourth wiring line 210 is disposed on the gate stack 120 to overlap at least partially, and can be connected to each of the first wiring line 191 and the third wiring line 192 via a passage 215.

[0115] The fifth wiring line 220 is disposed on the gate stack 120 to overlap at least partially, and can be connected to the second wiring line 193 via the passage 225.

[0116] The sixth wiring line 210 is disposed on the gate stack 120 to overlap at least partially, and can be connected to the first wiring line 191 and the third wiring line 192 via the passage 215.

[0117] exist Figure 17 In this embodiment, a third wiring layer comprising multiple wiring lines is formed on the second wiring layer of the integrated circuit. The third wiring layer may include multiple wiring lines extending in the X direction and arranged parallel to the Y direction. The third wiring layer may include a seventh and eighth wiring line. The seventh and eighth wiring lines may be wiring lines 310 and 320.

[0118] The seventh cabling line 310 is disposed on the first cabling line 191 to at least partially overlap, and can be connected to the fourth cabling line 210 and the sixth cabling line 210 via the passage 215.

[0119] The eighth cabling line 320 is disposed on the second cabling line 193 to at least partially overlap, and can be connected to the fifth cabling line 220 via the passage 225.

[0120] According to some embodiments, the source contacts of the transistors in the standard cell are each independently configured for a single transistor. Here, the expression "independently configured" means that one source contact is used for one transistor, and does not mean that one source contact is shared by multiple transistors.

[0121] As a summary of the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the invention as defined by the appended claims. Therefore, the preferred embodiments of the invention disclosed herein are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. An integrated circuit, the integrated circuit comprising: a first standard cell including a first first-type transistor, a first second-type transistor, a third second-type transistor, and a third first-type transistor; a second standard cell including a second first-type transistor, a second second-type transistor, a fourth second-type transistor, and a fourth first-type transistor; and a plurality of wiring layers disposed on the first standard cell and the second standard cell and including a first wiring layer, a second wiring layer, and a third wiring layer stacked in order; and wherein a source contact of the first first-type transistor and a source contact of the second first-type transistor are electrically connected by a first power rail of the plurality of wiring layers, wherein a source contact of the third first-type transistor and a source contact of the fourth first-type transistor are electrically connected by a second power rail of the plurality of wiring layers, and wherein drain contacts of the first first-type transistor, the first second-type transistor, the third second-type transistor, and the third first-type transistor of the first standard cell and drain contacts of the second first-type transistor, the second second-type transistor, the fourth second-type transistor, and the fourth first-type transistor of the second standard cell are electrically connected by the first wiring layer, the second wiring layer, and the third wiring layer. the first standard cell and the second standard cell are adjacent in a first direction, 2. The integrated circuit of claim 1, wherein, wherein the first first-type transistor and the second first-type transistor are formed on a first active region, wherein the first second-type transistor, the second second-type transistor, the third second-type transistor, and the fourth second-type transistor are formed on a second active region, and wherein the third first-type transistor and the fourth first-type transistor are formed on a third active region.

3. The integrated circuit of claim 2, the first wiring layer includes a plurality of wiring lines extending in a first direction, wherein wherein the second wiring layer includes a plurality of wiring lines extending in a second direction intersecting the first direction, wherein the third wiring layer includes a plurality of wiring lines extending in the first direction, and wherein the wiring lines of the first wiring layer, the wiring lines of the second wiring layer, and the wiring lines of the third wiring layer form an electrical connection loop. the first wiring layer includes:

4. The integrated circuit of claim 3, wherein, a first wiring line electrically connecting a drain contact of the first first-type transistor and a drain contact of the second first-type transistor; a second wiring line electrically connecting gate contacts of the first first-type transistor, the second first-type transistor, the first second-type transistor, and the second second-type transistor; a third wiring line electrically connecting a drain contact of the first second-type transistor and a drain contact of the second second-type transistor; and a fourth wiring line electrically connecting a drain contact of the third second-type transistor and a drain contact of the fourth second-type transistor. a fourth wiring line electrically connecting a drain contact of the third second-type transistor and a drain contact of the fourth second-type transistor; a fifth wiring line electrically connecting gate contacts of the third first-type transistor, the fourth first-type transistor, the third second-type transistor, and the fourth second-type transistor; and a sixth wiring line electrically connecting a drain contact of the third first-type transistor and a drain contact of the fourth first-type transistor.

5. The integrated circuit of claim 4, wherein, the second wiring layer includes: a seventh wiring line electrically connecting the first wiring line, the third wiring line, the fourth wiring line, and the sixth wiring line of the first standard cell; an eighth wiring line electrically connecting the second wiring line and the fifth wiring line; and a ninth wiring line electrically connecting the first wiring line, the third wiring line, the fourth wiring line, and the sixth wiring line of the second standard cell.

6. The integrated circuit of claim 5, wherein, the third wiring layer includes: a tenth wiring line electrically connected to the eighth wiring line and outputting an output signal; and an eleventh wiring line electrically connecting the seventh wiring line and the ninth wiring line.

7. The integrated circuit of claim 5, wherein, the drain contacts of the transistors of the first standard cell and the drain contacts of the transistors of the second standard cell are disposed parallel to the wiring lines of the second wiring layer.

8. The integrated circuit of claim 4, wherein, the integrated circuit further includes: an active region isolation film that traverses between adjacent ones of the first active region, the second active region, and the third active region, and the second wiring line and the fifth wiring line are each disposed on the active region isolation film.

9. The integrated circuit of claim 8, wherein, the first wiring line and the sixth wiring line are each disposed on the first active region and the third active region, respectively, and wherein the third wiring line and the fourth wiring line are disposed on the second active region.

10. The integrated circuit of claim 1, wherein, the first standard cell and the second standard cell are adjacent in a first direction, and wherein the drain contacts of the first first-type transistor, the first second-type transistor, the third second-type transistor, and the third first-type transistor of the first standard cell are disposed in a continuous structure in the first standard cell along a second direction that intersects the first direction, and the drain contacts of the second first-type transistor, the second second-type transistor, the fourth second-type transistor, and the fourth first-type transistor of the second standard cell are disposed in a continuous structure in the second standard cell along the second direction.

11. An integrated circuit, the integrated circuit comprising: a first standard cell including a first p-type transistor and a first n-type transistor; a second standard cell disposed adjacent to the first standard cell and including a second p-type transistor and a second n-type transistor; and a plurality of wiring layers disposed on the first standard cell and the second standard cell and including a first wiring layer, a second wiring layer, and a third wiring layer stacked in order, wherein a source contact of the first p-type transistor and a source contact of the second p-type transistor are electrically connected by a power rail of the plurality of wiring layers, wherein a drain contact of the first p-type transistor and a drain contact of the first n-type transistor are connected to each other, wherein a drain contact of the second p-type transistor and a drain contact of the second n-type transistor are connected to each other, wherein the drain contacts of the transistors of the first standard cell and the drain contacts of the transistors of the second standard cell are electrically connected by wiring lines of the first wiring layer, the second wiring layer, and the third wiring layer, wherein the wiring lines of the second wiring layer are disposed parallel to each other in a first direction with the drain contacts of the transistors of the first standard cell and the drain contacts of the transistors of the second standard cell, and wherein the wiring lines of the first wiring layer and the wiring lines of the third wiring layer are disposed to extend in a second direction perpendicular to the first direction.

12. The integrated circuit of claim 11, wherein, the first p-type transistor and the second p-type transistor are formed on a first active region, wherein the first n-type transistor and the second n-type transistor are formed on a second active region, and wherein an active region isolation film is formed between the first active region and the second active region.

13. The integrated circuit of claim 12, wherein, at least one of the wiring lines of the third wiring layer is disposed on the active region isolation film and outputs an output signal from the drain contacts of the transistors of the first standard cell and the drain contacts of the transistors of the second standard cell.

14. The integrated circuit of claim 13, wherein, the wiring lines of the first wiring layer include: a first wiring line electrically connecting a drain contact of the first p-type transistor and a drain contact of the second p-type transistor; a second wiring line electrically connecting gate contacts of the first p-type transistor, the second p-type transistor, the first n-type transistor, and the second n-type transistor; and a third wiring line electrically connecting a drain contact of the first n-type transistor and a drain contact of the second n-type transistor.

15. The integrated circuit of claim 14, wherein, the wiring lines of the second wiring layer include: a fourth wiring line electrically connecting the first wiring line and the third wiring line; a fifth wiring line disposed adjacent to the fourth wiring line on a first side and electrically connected to the second wiring line; and a sixth wiring line disposed adjacent to a second side of the fifth wiring line and electrically connecting the first wiring line and the third wiring line.

16. The integrated circuit of claim 15, wherein, the wiring lines of the third wiring layer include: a seventh wiring line electrically connecting the fourth wiring line and the sixth wiring line; and an eighth wiring line electrically connecting the fifth wiring line and the seventh wiring line. An eighth wiring line electrically connected to the fifth wiring line and outputting the output signal.

17. The integrated circuit of claim 16, wherein, The first wiring line, the third wiring line, and the seventh wiring line are formed on an active region, and the second wiring line and the eighth wiring line are formed on an active region isolation film.

18. The integrated circuit of claim 11, wherein, The drain contacts of the first p-type transistor and the first n-type transistor are arranged as a continuous structure extending in the first standard cell, and The drain contacts of the second p-type transistor and the second n-type transistor are arranged as a continuous structure extending in the second standard cell.

19. An integrated circuit, the integrated circuit comprising: a first standard cell including a first first-type transistor and a first second-type transistor; a second standard cell disposed adjacent to the first standard cell in a first direction and including a second first-type transistor and a second second-type transistor; and a plurality of wiring layers formed on the first standard cell and the second standard cell and including a first wiring layer, a second wiring layer, and a third wiring layer stacked in order; wherein source contacts of the first first-type transistor and the second first-type transistor are independently disposed from each other, wherein power supply rails of the plurality of wiring layers are electrically connected such that the source contacts of the first first-type transistor and the second first-type transistor are electrically connected and a power supply voltage is applied, wherein first and third wiring lines of the first wiring layer are electrically connected to drain contacts of the transistors of the first standard cell and the transistors of the second standard cell and extend in the first direction, wherein a second wiring line of the first wiring layer is electrically connected to gate contacts of the transistors of the first standard cell and the transistors of the second standard cell and extends in the first direction, wherein first and third wiring lines of the second wiring layer are electrically connected to the first and third wiring lines of the first wiring layer and extend in a second direction perpendicular to the first direction, and wherein a second wiring line of the second wiring layer is electrically connected to the second wiring line of the first wiring layer and extends in the second direction.

20. The integrated circuit of claim 19, wherein, drain contacts of the first first-type transistor and the first second-type transistor are arranged as a continuous structure extending in the second direction, wherein drain contacts of the second first-type transistor and the second second-type transistor are arranged as a continuous structure extending in the second direction.

Images