Current mode interleaved controlled converter and control chip

Abstract

The application discloses a current mode staggered control converter and a control chip, wherein the converter comprises a VIN input power supply with a voltage of 20V-100V, forward transformers T1 and T2, two output paths formed by the transformers and subsequent devices, a capacitor C0 as a VCC pin filter capacitor, a resistor R3 as an RT pin resistor connected to the ground and used for controlling the frequency of an oscillator, capacitors C1 and C2 as COMP1 and COMP2 pin capacitors connected to the ground and used for adjusting loop stability, capacitors C3 and C4 as SS1 and SS2 pin capacitors connected to the ground and used for realizing soft start of the system, N3 and N4 as natural synchronous rectifier devices in the forward converter, the first output channel and the second output channel adopting the same structure, an auxiliary winding La providing power supply for an IC control chip VCC through a diode D1, and an output capacitor Cout1 as an output capacitor of the first channel. The whole system is driven and controlled by only one control chip, and the power density is improved, the volume of the scheme is reduced, the cost of the scheme is lowered, and the system performance is not sacrificed.

Description

Technical Field

[0001] This invention relates to the field of power management technology, specifically to a current-mode interleaved control converter and control chip. Background Technology

[0002] Single-ended forward converters are widely used in switching power supplies due to their simple structure, reliable operation, high efficiency, and input / output electrical isolation. During normal operation, the maximum duty cycle utilization of a forward converter is typically no more than 50%, meaning that the converter is idle for a significant portion of the time. Utilizing this idle time can further increase the converter's output power. Therefore, adding an output channel is an excellent choice. This allows for the utilization of the original system's EMC (electromagnetic interference) resources while simultaneously reducing system size and lowering costs while increasing output power. Summary of the Invention

[0003] To address the aforementioned problems, this invention discloses a current-mode interleaved control converter and its control chip. The converter includes an IC control chip, forward transformers (T1, T2), capacitors (C0, C1, C2, C3, C4), resistor R3, output sampling resistor R5, power switching transistors (N1, N2), current sampling resistors (R1, R2), a first channel, a second channel, synchronous rectifier devices (N3, N4), output power supply inductor L1, auxiliary winding La, diode D1, output capacitor Cout1, isolation components, a VIN input power supply (VIN is 20V–100V), forward transformers T1 and T2. These components form two outputs, one for each of the following devices: capacitor C0 is the VCC pin filter capacitor, resistor R3 is the RT pin ground resistance, used to control the oscillator frequency; capacitors C1 and C2 are COMP1 and COMP2 pin ground capacitances, used to adjust loop stability; capacitors C3 and C4 are SS1 and SS2 pin ground capacitances, used to achieve soft start of the system; N3 and N4 form a natural synchronous rectifier in the forward converter; the first and second output channels use the same structure; the auxiliary winding La supplies power to the IC control chip VCC through diode D1; and the output capacitor Cout1 is the output capacitor of the first channel.

[0004] As an improvement of the present invention, the IC control chip includes a voltage regulation module, an LDO / BIAS / UVLO module and an OSC oscillator. The voltage regulation module is used to convert the high voltage VIN into the medium voltage power supply VCC inside the IC control chip. The medium voltage power supply VCC is usually 8 to 15V and is mainly used to power the drive module Driver.

[0005] As an improvement of the present invention, the LDO / BIAS / UVLO module converts the medium-voltage power supply VCC into an internal low-voltage power supply VDD, generates a bias, enables EN, and determines the start-up voltage and undervoltage voltage of VCC.

[0006] As an improvement of the present invention, the first channel includes a RAMP ramp module for ramp compensation, a COMP1 pin, and a COMP1 pin that is pulled up to the internal power supply VDD by a resistor r1. A clamping structure is provided between the SS1 pin of the IC control chip and the COMP1 pin. The SS1 pin has a charging current controlled by the enable EN. The COMP1 pin is connected to the negative input terminal of the amplifier CMP2 through transistors q1 and q2 and resistors r2 and r3. The positive input terminals of amplifiers CMP1 and CMP2 are connected to the output of the RAMP module. The negative input terminal of the COMP1 pin is a 0.5V reference. The function of amplifiers CMP1 and CMP2 is to control the output shutdown. Amplifier CMP1 forces the output shutdown when overcurrent protection is triggered, while amplifier CMP2 controls the output shutdown under normal loop operation.

[0007] As an improvement of the present invention, the outputs of amplifiers CMP1 and CMP2 are sent to an OR gate, the output of the OR gate is sent to the R terminal of an RS flip-flop to control the drive to turn off, the S terminal of the RS flip-flop is a clock signal CLK1 to control the drive to turn on, and the output of the RS flip-flop is sent to the drive module.

[0008] As an improvement of the present invention, the clamping structure consists of an operational amplifier AMP and an NMOS n1, which is used to ensure that the SS1 signal is not lower than the COMP1 pin signal. Therefore, when the system is powered on, the rising speed of the SS1 pin can be controlled by controlling the rising speed of the SS1 pin through the external capacitor connected to the SS1 pin.

[0009] As an improvement of the present invention, the isolation component consists of a TL431+ optocoupler and is connected to the COMP pin of the chip.

[0010] As an improvement of the present invention, the OSC oscillator determines the switching frequency of the system, and the frequency is adjusted by an external resistor connected to the RT pin.

[0011] The beneficial effects of this invention are as follows: The dual-channel converter provided by this invention saves on peripheral costs, reduces the size of the solution, and increases the output power. Compared with traditional slope compensation technology, the slope compensation function designed in this invention does not perform slope compensation when the duty cycle is below 50%, which can more accurately achieve the preset output power. This invention provides a dual-channel forward converter and control chip. The two output channels are completely independent, and the functions of two converters are realized using the resources of one converter system. Moreover, the drive output phases of the two channels are 180° apart, which greatly avoids the increase of input ripple current. The entire system is driven and controlled by only one control chip. It has been well optimized in terms of improving power density, reducing solution size, and reducing solution cost, without sacrificing system performance. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the circuit structure of a current-mode interleaved controller.

[0013] Figure 2 This is a schematic diagram of the oscillator circuit structure.

[0014] Figure 3 This is a schematic diagram of the key signal waveform.

[0015] Figure 4 This is a schematic diagram of the circuit structure of the slope compensation module. Detailed Implementation

[0016] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0017] Example: A current-mode interleaved control converter and control chip. The converter includes an IC control chip, forward transformers (T1, T2), capacitors (C0, C1, C2, C3, C4), resistor R3, output sampling resistor R5, power switching transistors (N1, N2), current sampling resistors (R1, R2), a first channel, a second channel, synchronous rectifier devices (N3, N4), output power supply inductor L1, auxiliary winding La, diode D1, output capacitor Cout1, isolation components, and VIN input power supply. Forward transformers T1 and T2, together with subsequent devices, form two outputs. Capacitor C0 is V... The CC pin is filtered by a capacitor, resistor R3 is the RT pin to ground resistance, capacitors C1 and C2 are the COMP1 and COMP2 pins to ground capacitances, and capacitors C3 and C4 are the SS1 and SS2 pins to ground capacitances. The first output channel and the second output channel use the same structure. The auxiliary winding La supplies power to the IC control chip VCC through diode D1. The output capacitor Cout1 is the output capacitor of the first channel. The IC control chip includes a voltage regulation module, an LDO / BIAS / UVLO module, and an OSC oscillator. The voltage regulation module is used to convert the high voltage VIN into the IC control chip's internal medium voltage power supply V. The LDO / BIAS / UVLO module converts the medium-voltage power supply VCC to an internal low-voltage power supply VDD, generates bias, enables EN, and determines the start-up and undervoltage of VCC. The first channel includes a RAMP ramp module and a COMP1 pin. The COMP1 pin is pulled up to the internal power supply VDD by a resistor r1. A clamping structure is provided between the SS1 pin of the IC control chip and the COMP1 pin. The SS1 pin has a charging current controlled by the enable EN. The COMP1 pin is fed to the negative input terminal of the amplifier CMP2 after passing through transistors q1 and q2 and resistors r2 and r3. The positive input terminals of amplifiers CMP1 and CMP2 are connected to the output of the RAMP module. The negative input terminal of amplifier CMP1 is a 0.5V reference. The outputs of amplifiers CMP1 and CMP2 are sent to an OR gate, and the output of the OR gate is sent to the R terminal of an RS flip-flop. The S terminal of the RS flip-flop is the clock signal CLK1. The output of the RS flip-flop is sent to the driver module. The clamping structure consists of an operational amplifier AMP and an NMOS transistor n1. The isolation component consists of a TL431 and an optocoupler, and is connected to the COMP pin of the chip. The OSC oscillator determines the switching frequency of the system, and the frequency is adjusted by an external resistor connected to the RT pin.

[0018] Working principle: From the perspective of the entire topology, looking at a single channel, during the conduction phase of the power switch N1, the input power supply charges the primary inductor Lp1 of transformer T1. The primary inductor Lp1 is positive at the top and negative at the bottom, and the current of the primary inductor Lp1 shows a ramp-up trend. Its current magnitude can be sampled by the sampling resistor R1. At the same time, the secondary inductor Ls1 of transformer T1 is positive at the top and negative at the bottom. The voltage of the secondary inductor Ls1 is determined by the turns ratio of transformer T1, which can be expressed as follows: VIN(Np / Ns), where Np and Ns are the number of turns of the primary and secondary windings (transformer T1 (T2) is formed by coupling the primary and secondary windings, respectively).

[0019] At this point, the voltage across the secondary inductor Ls1 is fixed. The secondary inductor Ls1 charges the output power supply inductor L1. The output power supply inductor L1 is positive on the left and negative on the right. Therefore, the synchronous rectifier N4 is turned on and the synchronous rectifier N3 is turned off. The entire output circuit is: upper end of secondary inductor Ls1 → output power supply inductor L1 → output capacitor Cout1 → synchronous rectifier N4 → lower end of secondary inductor Ls1. Afterwards, as the voltage of CS1 continuously rises, the voltage after compensation by the RAMP1 module also continuously rises. For amplifier CMP2, the negative input voltage is determined by the COMP1 pin and is relatively fixed, while the positive input voltage is continuously rising. At a certain moment, amplifier CMP2 flips, controlling the output OUT1 to turn off. After that, the primary inductor Lp1 becomes positive on the bottom and negative on the top. Figure 1(The absorption circuit is omitted). The secondary inductor Ls1 is positive at the bottom and negative at the top. Synchronous rectifier N3 is turned on, and synchronous rectifier N4 is turned off. The output power supply inductor L1 is negative on the left and positive on the right. The output circuit is: output power supply inductor L1 → output capacitor Cout1 → synchronous rectifier N3 → output power supply inductor L1. It can be seen that the entire secondary circuit system of the transformer actually constitutes a BUCK circuit. From the perspective of the IC control chip, looking at a single channel, after the VIN input power supply is powered on, the Regulator module (voltage adjustment module) generates a medium voltage power supply VCC for the IC control chip, usually 8-15V. This power supply is mainly used for driving. The VCC power supply generates various references, biases and enable through the LDO / BIAS / UVLO module. After the enable is generated, other modules can work. After the enable EN is generated, the Softstart module (soft start module) generates current to charge the external capacitor of the SS1 pin. The SS1 pin rises slowly. The clamping relationship between the COMP1 pin and the COMP1 pin causes the COMP1 pin voltage to rise slowly. When the COMP1 pin voltage is very low, the negative input terminal of amplifier CMP2 remains at 0V, and the output of amplifier CMP2 remains high. Therefore, the output of the IC control chip remains low. When the COMP1 pin voltage rises above 1.4V, which is the superimposed Vbe voltage of the two transistors q1 and q2, amplifier CMP2 outputs a low level for a certain period of time. Then, the RS flip-flop can be controlled to turn on by the clock signal CLK1. After the output is turned on, the CS1 sampling voltage rises. For amplifier CMP2, when the positive input voltage is higher than the negative input voltage, the output is turned off again. Therefore, the magnitude of the COMP1 pin voltage directly determines the magnitude of the conduction time. The integrated soft-start circuit can ensure that the COMP1 pin voltage rises slowly when powered on, thereby controlling the inductor current to rise slowly, reducing the current stress on the converter, and protecting the entire converter.

[0020] As mentioned above, the two channels are completely independent and do not affect each other. The control chip uses an oscillator circuit to maintain a 180° phase difference between the two channels, thereby minimizing input current ripple and ensuring the stability of the entire system. The oscillator circuit structure is as follows: Figure 2As shown, the operational amplifier AMP and N1 form a negative feedback structure. The voltage at pin RT is fixed at 2V. Therefore, the external resistor connected to pin RT determines the current in the P1 / N1 branch. PMOS transistors P2, P3, P4, and P5 form a current mirror with P1. The current branches of P2 to P5 charge capacitors C1 to C4 respectively, and C1 to C4 have the same capacitance value. C1 to C4 are discharged by NMOS transistors N2 to N5 respectively. P4, P5, N4, N5, C3, C4, CMP1, CMP2, NOR1, NOR2, INV1, and INV2 form an oscillator. The outputs s1 and s2 of INV1 are inverted. When s1 is low, s2 is high. At this time, the voltage of C3 is 0V, P5 charges C4, and the output of amplifier CMP1 is low. When the voltage of C4 exceeds 2V, the output of CMP2 is high, which controls s1 to go high. When s2 goes low, the voltage of C4 is 0V, and P4 charges C3. When the voltage of C3 exceeds 2V, it controls s1 to go low and s2 to go high, thus forming an oscillator function. S2 outputs to the CP terminal of the D flip-flop DFF. DFF forms a divide-by-two structure. When s2 goes high for the first time, Q goes high and QN goes low. At this time, the clock signal CLK1 is high and CLK2 is low. When s2 goes high for the second time, Q goes low and QN goes high. At this time, CLK1 is low and CLK2 is high. Thus, the time points when the two signals CLK1 and CLK2 go from low to high are after one cycle of oscillator flip, so there is a 180° phase difference between CLK1 and CLK2. The two outputs of signal s2 and DFF are used to control the discharge of capacitors C1 and C2. After the capacitors C1 and C2 are charged to a high potential, they are discharged. Therefore, the voltage of C1 and C2 exhibits a ramp characteristic.

[0021] Figure 3 The diagram shows waveforms of several key signals. CLK1 and CLK2 are out of phase by one oscillator cycle, and their frequencies are half the oscillator frequency. Therefore, CLK1 and CLK2 are 180° out of phase. If the control chip is turned on by the falling edge of CLK1 or CLK2, then for each channel, when the on-time exceeds 50%, the ramp signal starts to rise. This ramp signal is superimposed on the current sampling pin CS, forming a ramp compensation function to prevent subharmonic oscillation problems that easily occur when the duty cycle of the current control mode exceeds 50%. Compared with traditional ramp compensation technology, the ramp compensation function designed in this invention does not perform ramp compensation when the duty cycle is below 50%, and can more accurately achieve the preset output power.

[0022] The circuit structure diagram of the slope compensation module is shown below. Figure 4The operational amplifier AMP, the switching transistor N1, and the resistor R1 form a voltage-to-current function. The slope signal Slope is converted into a slope current signal I_slope through the voltage-to-current structure. This slope current signal flows through the pin CS superimposed by the resistor R2. The signal CS_RAMP after slope compensation is used to output to other modules of the control chip.

[0023] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] Finally, it should be noted that the above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A current-mode interleaved control converter containing a control chip, characterized in that, The converter includes an IC control chip, forward transformers T1 and T2, capacitors C0, C1, C2, C3, and C4, resistor R3, output sampling resistor R5, power switches N1 and N2, current sampling resistors R1 and R2, a first channel, a second channel, synchronous rectifiers N3 and N4, output power supply inductor L1, auxiliary winding La, diode D1, output capacitor Cout1, isolation components, and VIN input power supply. Forward transformers T1 and T2, together with subsequent components, form two... The first and second output channels use the same structure. Capacitor C0 is the filter capacitor for the VCC pin of the IC control chip; resistor R3 is the resistance to ground for the RT pin of the IC control chip; capacitors C1 and C2 are the capacitances to ground for the COMP1 and COMP2 pins of the IC control chip, respectively; and capacitors C3 and C4 are the capacitances to ground for the SS1 and SS2 pins of the IC control chip, respectively. The auxiliary winding La supplies power to the VCC pin of the IC control chip through diode D1. Output capacitor Cout1 is the output capacitor for the first channel. The IC control chip includes a voltage regulation module, an LDO / BIAS / UVLO module, and an OSC oscillator. The voltage regulation module is used to convert the high voltage VIN into the medium voltage power supply VCC inside the IC control chip. The LDO / BIAS / UVLO module converts the medium-voltage power supply VCC into an internal low-voltage power supply VDD, generates bias, enables EN, and determines the start-up voltage and undervoltage of VCC. The first channel includes a RAMP ramp module. The COMP1 pin of the IC control chip is pulled up to the internal power supply VDD by resistor r1. A clamping structure is provided between the SS1 pin and the COMP1 pin of the IC control chip. The SS1 pin of the IC control chip has a charging current controlled by the enable EN. The COMP1 pin of the IC control chip is connected to the negative input terminal of amplifier CMP2 through transistors q1 and q2 and resistors r2 and r3. The positive input terminals of amplifiers CMP1 and CMP2 are connected to the output of the RAMP ramp module. The negative input terminal of amplifier CMP1 is a 0.5V reference. The outputs of amplifiers CMP1 and CMP2 are sent to an OR gate, the output of which is sent to the R terminal of an RS flip-flop. The S terminal of the RS flip-flop is the clock signal CLK1, and the output of the RS flip-flop is sent to the driver module. The clamping structure consists of an operational amplifier AMP and an NMOS n1. The isolation component consists of a TL431 and an optocoupler, and is connected to the COMP1 pin of the IC control chip. The OSC oscillator determines the switching frequency of the system, which is adjusted by an external resistor connected to the RT pin.

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