A multi-mode test system for semiconductor testing

Abstract

The invention provides a multi-mode test system for semiconductor testing, comprising a PC host and a DA module and an AD module connected to the PC host by signal. The PC host is connected to a signal control module by signal through the DA module, the signal control module is connected to a power output module by signal, the power output module is connected to a test module by signal, the test module is used to complete the test operation of the test device, the test module is also connected to a sampling module by signal, the sampling module is connected to a signal processing module by signal, the signal processing module feeds back the test signal to the PC host by the AD module, and completes the test process of the test device. The invention adjusts the signal control module and the power output module in the test system, so that the signal can be flexibly adjusted during the test process, cooperates with the power output module to complete the amplification and output of the signal, and flexibly samples the test signal at the same time, can obtain accurate collection, and is convenient for completing the semiconductor test process.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor testing systems, and in particular relates to a multi-mode testing system for semiconductor testing. Background Art

[0002] Semiconductor devices are electronic devices with conductivity between good conductors and insulators, which use the special electrical properties of semiconductor materials to perform specific functions.

[0003] When testing semiconductor devices, metal electromigration failure and metal stress migration failure are the main factors affecting the reliability performance of semiconductor devices. The metal electromigration failure refers to the fact that when the device is working, a certain current passes through the metal interconnect and generates an electric field. Under the action of the electric field, metal ions will produce mass transport along the conductor, forming metal ion migration. The migration of metal ions is likely to produce voids in the local area of ​​the metal interconnect. When the voids reach a certain level, the resistance of the metal interconnect is greatly increased, which is likely to cause the performance degradation or failure of the semiconductor device. The metal stress migration failure refers to the fact that when the device is working at a certain temperature, the thermal expansion coefficient of the metal interconnect is inconsistent with that of other material layers, so stress is formed between the metal interconnect and other material layers, so that the small gaps between the grains in the metal interconnect or the back-end through hole gather to the place where the stress is concentrated to form voids. When the voids reach a certain level, it is easy to cause the metal interconnect to be broken, which is easy to cause the performance degradation or failure of the semiconductor device, affecting the overall efficiency of the semiconductor device test.

[0004] The existing semiconductor testing system is relatively simple. It can only test some parameters of some complex devices such as bidirectional SCR, Darlington array, optocoupler, optoelectronic logic, relay, three-terminal regulator, bidirectional trigger diode, etc., and cannot perform curve scanning of semiconductor devices, which seriously affects the analysis and judgment of semiconductor performance and affects the test results. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a multi-mode testing system for semiconductor testing in view of the above-mentioned deficiencies in the prior art, so as to solve the problems raised in the above-mentioned background technology.

[0006] To solve the above technical problems, the technical solution adopted by the present invention is: a multi-mode test system for semiconductor testing, comprising a PC host and a DA module and an AD module connected to the PC host by signals;

[0007] The PC host is connected to a signal control module via a DA module signal, the signal control module is connected to a power output module via a signal, and the power output module is connected to a test module via a signal;

[0008] The test module is used to complete the test operation of the test device;

[0009] The test module is also signal-connected to a sampling module, and the sampling module is signal-connected to a signal processing module. The signal processing module feeds back the test signal to the PC host through the AD module to complete the test process of the test device.

[0010] Preferably, the PC host is preset with test software, the test is written based on the IGBT test standard, the test feedback data is stored, displayed and judged, and the hardware encryption function is completed according to the design. The detection serial port is started by software, and the detection instruction is sent after the serial port is opened, and the detection code is returned according to the corresponding rules to realize the combined encryption of software and hardware.

[0011] Preferably, the DA module uses a high-speed DAC709KH chip with a 16-bit parallel port input. The high-speed DAC709KH chip converts the data signal into a voltage of an analog signal, and the voltage is -10V to 10V. During the test, the DA module sends out at least one pulse signal.

[0012] Preferably, the signal control module is used to divide the signal into a low source signal and a high source signal, and output them. The low source signal is divided into a low source voltage source and a low source current source, and the high source signal is divided into a high source voltage source and a high source current source. The power output module amplifies the signal into the required power signal and outputs it to the test module.

[0013] Preferably, the test module is used in conjunction with a power output module to complete the test of the test device.

[0014] Preferably, the sampling module includes sampling of voltage signals or current signals, and is used to collect the measured voltage signals or current signals generated on the test module after the voltage or current is loaded on the test module connected to the test device.

[0015] Preferably, the sampling modes of the sampling module are divided into ordinary voltage sampling, differential current sampling, ordinary current sampling, high voltage sampling and large current sampling.

[0016] Preferably, the signal processing module judges the signal of the sampling module to determine whether it is a voltage signal or a current signal, and amplifies or reduces it into a standard voltage signal to transmit to the AD module.

[0017] Preferably, the AD module is also connected to a filter circuit, and the filter circuit is divided into a low-pass filter and a high-pass filter. The low-pass filter is a low-pass filter composed of an operational amplifier, and the high-pass filter is a UAF42AP filter chip.

[0018] Preferably, the AD module is a 16-bit high-speed ADC700KP chip with a sampling speed of 2uS, and a sample holder SHC5320KP is added in front of the high-speed ADC700KP chip to ensure the stability of the signal, and then feed the signal back to the PC host.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] The present invention adjusts the signal control module and the power output module in the test system so that the signal can be flexibly adjusted during the test process, and cooperates with the power output module to complete the signal amplification and output. At the same time, the test signal is flexibly sampled, and different test signals can be accurately collected respectively, so that the test system can test multiple units at the same time, and the test types are increased to 19 categories and 27 categories, which is convenient for completing the semiconductor test process. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is the overall principle diagram of the present invention;

[0022] Figure 2 It is the principle diagram of the integration circuit of the present invention;

[0023] Figure 3 It is a principle framework diagram of the signal control module of the present invention;

[0024] Figure 4 It is a schematic diagram of a high source voltage source circuit in a signal control module of the present invention;

[0025] Figure 5 It is a schematic diagram of a high source current source circuit in a signal control module of the present invention;

[0026] Figure 6 It is a schematic diagram of a low source voltage source circuit in a signal control module of the present invention;

[0027] Figure 7 It is a schematic diagram of a low source current source circuit in a signal control module of the present invention;

[0028] Figure 8 It is the circuit principle diagram of the power output module of the present invention;

[0029] Fig. 9 It is a common voltage sampling circuit diagram in the sampling module of the present invention;

[0030] Fig.10 is a differential current sampling circuit diagram in the sampling module of the present invention;

[0031] Fig.11 It is a common current sampling circuit diagram in the sampling module of the present invention;

[0032] Fig.12It is a high voltage sampling circuit diagram in the sampling module of the present invention;

[0033] Fig.13 It is a circuit diagram of a large current sampling in a sampling module of the present invention;

[0034] Fig.14 1 is a schematic diagram of a filter circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] like Figure 1 As shown, the present invention provides a technical solution: a multi-mode test system for semiconductor testing, comprising a PC host 1 and a DA module 2 and an AD module 3 connected to the PC host 1 by signals;

[0037] The PC host 1 is connected to the signal control module 4 via the DA module 2, the signal control module 4 is connected to the power output module 5, and the power output module 5 is connected to the test module 6;

[0038] The test module 6 is used to complete the test operation of the test device 7;

[0039] The test module 6 is also signal-connected to a sampling module 8 , and the sampling module 8 is signal-connected to a signal processing module 9 . The signal processing module 9 feeds back the test signal to the PC host 1 through the AD module 3 , thereby completing the test process of the test device 7 .

[0040] The PC host 1 is preset with test software, and the test is written based on the IGBT test standard. The test feedback data is stored, displayed and judged, and the hardware encryption function is completed according to the design. The detection serial port is started by software, and the detection instruction is sent after the serial port is opened. The detection code is returned according to the corresponding rules to realize the combination of software and hardware encryption, which mainly analyzes the original binary file format, analyzes the serial port sending instructions, sends the serial port instructions, calculates the document sending verification, and realizes the design of the rectangular coordinate system.

[0041] The test software uses a multi-document interface, which allows you to edit multiple test files at the same time without affecting each other. The input interface is intuitive and easy to operate. It has maximum and minimum value limits to prevent damage to the equipment caused by excessive current or voltage parameters. When the test file is edited, it can be saved or sent directly for testing. There is a progress bar to remind you when sending. After sending, the test is carried out.

[0042] The DA module 2 uses a high-speed DAC709KH chip with a 16-bit parallel port input. The high-speed DAC709KH chip converts the data signal into a voltage of an analog signal, and the voltage is -10V to 10V.

[0043] In order to improve the test speed, a pulse test is adopted, which requires the DA module 2 to send out at least one pulse signal. The higher the voltage loaded on the test device 7 connected to the test module 6 during the test, the slower the rise time of the pulse is required. If the rise time is too fast, a long-term oscillation of the current or voltage will occur, causing the measured signal to oscillate, and it is impossible to obtain a correct test result. If the rise time is too slow, the power source design will require a larger power to meet the pulse power requirements. Four sets of integration circuits are added to the signal after the DA module 2 comes out, as shown in the figure. Figure 2 As shown, the slope of the pulse rise time required to adapt to different tests is obtained.

[0044] The signal control module 4 is used to divide the signal into a low source signal and a high source signal and output them. The low source signal is divided into a low source voltage source and a low source current source, and the high source signal is divided into a high source voltage source and a high source current source. Figure 3 As shown;

[0045] During use, the external 220V AC power is first transformed by transformer T, then rectified into DC power by the rectifier bridge, and then filtered into a constant voltage by capacitors C9 and C10.

[0046] At the beginning, thyristor Q12 is not turned on and the output voltage is 0. After comparison by comparator U7A, the anode terminal is greater than 5V, so the output voltage Q10 is turned on and thyristor Q12 is also turned on. At this time, the voltage is output to capacitor CF1. When capacitor CF1 is fully charged, the voltage continues to rise. After voltage division by resistors R32 and R33, when it is greater than 5V, comparator U7B outputs a negative voltage, Q10 is turned off, and thyristor Q12 is also turned off.

[0047] The voltage stabilization principle is as follows: when the voltage is too low, the voltage between the resistor R32 and the resistor R34 decreases, and the output voltage of the comparator U7A increases, thereby increasing the output voltage of Q10 and connecting the thyristor Q12, that is, the voltage increases;

[0048] When the voltage is too high, the voltage between the resistor R32 and the resistor R34 increases, and the output voltage of the comparator U7A decreases, thereby reducing the output voltage of Q10 and turning off the thyristor Q12, that is, the voltage decreases.

[0049] The above process can control the output voltage. Since capacitor CF1 uses a large 10mF capacitor as an energy storage device, it can release a large current during an instantaneous pulse test, making it easy to complete the test process of the semiconductor device.

[0050] When testing the high source voltage source, the simplified schematic diagram is as follows Figure 4 As shown; wherein R113 = R2116, R175 = R176, Figure 3 In the test, voltage should be loaded to both ends of the CE of the device under test, namely VCE. VCE is controlled by the input voltage Ui. As long as a voltage of -10V to 10V is added to Ui, a voltage of -2000V to +2000V can be generated at CE. Since U121 is a follower,

[0051] Va=VE

[0052] And because R176=R175, U129 is an inverter, so

[0053] Vd=-VE

[0054] According to the operational amplifier formula,

[0055]

[0056] Since R113=R2116, we can get

[0057]

[0058]

[0059] It can be seen that the voltage applied to the device under test is determined by the control voltage Ui and changes linearly with Ui. In actual use, it is divided into three gears, namely 0~10V; 0~100V; 0~2000V. It runs well and the loading voltage is accurate.

[0060] When testing a high current source, the simplified schematic diagram is as follows Figure 5 As shown;

[0061] In the figure, a current is loaded to flow through the device under test, i.e. ICE. ICE is controlled by the input voltage Ui. As long as a voltage of -10V to 10V is added to Ui, a maximum current of -1250A to +1250A can be generated at CE. Because R220 is connected in series with the device under test, the current flowing through R220 is equal to ICE.

[0062] Because U210 is a follower,

[0063] Vf=VE

[0064] According to the operational amplifier formula,

[0065]

[0066] The current through IE and resistor R220 is

[0067]

[0068] Substituting into the above formula, we get

[0069]

[0070] It can be seen from the above formula that the current applied to the device under test is determined by the control voltage Ui, and changes linearly with Ui. In actual use, it is divided into 11 gears, namely 0~1uA; 0~10uA; 0~100uA; 0~1mA; 0~10mA; 0~100mA; 0~1A; 0~10A; 0~50A; 0~500A; 0~1250A, which runs well and the loading voltage is accurate.

[0071] When testing low source voltage, the simplified schematic diagram is as follows Figure 6 As shown;

[0072] In the figure, voltage is applied to both ends of the device under test GE, namely VGE. VGE is controlled by the input voltage Ui. As long as a voltage of -10V to 10V is added to Ui, a voltage of -20V to +20V can be generated at GE.

[0073] The analysis method is similar to that of the high source voltage source, and the final formula is:

[0074]

[0075] It can be seen that the voltage applied to the device under test is determined by the control voltage Ui and changes linearly with Ui.

[0076] When testing a low current source, the simplified schematic diagram is as follows Figure 7 As shown;

[0077] In the figure, the current to be loaded flows through the device under test, that is, IGE. IGE is controlled by the input voltage Ui. As long as a voltage of -10V to 10V is added to Ui, a current of -10A to +10A can be generated in GE.

[0078] The analysis method is similar to that of the high current source, and the final formula is:

[0079]

[0080] It can be seen that the current applied to the device under test is determined by the control voltage Ui and changes linearly with Ui.

[0081] In actual use, it is divided into 8 gears, namely 0~1uA; 0~10uA; 0~100uA; 0~1mA; 0~10mA; 0~100mA; 0~1A; 0~10A, which runs well and the loading voltage is accurate.

[0082] The power output module 5 amplifies the signal into the required power signal and outputs it to the test module 6. Figure 8 As shown, the power output module adopts a three-stage push-pull method. The current signal sent by the signal control module first drives the bias-amplified transistor MJE340. If the current does not reach the turn-on current of the transistor MJE340, the three-stage amplification is all cut off and the operational amplifier will output directly.

[0083] If the current reaches the turn-on current of transistor MJE340, the bias amplifier works, and transistor MJE340 outputs a signal to the intermediate amplifier. The intermediate amplifier transistors MJE15030 and MJE15031 work. Similarly, if the current does not reach the turn-on current of MJE15031, the intermediate amplifier does not work, and transistor MJE340 amplifies the output. This is analogous to the final drive of the four power output amplifier transistors MJE4343 to output current. The stage-by-stage amplification allows one power amplifier to be compatible with both tiny currents and large currents. The minimum current reaches 100nA, and the maximum current can reach 50A, which improves the accuracy and reliability of the test process and improves the efficiency of the test.

[0084] The test module 6 is used in conjunction with the power output module 5 to complete the test of the test device 7 .

[0085] The sampling module 8 includes a sampling module for voltage signals or current signals, and is used to collect the measured voltage signals or current signals generated on the test module 6 after the voltage or current is loaded on the test module 6 connected to the test device 7 .

[0086] The sampling modes of the sampling module 8 are divided into common voltage sampling, differential current sampling, common current sampling, high voltage sampling and high current sampling.

[0087] The common voltage sampling circuit is as follows Fig. 9 As shown, for low voltage sampling in the line that generally does not exceed 50V, ordinary voltage sampling is adopted, which is a standard differential amplifier circuit, that is, the voltage at both ends of CE is amplified and output.

[0088] The differential current sampling circuit diagram is as follows Fig.10As shown, for low source lines that generally do not exceed 20A, ordinary differential current sampling is used. It is a standard differential amplifier circuit. Here, because the current flowing through the sampling resistor is equal to the current of the device under test, the current sampled to the sampling resistor is the current flowing through the device under test. And because the structure of the sampling resistor is certain, as long as the voltage of the sampling resistor is obtained, the current can be obtained through the following formula.

[0089]

[0090] Where I is the current flowing through the sampling resistor (the current flowing through the device under test), U is the voltage of the sampling resistor, and R is the resistance value of the sampling resistor.

[0091] The schematic diagram of the common current sampling circuit is as follows Fig.11 As shown, for high source lines that generally do not exceed 50A, ordinary current sampling calculation method is used, which is the same as differential current sampling.

[0092] High voltage sampling circuit diagram Fig.12 As shown, when testing high voltage, the voltage is relatively high. If it is sampled directly like the ordinary voltage differential sampling method, the sampling op amp will be burned out. Therefore, the voltage is proportionally divided before passing through the op amp, and the original voltage is proportionally reduced to a voltage that will not burn out the op amp. It does not exceed 10V in the test machine.

[0093] The high current sampling circuit diagram is as follows Fig.13 As shown, when the current is greater than 50A, the resistance of the sampling resistor is very small, about 0.001. With such a small resistance, the accuracy of the resistor is difficult to reach 0.1%, so the design is carried out in a shunt accumulation manner, and 10 groups of sampling circuits are divided. Each group of sampling circuits corresponds to a group of current sources. In this way, accurate sampling can be achieved without burning out the device due to uneven current distribution in each group. Through the above circuit designs of the sampling module 8, the current and voltage can be accurately tested, and the sampling accuracy is directly related to the test accuracy. Therefore, the PC host 1 samples 2 / 3 after sending the measurement pulse, which can avoid the oscillation of the pulse in the initial state.

[0094] The signal processing module 9 judges the signal of the sampling module 8 to determine whether it is a voltage signal or a current signal, and amplifies or reduces it into a standard voltage signal and transmits it to the AD module 3.

[0095] The AD module 3 is also connected to a filter circuit, specifically as follows Fig.14 As shown, the filter circuit is divided into low-pass filtering and high-pass filtering. The low-pass filter is a low-pass filter composed of an operational amplifier, and the high-pass filter is a UAF42AP filter chip.

[0096] Therefore, the AD module 3 is specifically a 16-bit high-speed ADC700KP chip with a sampling speed of 2uS, and a sample holder SHC5320KP is added in front of the high-speed ADC700KP chip to ensure the stability of the signal, and then feed the signal back to the PC host 1.

[0097] In order to improve the test speed, a scanning test and an adapter are also provided, which are controlled by the PC host 1. Before each test, the corresponding relay is energized to the unit to be tested. The programming is easy and convenient, and multiple devices can be measured at one time. The test speed is particularly outstanding for multi-package devices.

[0098] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0099] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A multi-mode test system for semiconductor testing, characterized in that: It comprises a PC host (1) and a DA module (2) and an AD module (3) connected to the PC host (1) for signal communication; The PC host (1) is connected to a signal control module (4) via a DA module (2) signal, the signal control module (4) is connected to a power output module (5) signal, and the power output module (5) is connected to a test module (6) signal; The test module (6) is used to complete the test operation of the test device (7); The test module (6) is also signal-connected to a sampling module (8), the sampling module (8) is signal-connected to a signal processing module (9), and the signal processing module (9) feeds back the test signal to the PC host (1) through the AD module (3), thereby completing the test process of the test device (7); The signal control module (4) is used to divide the signal into a low source signal and a high source signal and output them, the low source signal is divided into a low source voltage source and a low source current source, and the high source signal is divided into a high source voltage source and a high source current source, and the power output module (5) amplifies the signal into a required power signal and outputs it to the test module (6); The signal control module (4) comprises a transformer T connected to an external 220V alternating current, a rectifier bridge A2, a thyristor Q12 and a thyristor Q13, a capacitor C9, a capacitor C10, a transistor Q10, a transistor Q11, a comparator U7A, a comparator U7B, a resistor R32, a resistor R34, a resistor R41, and a resistor R33; The transformer T is connected to two ends of the rectifier bridge A2, one end of the thyristor Q12 and the capacitor C9 are connected to one output end of the rectifier bridge A2, the other end of the capacitor C9 is connected in series with the capacitor C10 and then connected to the other end of the rectifier bridge A2, the other two ends of the thyristor Q12 are respectively connected to the transistor Q10 and the resistor R32, the second end of the transistor Q10 is connected to the comparator U7A, the third end of the transistor Q10 is respectively connected to one end of the transistor Q11 and the capacitor C9, the second end of the transistor Q11 is connected to the comparator U7B, the third end of the transistor Q11 is connected to the thyristor Q13, and the other two ends of the thyristor Q13 are respectively connected to the capacitor C10 and the resistor R 33, the other two ends of the comparator U7A are respectively connected to a 5V voltage and an output end of a resistor R32, the other two ends of the comparator U7B are respectively connected to a 5V voltage and an output end of a resistor R41, the resistors R32, R34, R41 and R33 are sequentially connected in series, the resistors R32 and R34 are connected in series in parallel with the capacitor CF1, the resistors R41 and R33 are connected in series in parallel with the capacitor CF2, the capacitor C9, the third end of the transistor Q10, the output end of the resistor R34 and the output end of the capacitor CF1 are all grounded, the output end of the capacitor CF1 is connected to the input end of the capacitor CF2, the capacitor CF1 and the capacitor CF2 are used to output a 65V high source signal and a 35V low source signal; During use, the external 220V AC power is first transformed by transformer T, then rectified into DC power by rectifier bridge A2, and then filtered into constant voltage by capacitors C9 and C10; At the beginning, the thyristor Q12 is not turned on, and the output voltage is 0. After comparison by the comparator U7A, the anode terminal is greater than 5V at this time, so the output voltage of the transistor Q10 is turned on, and the thyristor Q12 is also turned on. At this time, the voltage is output to the capacitor CF1. When the capacitor CF1 is fully charged, the voltage continues to rise. After the voltage is divided by the resistors R32 and R33, when it is greater than 5V, the comparator U7B outputs a negative voltage, the transistor Q10 is turned off, and the thyristor Q12 is also turned off; The voltage stabilization principle is as follows: when the voltage is too low, the voltage between the resistor R32 and the resistor R34 decreases, and the output voltage of the comparator U7A increases, thereby increasing the output voltage of the transistor Q10 and turning on the thyristor Q12, that is, the voltage increases; when the voltage is too high, the voltage between the resistor R32 and the resistor R34 increases, and the output voltage of the comparator U7A decreases, thereby decreasing the output voltage of the transistor Q10 and turning off the thyristor Q12, that is, the voltage decreases.

2. A multi-mode test system for semiconductor testing according to claim 1, characterized in that: The PC host (1) is pre-installed with test software, the test is written based on the IGBT test standard, the test feedback data is stored, displayed and judged, and the hardware encryption function is completed according to the design. The detection serial port is started by software, and the detection instruction is sent after the serial port is opened, and the detection code is returned according to the corresponding rules, so as to realize the combined encryption of software and hardware.

3. A multi-mode test system for semiconductor testing according to claim 1, characterized in that: The DA module (2) uses a high-speed DAC709KH chip with a 16-bit parallel port input. The high-speed DAC709KH chip converts the data signal into a voltage of an analog signal, wherein the voltage is -10V to 10V. During testing, the DA module (2) sends out at least one pulse signal.

4. A multi-mode test system for semiconductor testing according to claim 1, characterized in that: The test module (6) is used in conjunction with the power output module (5) to complete the test of the test device (7).

5. A multi-mode test system for semiconductor testing according to claim 1, characterized in that: The sampling module (8) includes a sampling module for a voltage signal or a current signal, and is used to collect the measured voltage signal or current signal generated on the test module (6) after the voltage or current is loaded on the test module (6) connected to the test device (7).

6. A multi-mode test system for semiconductor testing according to claim 5, characterized in that: The sampling modes of the sampling module (8) are divided into common voltage sampling, differential current sampling, common current sampling, high voltage sampling and high current sampling.

7. A multi-mode test system for semiconductor testing according to claim 1, characterized in that: The signal processing module (9) judges the signal of the sampling module (8), determines whether it is a voltage signal or a current signal, and amplifies or reduces it into a standard voltage signal and transmits it to the AD module (3).

8. A multi-mode test system for semiconductor testing according to claim 1, characterized in that: The AD module (3) is also connected to a filter circuit, which is divided into a low-pass filter and a high-pass filter. The low-pass filter is a low-pass filter composed of an operational amplifier, and the high-pass filter is a UAF42AP filter chip.

9. A multi-mode test system for semiconductor testing according to claim 1, characterized in that: Therefore, the AD module (3) is specifically a 16-bit high-speed ADC700KP chip with a sampling speed of 2uS, and a sample holder SHC5320KP is added in front of the high-speed ADC700KP chip to ensure the stability of the signal, and then the signal is fed back to the PC host (1).

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