PCELL layout design optimization method and device, medium and equipment

Abstract

The invention provides a PCELL layout design optimization method and device, a medium and equipment, and is applied to the technical field of chip design. Flexible layout drawing is carried out by acquiring the PCELL containing the process parameters and the graph adjustable parameters, so that the layout structure parameters of the current PCELL are obtained. A three-dimensional device simulation model is constructed by using the parameters, and a simulation compact model is created by using an artificial neural network algorithm to describe the electrical behavior of the device. And verifying the electrical performance trend of the three-dimensional device simulation model by using the PCELL and the simulation compact model. And when the verification is passed, further verifying whether the module test circuit meets a preset PPA index. And if yes, fixing the structural parameters of the current PCELL layout. According to the method, process and design requirements are integrated through a construction and parameterization method, and simulation and verification of closed-loop feedback are utilized, so that the design precision and the process maturity are improved, the development period is shortened, and the reliability and efficiency of the process are enhanced.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a PCELL layout design optimization method, device, medium and equipment. Background Art

[0002] As semiconductor process technology has entered the nanometer node, the introduction of the three-dimensional fin field effect transistor (FinFET) structure has effectively solved the short channel effect problem. The core feature of FinFET is a folded conductive channel composed of a fin-shaped thin layer of silicon, which is surrounded and controlled by the gate on three sides, which makes it have stronger gate control capability than the traditional planar MOSFET.

[0003] During the layout design phase, designers rely on parameterized cells (PCELL) to automatically generate device layouts that match the schematic. PCELL enables users to flexibly adjust the device layout structure by designing related CDF parameters and calling functions. The reliability and ease of use of the PCELL function directly affect the quality of layout drawing. However, integrated circuit technology is rapidly advancing to more advanced nodes, and the introduction of FinFET technology has further increased the complexity and cycle of device process research and development.

[0004] Therefore, how to effectively combine process and design, shorten the device development cycle and improve the maturity and reliability of the process has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] In view of the above problems, the present invention provides a PCELL layout design optimization method, device, medium and equipment that overcome the above problems or at least partially solve the above problems. The technical solution is as follows:

[0006] A PCELL layout design optimization method, comprising:

[0007] Obtaining a device PCELL of a FinFET device, wherein the device PCELL includes device process parameters and pattern adjustable parameters;

[0008] Drawing a device layout for the FinFET device using the graphic adjustable parameters to obtain current PCELL layout structure parameters of the FinFET device;

[0009] Based on the current PCELL layout structure parameters, construct a three-dimensional device simulation model of the FinFET device;

[0010] At least using the three-dimensional device simulation model to construct a simulation compact model based on an artificial neural network algorithm, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device;

[0011] Using the device PCELL and the simulation compact model, verify the device electrical performance influence trend of the three-dimensional device simulation model to obtain a simulation trend verification result;

[0012] When the simulation trend verification result is passed, verify whether the module test circuit of the simulation compact model meets the preset circuit PPA index. If so, output and fix the current PCELL layout structure parameters.

[0013] A PCELL layout design optimization device comprises: a device PCELL acquisition unit, a device layout drawing unit, a three-dimensional device simulation model construction unit, a simulation compact model construction unit, a simulation trend verification result acquisition unit, a circuit index verification unit and a PCELL layout structure parameter output unit.

[0014] The device PCELL obtaining unit is used to obtain the device PCELL of the FinFET device, wherein the device PCELL includes device process parameters and graphic adjustable parameters;

[0015] The device layout drawing unit is used to draw the device layout of the FinFET device using the graphic adjustable parameters to obtain the current PCELL layout structure parameters of the FinFET device;

[0016] The three-dimensional device simulation model construction unit is used to construct a three-dimensional device simulation model of the FinFET device based on the current PCELL layout structure parameters;

[0017] The simulation compact model construction unit is used to construct a simulation compact model based on an artificial neural network algorithm using at least a three-dimensional device simulation model, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device;

[0018] The simulation trend verification result obtaining unit is used to verify the device electrical performance influence trend of the three-dimensional device simulation model by using the device PCELL and the simulation compact model to obtain a simulation trend verification result;

[0019] The circuit indicator verification unit is used to verify whether the module test circuit of the simulation compact model meets the preset circuit PPA indicator when the simulation trend verification result is passed, and if so, trigger the PCELL layout structure parameter output unit;

[0020] The PCELL layout structure parameter output unit is used to output and fix the current PCELL layout structure parameters.

[0021] A computer-readable storage medium stores a program, which implements the PCELL layout design optimization method when executed by a processor.

[0022] An electronic device, comprising at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other via the bus; and the processor is used to call program instructions in the memory to execute the PCELL layout design optimization method.

[0023] By means of the above technical scheme, the present invention provides a PCELL layout design optimization method, device, medium and equipment to obtain the device PCELL of a FinFET device, wherein the device PCELL includes device process parameters and graphic adjustable parameters; the device layout of the FinFET device is drawn using the graphic adjustable parameters to obtain the current PCELL layout structure parameters of the FinFET device; based on the current PCELL layout structure parameters, a three-dimensional device simulation model of the FinFET device is constructed; at least using the three-dimensional device simulation model, a simulation compact model based on an artificial neural network algorithm is constructed, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device; using the device PCELL and the simulation compact model, the device electrical performance influence trend of the three-dimensional device simulation model is verified to obtain a simulation trend verification result; when the simulation trend verification result is passed, verify whether the module test circuit of the simulation compact model meets the preset circuit PPA index, and if so, output and fix the current PCELL layout structure parameters. Through the construction and parameterization of PCELL, the present invention can flexibly adjust the layout to match the process requirements, effectively combining the dual needs of process and design, and then through the closed-loop feedback mechanism of simulation and verification, it not only improves the design accuracy and process maturity, but also effectively shortens the device development cycle and improves the reliability and efficiency of the entire process.

[0024] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0026] Figure 1A schematic diagram showing a flow chart of an implementation method of a PCELL layout design optimization method provided by an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of a three-dimensional device structure of a FinFET device provided by an embodiment of the present invention is shown;

[0028] Figure 3 A schematic diagram showing the composition of a three-dimensional device structure of a FinFET device provided by an embodiment of the present invention is shown;

[0029] Figure 4 A schematic diagram showing the influence trend of a three-dimensional device structure on the electrical performance of a device provided by an embodiment of the present invention;

[0030] Figure 5 A flow chart showing another implementation of the PCELL layout design optimization method provided by an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of a PCELL layout provided by an embodiment of the present invention is shown;

[0032] Figure 7 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0033] Figure 8 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0034] Fig. 9 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0035] Fig.10 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0036] Fig.11 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0037] Fig.12 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0038] Fig.13 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0039] Fig.14 A schematic diagram of another PCELL layout provided by an embodiment of the present invention is shown;

[0040] Fig.15A flow chart showing another implementation of the PCELL layout design optimization method provided by an embodiment of the present invention;

[0041] Fig.16 An optimized logic block diagram of the device PCELL provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0043] As semiconductor process technology gradually enters the nano-node, three-dimensional fin field effect transistor (FinFET) is being widely adopted as an innovative device structure. The FinFET structure, with its unique design, effectively overcomes the short channel effect common in traditional planar MOSFET. Its main feature is that a folded conductive channel is formed by a thin layer of silicon in the shape of a fin, and the three sides of the fin are surrounded by a gate, which significantly enhances the gate's control over the channel. This feature makes FinFET an ideal choice in nano-scale semiconductor manufacturing.

[0044] In the design process of integrated circuits, the application of process design kits (PDKs) is crucial. PDKs support schematic design, layout design, and physical verification of integrated circuits. In the layout design stage, designers automatically generate device layouts by calling parameterized units (PCELLs). The design of PCELLs involves related CDF (Component Description Format) parameters and calling functions, and the device layout structure can be flexibly adjusted by modifying these parameters. The reliability and ease of use of the PCELL function directly affect the quality of layout drawing. However, with the transition to FinFET technology, the complexity of the PCELL layout structure of FinFET devices has increased significantly, posing new challenges.

[0045] Faced with the continuous development of integrated circuit design towards more advanced nodes, especially the introduction of FinFET technology, the device process R&D cycle has been significantly extended, usually in years. In order to meet this challenge, it is inevitable to introduce design-co-optimization methodology to accelerate the development of advanced processes. The current process R&D process generally follows the principle of first conducting device structure design and process R&D, and then developing a process design kit. However, with the adoption of co-optimization methodology and the extension of the R&D cycle, the traditional process development process needs to be adjusted. By shifting the relevant development process to the left, the iterative design process of processes and chips can be accelerated.

[0046] In the early stages of FinFET process development, it is necessary to continuously test devices with various layout structures. The introduction of design-process co-optimization methodology requires more flexible layout design capabilities. However, existing solutions are difficult to meet this demand, and more parameterized devices require longer optimization time.

[0047] Based on this, a PCELL layout design optimization method is provided in an embodiment of the present invention. First, by obtaining a PCELL containing process parameters and graphic adjustable parameters, a flexible layout drawing is performed to obtain the layout structure parameters of the current PCELL. Subsequently, a three-dimensional device simulation model is constructed using these parameters, and an artificial neural network algorithm is used to create a simulation compact model to describe the electrical behavior of the device. The electrical performance trend of the three-dimensional device simulation model is verified using PCELL and the simulation compact model. When the verification passes, it is further verified whether the module test circuit meets the preset PPA index. If so, the current PCELL layout structure parameters are fixed. It can be seen that the present invention integrates process and design requirements through construction and parameterization methods, and uses closed-loop feedback of simulation and verification to improve design accuracy and process maturity, shorten the device development cycle, and enhance the reliability and efficiency of the process.

[0048] like Figure 1 As shown, a flow chart of an implementation of a PCELL layout design optimization method provided by an embodiment of the present invention is provided, and the method may include:

[0049] S100, obtaining a device PCELL of a FinFET device, wherein the device PCELL includes device process parameters and graphic adjustable parameters.

[0050] Among them, FinFET device (fin field effect transistor) is a three-dimensional semiconductor device used in modern integrated circuits.

[0051] Among them, the device PCELL (Parameterized Cell) is an automated layout unit used in chip design. By assigning values ​​to its parameters, many different sub-units can be created simply and quickly, making circuits and layouts more convenient.

[0052] The device process parameters refer to the specific details of the FinFET device manufacturing process. The device process parameters determine the physical and electrical properties of the FinFET device. The device process parameters can be obtained by user input.

[0053] Optionally, the device process parameters may include channel length (Lch), channel width (Wch), fin height (HFin), oxide layer thickness (Tox), channel doping concentration (Nch), source and drain doping concentration (Nsd) and substrate doping concentration (Nsub).

[0054] Among them, the graphic adjustable parameters refer to the geometric parameters that can be adjusted when designing the parameterized cells of the FinFET device. The graphic adjustable parameters act on the specific layout of the FinFET device to meet the required electrical performance and physical requirements.

[0055] Optionally, the graphic adjustable parameters may include fin graphic parameters, gate graphic parameters, M0 layer metal graphic parameters, V0 layer graphic parameters, V0G layer graphic parameters, M1 layer metal graphic parameters, M0G layer metal graphic parameters, N / P injection layer parameters and N well graphic parameters. The basic parameters in the graphic adjustable parameters may be obtained by user input, and the restriction parameters are calculated by the basic parameters and the restriction relationship.

[0056] The embodiment of the present invention obtains the PCELL of the FinFET device, which includes the device process parameters and graphic adjustable parameters, so that the designer can flexibly adjust the layout to match the process requirements.

[0057] Among them, the CDF parameter naming method defined by the device process parameters and the graphic adjustable parameters may include: 1. The rectangular side parallel to the x-axis of the layout coordinate is called the width (W), the rectangular side parallel to the y-axis of the layout coordinate is called the length (L), and the center spacing of the rectangular array graphics is defined as P. 2. Establish naming rules for the width and length of rectangles of different layers. The naming is carried out in the format of "device width / length (uppercase letters) + layout layer (lowercase letters)". For example, "Waa" represents the width of the active area, "Laa" represents the length of the active area, and "Pgt" represents the gate spacing. 3. During the graphic drawing process, some graphics (such as graphic A) may need to be designed based on the relative parameters of other graphics (such as graphic B). For this purpose, four relative position parameters are defined, representing the left side, right side, top side and bottom side respectively. These parameters are abbreviated as l (left), r (right), t (top) and b (bottom) in the device naming. The embodiment of the present invention facilitates subsequent design and communication by establishing a clear and consistent parameter naming system for device design.

[0058] S110, using graphic adjustable parameters to draw the device layout of the FinFET device to obtain the current PCELL layout structure parameters of the FinFET device.

[0059] Device layout drawing is the process of converting circuit design into geometric graphics in integrated circuit design for manufacturing on semiconductor wafers. Device layout drawing involves using computer-aided design tools to create detailed physical graphic representations of various devices and interconnections. These graphics define the size, shape and location of each device, as well as how they are connected.

[0060] Among them, PCELL layout structure parameters refer to the structural parameters corresponding to the generated layout instance after the device layout of the FinFET device is drawn using graphical adjustable parameters. PCELL layout structure parameters support customizing the shape, size, position and other geometric features of the layout unit by setting or adjusting parameters. This allows the same FinFET device to quickly generate different geometric versions under different conditions without having to draw from scratch.

[0061] S120. Based on the current PCELL layout structure parameters, a three-dimensional device simulation model of the FinFET device is constructed.

[0062] Specifically, the embodiment of the present invention can create a three-dimensional device simulation model having a three-dimensional device structure corresponding to the current PCELL layout structure parameters through 3D simulation software. Figure 2As shown in (1)-(9), the three-dimensional device structure, i.e., the three-dimensional schematic diagram of the FinFET device under the current PCELL layout structure parameters, is consistent with the actual structure of the FinFET device.

[0063] like Figure 3 As shown, in the three-dimensional device simulation model, each adjustable parameter is consistent with the current PCELL layout structure parameters, and the three-dimensional device structure includes the following components: a substrate 10, a fin structure 20, a dielectric material layer 30 on the substrate, a silicon germanium epitaxial layer 40, a source and drain region 50, a virtual gate 60 and a gate 70.

[0064] The embodiments of the present invention can utilize the three-dimensional device simulation model of the FinFET device to analyze the impact of different device process parameters and graphic adjustable parameters on device performance through simulation, and establish the weight ranking of parameter impact and the trend of impact on electrical performance. These results are used to guide the subsequent device optimization design. For example: In the case of using the current three-dimensional device structure, the impact of different fin widths on the device threshold voltage (Vth), subthreshold swing (SS) and drain-induced barrier lowering (DIBL) are as follows: Figure 4 As shown in (a), (b) and (c).

[0065] S130, constructing a simulation compact model based on an artificial neural network algorithm using at least the three-dimensional device simulation model, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device.

[0066] Among them, the simulation compact model (Compact Model) is a mathematical model used to describe the electrical behavior of semiconductor devices, which is usually used in circuit simulation tools to effectively simulate device performance in system-level design.

[0067] Specifically, the embodiments of the present invention can use a three-dimensional simulation model to obtain electrical characteristic data under various operating conditions. For example: current, voltage relationship, threshold voltage and leakage current, etc. Use machine learning methods (such as artificial neural networks) to train the simulation compact model. The neural network can learn complex nonlinear relationships from simulation data and help generate a mathematical model that can accurately predict device behavior. The simulation compact model is verified to ensure that it can accurately simulate device behavior under various conditions. By adjusting the model parameters of the simulation compact model, the corresponding simulation accuracy can be improved.

[0068] S140. Using the device PCELL and the simulation compact model, verify the influence trend of the device electrical performance of the three-dimensional device simulation model to obtain the simulation trend verification result.

[0069] The device electrical performance impact trend refers to the trend of how the electrical characteristics of FinFET devices (such as current, voltage, threshold voltage, subthreshold swing, etc.) change under different parameter conditions. The device electrical performance impact trend reflects the impact of device design and process changes on device performance.

[0070] Specifically, the embodiment of the present invention can use the simulation compact model to simulate different PCELL configurations, predict their electrical performance, obtain simulation results, compare the simulation results with experimental data (such as actual tests or higher-precision model results), and verify the accuracy of the simulation compact model's influence on electrical performance. If the simulation results are consistent with the experimental data, it means that the simulation compact model can accurately capture the influence trend of electrical performance.

[0071] When the simulation trend verification result is passed, step S150 is executed.

[0072] S150, verify whether the module test circuit of the simulation compact model meets the preset circuit PPA index, if yes, execute step S160.

[0073] S160, output and fix the current PCELL layout structure parameters.

[0074] Among them, the module test circuit refers to a circuit used to test and verify the performance of specific functional modules (such as amplifiers, filters, storage units, etc.) during the integrated circuit design and verification process.

[0075] Among them, the circuit PPA index refers to the three key criteria for evaluating the performance of electronic circuit design: power consumption, performance, and area. The circuit PPA index is an important factor in measuring the quality and efficiency of integrated circuit design.

[0076] Specifically, an embodiment of the present invention can generate a symbolic representation (Symbol) of the electrical behavior of a FinFET device using a simulation compact model. A module test circuit is established by a fully customized circuit design method. For example, the established module test circuit can be a multiplier-accumulator circuit. A circuit PPA index is established for the module test circuit in advance, and the weight ranking of the index is set. For the multiplier-accumulator test circuit, the following indicators can be set: power consumption index P1, energy efficiency ratio index P2, and area index A1. Using the principle of area minimization, the area index A1 is given the highest weight ranking RANK1, followed by the energy efficiency ratio index RANK2, and finally the power consumption index RANK3. The module test circuit is simulated to obtain the circuit performance results, and compared with the preset circuit PPA index. If the circuit performance results meet the index requirements of the preset circuit PPA index, the current PCELL layout structure parameters are output and fixed, and the adjustable structure parameter function is turned off to ensure the stability and consistency of the design.

[0077] The present invention provides a PCELL layout design optimization method, which includes: obtaining a device PCELL of a FinFET device, wherein the device PCELL includes a device process parameter and a graphic adjustable parameter; using the graphic adjustable parameter to draw a device layout of the FinFET device to obtain the current PCELL layout structure parameters of the FinFET device; constructing a three-dimensional device simulation model of the FinFET device based on the current PCELL layout structure parameters; at least using the three-dimensional device simulation model to construct a simulation compact model based on an artificial neural network algorithm, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device; using the device PCELL and the simulation compact model to verify the device electrical performance influence trend of the three-dimensional device simulation model to obtain a simulation trend verification result; when the simulation trend verification result is passed, verifying whether the module test circuit of the simulation compact model meets the preset circuit PPA index, and if so, outputting and fixing the current PCELL layout structure parameters. Through the construction and parameterization of PCELL, the present invention can flexibly adjust the layout to match the process requirements, effectively combining the dual needs of process and design, and then through the closed-loop feedback mechanism of simulation and verification, it not only improves the design accuracy and process maturity, but also effectively shortens the device development cycle and improves the reliability and efficiency of the entire process.

[0078] Optional, in the above Figure 1 On the basis of one or more corresponding embodiments, in another optional embodiment provided by the embodiment of the present invention, the method may further include:

[0079] When the verification module test circuit does not meet the preset circuit PPA index, the device PCELL is corrected according to the preset device performance index, and the step of using the graphic adjustable parameters to draw the device layout of the FinFET device is returned to obtain the current PCELL layout structure parameters of the FinFET device.

[0080] Device performance indicators refer to specific parameters used to evaluate and optimize device performance. Device performance indicators are used to ensure that the performance of a device in a specific application meets the expected standards.

[0081] Optionally, the device performance indicators may include switching current (Ion / Ioff), subthreshold swing (SS) and threshold voltage (Vth), etc.

[0082] Through rapid iteration and feedback loops, the embodiments of the present invention can quickly identify and correct problems that cause the PPA index to not be met, thereby timely correcting the device PCELL to make it closer to the ideal performance index, thereby reducing repeated experiments in the FinFET device development cycle and improving overall design efficiency.

[0083] Optional, based on Figure 1 The method shown, such as Figure 5 As shown, a flow chart of another implementation of the PCELL layout design optimization method provided by an embodiment of the present invention is shown, and step S110 may specifically include:

[0084] S200, based on the gate pattern parameters, draw the device gate rectangular pattern and active area pattern area with the layout coordinate origin as the center to obtain the first PCELL layout.

[0085] Among them, the gate pattern parameters may include gate width (Wgt), gate pitch (Pgt), gate length (Lgt), number of virtual gates (Ndumgate), virtual gate width (Wdumgate) and gate extension length (Lgtex2gtt / Lgtex2gtb).

[0086] Among them, the gate width, gate spacing, number of virtual gates and virtual gate width can be obtained by user input. The gate length is calculated by the formula: Lgt = (Wch / (Wfin+2×Hfin)×Pfin. The gate extension length is divided into the top and bottom, namely: Length Gate extension (Top) and Length Gate extension (Bottom) parameters.

[0087] Specifically, Figure 6As shown, the embodiment of the present invention can draw the gate rectangular pattern of the device with the layout coordinate (0, 0) as the center according to the gate pattern parameters. On this basis, on the left and right sides of the gate, a virtual gate array is drawn according to the number of virtual gates. At the same time, the extension area of ​​the gate and the virtual gate is drawn according to the extension length of the top and bottom. Figure 7 As shown in the figure, the width of the active area is determined by the gate spacing and the number of virtual gates, and its calculation formula is: Laa = Pgate × Ndumgate. The height of the active area is the same as the gate width, that is: Waa = Wgate. At the center point (0, 0) of the layout, draw a rectangular active area with a horizontal width of Waa and a vertical length of Laa.

[0088] S210. Based on the first PCELL layout, according to the M0 layer metal graphic parameters, draw the M0 layer metal graphic area with the central symmetric point between adjacent virtual gates as the center to obtain the second PCELL layout.

[0089] The M0 layer metal pattern parameters may include the M0 layer metal width (Wm0) and the M0 layer metal length (Lm0). The M0 layer metal width may be obtained by user input. The M0 layer metal length is consistent with the gate length.

[0090] Specifically, the embodiment of the present invention can draw a rectangular array composed of M0 layer metal with adjacent gates and virtual gates as the center. Each rectangle has a lateral width of Wm0 and a longitudinal length of Lm0. Figure 8 shown.

[0091] S220. Based on the second PCELL layout, according to the V0 layer graphic parameters and with the M0 layer metal bottom spacing as the bottom starting position, draw a V0 hole array for connecting the M1 layer and the M0 layer to obtain a third PCELL layout.

[0092] The V0 layer graphic parameters may include the V0 hole width (Wv0), the V0 hole spacing (Pv0), and the distance between the V0 hole and the end of the M0 / M1 layer (Lm02v0 / Lm12v0). The V0 layer graphic parameters may be obtained by user input.

[0093] Specifically, the embodiment of the present invention can use the bottom end spacing of the M0 layer metal as the initial reference point, and then draw the V0 hole array for connecting the M1 layer and the M0 layer, such as Fig. 9 shown.

[0094] S230. On the basis of the third PCELL layout, according to the M1 layer metal pattern parameters, draw the M1 layer metal pattern area based on the center points of each column V0 array to obtain a fourth PCELL layout.

[0095] The M1 layer metal pattern parameters may include the M1 layer metal width (Wm1) and the M1 layer metal length (Lm1). The M1 layer metal width may be obtained by user input. The M1 layer metal length is consistent with the gate length.

[0096] Specifically, in the embodiment of the present invention, an M1 rectangular array can be drawn at the center of each column of V0 hole array. The horizontal width of each rectangle is Wm1, and the vertical length is Lm1. Lv02m1 is the distance from the V0 hole to the M1 layer, such as Fig.10 shown.

[0097] S240. Based on the fourth PCELL layout, draw the M0G layer metal graphic area according to the M0G layer metal graphic parameters, and draw the V0G hole in the center of the M0G layer metal graphic according to the V0G layer graphic parameters, and then draw the M1 layer metal graphic with the V0G hole as the center to obtain the fifth PCELL layout.

[0098] Among them, the M0G layer metal pattern parameters may include the M0G layer metal width (Wm0g), the M0G layer metal length (Lm0g) and the distance between the M0G metal and the gate end (Lm0g2gt). The M0G layer metal pattern parameters are obtained by user input. The M0G layer metal width needs to satisfy: Wm0g>Wv0. The M0G layer metal length needs to satisfy: Lm0g>Wv0.

[0099] The V0G layer graphic parameters may include the V0G hole width (Wv0g), the V0G hole spacing (Pv0g), and the distance between the V0G hole and the end of the M0 / M1 layer (Lm02v0g / Lm12v0g). The V0G layer graphic parameters may be obtained by user input.

[0100] Specifically, in the embodiment of the present invention, a M0G rectangular pattern can be drawn at a position Lm0g2gt away from the top or bottom of the gate, with a horizontal width of Wm0g and a vertical length of Lm0g. A V0G hole is placed at the center of each M0G rectangular pattern. Then, a rectangular metal of the M1 layer is drawn with the V0G hole as the center, such as Fig.11 shown.

[0101] S250. On the basis of the fifth PCELL layout, according to the N / P injection layer parameters, draw the SP / SN layer graphic area based on the center of the gate to obtain the sixth PCELL layout.

[0102] Among them, the N / P injection layer parameters may include the SP / SN layer width (Wsp / Wsn) and the SP / SN layer length (Lsp / Lsn). The SP / SN layer width satisfies the relationship: Wsx = Pgate × Ndumgate + Wsxex × 2, where Wsxex is the extension parameter of the lateral length, which is obtained by user input. The SP / SN layer length satisfies the relationship: Lsx = Lgate + lgextop + lgexbottom.

[0103] Specifically, the embodiment of the present invention can draw a rectangular figure with the center of the gate as the reference, and its horizontal width is Wsx and its vertical length is Lsx, such as Fig.12 shown.

[0104] S260 . Based on the sixth PCELL layout, according to the N-well pattern parameters, draw the Nwell layer pattern area based on the center of the gate to obtain the seventh PCELL layout.

[0105] Among them, the N-well graphic parameters may include the lateral diffusion of Nwell relative to SP / SN (Wwspexl / Wwspexr) and the longitudinal diffusion length of Nwell relative to SP / SN (Llspextop / Llspexbot). The N-well graphic parameters can be obtained by user input. The lateral diffusion of Nwell relative to SP / SN corresponds to the left and right sides respectively. The longitudinal diffusion length of Nwell relative to SP / SN corresponds to the upper and lower sides respectively.

[0106] Specifically, draw the graphic area of ​​the Nwell layer. Based on the center of the gate, draw a rectangular graphic with a horizontal width of Wnw and a vertical length of Lnw, such as Fig.13 shown.

[0107] Wherein, the calculation formula of Wnw is Wnw=Wsp+Wwspex1+WwspexrWnw=Wsp+Ww spex1+Wwspexr. The calculation formula of Lnw is: Lnw=Llspextop+LlspexbotLnw=Llspextop+Llspexbot.

[0108] S270. On the basis of the seventh PCELL layout, according to the fin Fin graphic parameters, with the gate center as the starting point, the gate center coincides with the fin spacing center, and the Fin graphic area is drawn along the positive and negative directions of the y-axis, wherein the Fin graphic in the Fin graphic area is perpendicular to the gate direction, to obtain the eighth PCELL layout.

[0109] The fin graphic parameters may include fin width (Wfin) and fin spacing (Pfin). The fin graphic parameters may be obtained by user input.

[0110] Specifically, the embodiment of the present invention can use the center of the gate as the starting point, align it with the center of the fin spacing, and establish a rectangular Fin array along the positive and negative directions of the y-axis, where the Fin pattern is perpendicular to the gate direction. The calculation formula for the total width and length of the Fin area is as follows:

[0111] Lfinmax=[Lmax / Pfin]+4×Pfin

[0112] Wfinmax=Wmax+2×WexfiN

[0113] The length of the fin area is calculated by dividing the length of the largest pattern by the fin pitch and rounding it up, then extending it by 2 times the fin pitch on both the top and bottom sides.

[0114] The width of the Fin region is related to the width of the largest pattern and is extended by the Wexfin distance on both sides. Wexfin is the CDF parameter associated with the Fin image and is obtained by user input.

[0115] Optionally, for an NMOS device, the maximum pattern area is the SP layer; for a PMOS device, the maximum pattern area is the NW layer.

[0116] The Fin graphic area drawn is as follows Fig.14 shown.

[0117] S280, extracting the structural information of the eighth PCELL layout, and obtaining the current PCELL layout structural parameters of the FinFET device.

[0118] The embodiment of the present invention gradually constructs the PCELL layout, and each step is expanded and optimized based on the previous step, making the design process more modular. At the same time, based on parametric design, users can flexibly adjust the size and position parameters of each layer according to different design requirements, thereby realizing the design of FinFET devices with different specifications and performances. When the design requirements or process parameters change, the design can be quickly updated by adjusting the corresponding parameters, which not only improves the accuracy and efficiency of the design, but also provides strong support for the optimized design of FinFET devices.

[0119] Optional, based on Figure 1 The method shown, such as Fig.15 As shown, a flow chart of another implementation of the PCELL layout design optimization method provided by an embodiment of the present invention is shown, and step S130 may specifically include:

[0120] S300, obtaining an electrical characteristic curve data set of a three-dimensional device simulation model, wherein the electrical characteristic curve data set includes simulation trend data of the influence of different device process parameters and different graphic adjustable parameters of the three-dimensional device simulation model on the device electrical performance.

[0121] The simulation trend data may include electrical characteristic curve data including a relationship curve between drain current (Id) and gate voltage (Vg) and a relationship curve between current (Id) and drain-source voltage (Vd).

[0122] Specifically, the embodiment of the present invention can run a three-dimensional device model in simulation software, calculate the electrical response of the device under different conditions, and generate a variety of electrical characteristic data, such as current, voltage, power density, etc. The required electrical characteristic curves, such as Id-Vg and Id-Vd curves, are extracted from the simulation results. These curves reflect the conductive performance of the device under different voltages.

[0123] S310 , dividing the electrical characteristic curve data set into a training data set and a test data set.

[0124] S320: Use the training data in the training data set to train the pre-built artificial neural network algorithm to generate a prediction model.

[0125] Among them, artificial neural network algorithms can be built based on programming languages ​​such as Python.

[0126] S330: Input the test data in the test data set into the prediction model to obtain the prediction data output by the prediction model.

[0127] S340, calculating the root mean square error between the predicted data and the test data.

[0128] Among them, the root mean square error (RMSE) is a statistical indicator used to evaluate the accuracy of the prediction model. The root mean square error measures the prediction error of the model by measuring the difference between the predicted value and the actual observed value. Specifically, the RMSE value is the average of the squares of these differences (errors) and then the square root. The smaller the RMSE value, the higher the prediction accuracy of the model, that is, the smaller the difference between the predicted value and the actual value.

[0129] S350, determine whether the root mean square error exceeds a preset root mean square threshold, if not, execute step S360, if yes, execute step S370.

[0130] The preset RMS threshold can be obtained by user input according to actual needs of the user.

[0131] S360, using a hardware description language for analog circuit design to implement an artificial neural network algorithm, and generating a simulation compact model based on the artificial neural network algorithm.

[0132] The hardware description language used for analog circuit design may be a Veriloga programming language.

[0133] S370, adjust the algorithm result or parameter of the artificial neural network algorithm, and return to execute step S320.

[0134] The embodiment of the present invention can generate an efficient prediction model by using the electrical characteristic curve data set for training an artificial neural network. The use of the neural network prediction model can capture complex nonlinear relationships and achieve accurate prediction of device performance. The accuracy of the model is ensured by comparing the test data with the predicted data. When the error exceeds the threshold, adjustments are made to further improve the model accuracy. Once a simulation compact model based on an artificial neural network is generated, it can be implemented through a hardware description language and directly applied to the circuit design process, thereby simplifying the process from device simulation to circuit implementation and improving design efficiency.

[0135] Optional, in the above Fig.15 On the basis of one or more corresponding embodiments, in another optional embodiment provided by the embodiment of the present invention, the device PCELL and the simulation compact model are used to verify the influence trend of the device electrical performance of the three-dimensional device simulation model, and obtain the simulation trend verification result, which may specifically include:

[0136] Generate a symbolic representation of the electrical behavior of the FinFET device using a simulation compact model; generate a TCAD process simulation model by combining the symbolic representation and the device PCELL; use the TCAD process simulation model to test the effects of different device process parameters and different graphically adjustable parameters on the device electrical performance of the three-dimensional device simulation model, and obtain measured trend data; verify whether the trends of the measured trend data and the simulation trend data are consistent, if so, the simulation trend verification result is passed, otherwise, the simulation trend verification result is failed.

[0137] Among them, the symbol representation is a graphic symbol that can be used in circuit design, which contains the pins and connection information of the device.

[0138] Among them, the TCAD process simulation model (Technology Computer-Aided Design) is a computer-aided design tool used to simulate and analyze the manufacturing process and performance of semiconductor devices. The TCAD process simulation model predicts the behavior of devices under different manufacturing conditions through numerical simulation methods.

[0139] Specifically, an embodiment of the present invention can create a test library in a circuit design platform and import process-related files, including techfile.tf, display.drf, and stream.map. A simulation compact model of an N / P-type MOS device, namely a Verilog-A model, is established in the test library. The device symbol is automatically generated based on the Verilog-A model for use in circuit schematic design. The device PCELL is imported for circuit and layout design. The measured trend data obtained by tape-out based on the TCAD process simulation model is compared with the simulation trend data. If the trend is found to be inconsistent, the TCAD process simulation model is optimized.

[0140] The embodiment of the present invention not only improves the efficiency of design and verification, but also enhances the accuracy and reliability of the model and design through the combination of symbolic representation, TCAD process simulation model generation and actual measurement verification, and supports efficient device development and continuous optimization.

[0141] Optionally, the embodiment of the present invention may also optimize the TCAD process simulation model when the simulation trend verification result fails, and based on the optimized TCAD process simulation model, return to execute the step of using the TCAD process simulation model to test the effects of different device process parameters and different graphic adjustable parameters on the device electrical performance of the three-dimensional device simulation model.

[0142] Specifically, the embodiment of the present invention can identify the specific differences between the measured trend data and the simulated trend data, and analyze the possible reasons for the differences, such as physical effects not considered in the model, inaccurate parameter settings, or insufficient model complexity, to generate inconsistency analysis results. According to the inconsistency analysis results, the device process parameters and graphic adjustable parameters in the TCAD process simulation model are adjusted. After each model adjustment, the simulation is rerun and compared with the measured data. After multiple iterations, the measured trend data is gradually approached.

[0143] The embodiment of the present invention optimizes the TCAD process simulation model to make the simulation trend data more consistent with the measured trend data, thereby ensuring the validity of the simulation trend verification result.

[0144] In order to facilitate understanding of the optimization logic of the device PCELL of the embodiment of the present invention, Fig.16Explanation: First, determine the optimization target range of device performance parameters and set device performance indicators, including on / off current ratio (Ion / Ioff), subthreshold swing (SS), and threshold voltage (Vth). Next, generate a symbolic representation of the electrical behavior of the FinFET device based on the simulation compact model, and create a module test circuit through a fully customized circuit design method. Set performance PPA indicators for the module test circuit and set weight rankings. Simulate and tape-out verify the module test circuit to obtain its performance results, and compare them with the performance PPA indicators in turn. If the simulation results do not meet these indicators, optimize the TCAD process simulation model, device process parameters, and current PCELL layout structure parameters until the preset device performance indicators are met. Then, modify the device PCELL, three-dimensional device simulation model, and simulation compact model in turn, redesign the module test circuit, and simulate and tape-out verify the module test circuit again until the simulation results meet the performance PPA indicators. At this time, output and fix the PCELL layout structure parameters, and disable the adjustable structure parameter function.

[0145] Although operations are depicted in a particular order, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order.Multitasking and parallel processing may be advantageous under certain circumstances.

[0146] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0147] Corresponding to the above method embodiments, an embodiment of the present invention also provides a PCELL layout design optimization device, which may include: a device PCELL acquisition unit, a device layout drawing unit, a three-dimensional device simulation model construction unit, a simulation compact model construction unit, a simulation trend verification result acquisition unit, a circuit indicator verification unit and a PCELL layout structure parameter output unit.

[0148] The device PCELL obtaining unit is used to obtain the device PCELL of the FinFET device, wherein the device PCELL includes device process parameters and graphic adjustable parameters.

[0149] The device layout drawing unit is used to draw the device layout of the FinFET device using graphically adjustable parameters to obtain the current PCELL layout structure parameters of the FinFET device.

[0150] The three-dimensional device simulation model building unit is used to build a three-dimensional device simulation model of the FinFET device based on the current PCELL layout structure parameters.

[0151] The simulation compact model construction unit is used to construct a simulation compact model based on an artificial neural network algorithm using at least a three-dimensional device simulation model, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device.

[0152] The simulation trend verification result obtaining unit is used to verify the device electrical performance influence trend of the three-dimensional device simulation model by using the device PCELL and the simulation compact model, and obtain the simulation trend verification result.

[0153] The circuit indicator verification unit is used to verify whether the module test circuit of the simulation compact model meets the preset circuit PPA indicator when the simulation trend verification result is passed. If so, the PCELL layout structure parameter output unit is triggered.

[0154] The PCELL layout structure parameter output unit is used to output and fix the current PCELL layout structure parameters.

[0155] Optionally, the PCELL layout design optimization device may also include a parameter correction unit.

[0156] The parameter correction unit is used to correct the device PCELL according to the preset device performance index and trigger the device layout drawing unit when the verification module test circuit does not meet the preset circuit PPA index.

[0157] Optionally, the adjustable graphic parameters include fin graphic parameters, gate graphic parameters, M0 layer metal graphic parameters, V0 layer graphic parameters, V0G layer graphic parameters, M1 layer metal graphic parameters, M0G layer metal graphic parameters, N / P injection layer parameters and N well graphic parameters.

[0158] Optionally, the device layout drawing unit is specifically used to draw the device gate rectangular graphic and active area graphic area according to the gate graphic parameters and the layout coordinate origin as the center to obtain a first PCELL layout; on the basis of the first PCELL layout, according to the M0 layer metal graphic parameters, with the central symmetry point between adjacent virtual gates as the center, draw the M0 layer metal graphic area to obtain a second PCELL layout; on the basis of the second PCELL layout, according to the V0 layer graphic parameters, with the M0 layer metal bottom end spacing as the bottom starting position, draw the V0 hole array for connecting the M1 layer and the M0 layer to obtain a third PCELL layout; on the basis of the third PCELL layout, according to the M1 layer metal graphic parameters, based on the center points of each column of the V0 array, draw the M1 layer metal graphic area to obtain a fourth PCELL layout; on the basis of the fourth PCELL layout, according to the M0G layer metal graphic parameters, draw the M0G layer metal graphic area, and according to Based on the V0G layer graphic parameters, a V0G hole is drawn at the center of the M0G layer metal graphic, and then the M1 layer metal graphic is drawn with the V0G hole as the center to obtain the fifth PCELL layout; based on the fifth PCELL layout, according to the N / P injection layer layer parameters, the SP / SN layer graphic area is drawn based on the center of the gate to obtain the sixth PCELL layout; based on the sixth PCELL layout, according to the N well graphic parameters, the Nwell layer graphic area is drawn based on the center of the gate to obtain the seventh PCELL layout; based on the seventh PCELL layout, according to the fin Fin graphic parameters, with the center of the gate as the starting point, the center of the gate coincides with the center of the fin spacing, and the Fin graphic area is drawn along the positive and negative directions of the y-axis, wherein the Fin graphic in the Fin graphic area is perpendicular to the gate direction to obtain the eighth PCELL layout; the structural information of the eighth PCELL layout is extracted to obtain the current PCELL layout structural parameters of the FinFET device.

[0159] Optionally, the simulation compact model construction unit includes: an electrical characteristic curve data set acquisition subunit, a data set division subunit, a prediction model generation subunit, a prediction data acquisition subunit, a root mean square error calculation subunit, an error judgment subunit, a model generation subunit and an algorithm adjustment subunit.

[0160] The electrical characteristic curve data set acquisition subunit is used to obtain the electrical characteristic curve data set of the three-dimensional device simulation model, wherein the electrical characteristic curve data set includes simulation trend data of the influence of different device process parameters and different graphic adjustable parameters of the three-dimensional device simulation model on the device electrical performance.

[0161] The data set division subunit is used to divide the electrical characteristic curve data set into a training data set and a test data set.

[0162] The prediction model generation subunit is used to train the pre-built artificial neural network algorithm using the training data in the training data set to generate a prediction model.

[0163] The prediction data acquisition subunit is used to input the test data in the test data set into the prediction model to obtain the prediction data output by the prediction model.

[0164] The root mean square error calculation subunit is used to calculate the root mean square error between the prediction data and the test data.

[0165] The error determination subunit is used to determine whether the root mean square error exceeds a preset root mean square threshold, and if not, trigger the model generation subunit.

[0166] The model generation subunit is used to implement the artificial neural network algorithm using a hardware description language used for analog circuit design, and to generate a simulation compact model based on the artificial neural network algorithm.

[0167] The algorithm adjustment subunit is used to adjust the algorithm results or parameters of the artificial neural network algorithm and trigger the prediction model generation subunit.

[0168] Optionally, the simulation trend verification result acquisition unit includes: a symbol representation generation subunit, a TCAD process simulation model generation subunit, a measured trend data acquisition subunit and a trend verification subunit.

[0169] A symbolic representation generation subunit is used to generate a symbolic representation of the electrical behavior of the FinFET device using the simulation compact model.

[0170] The TCAD process simulation model generation subunit is used to generate a TCAD process simulation model by combining the symbolic representation and the device PCELL.

[0171] The measured trend data acquisition subunit is used to use the TCAD process simulation model to test the influence of different device process parameters and different graphic adjustable parameters on the device electrical performance of the three-dimensional device simulation model, and obtain the measured trend data.

[0172] The trend verification subunit is used to verify whether the trends of the measured trend data and the simulated trend data are consistent. If so, the simulation trend verification result is passed, otherwise, the simulation trend verification result is failed.

[0173] Optionally, the simulation trend verification result obtaining unit may also include: a TCAD process simulation model optimization subunit.

[0174] The TCAD process simulation model optimization value unit is used to optimize the TCAD process simulation model when the simulation trend verification result fails, and trigger the measured trend data acquisition subunit based on the optimized TCAD process simulation model.

[0175] Regarding the device in the above embodiment, the specific manner in which each unit performs the operation has been described in detail in the embodiment of the method, and will not be elaborated here.

[0176] The present invention provides a PCELL layout design optimization device, which is used to: obtain the device PCELL of a FinFET device, wherein the device PCELL includes device process parameters and graphic adjustable parameters; use the graphic adjustable parameters to draw the device layout of the FinFET device to obtain the current PCELL layout structure parameters of the FinFET device; construct a three-dimensional device simulation model of the FinFET device based on the current PCELL layout structure parameters; at least use the three-dimensional device simulation model to construct a simulation compact model based on an artificial neural network algorithm, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device; use the device PCELL and the simulation compact model to verify the device electrical performance influence trend of the three-dimensional device simulation model to obtain a simulation trend verification result; when the simulation trend verification result is passed, verify whether the module test circuit of the simulation compact model meets the preset circuit PPA index, and if so, output and fix the current PCELL layout structure parameters. Through the construction and parameterization of PCELL, the present invention can flexibly adjust the layout to match the process requirements, effectively combining the dual needs of process and design, and then through the closed-loop feedback mechanism of simulation and verification, it not only improves the design accuracy and process maturity, but also effectively shortens the device development cycle and improves the reliability and efficiency of the entire process.

[0177] The PCELL layout design optimization device includes a processor and a memory. The above-mentioned device PCELL acquisition unit, device layout drawing unit, three-dimensional device simulation model construction unit, simulation compact model construction unit, simulation trend verification result acquisition unit, circuit index verification unit and PCELL layout structure parameter output unit are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0178] The processor contains a core, which calls the corresponding program unit from the memory. One or more cores can be set, and the process and design requirements can be integrated through construction and parameterization methods by adjusting the core parameters, and the closed-loop feedback simulation and verification can be used to improve the design accuracy and process maturity, shorten the development cycle, and enhance the reliability and efficiency of the process.

[0179] An embodiment of the present invention provides a computer-readable storage medium having a program stored thereon, which implements the PCELL layout design optimization method when executed by a processor.

[0180] An embodiment of the present invention provides a processor, which is used to run a program, wherein the PCELL layout design optimization method is executed when the program is running.

[0181] An embodiment of the present invention provides an electronic device, the electronic device includes at least one processor, and at least one memory and a bus connected to the processor; wherein the processor and the memory communicate with each other through the bus; the processor is used to call program instructions in the memory to execute the above-mentioned PCELL layout design optimization method. The electronic device in this article can be a server, a PC, a PAD, a mobile phone, etc.

[0182] The present invention also provides a computer program product, which, when executed on an electronic device, is suitable for executing a program that initializes the steps of the PCELL layout design optimization method.

[0183] In the present invention, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0184] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0185] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0186] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A PCELL layout design optimization method, characterized in that: include: Obtaining a device PCELL of a FinFET device, wherein the device PCELL includes device process parameters and pattern adjustable parameters; Drawing a device layout for the FinFET device using the graphic adjustable parameters to obtain current PCELL layout structure parameters of the FinFET device; Based on the current PCELL layout structure parameters, construct a three-dimensional device simulation model of the FinFET device; At least using the three-dimensional device simulation model to construct a simulation compact model based on an artificial neural network algorithm, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device; Using the device PCELL and the simulation compact model, verify the device electrical performance influence trend of the three-dimensional device simulation model to obtain a simulation trend verification result; When the simulation trend verification result is passed, verify whether the module test circuit of the simulation compact model meets the preset circuit PPA index. If so, output and fix the current PCELL layout structure parameters.

2. The method according to claim 1, characterized in that Also includes: When it is verified that the module test circuit does not meet the preset circuit PPA index, the device PCELL is corrected according to the preset device performance index, and the step of using the graphic adjustable parameters to draw the device layout of the FinFET device to obtain the current PCELL layout structure parameters of the FinFET device is returned.

3. The method according to claim 1, characterized in that The adjustable graphic parameters include fin graphic parameters, gate graphic parameters, M0 layer metal graphic parameters, V0 layer graphic parameters, V0G layer graphic parameters, M1 layer metal graphic parameters, M0G layer metal graphic parameters, N / P injection layer parameters and N well graphic parameters.

4. The method according to claim 3, characterized in that The step of drawing a device layout of the FinFET device using the graphic adjustable parameters to obtain a current PCELL layout structure parameter of the FinFET device includes: According to the gate pattern parameters, with the origin of the layout coordinates as the center, draw the device gate rectangular pattern and the active area pattern area to obtain the first PCELL layout; On the basis of the first PCELL layout, according to the M0 layer metal pattern parameters, the M0 layer metal pattern area is drawn with the central symmetric point between adjacent virtual gates as the center to obtain a second PCELL layout; On the basis of the second PCELL layout, according to the V0 layer graphic parameters, with the M0 layer metal bottom spacing as the bottom starting position, a V0 hole array for connecting the M1 layer and the M0 layer is drawn to obtain a third PCELL layout; On the basis of the third PCELL layout, according to the M1 layer metal pattern parameters, the M1 layer metal pattern area is drawn based on the center point of each column V0 array to obtain a fourth PCELL layout; On the basis of the fourth PCELL layout, according to the M0G layer metal pattern parameters, draw the M0G layer metal pattern area, and according to the V0G layer pattern parameters, draw the V0G hole in the center of the M0G layer metal pattern, and then draw the M1 layer metal pattern with the V0G hole as the center, to obtain the fifth PCELL layout; On the basis of the fifth PCELL layout, according to the N / P injection layer parameters, the SP / SN layer graphic area is drawn based on the center of the gate to obtain a sixth PCELL layout; On the basis of the sixth PCELL layout, according to the N-well pattern parameters, an Nwell layer pattern area is drawn based on the center of the gate to obtain a seventh PCELL layout; On the basis of the seventh PCELL layout, according to the fin Fin graphic parameters, with the center of the gate as the starting point, the center of the gate coincides with the center of the fin spacing, and the Fin graphic area is drawn along the positive and negative directions of the y-axis, wherein the Fin graphic in the Fin graphic area is perpendicular to the gate direction, to obtain the eighth PCELL layout; The structural information of the eighth PCELL layout is extracted to obtain the current PCELL layout structural parameters of the FinFET device.

5. The method according to claim 1, characterized in that: The method of at least using a three-dimensional device simulation model to construct a simulation compact model based on an artificial neural network algorithm comprises: Obtaining an electrical characteristic curve data set of the three-dimensional device simulation model, wherein the electrical characteristic curve data set includes simulation trend data of the influence of the three-dimensional device simulation model on the electrical performance of the device under different device process parameters and different graphic adjustable parameters; Dividing the electrical characteristic curve data set into a training data set and a test data set; Using the training data in the training data set to train a pre-built artificial neural network algorithm to generate a prediction model; Inputting the test data in the test data set into the prediction model to obtain the prediction data output by the prediction model; Calculating a root mean square error between the predicted data and the test data; Determine whether the root mean square error exceeds a preset root mean square threshold; if not, implement the artificial neural network algorithm using a hardware description language for analog circuit design to generate a simulation compact model based on the artificial neural network algorithm; if yes, adjust the algorithm result or parameter of the artificial neural network algorithm, and return to execute the step of training the pre-built artificial neural network algorithm using the training data to generate a prediction model.

6. The method according to claim 5, characterized in that The device PCELL and the simulation compact model are used to verify the influence trend of the device electrical performance of the three-dimensional device simulation model, and obtain the simulation trend verification result, including: generating a symbolic representation of the electrical behavior of the FinFET device using the simulation compact model; Combining the symbolic representation with the device PCELL, generating a TCAD process simulation model; Using the TCAD process simulation model, testing the influence of different device process parameters and different graphic adjustable parameters on the device electrical performance of the three-dimensional device simulation model to obtain measured trend data; Verify whether the trends of the measured trend data and the simulated trend data are consistent. If yes, the simulation trend verification result is passed. Otherwise, the simulation trend verification result is failed.

7. The method according to claim 6, characterized in that Also includes: When the simulation trend verification result fails, the TCAD process simulation model is optimized, and based on the optimized TCAD process simulation model, the step of returning to execute the step of using the TCAD process simulation model to test the influence of different device process parameters and different graphic adjustable parameters on the device electrical performance of the three-dimensional device simulation model to obtain measured trend data.

8. A PCELL layout design optimization device, characterized in that: include: Device PCELL acquisition unit, device layout drawing unit, 3D device simulation model building unit, simulation compact model building unit, simulation trend verification result acquisition unit, circuit index verification unit and PCELL layout structure parameter output unit, The device PCELL obtaining unit is used to obtain the device PCELL of the FinFET device, wherein the device PCELL includes device process parameters and graphic adjustable parameters; The device layout drawing unit is used to draw the device layout of the FinFET device using the graphic adjustable parameters to obtain the current PCELL layout structure parameters of the FinFET device; The three-dimensional device simulation model construction unit is used to construct a three-dimensional device simulation model of the FinFET device based on the current PCELL layout structure parameters; The simulation compact model construction unit is used to construct a simulation compact model based on an artificial neural network algorithm using at least a three-dimensional device simulation model, wherein the simulation compact model is used to describe the electrical behavior of the FinFET device; The simulation trend verification result obtaining unit is used to verify the device electrical performance influence trend of the three-dimensional device simulation model by using the device PCELL and the simulation compact model to obtain a simulation trend verification result; The circuit indicator verification unit is used to verify whether the module test circuit of the simulation compact model meets the preset circuit PPA indicator when the simulation trend verification result is passed, and if so, trigger the PCELL layout structure parameter output unit; The PCELL layout structure parameter output unit is used to output and fix the current PCELL layout structure parameters.

9. A computer-readable storage medium having a program stored thereon, characterized in that: When the program is executed by the processor, the PCELL layout design optimization method as described in any one of claims 1 to 7 is implemented.

10. An electronic device, comprising at least one processor, and at least one memory and a bus connected to the processor; wherein: The processor and the memory communicate with each other via the bus; The processor is used to call the program instructions in the memory to execute the PCELL layout design optimization method as described in any one of claims 1 to 7.

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